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Characterization and modeling of planar spiral inductors and pad stack parasitic effects

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Title:
Characterization and modeling of planar spiral inductors and pad stack parasitic effects
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Book
Language:
English
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Capwell, John
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University of South Florida
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Tampa, Fla.
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Subjects / Keywords:
passive components
characterization
inter-connects
capacitors
substrate
Dissertations, Academic -- Electrical Engineering -- Masters -- USF   ( lcsh )
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government publication (state, provincial, terriorial, dependent)   ( marcgt )
bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

Notes

Summary:
ABSTRACT: This thesis concentrates on RF/microwave characterization and modeling of planar spiral inductors and pad stack parasitics. The inductors varied in size from 1.9 to 15.3 nH. Several approaches were examined for modeling the planar spiral inductors. The approach developed herein is built around an existing composite model (available in commercial computer-aided design software), with added series and shunt impedances at both the input and output of the existing composite model. Artificial neural network (ANN) software was used to determine the correction impedance values. Another approach investigated was to model the S-parameters of the inductor using a space- mapping model of the input parameters for the existing model. The correction impedance modeling approach was theoretically sound but the level of accuracy need for the ANN model was not obtainable. The space mapping approach had merit but a substrate and parameter scalable model could not be achieved. A pad stack is a section of microstrip line that a surface mounted element is affixed to; these pad stacks are standardized for specific element sizes, so for example any 0805 (80 mils by 50 mils) element may have the same pad stack whether it is a capacitor, inductor or resistor. The pad stack models were necessary because a capacitor model originally developed at the University of South Florida did not include parasitic effects for different input connections. The pad stack parasitic models can be broken down into three types: dual-input, tri-input, and quad-input. Each of the dual- and tri- input models have input angles of either 0 degrees, 45 degrees, or 90 degrees. The models were developed using a combination of microstrip and lumped elements.
Thesis:
Thesis (M.S.E.E.)--University of South Florida, 2003.
Bibliography:
Includes bibliographical references.
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Statement of Responsibility:
by John Capwell.
General Note:
Title from PDF of title page.
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Document formatted into pages; contains 71 pages.

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aleph - 001441471
oclc - 53961821
notis - AJM5911
usfldc doi - E14-SFE0000144
usfldc handle - e14.144
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ABSTRACT: This thesis concentrates on RF/microwave characterization and modeling of planar spiral inductors and pad stack parasitics. The inductors varied in size from 1.9 to 15.3 nH. Several approaches were examined for modeling the planar spiral inductors. The approach developed herein is built around an existing composite model (available in commercial computer-aided design software), with added series and shunt impedances at both the input and output of the existing composite model. Artificial neural network (ANN) software was used to determine the correction impedance values. Another approach investigated was to model the S-parameters of the inductor using a space- mapping model of the input parameters for the existing model. The correction impedance modeling approach was theoretically sound but the level of accuracy need for the ANN model was not obtainable. The space mapping approach had merit but a substrate and parameter scalable model could not be achieved. A pad stack is a section of microstrip line that a surface mounted element is affixed to; these pad stacks are standardized for specific element sizes, so for example any 0805 (80 mils by 50 mils) element may have the same pad stack whether it is a capacitor, inductor or resistor. The pad stack models were necessary because a capacitor model originally developed at the University of South Florida did not include parasitic effects for different input connections. The pad stack parasitic models can be broken down into three types: dual-input, tri-input, and quad-input. Each of the dual- and tri- input models have input angles of either 0 degrees, 45 degrees, or 90 degrees. The models were developed using a combination of microstrip and lumped elements.
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Characterization and Modeling of Planar Spiral Inductors and Pad Stack Parasitic Effects by John Capwell A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Thomas Weller, Ph.D. Lawrence Dunleavy, Ph.D. Horace Gordon, M.S.E.E. Date of Approval: September 15, 2003 Keywords: passive components, measurements, inter-connects, capacitors, substrate scalable Copyright 2003 John Capwell

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i Table of Contents List of Tables................................................................................................................. ....iii List of Figures................................................................................................................ ....iv List of Symbols and Acronyms.......................................................................................viii Abstract....................................................................................................................... .......ix Chapter 1 Introduction.......................................................................................................1 1.1 Overview.............................................................................................................1 Chapter 2 Planar Spiral Inductors......................................................................................4 2.1 Overview.............................................................................................................4 2.2 Previous Models..................................................................................................5 2.3 Design Specifications..........................................................................................7 2.4 Characterization..................................................................................................8 2.5 Model Extraction Techniques.............................................................................9 2.5.1 Impedance Parameter Model Extraction...................................................10 2.5.1.1 Comparison...........................................................................................13 2.5.1.2 Summary...............................................................................................20 2.5.2 Space Mapping Model Extraction............................................................20 2.5.2.1 Comparison...............................................................................................22 2.5.2.2 Summary...................................................................................................25 2.6 Other Modeling Methods..................................................................................25 2.7 Summary...........................................................................................................26 Chapter 3 Pad Stack Parasitics.........................................................................................27 3.1 Overview...........................................................................................................27 3.2 Motivation.........................................................................................................28

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ii 3.3 Design Specifications........................................................................................30 3.4 Characterization................................................................................................33 3.5 Model Extraction and Comparison...................................................................33 3.5.1 Dual Input Series Connections..................................................................33 3.5.1.1 Set #1...................................................................................................34 3.5.1.2 Set #2...................................................................................................36 3.5.1.3 Set #3...................................................................................................39 3.5.2 Tri Input Shunt Connections Sets.............................................................42 3.5.2.1 Set #4...................................................................................................42 3.5.2.2 Set #5...................................................................................................44 3.5.2.3 Set #6 and Set #7..................................................................................47 3.5.3 Quad Input Shunt Connections.................................................................49 3.5.3.1 Set #8...................................................................................................51 3.5.3.2 Set #9 and Set #10................................................................................54 3.6 Conclusions.......................................................................................................56 Chapter 4 Conclusion and Recommendations.................................................................57 References..................................................................................................................... ....58 Appendices ………………………………………………………………………………59 Appendix A: Equations for Calculating Induc tance of a Planar Spiral Inductor……..60

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iii List of Tables Table 1 – The Design Parameters for the Inductors Used in this Study ............................8 Table 2 – AParameter Comparison for Meas ured to Derived Correction Factor Model. ............................................................................................................................... ....14 Table 3 – BParameter Comparison for Meas ured to Derived Correction Factor Model. ............................................................................................................................... ....14 Table 4 – CParameter Comparison for Meas ured to Derived Correction Factor Model. ............................................................................................................................... ....14 Table 5 – DParameter Comparison for Meas ured to Derived Correction Factor Model. ............................................................................................................................... ....15 Table 6 – Optimized Results for a Sample of Inductor Space Mapping Coefficients......21 Table 7 – Pad Stack Parasitic Set Description..................................................................32

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iv List of Figures Figure 1 – Example of a Planar Spiral Induc tor. Legend: S: Spacing, R: Radius, and W: width of line................................................................................................................4 Figure 2 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Existing ADS Model to Measured Data for Inducto r with 5mil Line Width, 5mil Spacing, and Outer Radius of 62mil on 5mil Thick Substrate.........................................................6 Figure 3 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Existing ADS Model to Measured Data for Inducto r with 5mil Line Width, 5mil Spacing, and Outer Radius of 62mil on 14mil Thick Substrate.......................................................6 Figure 4 – Return Loss (S11) Magnitude (dB) an d Phase (deg) Comparison of Existing ADS Model to Measured Data for Inducto r with 5mil Line Width, 5mil Spacing, and Outer Radius of 62mil on 31mil Thick Substrate.......................................................7 Figure 5 – Cross-Sectional View of Multi-l ayer PCB Used to Measure Inductors............9 Figure 6 – Planar Spiral Induc tor Model Network Reduction..........................................11 Figure 7 – Z1 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate....................................................................................................................16 Figure 8 – Z2 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate....................................................................................................................16 Figure 9 – Y1 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate....................................................................................................................17 Figure 10 – Y2 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate....................................................................................................................17 Figure 11 – S11 Comparison Between the 3x3 ANN Model and Measurement for Planar Spiral Inductor with 5mil Line Widt h, 5mil Spacing, and 35mil Radius on 31mil FR4 Substrate............................................................................................................18

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v Figure 12 – S21 Comparison Between the 3x3 ANN Model and Measurement for Planar Spiral Inductor with 5mil Line Widt h, 5mil Spacing, and 35mil Radius on 31mil FR4 Substrate............................................................................................................19 Figure 13 – S22 Comparison Between the 3x3 ANN Model and Measurement for Planar Spiral Inductor with 5mil Line Widt h, 5mil Spacing, and 35mil Radius on 31mil FR4 Substrate............................................................................................................19 Figure 14 – Space Mapping Model...................................................................................21 Figure 15 – S11 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 10mil Spacing, and 35mil Radius on 5mil FR4 Substrate...................................................................................................22 Figure 16 – S21 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 10mil Spacing, and 35mil Radius on 5mil FR4 Substrate...................................................................................................23 Figure 17 – S11 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 10mil Spacing, and 35mil Radius on 14mil FR4 Substrate.................................................................................................23 Figure 18 – S21 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 10mil Spacing, and 35mil Radius on 14mil FR4 Substrate.................................................................................................24 Figure 19 – S11 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 10mil Spacing, and 35mil Radius on 31mil FR4 Substrate.................................................................................................24 Figure 20 – S21 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 10mil Spacing, and 35mil Radius on 31mil FR4 Substrate.................................................................................................25 Figure 21– Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated USF Capacitor Model 2113740A10 to M easured Data for 2113740A10 Capacitor with Input Rotated 45 on a 31mil FR4 Substrate....................................................29 Figure 22 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated USF Capacitor Model 2113740A 10 to Measured Data for 2113740A10 Capacitor with Input Rotated 90 on a 31mil FR4 Substrate...................................30 Figure 23 – Bond Pad Layout...........................................................................................33 Figure 24 – a) Set #1 Layout b) Set #1 Schematic..........................................................34

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vi Figure 25 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #1 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................35 Figure 26 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #1 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................35 Figure 27 – a) Set #2 Layout b) Set #2 Schematic..........................................................37 Figure 28 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #2 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................38 Figure 29 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #2 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................38 Figure 30 – a) Set #3 Layout b) Set #3 Schematic..........................................................40 Figure 31 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #3 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................41 Figure 32 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #3 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................41 Figure 33 – a) Set #4 Layout b) Set #4 Schematic..........................................................43 Figure 34 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #4 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................43 Figure 35 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #4 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................44 Figure 36 – a) Set #5 Layout b) Set #5 Schematic..........................................................45 Figure 37 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #5 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................46

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vii Figure 38 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #5 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................46 Figure 39 – a) Set #6 and Set #7 Layout, b) Set #6 and Set #7 Schematic.......................47 Figure 40 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #6 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................48 Figure 41 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #6 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................48 Figure 42 – Set #6 and Set #7 Layout...............................................................................50 Figure 43 – Cross Junction Lumped Element Schematic.................................................51 Figure 44 – a) Set #8 Layout b) Set #8 Schematic..........................................................52 Figure 45 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #8 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................53 Figure 46 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #8 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................53 Figure 47 – a) Set #6 and Set #7 Layout, b) Set #6 and Set #7 Schematic.......................54 Figure 48 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #9 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................55 Figure 49 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #10 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate....................................................................................55

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viii List of Symbols and Acronyms W Width of the input line H Thickness of the substrate c Speed of light C Capacitance eff Effective dielectric constant r Relative dielectric constant dB Decibels GSG Ground signal ground L Inductance MCROSS Microstrip cross-junction MLEF Microstrip line open-end effect MLIN Microstrip line MSTEP Microstrip step in width MTEE Microstrip T-junction Ohms, resistance units PCB Printed circuit board RF Radio frequency R Resistance Conductivity SOLR Short-Open-Load-Reciprocal Thru T Metal thickness TRL Thru-reflect-line X Reactance VNA Vector network analyzer 0_9.9Z Characteristic impedance of the pa d if the dielectric constant is 9.9 0 Z Characteristic impedance of the pa d with the dielectric constant of the substrate _9.9eff Effective dielectric constant of the substrate if the dielectric constant is 9.9 eff Effective dielectric c onstant of the substrate

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ix Characterization and Modeling of Planar Spiral Inductors a nd Pad Stack Parasitic Effects John Capwell ABSTRACT This thesis concentrates on RF/micro wave characterizati on and modeling of planar spiral inductors and pa d stack parasitics. Th e inductors varied in size from 1.9 to 15.3 nH. Several approaches were examined for modeling the planar spiral inductors. The approach developed herein is built around an existing composite model (available in commercial computer-aided design software), wi th added series and shunt impedances at both the input and output of the existing co mposite model. Artificial neural network (ANN) software was used to determine the correction impedance values. Another approach investigated was to model the Sparameters of the i nductor using a spacemapping model of the input parameters for th e existing model. The correction impedance modeling approach was theoretically sound but the level of accuracy need for the ANN model was not obtainable. The space mapping approach had merit but a substrate and parameter scalable model could not be achieved. A pad stack is a section of microstrip line that a surface mounted element is affixed to; these pad stacks are standardized for specific element sizes, so for example any 0805 (80 mils by 50 mils) element may ha ve the same pad stack whether it is a capacitor, inductor or resistor The pad stack models were necessary because a capacitor model originally developed at the University of South Florida did not include parasitic effects for different input connections. The pad stack parasitic m odels can be broken

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x down into three types: dual-input, tri-input, a nd quad-input. Each of the dualand triinput models have input angles of either 0 45 or 90 The models were developed using a combination of microstrip and lumped elements.

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1 Chapter 1 Introduction 1.1 Overview When designing RF/microwave circuits, it is important to take into account both the parasitic effects of the in terconnections to the elements (such as chip capacitors and inductors) as well as the parasitic effects of the elements themselves. In modern Computer Aided Engineering (CAE), the goa l is to design a ci rcuit virtually on a computer (using software such as Agilent’s Advanced Design SystemTM) and then manufacture it to produce the same response as the simulated design. The use of “ideal” elements (eg. perfect inductors and capacitors) in a circuit schematic can give an accurate response at low frequencies, but accounting fo r parasitic effects becomes increasingly important as the frequency is increased. In order to avoid manual tuning of the hardware, accurate models need to be used that acc ount for the parasitics at RF/microwave frequencies for not only the circuit elements but for the interconnections as well. This thesis will examine two main topics: planar spiral inductor modeling and pad stack parasitic modeling. The pad stack parasiti c models were created for different input connections to desired circuit elements. Th e planar spiral inductor models were developed for inductors with varying geomet ries and substrate heights. The pad stack parasitic models and planar spiral inductor mode ls are designed to be accurate from .05 to 10 GHz.

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2 The second chapter covers th e process of modeling planar spiral inductors. The models include the following input parameters : the number of turns of the inductor, the line width, the spacing between the lines, the di electric constant of the substrate, and the height of the substrate. The models are intend ed to be used in Agilent’s Advanced Design System (ADS). The third chapter will cove r pad stack parasitic eff ects. Pad stacks are the transmission line elements that surface m ounted components are affixed to, for example an 0805 capacitor has pad stack dimensions of 50mil (length) by 40mil (width) with 30mil spacing between the pads. The pad stack parasitics result from the discontinuities caused by the connections to the pad stack conf iguration. A step in width and an angled input offset are examples of these types of discontinuities. The pad stack configuration can be broken down into three different t ypes: single-input, dual -input, and tri-input connections. Due to the use of a two-port VNA, the single-input models were developed from series measurements, but the multi-i nput models were developed from shunt measurements. The three-input models were de veloped with one of the inputs terminated by a 50 load. All the models are comprised of e ither a combination of lumped elements and microstrip elements, or just microstrip elements. The contributions of this thesis include an investigation of two planar spiral inductor modeling approaches and new pad stack parasitic models for surface mount capacitors and inductors. Two methods were investigated for the planar spiral inductor models: correction factor modeling using an ex isting planar spiral inductor models and a space mapping models for the inputs of the exis ting planar spiral inductor model. Even though both methods investigated did not produce a usable sp iral inductor model, they

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3 can be a good starting point for further research. The pad stac k models were designed to increase the versatility of the existing cap acitor models, by expanding the range of the layout configurations in which they can be accurately used.

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4 Chapter 2 Planar Spiral Inductors S W R Figure 1 – Example of a Planar Spiral Induc tor. Legend: S: Spacing, R: Radius, and W: width of line. 2.1 Overview Planar spiral inductors are popular desi gn elements in RF/microwave circuitry. These elements can replace surface mounted com ponents that have to be attached to the Printed Circuit Board (PCB) by a solder or e poxy process. The planar inductor can be manufactured along with the transmission lines ; hence the manufacturer saves the cost of a surface mounted component and process to affix the component to the PCB. In order to use these types of inductors an accurate model is needed. A preliminary model was designed using a preexisting model from Agilent’s ADS. This model gives an accurate response on some subs trate heights (see Figure 5), but fails on others. An alternative approach is to incorporate the existi ng model as the core of a new model, and build in correction terms to e nhance its accuracy. Artif icial neural network

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5 software (NueroModeler (1)) was used to ge nerate equations that express the correction factors as a function inductor geometry and frequency. 2.2 Previous Models Previous planar spiral inductor models have been developed using physics based equations (2), and are accurate at low frequencies, but are la cking at higher frequencies. Agilent’s Advanced Design Systems (ADS) ha s models for the planar spiral inductor (MSIND) that are frequency, geometry, and s ubstrate dependent. These models give an accurate prediction of the response of most i nductors used in this work on 14 mil and 31mil FR4 substrates, but are not accurate for any of the inductors on 5 mil thick substrates. As an example, the return lo ss for an inductor with 5mil line width, 5mil spacing, and radius of 62mil (see figure 1 for sp iral geometry) can be seen in Figures 2 through 4. There are obvious differences betw een measured and simulated results on the 5mil boards, but reasonable accuracy is achieved on the other two substrates.

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6 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend Model Magnitude Measured Magnitude Model Phase Measured Phase Figure 2 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Existing ADS Model to Measured Data for Inducto r with 5mil Line Width, 5mil Spacing, and Outer Radius of 62mil on 5mil Thick Substrate. 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 3 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Existing ADS Model to Measured Data for Inducto r with 5mil Line Width, 5mil Spacing, and Outer Radius of 62mil on 14mil Thick Substrate.

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7 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 4 – Return Loss (S11) Magnitude (dB) an d Phase (deg) Comparison of Existing ADS Model to Measured Data for Inducto r with 5mil Line Width, 5mil Spacing, and Outer Radius of 62mil on 31mil Thick Substrate. 2.3 Design Specifications The planar inductors were designed on FR4 using 3 substrate heights: 5mil, 14mil, and 31mil. The geometry of the inducto rs vary with the widt h of the line, the line spacing, the outside radius of the inductor, a nd the number of turns of the inductor. For each combination of line width and line spaci ng the outer radius was varied to get approximate inductance values that can be seen in Table 1 (See Appendix A for inductance equations). The minimum induc tance value is based on the smallest obtainable radius using the limitations of the printed circuit board (PCB) technology.

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8 Table 1 – The Design Parameters for the Inductors Used in this Study (N=number of turns). N Width (mils) Spacing (mils) Radius (mils) Inductance (nH) N Width (mils) Spacing (mils) Radius (mils) Inductance (nH) 1 5 5 35 1.9 2 5 5 45 7.60 1 5 5 45 3 2 5 5 52 10.25 1 5 5 62 4.98 2 5 5 64 15.18 1 5 10 40 1.90 2 5 10 55 7.83 1 5 10 50 2.90 2 5 10 62 10.27 1 5 10 62 4.385 2 5 10 75 15.22 1 5 15 45 1.90 2 5 15 65 8.20 1 5 15 55 2.861 2 5 15 71 10.27 1 5 15 75 5 2 5 15 85 15.15 1 10 5 45 1.90 2 10 5 60 8 1 10 5 57 3.06 2 10 5 67 10.37 1 10 5 75 5 2 10 5 80 15.16 1 10 10 50 1.92 2 10 10 70 8.42 1 10 10 60 2.84 2 10 10 75 10 1 10 10 81 5 2 10 10 90 15.20 1 10 15 55 1.96 2 10 15 80 8.89 1 10 15 67 3.03 2 10 15 85 10.41 1 10 15 87 5.04 2 10 15 99 15.03 1 15 5 55 1.96 2 15 5 75 8.65 1 15 5 65 2.84 2 15 5 80 10.20 1 15 5 87 5.04 2 15 5 95 15.27 1 15 10 60 2 2 15 10 90 10.63 1 15 10 72 3.04 2 15 10 104 15.16 1 15 10 92 4.99 1 15 15 65 2.05 1 15 15 77 3.06 2 15 15 97 10.23 1 15 15 98 5.05 2 15 15 113 15.16 2.4 Characterization Measurements were performed on an HP8719B Vector Networ k Analyzer (VNA) and JMicro probe station using 650 m pitch GGB ground-signal-ground (GSG) probes. Cascade’s WinCal 2.1 software was used to perform a Thru-Reflect-Line (TRL) calibration (3) and measure the S-parameters The measurements were performed from .05~10 GHz. The TRL calibration was performed on the back-side of the multi-layer PCB board (see Figure 5), setting up measuremen t reference planes at the edge of the

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9 pads for the “live” vias. The calibration s ubstrate thickness was maintained at 14mil, while the inductor substr ate thickness was varied between 5, 14, 31mil. The inductors were printed on one side of a multi-layer PCB board. This PCB board consisted of a metal layer (inductor la yer), a substrate, a buried metal layer (ground plane), another substrate, and then another me tal layer (calibration layer); see Figure 5 for a graphical representation of the cross-section of the test fixture board. The inductors are on one metal layer and the calib ration is performed on the othe r metal layer. “Live” vias were used to connect the inducto r metal layer to the lower metal layer. In order to use live vias to connect the two metal layers, metal was removed from the ground plane where the “live” vias were located. The term “live” via refers to a via used to pass the RF signal to another layer; this is in c ontrast to a ground via that conne cts a metal layer to a ground plane. Copper Ground Plane Copper signal line Copper via pad FR4 Dielectric FrontMetal Ground BackMetal Substrate Height 14mil Thick Substrate Planar Spiral Inductor Live Vias Measurement Reference Plane Figure 5 – Cross-Sectional View of Multi-l ayer PCB Used to Measure Inductors. 2.5 Model Extraction Techniques Two techniques are investigated in this section; impedance correction model extraction and space-mapping extraction. Each method uses the existing ADS model as the foundation for the m odel development.

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10 2.5.1 Impedance Parameter Model Extraction The impedance parameter model extraction process can be broken down into three main steps. The first step is to th eoretically derive expr essions for correction impedances. The second step is to calculate the correction impedances from the measured data, making the impedances dependent on the number of turns of the inductor (N), the width of the line (W), the spaci ng between the lines (S), the outer radius of the inductor (Ro), the substrate height (H), and the freque ncy (freq). The third step is to develop a suitable set of equations to predict the co rrection impedances, which are essentially multidimensional fits to the calculated values. The correction impedances were derived using ABCD parameter, admittance parameters and impedance parameter network theory (4). Through a sequence of network analysis manipulations the co rrection impedances were found as a function of the entire network ABCD parameters and the existing ADS inductor model parameters. The entire network ABCD parameters are the ABCD parameters derived from inductor measurements. The first step in the derivation is to re present the existing inductor model as an equivalent pi network (4). The combined network of the correction impedances and admittances, and the ADS model’s equivalent pi network, was simplified into two cascaded “Tee” junction networks (see Figure 6). Each of the remaining “Tee” junction networks were then represented by impe dance parameter matrices. The impedance parameter matrices were then converted in to ABCD parameter matrices. The reason for converting into ABCD parameter matrices is because they are easily combined when cascaded.

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11 Z1 Y1 Z2 Y2 Za Z1 ZL Z2 ZR Za/2 Za/2 Ya Yb Existing Inductor Model Correction FactorsCorrection Factors =1/(Y1+Ya)=1/(Y2+Yb) a) b) Figure 6 – Planar Spiral I nductor Model Network Reduction. Once these conversions are completed it is possible to solve for the series and shunt impedances (Z1, Z2, ZL, and ZR from Figure 6b). The final correction factor equations are: 2 1RB Z B CAD (1), 1RC L R Z Z Z Z C (2), 11a LYY Z (3), 21b RYY Z (4), 11 2RC R Z AZ Z ZC (5), 212 2RRCC RCRZZDZCZD Z ZZZC (6). Where 11 21 Y A Y 1 21 B Y 11221221 21 YYYY C Y and 11 21 Y D Y Y11, Y21, Y12, and Y22 are the impedance

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12 parameters for the measured data (4). These equations make it possible to calculate exact values for the correction fact ors from ABCD parameters derived from measurements of physical inductors, and the equivalent pi network parameters of the existing inductor model. The correction factors are calculated at each of the desired frequency points. Calculating the correction factors can be done using software such as MathCAD, spreadsheet software such as EXCEL, or simulation software such as ADS. ADS was chosen for this work because the existing i nductor models were already simulated for a comparison study, and only the measured data and correction factor e quations need to be added to calculate the correction impedances. ADS also has the ability to simulate over different desired frequency ranges. The necessary equations were created in the MeasEqn feature in ADS, making it possible to simu late, automatically display and check the agreement to the simulated response. The correct ion factors were exported into a series of ASCII files and then imported and manipulated into one file for inputting into the artificial neural netw ork (ANN) software. Once the data was ready for ANN software the neural networ k is trained and tested. Training the network is a type of optimization in the ANN software, and different optimization techniques can be used (e. g. QuasiNewton, gradient, random, etc). While training it is useful options is to obs erve how the ANN model outputs change as a function of each of the input variables. Also a good rule to follow while training is to use every other data point, as the complete data set can later be used during the testing process. The training process fits the ANN model to the data, a nd the testing process compares the model to another set of data.

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13 Three different formats were used to input the data into the ANN software: impedances, admittances and the reflection coefficient ( ) with respect to 50 (5). It was determined to input the original configur ations of the series impedances (Z1 and Z2 from Figure 6a) and the shunt admittances (Y1 and Y2 from Figure 6a). The four parameters were then separated into their real and imaginary parts. Using the eight separate factors, i.e. the r eal and imaginary parts for Z1, Z2, Y1, and Y2, a spreadsheet was generated for each, and then converted in to space delimited format for inputting into the ANN software. 2.5.1.1 Comparison Three different responses are compared in this study: the ABCD parameters of the measurements and the ABCD parameters of the new inductor model, the derived correction factor values a nd the values generated by th e ANN equation, and the Sparameters of the measurements verse the Sparameters of the new inductor model using the ANN correction factor equations. Comparisons of the ABCD parameters of the measurements to the new inductor model were used as a check of the equation derivation process. Ideally this is an exact match as the values for the correction factors for the new model are derived from a closed form expression. Table 2 through Table 5 show comparisons between measured data and derived data of the A, B, C, and D paramete rs, respectively. These tables show a nearly exact match between measurements and the new inductor model.

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14 Table 2 – A-Parameter Comparison for Measur ed to Derived Correction Factor Model. N W (mil) S (mil) Ro (mil) H (mil) Freq. (GHz) Measured AParameter Calculated AParameter 1 5 5 35 5 1 0.948756+j0.00192 0.948756+j0.00194 1 5 15 55 31 4 -0.4051+j0.02777 -0.4051+j0.02777 1 5 10 69 14 8 -0.61974-j0.05244 -0.61974-j0.05244 1 10 10 60 5 5 -0.53973+j0.02668 -0.53973+j0.02668 1 10 15 87 14 3 -0.27164+j0.02036 -0.27728+j.02036 1 15 15 98 31 9 1.2155-j0.02279 1.2122-j0.02279 2 10 10 85 5 2 0.07443+j0.02669 0.07443+j0.02669 2 10 15 104 31 6 1.22508-j0.01913 1.22508-j0.01913 2 5 5 52 14 7 -1.1377-j0.04766 -1.1377-j0.04766 Table 3 – BParameter Comparison for Measur ed to Derived Correction Factor Model. Table 4 – CParameter Comparison for Measur ed to Derived Correction Factor Model. N W (mil) S (mil) Ro (mil) H (mil) Freq. (GHz) Measured CParameter Calculated CParameter 1 5 5 35 5 1 0.0000747+j0.00472 .0000269+j0.00465 1 5 15 55 31 4 -0.00029+j0.00708 -0.00027+j0.00709 1 5 10 69 14 8 0.00019-j0.02244 0.00017-j0.02241 1 10 10 60 5 5 -0.000368+j0.01537 -0.000371+j0.0153 1 10 15 87 14 3 -0.00016+j0.01140 -0.00022+j0.0123 1 15 15 98 31 9 0.00176+j0.00406 0.00170+j0.00400 2 10 10 85 5 2 -0.00004+j0.01758 -0.00004+j0.01758 2 10 15 104 31 6 0.00169-j0.00369 0.00162-j0.00373 2 5 5 52 14 7 -0.000499-j0.03497 -.000505-j0.03505 N W (mil) S (mil) Ro (mil) H (mil) Freq. (GHz) Measured BParameter Calculated BParameter 1 5 5 35 5 1 0.55014+j21.40422 0.55014+21.40422 1 5 15 55 31 4 1.11946+112.9357 1.11946+j112.9357 1 5 10 69 14 8 -2.8276-j28.84469 -2.8276-j28.84469 1 10 10 60 5 5 -0.73962+j45.9798 -0.73962+j45.9798 1 10 15 87 14 3 -0.02925+j80.8210 -0.02825+j80.8210 1 15 15 98 31 9 4.3343-j36.10485 4.3343-j36.10495 2 10 10 85 5 2 0.36360+j56.6408 0.36360+j56.6408 2 10 15 104 31 6 3.17599-j27.8283 3.17599-j27.8283 2 5 5 52 14 7 -4.2457+j21.0403 -4.2457+j21.0403

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15 Table 5 – DParameter Comparison for Meas ured to Derived Correction Factor Model. N W (mil) S (mil) Ro (mil) H (mil) Freq. (GHz) Measured DParameter Calculated DParameter 1 5 5 35 5 1 0.94767+j0.0025 0.94767+j0.0025 1 5 15 55 31 4 -0.37062+j0.05068 -.37062+j0.05068 1 5 10 69 14 8 -0.28418-j0.06444 -0.28418-j0.6444 1 10 10 60 5 5 -0.5448+j0.02559 -0.5448+j0.02559 1 10 15 87 14 3 -0.28436+j0.02710 -0.28436+j0.02710 1 15 15 98 31 9 0.95267-j0.02005 0.92567-j0.02005 2 10 10 85 5 2 0.06445+j0.02555 0.06445+j0.02555 2 10 15 104 31 6 0.73725-j0.03649 0.73725-j03649 2 5 5 52 14 7 -1.5299-j0.057187 -1.5299-j0.057187 Comparisons of the ANN generated corre ction factors to the derived correction factors can be seen in Figure 7 – 10. Thes e comparisons are for an ANN model that is generated for a one turn spiral inductor with 5mil line width, 5mil line spacing, 35mil outer radius, on a 5mil substrate. This ANN model was generated for just this one inductor on a single substrate only. The re sults of an ANN model based on three inductors and three substrat es (“3x3 model”) are shown in Figures 11 – 14. The 3x3 ANN was tested and obtained a worst case percent error of 5.5%.

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16 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -500 0 500 1000 1500 2000 2500 3000R e a l -1500 -1000 -500 0 500 1000 1500I m a g i n a r y Legend Derived Real ANN Real Derived Imaginary ANN Imaginary Figure 7 – Z1 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -500 0 500 1000 1500 2000 2500 3000R e a l -1500 -1000 -500 0 500 1000 1500 2000I m a g i n a r y Legend Derived Real ANN Real Derived Imaginary ANN Imaginary Figure 8 – Z2 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate.

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17 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -0.0025 -0.002 -0.0015 -0.001 -0.0005 0 0.0005 R e a l -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0I m a g i n a r y Legend Derived Real ANN Real Derived Imaginary ANN Imaginary Figure 9 – Y1 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -0.003 -0.0025 -0.002 -0.0015 -0.001 -0.0005 0 0.0005R e a l -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 I m a g i n a r y Legend Derived Real ANN Real Derived Imaginary ANN Imaginary Figure 10 – Y2 Comparison Between Calculat ed and ANN Generated Data for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 5mil FR4 Substrate.

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18 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -35 -30 -25 -20 -15 -10 -5 0 5 10M a g n i t u d e ( d B ) -150 -100 -50 0 50 100P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 11 – S11 Comparison Between the 3x3 ANN Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 31mil FR4 Substrate.

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19 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 12 – S21 Comparison Between the 3x3 ANN Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -35 -30 -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -150 -100 -50 0 50 100 150P h a s e ( d e g ) Legend S22 Model Magnitude S22 Measured Magnitude S22 Model Phase S22 Measured Phase Figure 13 – S22 Comparison Between the 3x3 ANN Model and Measurement for Planar Spiral Inductor with 5mil Line Width, 5mil Spacing, and 35mil Radius on 31mil FR4 Substrate.

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20 2.5.1.2 Summary The method for deriving the correction f actors is a unique solution and works in theory, but it requires a level of accuracy for the impedance and admittance correction factors that cannot be direct ly obtained with existing curve fitting methods (i.e. ANN, polynomial, etc). The 3x3 ANN model had a wors e case error of 5.5%. It can be seen from figures 11-13 that a 5.5% error has a dras tic effect on the response. It was due to this limitation that another method of inductor modeling wa s investigated. 2.5.2 Space Mapping Model Extraction Space mapping is another approach of us ing an existing model as the fundamental part of a new model. In this case, the input parameters to the exis ting model are modified from the “nominal” (or physical) values in order to obtain the proper response. Then the modified input parameters are mapped to th e physical parameters of the inductors. The resulting space map can then be used in reve rse to transform the i nput parameters (the number of turn of the inductor (N), the wi dth of the line (W), th e spacing between the lines (S), the outer radius of the inductor (Ro), the subs trate height (H), dielectric constant (Er), and frequency (freq)) to the m odified inputs that are used with the existing model. In theory the existing model with th e modified inputs will be able to output the response for the inductor. A graphical representa tion of this process can be seen in figure 14.

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21 Space Mapping Parameter Model Corrected Parameters: N, W, S, Ro, H, Er Existing Inductor Model S-Parameters Inductor Parameters: N, W, S, Ro, H, Er Figure 14 – Space Mapping Model. The modified input parameters were calculated by optimizing the input parameters of the existing model until the s-parameter outputs matched the measured s-parameters. Some example of these modified input parameters can be seen in Table 6. Table 6 – Optimized Results for a Sample of Inductor Space Mapping Coefficients. Inductor Input Parameters Modified Input Parameter N W (mil) S (mil) Ro (mil) H (mil) Er N W (mil) S (mil) Ro (mil) H (mil) Er 1 5 10 50 5 4.3 1 4.9 8.7 48.7 6.52 4.3 1 5 10 50 14 4.3 1 6.1 10.2 49.9 15.2 4.3 1 5 10 50 31 4.3 1 4.87 10.3 47.9 29 4.3 2 5 15 85 5 4.3 2 5.1 14.2681.36 6.98 4.3 2 5 15 85 14 4.3 2 7.2 14.9787.33 14.81 4.3 2 5 15 85 31 4.3 2 6.32 15.3685.75 29 4.3

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22 2.5.2.1 Comparison Some examples of the modified input para meters can be seen can be seen in Table 6. These parameters were then inputted back into the existing ADS model; the results of the space mapping approach can be seen in Figure 15 through Figur e 20. These results show that the 14 mil and 31 mil data is an acceptable match but the 5mil data is not an acceptable match. 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -150 -100 -50 0 50 100P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 15 – S11 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Wi dth, 10mil Spacing, and 35mil Radius on 5mil FR4 Substrate.

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23 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -3 -2.5 -2 -1.5 -1 -0.5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 16 – S21 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Wi dth, 10mil Spacing, and 35mil Radius on 5mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -150 -100 -50 0 50 100P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 17 – S11 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Wi dth, 10mil Spacing, and 35mil Radius on 14mil FR4 Substrate.

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24 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 18 – S21 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Wi dth, 10mil Spacing, and 35mil Radius on 14mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -150 -100 -50 0 50 100P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 19 – S11 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Wi dth, 10mil Spacing, and 35mil Radius on 31mil FR4 Substrate.

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25 0 1 2 3 4 5 6 7 8 9 10Frequency (GHz) -6 -5 -4 -3 -2 -1 0 1M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 20 – S21 Comparison Between the Space Mapping Model and Measurement for Planar Spiral Inductor with 5mil Line Wi dth, 10mil Spacing, and 35mil Radius on 31mil FR4 Substrate. 2.5.2.2 Summary As with the ANN model extraction appr oach described in Section 2.5.1, an acceptable match between measurements and models developed using the space-mapping method could only be obtained for the 14 and 31 mil substrates, but not the 5 mil substrate. A method for curve fitting the re lationships between the modified inductor inputs among the multiple substrates was not determined. 2.6 Other Modeling Methods Two other model extraction methods were also investigated a lumped element model and a coupled line model. Like the pr eviously described met hods, the results were acceptable on the 14mil and 31mil thick substrates, but the 5mil model did not agree with

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26 the measured data. These additional studies confirmed a potential issue with the accuracy of the 5mil measured data. 2.7 Summary One uncertainly involved with the examined model extraction study was the related to the measurement technique used. In this work the measurement reference plane was located on the opposite side of the PCB from the inductors, thus there are live vias between the measurement reference plane and th e inductors. These vi as could contribute parasitic effects that are not easily accounted for in the mode ls. If the calibration had been performed on the same side of the PCB board as the inductors, it would remove uncertainties related to the vias. In a next iteration it would be advi sable of perform this adjustment in the measurement and calibration setup of the PCB design.

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27 Chapter 3 Pad Stack Parasitics 3.1 Overview The purpose of the pad stack study was to develop models that can be used with high frequency capacitor models to allow more versatility in the way the capacitors are configured on a circuit schematic layout. In this case, the baseline capacitor models were developed at the University of South Florida (USF) and assume 2-port series interconnects in which the input and output lines are parallel to each other. Using the pad stack models, new types of interconnects that ca n be used range from angled single inputs to multiple inputs of two and three lines. In practice, the different types of inputs are used to minimize the area of a PCB layout, and the models developed herein are representative of the types of component connections used in a realistic PCB. One challenge in developing the ne w pad stack models is that the USF capacitor model has the effect of the straight, series, 2-port pad stack incorporated into the model. It was desired to leave the original model in tact, and allow alternative pa d stack models to be used; therefore the pad stack models first comp ensate for the built-in effects of a straight 2-port interconnect and then account for the pa rasitic effects of th e actual interconnect being used. An example of a capacitor pad stack can be seen in Figure 26. This figure also shows that the USF capacitor model reference plane is external to the existing model topology. The USF capacitor model was develo ped using a microstrip taper as the transition between the capacitor pad stack widt h and the input micros trip line width, the

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28 latter always being adjusted to achieve a 50 characteristic impedan ce for the particular substrate. In this study 5mil, 14mil and 31mil substr ates heights were used. On the 14mil and 31mil substrates two different input line wi dths (connected directly to the pad stacks without the tapers mentioned above) were used to develop the models. The models were developed using an 0805 chip capacitor with a model number 2113740A10(2pF), then verified on capacitor 2113740A49(56pF) and 2113730A 66 (300pF). It will be shown that using a combination of microstrip elements and lumped elements, the various interconnections can be accurate ly modeled from through 9GHz. 3.2 Motivation Prior to this work, no pad stack parasiti c models were available for use with the USF capacitor models. More generally, this is the first known attempt to develop models that accurately negate built-i n pad stack effects for one inte rconnect configuration (i.e. the configuration used to deve lop the original models) whil e introducing circuit elements representative of a new configur ation. In order to demonstrate the need for such models, two comparisons are shown between measured data for a given pad stack configuration, compared to simulated data using only th e USF capacitor model. Figure 14 shows the reflection coefficient measurement of the dual-input 45 pad stack (see Set #3, section 3.3) compared to the original USF capaci tor model. Figure 21 shows the reflection coefficient measurement of the dual-input series 90 pad stack (see Set #2, section 3.3) compared to the USF capacitor model. These two figures show that when the input and output configurations are modified the USF capacitor model does not give an accurate response across the band. For frequencies below 1 GHz, the USF capacitor model by

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29 itself gives an accurate response, but as the frequency is increased deviations from the measurements are observed. This occurs due to more pronounced parasitic effects at higher frequencies. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -120 -100 -80 -60 -40 -20 0 20 40 60P h a s e ( d e g ) Legend Model Magnitude Measured Magnitude Model Phase Measured Phase Figure 21– Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated USF Capacitor Model 2113740A10 to Measur ed Data for 2113740A10 Capacitor with Input Rotated 45 on a 31mil FR4 Substrate.

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30 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -120 -100 -80 -60 -40 -20 0 20 40 60P h a s e ( d e g ) Legend Model Magnitude Measured Magnitude Model Phase Measured Phase Figure 22 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated USF Capacitor Model 2113740A 10 to Measured Data for 2113740A10 Capacitor with Input Rotated 90 on a 31mil FR4 Substrate. 3.3 Design Specifications Three different types of connections were investigated: dual-input series connections, tri-input connections, and quadinput connections (the number of inputs includes the interconnect lines plus the connection to the capacitor). The dual-input connections consist of input line connections at input angles of 0 45 and 90 The triinput connections have inputs on tw o sides with input angles of: 0 and 90 45 and 135 and 0 and 180 Due to the use of two-port meas urement equipment, the tri-input structures had to be measured in a shunt c onfiguration. The quad-input connections have one input on each of the unused pad stack sides, but due to the use of two-port measurement equipment one of the inputs had to be terminated in a 50 load. Like the

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31 tri-input configuration, all the quad-input configurations were measured in a shunt configuration. All of the different connection sets can be seen in Table 7. The pad stack parasitic models have been developed for 0805 USF capacitor models. The specific part numbers used were: 2113740A10, 2113740A49, and 2113740A66. The 0805 pad stack has a length of 40mils, a width of 50mils, and a pad spacing of 30mils. The pad stack models have been developed usi ng input line width of 8.5mils and 25.6mils on the 14mil and 31mil s ubstrates; only the 8.5mil input line width was used on the 5mil thick boards. All the models are scalable versus on substrate parameters such as dielectric constants and substrate height, as well as input line widths.

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32 Table 7 – Pad Stack Parasitic Set Description. Structure Set Number Name Set #1 2 Input Series Connection with 0 Offset Set #2 2 Input Series Connection with 90 Offset Set #3 2 Input Series Connection with 45 Offset Set #4 3 Input Shunt Connection with 0 Offset Set #5 3 Input Shunt Connection with 45 Offset Set #6 and Set #7 3 Input Shunt Connection with 0 & 90 Offset Set #8 4 Input Shunt Connection with 10 & 2-90 Offsets. The 0 Offset is terminated with a 50 Load. Set #9 and Set #10 4 Input Shunt Connection with 10 & 2-90 Offsets. The one of the 90 Offsets is terminated with a 50 Load.

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33 CapacitorPad Stack LengthPad Stack Width Pad Stack Spacing USF Capacitor Model Reference Plane Figure 23 – Bond Pad Layout. 3.4 Characterization The measurements used for model extraction were taken on the same equipment and software specified in Chapter 2.4. However, unlike the pl anar spiral inductor characterization, the TRL calibration was not the only calibration us ed. An SOLR (shortopen-load-reflect) calibration (6 ) was used on two pad stack configurations. The reason for choosing the SOLR calibration was the ab ility to perform meas urements with the microwave probes positioned at right angles The SOLR calibration and measurements were performed using WinCal 2.1. The SO LR calibration was used for Set #7 and Set #10 (see Table 7). 3.5 Model Extraction and Comparison 3.5.1 Dual Input Series Connections There are three dual-input series connections being examined, as seen in Table 7. Set #1 is the same configuration as that used by B. Lakshminarayanan (7) except the tapers used in that work to connect between feed lines and capacitor pad stack were replaced by steps in width. In Set #2 the capacitor is rotated 90 so the connections are

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34 on the length side of the pad stack, instead of the width side. In Set #3 the capacitor is rotated 45 so the connections are on th e corner of the pad stack. 3.5.1.1 Set #1 Set # 1 is a series two-port connection with input lines on the pad width side of the pad stack. The transition between th e bond pad and the input line width is a microstrip step element (MSTEP in Series IV and ADS). This structure shows how well a step in width can replace a taper in the or iginal capacitor model. The model for this connection is just a microstrip step in widt h. Figure 24 shows both the structure and the model. Figures 25 and 26 show the return loss and insertion loss comparisons between the model and measured data. Capacitor Model Reference Plane Measurement Reference Plane a) MSTEP W1=PADW W2=LINEW MSUB=MSUB1 Port 2 MSTEP W1=PADW W2=LINEW MSUB=MSUB1 Port 1 USF Capacitor Model MSUB=MSUB1 b) Figure 24 – a) Set #1 Layout, b) Set #1 Schematic.

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35 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -120 -100 -80 -60 -40 -20 0 20 40 60P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 25 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #1 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0M a g n i t u d e ( d B ) -150 -100 -50 0 50 100P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 26 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #1 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate.

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36 3.5.1.2 Set #2 Set #2 is a series 2-port connection with the inputs to th e bond pad on the pad length side of the pad stack. For this connection the capacitor was rotated 90 and the inputs are on the bond pad length side. It wa s first attempted to model this connection using a microstrip corner, but the size of th e bond pad violated the allowed parameters of the corner element as defined in Series IV and ADS. Instead, a “tee” junction was used and the unused side of the junction was ope n circuited (see Figur e 27b). Because the original capacitor model incor porates the bond pad effects, a microstrip line was added to the side of the junction connected to the capacitor model, with a negative line length equal to the bond pad length. A step in widt h is added at the i nput to account for the impedance step between the input line and the bond pad length width. A schematic can be seen in Figure 27b. The USF capacitor is represented in the schematic by the capacitor element labeled “Capacitor_Model” Figures 28 and 29 show the return loss and insertion loss comparisons between the model and measured data.

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37 CapacitorModel Reference Plane Measurement Reference Plane Figure 27 – a) Set #2 Layout, b) Set #2 Schematic. MSTEP W1=PADW W2=LINEW MSUB=MSUB1 Port 1 USF Capacitor Model MSUB=MSUB1 MSTEP W1=PADW W2=LINEW MSUB=MSUB1 Port 2 MLIN W1=PADW L=NEG_PADL MSUB=MSUB1 MLIN W1=PADW L=NEG_PADL MSUB=MSUB1 MLOC W1=PADW L=NEG_PADL MSUB=MSUB1 MLOC W1=PADW L=NEG_PADL MSUB=MSUB1 MTEE W1=PADW W2=PADL W3=PADW MSUB=MSUB1 MTEE W1=PADW W2=PADL W3=PADW MSUB=MSUB1

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38 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -120 -100 -80 -60 -40 -20 0 20 40 60P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 28 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #2 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -150 -100 -50 0 50 100P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 29 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #2 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate.

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39 3.5.1.3 Set #3 Set #3 is a series 2-port connection with inputs on the corner of the bond pad at an angle of 45 The 45 connection is modeled with a se ries inductor and a shunt capacitor to ground (see Figure 30a). The model reference plane is at the tip on the corner; (Figure 30b), where the dashed lines designate the re ference plane. The equation for the series inductance (L1) in nH and shunt capacitance (C1) in pF (8) can be seen below. Figures 31 and 32 show the return loss and inserti on loss comparisons between the model and measured data. ) 1 ln( 7206 0506 ( 3579 1 W H C C (7) H W t W t W L 1 ln 0459 2 0096 13 8372 2 0333 2871 0 6744 5 ln 8372 2 10 2 13(8) Where 0* Z c Ceff W= width of the input line in mm, H= thickness of the substrate in mm, eff=effective dielectric constant, Z0=Characteristic impedance, c= speed of light, t= metal thickness in mm.

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40 Capacitor Measurement Reference Plane Model Reference Plane ` Port 2 Port 1 USF Capacitor Model MSUB=MSUB1 ADS Capacitor C=C1 ADS Inductor L=L1 ADS Inductor L=L1 ADS Capacitor C=C1 Figure 30 – a) Set #3 Layout, b) Set #3 Schematic.

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41 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5M a g n i t u d e ( d B ) -120 -100 -80 -60 -40 -20 0 20 40 60P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11 Measured Phase Figure 31 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #3 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0M a g n i t u d e ( d B ) -150 -100 -50 0 50 100P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 32 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #3 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate.

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42 3.5.2 Tri Input Shunt Connections Sets The tri input shunt connections pad stacks are sets 4-7. For these connections the “Tee” junction element (MTEE in Series IV and MTEEO in ADS) and output series inductance at the input to the pad stack structures are used to model this effect. The difference between the sets will be discusse d in the corresponding sections below. The via data used in the models are measured for the corresponding substrate thickness. 3.5.2.1 Set #4 Set #4 is a shunt tri-input connection w ith the input line c onnections on the pad length sides of the bond pad (see Figure 33a). Th e input to this model has a step in width at the input to the “Tee” junction, and on the output of the “Tee” junction there is a microstrip line element with a negative line length and series induc tance. The inductance was added to compensate for negating the “Tee” junction element by using a negative length of microstrip line. The equation for the series output inductance (L1) (9) in nH can be seen in equation 9; this value was determ ined via circuit optimization. Figures 34 and 35 show the return loss and in sertion loss comparisons between the model and measured data, respectively. H W t W t W L 1 ln 6552 1 5551 6 5837 3 0586 4056 0 1674 7 ln 5837 3 10 2 13 (9) Where W= width of the input li ne in mm, H= thickness of th e substrate in mm, t= metal thickness in mm.

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43 Capacitor Measurement Reference Plane Model Reference Plane Via to Ground Figure 33 – a) Set #4 Layout, b) Set #4 Schematic. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Magnitude S11 Measured Magnitude Figure 34 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #4 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. Port 2 Port 1 MTEE W1=PADW W2=PADL W3=PADW MSUB=MSUB1 MSTEP W1=PADW W2=LINEW MSUB=MSUB1 MSTEP W1=PADW W2=LINEW MSUB=MSUB1 ADS Inductor L=L1 `USF Capacitor Model MSUB=MSUB1 S1P File File name=Via MLIN W1=PADW L=NEG_PADL MSUB=MSUB1

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44 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -120 -100 -80 -60 -40 -20 0 20 40P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 35 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #4 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 3.5.2.2 Set #5 Set #5 is a shunt tri-input connection with the input lin e connections on the corner of the bond pad at an angle of 45 It was found that no combination of microstrip elements could model this connection, so a lumped element equivalent circuit was designed. The lumped element circuit for th is connection is a series inductance at the input and output of the “Tee” junction element. The equations for these inductances (L1 and L2) (9) in nH can be seen below; thes e inductance values were determined using circuit optimization. Figures 37 and 38 show the return loss and insertion loss comparisons between the model and measured data, respectively. H W t W t W L 1 ln 5592 4 052 18 3093 3 0649 5559 1 6186 6 ln 3093 3 10 2 13(10)

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45 H W t W t W L 1 ln 2607 4545 2 625 1 0571 2941 0 25 3 ln 625 1 10 2 23(11) Where W= width of the input li ne in mm, H= thickness of th e substrate in mm, t= metal thickness in mm. Model Reference Plane CapacitorMeasurement Reference Plane Capacitor ADS Inductor L=L2 ADS Inductor L=21 Port 2 Port 1 MTEE W1=PADW W2=PADL W3=PADW MSUB=MSUB1 ADS Inductor L=L1 `USF Capacitor Model MSUB=MSUB1 S1P File File name=Via MLIN W1=PADW L=NEG_PADL MSUB=MSUB1 Figure 36 – a) Set #5 Layout, b) Set #5 Schematic.

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46 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Magnitude S11 Measured Magnitude Figure 37 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #5 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Magnitude S21 Measured Magnitude Figure 38 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #5 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate.

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47 3.5.2.3 Set #6 and Set #7 Set #6 and Set #7 are shunt tri-input conn ections with one input line on the width side of the bond pad and the other input lin e on the length side (see Figure 37a). The input of this model has a step in width at th e input to the “Tee” junction and on the output of the “Tee” junction there is a microstrip line element with a negative line length and series inductance. The equation for the series inductance (L1) (9) in nH can be seen below; these values were optimized to measur ed data. Figures 40 and 41 show the return loss and insertion loss comparisons between the model and measured data, respectively. H W t W t W L 1 ln 6552 1 5551 6 5837 3 0586 4056 0 1674 7 ln 5837 3 10 2 13(12) Where W= width of the input li ne in mm, H= thickness of th e substrate in mm, t= metal thickness in mm. Model Reference Plane Measurement Reference Plane Capacitor Figure 39 – a) Set #6 and Set #7 Layout b) Set #6 and Set #7 Schematic. Port 1 MTEE W1=PADW W2=PADL W3=PADW MSUB=MSUB1 MSTEP W1=PADW W2=LINEW MSUB=MSUB1 ADS Inductor L=L1 `USF Capacitor Model MSUB=MSUB1 S1P File File name=Via MLIN W1=PADW L=NEG_PADL MSUB=MSUB1 Port 2 MSTEP W1=PADW W2=LINEW MSUB=MSUB1

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48 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -45 -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Magnitude S11 Measured Magnitude Figure 40 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #6 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -140 -120 -100 -80 -60 -40 -20 0 20 40P h a s e ( d e g ) Legend S21 Model Magnitude S21 Measured Magnitude S21 Model Phase S21 Measured Phase Figure 41 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #6 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate.

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49 3.5.3 Quad Input Shunt Connections The four input shunt connection pad stack s are sets 8, 9 and 10. Set #10 is the same structure as set #9 except it is set up for an SOLR calibrati on. All the four-input connections can be modeled with a crossjunction element (MCROS in Series IV and MCROSO in ADS) or cross-junction lumped element equivalent circuit. The cross junction element gives an accurate respons e but the 0805 pad dimensions violate the Series IV and ADS element parameters on th e 5mil and 14mil substrate thicknesses, and an error is reported during simulations. Due to this error a lumped element equivalent circuit was developed (see Figure 42). The lump ed element equivalent circuit consists of shunt capacitors (C1) and series inductances parameters (L1, L2 and L3) these values are derived from the dimensions of the pad st ack (8) and are listed below. Since the pad dimension is rectangular, the inductance and capacitance of the two pad width sides and two pad length sides are equal. Like the “T ee” junction model, a microstrip line element with the width of the bond pad and a length the negative length of the bond pad is placed between the cross junction and the capacitor model to negate the effects of the bond pad that was integrated into the or iginal capacitor model. The via data and load data used in the model were measured for the corresponding substrate thickness. 4 * 19 9 0 9 9 0 eff effZ Z C C (13) 1 3 3122 log*86.6*30.9367 12121 *2401.5**1* 2 1000 22 74130 WWW HHH WWWW C W HHH WW H HH (14)

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50 1000 1 3 2 32 2 8 11 2 2 31 2 6 165 1 12 3 2H H W H W H W H W H W H W L (15) 1000 2 3 1 32 1 8 11 1 2 31 1 6 165 2 22 3 2H H W H W H W H W H W H W L (16) 1000 1 5 1 2 cos 2 5 2 1 1 7 1 5 337 3 H H W H W H W H W L (17) Model Reference Plane Measurement Reference Plane Via to Ground Capacitor Figure 42 – Set #6 and Set #7 Layout.

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51 ADS Capacitor C=C1 ADS Capacitor C=C1 ADS Inductor L=L1 ADS Inductor L=L1 Port 3 Port 1 ADS Inductor L=L3 ADS Capacitor C=C1 ADS Capacitor C=C1 ADS Inductor L=L2 ADS Inductor L=L2 Port 4 Port 2 Figure 43 – Cross Junction Lumped Element Schematic. 3.5.3.1 Set #8 Set #8 is a shunt four-input connection with inputs on all four sides. A 50 Ohm load was connected on a “width” side of th e pad (see Figure 44a). Figures 45 and 46 show the return loss and insertion loss co mparisons between the model and measured data, respectively.

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52 Model Reference Plane 50 ohm CapacitorMeasurement Reference Plane Via to Ground Via to Ground Figure 44 – a) Set #8 Layout, b) Set #8 Schematic. Port 2 Port 1 USF Capacitor Model MSUB=MSUB1 S1P File File name=Via MLIN W1=PADW L=NEG_PADL MSUB=MSUB1 MLIN W1=LINEW2 L=LINEL2 MSUB=MSUB1 MSTEP W1=PADL W2=LINEW1 MSUB=MSUB1 MSTEP W1=PADL W2=LINEW3 MSUB=MSUB1 Custom Cross W1=PADL W2=PADW W3=PADL MSUB=MSUB1 MSTEP W1=PADW W2=LINEW MSUB=MSUB1 S1P File File name= 50 Ohm Load

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53 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -12 -10 -8 -6 -4 -2 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11Measured Phase Figure 45 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #8 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -140 -120 -100 -80 -60 -40 -20 0 20 40P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11Measured Phase Figure 46 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #8 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate.

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54 3.5.3.2 Set #9 and Set #10 Set #9 and Set #10 are shunt four-input s hunt connection with inputs on all four sides, but in this case a load is attached to a pad length side. (F igure 47). Figures 48 and 49 show the return loss and inserti on loss comparisons between the model and measured data, respectively. Model Reference Plane Measurement Reference Plane 50 Ohm Capacitor Figure 47 a) Set #6 and Set #7 Layout b) Set #6 and Set #7 Schematic. Port 2 Port 1 USF Capacitor Model MSUB=MSUB1 S1P File File name=Via MLIN W1=PADW L=NEG_PADL MSUB=MSUB1 MSTEP W1=PADL W2=LINEW1 MSUB=MSUB1 MSTEP W1=PADL W2=LINEW3 MSUB=MSUB1 Custom Cross W1=PADL W2=PADW W3=PADL MSUB=MSUB1 MSTEP W1=PADW W2=LINEW MSUB=MSUB1 S1P File File name= 50 Ohm Load MLIN W1=LINEW3 L=LINEL3 MSUB=MSUB1

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55 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -12 -10 -8 -6 -4 -2 0M a g n i t u d e ( d B ) -200 -150 -100 -50 0 50 100 150 200P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11Measured Phase Figure 48 – Return Loss (S11) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #9 Pad Stack Model with U SF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate. 0 1 2 3 4 5 6 7 8 9Frequency (GHz) -40 -35 -30 -25 -20 -15 -10 -5 0M a g n i t u d e ( d B ) -140 -120 -100 -80 -60 -40 -20 0 20 40P h a s e ( d e g ) Legend S11 Model Magnitude S11 Measured Magnitude S11 Model Phase S11Measured Phase Figure 49 – Insertion Loss (S21) Magnitude (dB) and Phase (deg) Comparison of Simulated Set #10 Pad Stack Model with USF Capacitor 2113740A10 to Measured Data on 31mil FR4 Substrate.

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56 3.6 Conclusions This study shows how pad stack configur ations can be modeled. These models consist primarily of microstrip elements, but when such elements were not available or inadequate, equivalent lumped element designs were developed. It was demonstrated that the models give an accurate response from 0.05-9GHz.

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57 Chapter 4 Conclusions and Recommendations The planar spiral inductor modeling and pad stack parasitic modeling studies are good starting points for further research. The planar spiral modeli ng techniques did not work as anticipated but that theory is sound and could benefit some other types of component modeling. One recommendation for th e planar spiral induc tor modeling is to have the measurement reference plane on the same substrate was the inductor. Not having the reference plane on the second substrate will add extra measurement time, but it should clear up some of the measurement ambi guity. The pad stack parasitic models have been developed for 0805 capacitor models. Furthe r studies using different pad stack sizes (such as 0201, 0402, 0603 and 1206) and differe nt surface mounted el ements (resistors and inductors) could be done.

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58 References (1) Zang, Q. L. Neural Networks for RF and Microwave Design, Boston: Artech House, 2000. (2) Remke, R.L. and Burdick, G.A. Spiral Inductors for Hy brid and Microwave Applications, Proc. 24th Electron Components Conference, Washington, D.C., May 1974, pp. 152-161. (3) Tippet, J.C. and Spaecaile R.A., A rigorous technique for measuring the scattering matrix of a multiport de vice with a 2-port network analyzer, IEEE Trans. Microwave Theory and Tech., vol. 30, no. 5, pp. 661-666, May 1982. (4) Pozar, D. M. Microwave Engineering ,New York: John Wiley & Sons, 1998. (5) Ulaby, F. A. Applied Electromagnetics, New Jersey: Prentice Hall, 1997. (6) Basu, S. and Hayden, L. An SOLR Calibration for Accurate Measurement of Orthogonal On-wafer DUTs, IEEE MTT-S Digest, pp. 1335-1338, 1997. (7) Lakshminarayanan, B. Development of Equivalent Circuit Models for Surface Mount Multi-layer Capacitor, Tampa: University of South Florida, 1999. (8) Gupta, K. C. Microstrip Lines and Slotlines, Boston: Artech House, 1996. (9) Wadell, B. C. Transmission Line Design Handbook, MA: Artech House, Inc., 1991.

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59 Appendices

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60 Appendix A: Equations for Calculating I nductance of a Planar Spiral Inductor The equations and formulas were used to calculate the approximant inductances seen in Table 1. The inductance values were solved for in MathCAD software. These equations were obtained from a paper by G. Burkett (2), but were modified for the calculating the inductance from the outer radius instead of the inner radius. So the input went from the inner radius, the number of turn s, the line width, and the line spacing to the outer radius, the number of turns, th e line width, and the line spacing. rorinSWW (18) Was replace with: rironSWW 2rori a (19) crori (20) 220.8 6.010na Ind ac (21) Where ri is the inner radius, ro is the outer radius, W is the wid th of the line, S is the line spacing, N is the number of turns, and the i nductance (Ind) is in nH. All the dimensions are in mils.