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Fault tolerant design verification through the use of laser fault injection

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Fault tolerant design verification through the use of laser fault injection
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Wiley, Paris D
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upset
FPGA
event
single
latchup
radiation
Dissertations, Academic -- Electrical Engineering -- Masters -- USF   ( lcsh )
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government publication (state, provincial, terriorial, dependent)   ( marcgt )
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Abstract:
ABSTRACT: Laser Fault Injection (LFI) testing has been demonstrated to be a useful tool in the prediction of single event upset rates in microcircuits. In addition LFI has contributed to the basic understanding of the mechanisms that cause single event upsets. However, very little research has been performed on the viability of LFI as a tool for verifying fault tolerant designs incorporated in ASICs, FPGAs, microprocessors and embedded systems. Current fault tolerant design verification techniques such as simulation and test have several significant limitations that prevent the complete verification of a fault tolerant design. However, LFI possesses spatial, temporal and financial advantages related to its use, which are very beneficial. This thesis presents results of the fault tolerance verification tests that were performed using laser fault injection on a four-bit fault tolerant filter that was implemented in a commercial FPGA.
Thesis:
Thesis (M.S.E.E.)--University of South Florida, 2004.
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Includes bibliographical references.
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by Paris D. Wiley.
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Fault Tolerant Design Verification Through The Use of Laser Fault Injection by Paris D. Wiley A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Wilfrido Moreno, Ph.D. Fernando Falquez Ph.D. John Samson, Jr., Ph.D. Date of Approval: February 27, 2004 Keywords: Radiation, Latchup, Single, Event, Upset, FPGA Copyright 2004, Paris D. Wiley

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Acknowledgments I would like to take this opportunity to thank my major professor, Dr. Wilfrido Moreno, of the Department of Electrical Engineering, for his help and advice throughout this endeavor. Additionally, I would like to thank Drs. Andy Falquez and John Samson for introducing me to the concept of laser fault injection as well as informing me of the research opportunity that existed with Dr. Moreno in the Laser Restructuring Laboratory. Finally, I would like to thank Joan Tesch, of Honeywell, for her assistance with the Actel tools needed to design, simulate and synthesize the FPGA that was used as the test vehicle.

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i Table of Contents List of Tables ................................ ................................ ................................ ..................... iii List of Figures ................................ ................................ ................................ .................... iv Acronyms and Abbreviations ................................ ................................ .............................. v Abstract ................................ ................................ ................................ .............................. vi Chapter 1 Introduction ................................ ................................ ................................ ....... 1 1.1 Single Event Effects in Semiconductors ................................ ............................ 1 1.1.1 Single Event Transients ................................ ................................ ...... 2 1.1.2 Single Event Upsets ................................ ................................ ............ 3 1.1.3 Single Event Latchups ................................ ................................ ........ 5 1.2 Fault Tolerance Verification ................................ ................................ .............. 7 1.2.1 Analysis ................................ ................................ ............................... 7 1.2.2 Simulation ................................ ................................ ........................... 8 1.2.3 Test ................................ ................................ ................................ ...... 9 1.2.3.1 Heavy Ion Facilities ................................ ............................. 9 1.2.3.2 Laser Fault Injection ................................ .......................... 11 Chapter 2 Laser Fault Injection Background ................................ ................................ .. 12 2.1 Laser Fault Injection Benefits ................................ ................................ .......... 12 2.2 Disadvantages of Laser Fault Injection ................................ ............................ 13 2.3 Laser Theory ................................ ................................ ................................ .... 15 Chapter 3 Experimental Details ................................ ................................ ...................... 17 3.1 Objective ................................ ................................ ................................ .......... 17 3.2 Part Selection ................................ ................................ ................................ ... 17 3.3 Filter Design ................................ ................................ ................................ ..... 18 3.4 Filter Simulation ................................ ................................ .............................. 20 3.5 Filter Layout ................................ ................................ ................................ ..... 20 3.6 Test Sample Delidding ................................ ................................ ................... 22 3.7 Test Facility ................................ ................................ ................................ ..... 23 3.8 Test Equipment ................................ ................................ ................................ 24 3.9 Test Software ................................ ................................ ................................ ... 25 3.10 Test Board ................................ ................................ ................................ ...... 25 3.11 Test Setup Verification ................................ ................................ .................. 27 3.12 Origin Selection ................................ ................................ ............................. 28

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ii 3.13 Upset Threshold Determination ................................ ................................ ..... 28 3.14 Exposure Location Determination ................................ ................................ 29 3.15 Test Procedure ................................ ................................ ............................... 30 Chapter 4 Experiment Results ................................ ................................ ........................ 32 4.1 Word A Bit 2 ................................ ................................ ................................ .... 33 4.1.1 Word A Bit 2 Procedure ................................ ................................ ... 34 4.1.2 Word A Bit 2 Summary ................................ ................................ .... 38 4.2 Word B Bit 2 ................................ ................................ ................................ .... 39 4.2.1 Word B Bit 2 Procedure ................................ ................................ .... 40 4.2.2 Word B Bit 2 Summary ................................ ................................ .... 43 4.3 Word C Bit 2 ................................ ................................ ................................ .... 44 4.3.1 Word C Bit 2 Procedure ................................ ................................ .... 45 4.3.2 Word C Bit 2 Summary ................................ ................................ .... 46 4.4 Word FT Bit 2 ................................ ................................ ................................ .. 46 4.4.1 Word FT Bit 2 Procedure ................................ ................................ .. 48 4.4.2 Word FT Bit 2 Summ ary ................................ ................................ .. 48 4.5 Other Injection Locations ................................ ................................ ................ 49 Chapter 5 Issues Observed/Future Work ................................ ................................ ........ 50 5.1 Latchup Sensitivity Determination ................................ ................................ .. 50 5.2 Frequency Doubler ................................ ................................ ........................... 51 5.3 Critical Cell Location Determination ................................ ............................... 51 5.4 Back Side Die Lapping ................................ ................................ .................... 52 Chapter 6 Conclusion ................................ ................................ ................................ ...... 53 References ................................ ................................ ................................ .......................... 55 Appendices ................................ ................................ ................................ ......................... 57 Appendix A Fault Tolerant FPGA VHDL Code ................................ ................ 58 Appendix B LabWindows Test Software Code ................................ ............... 62

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iii List of Tables Table 1. Test Setup Characterization Results ................................ ................................ ... 28 Table 2. Word A Bit 2 Upset Results with Expected Output = 0000 ............................... 36 Table 3. Word A Bit 2 Upset Results with Expected Output = 1111 ............................... 37 Table 4. Word A Bit 2 Latchup Results with Decreasing Power ................................ ..... 38 Table 5. Word B Bit 2 Upset Results with Expected Output = 0000 ............................... 41 Table 6. Word B Bit 2 Upset Results with Expected Output = 1111 ............................... 42 Table 7. Word B Bit 2 Latchup Results with Decreasing Power ................................ ...... 43

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iv List of Figures Figure 1. Single Event Transient in a Two-Input AND Gate ................................ ............. 3 Figure 2. Six-Transistor SRAM Cell Sensitive Upset Regions ................................ .......... 4 Figure 3. Single Event Upset in a Synchronous Two-Input AND Gate ............................. 5 Figure 4. Typical Bulk CMOS Structure Detailing the SCR Transistors ........................... 6 Figure 5. Bulk CMOS SCR Equivalent Circuits ................................ ................................ 6 Figure 6. Charge Collection Differences between Lasers and Heavy Ions ...................... 14 Figure 7. Fault Tolerant Filter Block Diagram ................................ ................................ 19 Figure 8. Fault Tolerant Filter Pinout ................................ ................................ ............... 21 Figure 9. Fault Tolerant Filter Cell Used ................................ ................................ .......... 22 Figure 10. De-lidded Fault Tolerant FPGA Test Sample ................................ ................. 22 Figure 11. Detailed Layout of the Fault Tolerant FPGA Test Board ............................... 27 Figure 12. Fault Tolerant FPGA Origin Designation ................................ ....................... 29 Figure 13. Test Procedure Block Diagram ................................ ................................ ....... 31 Figure 14. Exceed Diagram Showing the Location of Word A Bit 2 ............................... 33 Figure 15. Estimate of Physical Location of Word A Bit 2 ................................ .............. 34 Figure 16. Word A Bit 2 Upset Results with Expected Output = 0000 ............................ 36 Figure 17. Word A Bit 2 Upset Results with Expected Output = 1111 ............................ 37 Figure 18. Exceed Diagram Showing the Location of Word B Bit 2 ............................... 39 Figure 19. Estimate of Physical Location of Word B Bit 2 ................................ .............. 40 Figure 20. Word B Bit 2 Upset Results with Expected Output = 0000 ............................ 42 Figure 21. Word B Bit 2 Upset Results with Expected Output = 1111 ............................ 43 Figure 22. Exceed Diagram Showing the Location of Word C Bit 2 ............................... 44 Figure 23. Estimate of Physical Location of Word C Bit 2 ................................ .............. 45 Figure 24. Exceed Diagram Showing the Location of Word FT Bit 2 ............................. 47 Figure 25. Estimate of the Physical Location of Word FT Bit 2 ................................ ...... 47

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v Acronyms and Abbreviations ASIC Application Specific Integrated Circuit CMOS Complementary Metal Oxide Semiconductor DRAM Dynamic Random Access Memory EDAC Error Detection and Correction EMI Electromagnetic Interference EPI Epitaxial FPGA Field Programmable Gate Array GPIB General Purpose Instrumentation Bus I/O Input/Output IDC Insulation Displacement Connector LED Light Emitting Diode LFI Laser Fault Injection LRL Laser Restructuring Laboratory Nd:YAG Neodymium:Yttrium-Aluminum-Garnet SCR Silicon-Controlled Rectifier SEL Single Event Latchup SEU Single Event Upset SOI Silicon on Insulator SRAM Static Random Access Memory VHDL VHSIC Hardware Description Language VHSIC Very High Speed Integrated Circuit

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vi Fault Tolerant Design Verification Through The Use of Laser Fault Injection Paris D. Wiley ABSTRACT Laser Fault Injection (LFI) testing has been demonstrated to be a useful tool in the prediction of single event upset rates in microcircuits. In addition LFI has contributed to the basic understanding of the mechanisms that cause single event upsets. However, very little research has been performed on the viability of LFI as a tool for verifying fault tolerant designs incorporated in ASICs, FPGAs, microprocessors and embedded systems. Current fault tolerant design verification techniques such as simulation and test have several significant limitations that prevent the complete verification of a fault tolerant design. However, LFI possesses spatial, temporal and financial advantages related to its use, which are very beneficial. This thesis presents results of the fault tolerance verification tests that were performed using laser fault injection on a four-bit fault tolerant filter that was implemented in a commercial FPGA.

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1 Chapter 1 Introduction Decreasing feature sizes, decreasing operating voltages and increasing operating speeds of todays microcircuits have led to a new issue that must be dealt with in the electrical design process: the single event fault. A single event fault, in an electronic device, is a condition where an outside stimulus causes the microcircuit to cease operation in a predictable and controllable manner. This type of error is not caused by a defect in the production of the microcircuit or an error in the implementation of the devices design. A single event fault is created by the microcircuits physical environment. Stray electric fields, random Electrical Magnetic Interference (EMI) gamma radiation and high-energy charged particles have been shown to change the logical state of digital components by depositing sufficient energy in a microcircuits sensitive region to increase or decrease the associated logics voltage beyond the technologys threshold [1]. 1.1 Single Event Effects in Semiconductors Single event faults in semiconductors are categorized with respect to their duration as transients, upsets or latchups. Each of the fault types creates its own unique impact on system performance and requires a specific method for verification and

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2 correction. Additionally, each of these categories has several sub-types such as multiple bit upsets, stuck bits and Single Event Functional Interrupt (SEFI). 1.1.1 Single Event Transients Single Event Transients (SET) are momentary voltage excursions that temporarily affect the operating characteristics of electronic components. Although these transients usually subside within a few microseconds, after the inducing phenomenon disappears, they may be mistaken as a signals transition by edge triggered logic and cause an unintended reaction. Additionally, these transients may be captured by memory cells or registers and stored if they exceed the voltage threshold for the device or occur on the devices input pins and coincide with the devices control signals. Once stored, the transient or faulty condition will remain indefinitely within the memory device even when the transient condition returns to its normal state. As the operating frequencies of processors, memories and data buses continue to increase, so does the probability that single event transients, within these devices or at the devices interfaces, will be captured during a processing cycle and become an upset. In fact, several studies have shown that the ratio of single event transients, which are captured and stored in memory devices as single event upsets, increases linearly with clock frequency. The ratio reaches a maximum probability whenever the clock cycle duration is less than or equal to the transient duration [2]. When such conditions exist all transients will occur during an active clock edge and all that exceed the technologys voltage threshold will be stored as upsets. An example of a single event transient in a two-input AND gate and its affect on the output of the device is presented in Figure 1.

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3 Figure 1. Single Event Transient in a Two-Input AND Gate 1.1.2 Single Event Upsets A Single Event Upset (SEU) differs from a single event transient in that the change to the logical state of a memory cell or flip-flop does not return to normal once the excitation subsides. Single event upsets may be caused by a transient that was on a data bus and is subsequently stored during a read cycle or it may be caused by a transient inside the memory cell itself. These upsets are not permanent but may cause a processor or memory device to cease functioning properly if they occur in the control portion of the device or may generate an erroneous data value which may lead to errors in execution. Many devices that are designed for high reliability applications incorporate the use of Error Detection and Correction (EDAC) to periodically check memory elements for upsets. If an upset is found, the correct information is re-written to the memory device before the altered bit causes a system failure. A schematic detailing the sensitive upset A B C=A B A B C C 1 0 1 0 1 0 Expected 1 0 Actual Transient

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4 regions in a six-transistor memory cell is presented in Figure 2 and an example of an upset in a synchronous two-input AND gate is presented in Figure 3. Figure 2. Six-Transistor SRAM Cell Sensitive Upset Regions V DD V SS R G RG p 1 (OFF) p 2 (ON) n 1 (ON) n 2 (OFF) Sensitive Junction Sensitive Junction

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5 Figure 3. Single Event Upset in a Synchronous Two-Input AND Gate 1.1.3 Single Event Latchups Single Event Latchups (SEL) are the most serious of the single event phenomenon since they possess the potential to permanently damage a device and render the system useless. The four-layer parasitic transistors that exist in CMOS designs are responsible for SEL. These parasitic transistors form a silicon-controlled rectifier (SCR) which can be triggered if the current generated from an ion strike forward biases the device. Figure 4 illustrates the parasitic transistors that are present in a typical CMOS process while Figure 5 presents the equivalent circuits for the SCR. A B C=A B A B CLK C C 1 0 1 0 1 0 1 0 Expected 1 0 Actual Clock Input Transient

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6 Figure 4. Typical Bulk CMOS Structure Detailing the SCR Transistors Figure 5. Bulk CMOS SCR Equivalent Circuits +V S -V S + V1 + V2 V V A RL P N P N J1 J2 J3 n+ p+ n+ p+ p-Well n + Substrate V SS V DD

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7 Once the SCR has been triggered the resistance between the power supply and ground decreases significantly. The decrease in resistance between the power supply and ground is usually to the point where a pseudo-short exists between them. This pseudoshort causes a substantial increase in the devices supply current, which frequently results in the microcircuit being destroyed. Device destruction is due to either heat damaging the silicon substrate or a bond wire fusing open as a result of the excessive current. 1.2 Fault Tolerance Verification Due to the errors that can be induced in a microcircuit by the environment in which it operates many designers, in areas such as communications, bio-medical and space applications, must incorporate fault-tolerant techniques in designs to maintain the integrity and performance of the system. However, once a fault tolerant design has been completed the verification process is usually very difficult due to current limitations in the traditional types of verification. The traditional types of verification are analysis, simulation and test. 1.2.1 Analysis Analysis is usually the most difficult method that can be applied in order to verify fault tolerance in a design. Difficulties result since modeling an actual system is very difficult and the mechanisms involved in the fault activation and in the error propagation process are highly complex and are not fully understood in most cases [3]. Knowledge of specific details about a devices manufacturing process, such as transistor feature size, diffusion depth and silicon doping level allows for an estimation of the amount of charge

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8 an ion or noise source will deposit in a devices critical area to be calculated. A prediction of the potential rate of upset can be made once the deposited charge is known and compared to the critical charge needed to alter a memory element. However, such microcircuit processing information is often very difficult to obtain, especially for commercial parts, since most manufacturers consider such manufacturing information to be proprietary. Additionally, deposited charge calculations often require numerous assumptions that may limit the accuracy of the results to an order of magnitude estimation. 1.2.2 Simulation Simulation is the most common approach utilized for the verification of fault tolerant designs. This verification method incorporates the use of a software test bench to model and predict the effects of a single event upset based on the response of the systems internal components. Development of a fault tolerant simulation test bench is often a very time consuming process since a typical design may consist of numerous internal components and the generation and verification of an upset model of each one may require significant resources. For most systems, the total required generation and validation effort is too massive and usually results in truncation of the effort to known critical elements. Several commercially available software tools are available to aid the simulation design verification effort.

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9 1.2.3 Test The final method employed to validate a fault tolerant design is to test the device in an environment that will cause an upset. Several types of facilities are used for this type of testing. Such facilities include heavy ion facilities, electromagnetic interference laboratories and laser laboratories. Each type of facility possesses its own advantages and disadvantages. 1.2.3.1 Heavy Ion Facilities When testing at a heavy ion facility, a particle accelerator is used to first strip electrons from neutrally charged particles and then accelerates the remaining ions towards the device under test. This test method best simulates the effects of a device operating in a space environment since the ion and its associated effects are virtually identical to what is observed in space. However, this test method has several significant drawbacks that limit its effectiveness in validating a complete fault tolerant design. The first drawback of using a particle accelerator, to verify a fault tolerant design, is that the charged particles cannot be targeted to strike a specific logic cell since the ion beam diameter cannot be focused below a few centimeters. Therefore, even if a designer or test engineer knows the physical location of the most critical element in a design it is often difficult, if not impossible, to individually target critical locations since most critical elements occupy an area of less than a few square microns and are surrounded by numerous other active elements. A second drawback to using this test method, to verify a fault tolerant design, is that the ion beam cannot be timed to coincide with a specific clock cycle such as a read from memory or a write to memory. This limitation arises due

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10 to the requirement to physically maneuver a large lead plug in order to affect beam control. Since beam control is a mechanical act it takes up to one second to complete. Such a time frame is orders of magnitude longer than required to accurately time the beam to most clock edges. Most clock edges typically operate in the megahertz or gigahertz frequency range. A third drawback to this validation method is that particle accelerator facilities are very expensive to use and require a significant amount of effort to adapt the test setup to the facilitys test fixtures. Typical rates for these facilities range from $600/hr to over $2500/hr and a typical test development cycle can exceed three months. Additionally, these facilities often require the test device to be operated in a vacuum in order to eliminate the beam degradation that occurs in air. This results in a requirement to develop a signal interface for the vacuum chamber. In addition, operation in a vacuum usually requires the design of a special cooling method for the microcircuit since the lack of air limits the cooling that is typically accomplished through convection. Another drawback to this verification approach is that there are only a few particle accelerator facilities located within the United States. Since numerous corporations and physics experiments compete for their availability they often have a three to six month waiting list. This may not be a significant issue for most testing efforts since the development time often exceeds the three to six months required for scheduling. However, if problems in the development process cause the scheduled test date to be missed, even by a few days, the next available test date may often be months away.

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11 1.2.3.2 Laser Fault Injection Laser fault injection does not suffer from the limitations encountered in the use of heavy ion facilities. Since the laser beam diameter can be focused down to the width of a single storage element it allows the tester to select a single critical area of the chip and test it directly. Thus, the effects of an upset in an individual element can be determined independently of the sensitivity of other adjacently located areas. Additionally, since the laser can be turned on and off by solid state circuitry, instead of the mechanical insertion of a beam plug, it can be timed with high-speed clock edges and specific vector lines in a test pattern. Another benefit of using laser fault injection to verify fault tolerant designs is that this test method is fairly inexpensive. Typical laser test setups cost a few hundred thousand dollars and can be performed in the open air. Although there are not a significant number of laser facilities in the United States, that have the capability to perform this type of verification testing, their waiting lists are usually small since they are not usually used by most corporations and physics researchers. The Laser Fault Injection verification technique provides a method for the complete verification of a fault tolerant FPGA and makes FPGAs a more critical element in the development process of fault-tolerant ASICs.

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12 Chapter 2 Laser Fault Injection Background The first published reports of incorporating the use of a laser to simulate the effects of ionizing radiation were made in 1965 [4]. However, the use of laser fault injection for the testing and verification of soft errors in electronic devices is a relatively new development. The delay in the utilization of lasers to simulate these effects in microelectronics was partially due to the fact that the first confirmed and published reports of single event upsets in spacecraft electronics was not made until 1975 [5]. Since then, significant research has been performed in the area of laser fault injection, which has resulted in numerous device types being successfully tested. Several devices that were successfully tested using laser fault injection techniques are radiation hardened microprocessors [6], DRAMs [7] and SRAMs [1] as well as numerous analog components such as op-amps and voltage comparators [8]. 2.1 Laser Fault Injection Benefits The most significant benefit associated with the use of laser fault injection in the testing of microcircuits is the ability to concentrate the lasers charge collection area in a repeatable location at a precise time, which is limited by the precision of the laser equipment itself. Such spatial and temporal precision cannot be obtained with most other

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13 single event upset test apparatus [15]. The typical accuracy of todays LFI test setups approach exposure sizes of less than 1 m m in diameter with X-Y-Z axis precision of 0.1 m m or better. Accurate compact exposure size coupled with lateral positioning accuracy allow the laser beam diameter and positioning to be on the same order of magnitude as the feature size of many commercial microcircuits. However, the lasers diameter is still approximately 10 times larger than the diameter of a charge track induced by a heavy ion. Another significant benefit of using laser fault injection in single event testing is the significantly reduced cost required to perform a test versus what is required at facilities that offer heavy ion beams. As described previously, the cost associated with performing laser fault injection testing can be significantly less than the cost associated with performing a similar test at a cyclotron facility. 2.2 Disadvantages of Laser Fault Injection Although laser fault injection possesses the benefit of positioning and timing, it suffers from several significant disadvantages when compared to other single event test methods. Primarily, it is difficult, if not impossible, to concentrate the laser under a metalization layer due to the metals reflective nature [10]. For newer devices, such as FPGAs and microprocessors that have three or more metalization layers, a majority of a devices sensitive regions can be physically covered and thus inaccessible to the laser. Research is currently being undertaken to resolve the metalization issue by either thinning the backside of the dies silicon substrate and exposing the device from the bottom [9-10] or de-focusing the laser so that it converges under the metalization layer.

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14 A second issue with using a laser to inject faults in microcircuits is that the charge collection profile is different than is observed with heavy ions [11,12]. Since heavy ions that exist in outer space can have energies in excess of 1 GeV, they penetrate the entire part and package with very little reduction in energy, thus depositing charge in a linear fashion along the ions path. This charge deposition remains fairly linear until the ion reaches the Bragg peak where its velocity has slowed to the point that it begins to stop. A laser on the other hand collects charge very near the dies surface and decreases exponentially with distance traveled. This effect is magnified if the lasers wavelength is not optimized for the silicons doping level and surface roughness [10]. A diagram illustrating the difference in charge collection profiles between a laser and a heavy ion is shown in Figure 6. Figure 6. Charge Collection Differences between Lasers and Heavy Ions The difference in these two charge collection profiles may result in a significant variation in upset and latchup test results even if both test methods deposit an equivalent amount of charge into the devices substrate. Additionally, upset and latchup rate calculations may not correlate if laser fault injection test results are used to estimate the Laser Ion

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15 single event upset rate for a device in a heavy ion environment. This is especially true if the laser used does not have a wavelength optimized for the specific material or if the pulse length of the laser is not short compared to the charge collection time in the depletion and funneling region. For example, many of todays complex and high speed microcircuits decrease their power consumption by incorporating the use of either an epitaxial, epi, layer or an insulation layer, such as SOI, to help minimize the amount of leakage current that is observed through the substrate of the device. The effect of these layers is to electrically isolate the top of the substrate from the area below the substrate, thus limiting the amount of generated charge that can migrate to the surface due to the presence of electric fields. 2.3 Laser Theory A laser operates by injecting current into a forward biased p-n junction, which creates pairs of free electrons and holes. Light is emitted when the electrons and holes combine. The emitted light, for low levels of current, is incoherent since the recombination of the electrons and holes is random. However, if the current injected is sufficiently large a condition called population inversion is achieved. During population inversion an incoming photon is more likely to stimulate the coherent emission of another photon than to be absorbed, which results in optical gain. If the p-n junction is combined with an optical cavity, which reflects some of the light back into the p-n junction and the associated gain is larger than the losses that exist in the laser cavity, then lasing occurs [14]. Lased light radiates from the source until it impinges on a solid material and begins to diffuse.

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16 With respect to laser fault injection testing, most laser work has assumed that the light is absorbed by a fundamental band-to-band absorption process, producing ionization by exciting carriers from the valence to the conduction band, [16]. As the light penetrates the silicon material of the semiconductor, each absorbed photon is assumed to produce a single electron-hole pair. The light is then absorbed exponentially with depth, as described by Beers Law: I = I o e a x with the absorption coefficient depending strongly on wavelength. [16]. For laser fault injection testing in silicon devices, it has been shown that the Nd :YAG laser ( l = 1.06 m m) is nearly ideal, with a penetration depth of about 700 m m, [16]. If the laser frequency is increased, through the use of a frequency doubler, the penetration depth is severely reduced and the charge collection area is limited to the surface. For example, at a wavelength of 590 nm the penetration depth of the laser decreases to approximately 2 m m, [15]. The reduction in penetration depth due to frequency doubling was of interest to this research since USFs Laser Restructuring Laboratory, (LRL), incorporates the use of a frequency doubler. However, since the focus of this research was to show that laser fault injection can produce repeatable upset in an FPGA and not to determine the upset rate in a heavy ion environment the use of the frequency doubler was deemed acceptable.

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17 Chapter 3 Experimental Details 3.1 Objective The objective of this research was to demonstrate that an upset could be induced, with repeatability and without causing permanent damage to the device, in a digital FPGA using laser fault injection. Similar work has been performed with processors and memory devices. However, the use of laser fault injection to induce non-destructive faults in FPGAs and verify fault tolerant designs had not been accomplished nor attempted. The technique developed during this research provides ASIC designers and test engineers of fault tolerant ASICs and FPGAs a method to completely test designs before proceeding to chip layout. Once chip layout has commenced design changes can cost hundreds of thousands of dollars and add many months to the development schedule. 3.2 Part Selection The Actel 42MX FPGA was chosen due to the availability of the test devices as well as simulation and programming resources. This device is fabricated using a 0.45 micron triple-metal CMOS process and has 36,000 gates, 954 sequential logic modules, 912 combinatorial logic modules and 24 decode logic modules. This Actel FPGA has a

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18 row-based architecture and uses a one-time programmable anti-fuse technology. It is packaged in an 84-pin plastic leaded chip carrier with 21 pins per side. 3.3 Filter Design In order to determine if laser fault injection was a viable option for the verification of fault tolerant FPGAs a fault tolerant FPGA was designed. The decision was made to generate a fault tolerant filter that averaged between one and sixteen of the last 4-bit words that were provided as input. The VHDL code for the filter was written as a text file and then imported into ModelSim version 5.4e and simulated. However, when the design went to chip layout it exceeded, by an approximate factor of two, the number of available gates. Therefore, the decision was made to modify the filter design so that it always averaged the last four 4-bit words that were provided as input. This modification simply removed the ability to select the number of previous results to be averaged. The modified design was also written in a text file and imported into ModelSim version 5.4e and simulated. The VHDL code for the modified filter is presented in Appendix A. Once the code was written, it was simulated using generic delays and verified to be fully operational. A block diagram of the filter is presented in Figure 7.

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19 Figure 7. Fault Tolerant Filter Block Diagram As detailed in the block diagram of Figure 7, the fault tolerant filter is comprised of three separate filters. In addition, a two-out-of-three voting network compares the output of the three filters and produces the fault tolerant result. Each filter operates independently of the others. Therefore, if an error is encountered in one filter it does not affect the results of the other two. In this design, the voting network was produced from the same cell types as the three filters. Thus, an upset in the voting network will propagate to the fault tolerant output. However, in an actual fault tolerant design the voting network would be implemented using radiation hardened cells that do not upset when exposed to a high-energy particle environment. Radiation hardened cells are typically 5-10x larger in size, draw significantly more current and operate much slower than normal cells. Therefore, this architecture allows the maintenance of high processing capability in the filters while maintaining overall fault tolerance. Filter A Filter B Filter C 2 of 3 Majority Network Data In 4 Filtered Data Out 1 Miscompare Out 4 4 4 4 4 4 Word A out Word C out Word B out 4 Clock In

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20 One the rising edge of a clock cycle, each individual filter reads the single 4-bit input word and stores it in a unique set of registers while discarding the fifth most recent value. The filter averages the four most recent values that are stored in the registers. Upon completion of the averaging calculations, the two-out-of-three voting network compares the three individual results and outputs the value obtained from any two that agree. Additionally, each individual filters outputs were routed to output pins so that a determination could be made regarding the location and identity of the upset bit if a disagreement in comparisons occurred. In most actual designs, the routing of intermediate results to output pins would not be performed since it would require the use of significantly more input/output pins. However, in this research it provided the ability to determine if the upsets were being induced in the desired and predicted region. 3.4 Filter Simulation Once the filter was designed, it was verified using the ModelSim version 5.4e simulator. Numerous input sequences were simulated and the outputs verified to be correct for all cases. In order to speed up the simulation process, a script was generated to rapidly input all required clock and data inputs. This script made it possible to simulate a different sequence of input data in a few seconds instead of the minutes that were required to manually enter the necessary data for every clock cycle. 3.5 Filter Layout Once the filter design was adequately verified through simulation, the design was converted into gates using the Actel tool Designer. No restrictions were placed on the

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21 routing of the design and Actel tool Designer was allowed to select the I/O pins to which each signal would be routed. Actel tool Designer created a successful gate level design with no errors reported. The FPGAs pinout is presented in Figure 8 and a diagram depicting the internal logic cells that were used is presented in Figure 9. Figure 8. Fault Tolerant Filter Pinout

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22 Figure 9. Fault Tolerant Filter Cell Used Once the fuse file had been completed, the part was programmed using the Actel tool Silicon Sculptor. The programming of the test samples and the post-programming verification were performed by the manufacturer. 3.6 Test Sample Delidding In order for the laser to reach the dies surface and induce an upset the plastic package top was removed using a 90% sulfuric acid solution. The lid removal was accomplished by first x-raying the device in order to determine the location of the die within the package. Next, an outline of the die was scribed into the plastic to form a

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23 containment border for the acid solution. Afterwards the 90% sulfuric acid solution was poured onto the package and allowed to sit for approximately 1 minute. After completion of the sulfuric acid soak the device was rinsed using de-ionized water. The addition of the sulfuric acid and subsequent rinsing with de-ionized water was repeated until the die was completely exposed. The exposed die is presented in Figure 10. Figure 10. De-lidded Fault Tolerant FPGA Test Sample After completion of the lid removal process, the device was visually inspected for damage (such as possible breakage of bond wires) at 10x magnification and then verified to be fully operational using the test setup. 3.7 Test Facility The test facility used to perform this research was the Laser Restructuring Laboratory at the Nanomaterials and Nanomanufacturing Research Center located at the University of South Florida. This facility has a high precision 6-axis, x, y, z, x-tilt, y-tilt and x/y planar rotation, translation table with an x-y positioning accuracy of 0.1 microns.

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24 The use of Nd :YAG, Argon or Excimer lasers available. However, the only one that was used during this research was the double frequency Nd :YAG The laser used in this research had an output wavelength of 1046 nm, which was doubled to a wavelength of 523 nm through the use of a frequency doubler. The laser possessed a minimum power of 1 milliwatt and a maximum power of 2 watts. The laser was focused onto the die through the use of a series of mirrors and microscope objectives. Use of the optical components provided the capability to create a laser spot with a power intensity in excess of 6.0E11 watts/cm 2 The laser and positioning system could be controlled manually or through the use of a custom software package that was written by the Laser Restructuring Laboratory. 3.8 Test Equipment The FPGA was tested using a VXi test station that included a Racal 1261B VXI High Power Intelligent Mainframe, a Racal 3151 waveform generator, a Tektronix 4801 Switching Matrix and a Racal 6062 Digital Multimeter. The test setup was controlled using a standard Pentium tm 75 MHz computer equipped with the Microsoft Windows 95 tm operating system and a GPIB card equipped with custom LabWindows tm software. The equipment was borrowed from Honeywells Component Analysis and Test Center, (CATC), where it was used extensively in the testing of both analog and digital components. For this research, the only card that was used was the Tektronix 4801 Switching Matrix. The Switching Matrix card was used to provide the required input stimulus and to read and store of the FPGAs output.

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25 3.9 Test Software The test software was written using LabWindows and provided the stimulus needed to operate the device as well as to monitor the devices outputs during the exposure and determine if an error had occurred. The software has a user interface that allows the operator to enter up to 16 4-bit words at a time to be used as the FPGAs data input as well as start and stop controls for the FPGA clock. Once the software initiates the start of a test sequence it places the data from the first of the sixteen data cells on the FPGAs data bus and then clocks the FPGA. A few milliseconds later, the FPGA reads the FPGAs four output data busses and compares the data with the expected results. The output data is stored after each clock cycle regardless of the presence of upsets and/or latchups. If an error is detected, a pop-up window appears stating that an upset was detected and the program is halted until the error is acknowledged. Due to a lack of time and the fact that the goal of this research was to demonstrate that laser fault injection is a viable method for the verification of a fault tolerant design, the test software was not integrated with the laser control software. The X and Y coordinates of the exposure and the upset/latchup results were manually maintained in a log. The manually recorded data was used to correlate the upset results, which were stored in the data file, to the laser power that was used. 3.10 Test Board In order to test the device a custom two-layer printed wiring board was designed. A detailed layout of this board is presented in Figure 11. The wiring board was used to interface the device under test to both the laser table and the VXi test station. The

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26 interface to the VXi test station was implemented with a 64-pin Insulation Displacement Connector, (IDC ), that mounted to the test board. In addition to the VXi performing the verification of the data, two additional features were designed into the exposure board to aid in the determination of an upset. Sixteen light emitting diodes, ( LEDs), were incorporated on the board. The LEDs visually displayed the output state for each of the FPGAs four 4-bit output data buses. The addition of the LEDs made it easy to visually determine the output state of each bit. Three 74ACT520 8-bit identity comparators were incorporated so that each of the four output buses could be compared to the others. The outputs of each of these three devices was then logically ORed together. If any one of the four outputs was not equal to the others a separate LED was illuminated. A detailed layout of the fault tolerant FPGA test board is presented in Figure 11.

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27 Figure 11. Detailed Layout of the Fault Tolerant FPGA Test Board 3.11 Test Setup Verification The test setup was verified by exposing the de-lidded device to a strobe of light while the FPGA and associated software were operational. The outputs were recorded and compared to the LEDs to assure that the setup was working properly. This method is commonly used to test single event upset, SEU, setups since the lights ionizing radiation affects all of the chips diffusions that are close to the surface. For this test a Honeywell Strobonar 109 was used. The test was performed numerous times. Each time the strobe of light caused the part to upset and the software correctly stored the results. The test setup results are presented in Table 1.

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28 Table 1. Test Setup Characterization Results Exposure # Expected Output Channel A Output Channel B Output Channel C Output Fault Tolerant Output 1 1101 1101 00 0 0 1 0 0 0 1101 2 1101 0010 110 0 0 1 10 00 0 0 3 1101 1101 00 0 0 1 0 0 0 1101 4 1101 1101 00 0 0 110 0 1101 5 1101 1101 00 0 0 1 0 0 0 1101 3.12 Origin Selection In order for the test to yield repeatable results, an origin was defined to which all future locations could be referenced. After inspecting the die carefully with a microscope, the decision was made to use the center of the letter O that is located within the die markings that are located at the bottom left corner of the die, which was just below pin 33. A picture of the origin selected is presented in Figure 12. 3.13 Upset Threshold Determination Once the test setups operation was verified and an origin had been selected and programmed into the translation table control software the minimum laser power needed to induce an upset without causing permanent damage to the test FPGA devices was determined. This step was important since only 6 de-lidded test samples were available. Since the exact locations of specific gates were not known, the devices upset threshold was determined by exposing random die locations to relatively low-energy laser pulses of 500 milliwatts. After approximately 50 exposures, the laser power was increase by 20 milliwatts and the process continued until upsets were observed.

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29 Figure 12. Fault Tolerant FPGA Origin Designation The characterization results demonstrated that the devices upset threshold was approximately 0.62 milliwatts. Although upsets were observed at slightly lower power levels, a laser power of 0.62 milliwatts yielded an intensity that consistently caused upsets in the device at all sensitive locations without causing permanent damage. It was also determined during this experiment that the device was extremely latchup sensitive. 3.14 Exposure Location Determination All efforts to obtain the X-Y coordinates of critical cells by Actel failed. Afterwards the decision was made to try to determine the exposure locations by comparing the relative locations that were provided in the Actel tool Designer to the repeatable patterns that could be visually observed on the die. After examination, it appeared that the repeatable patterns observed on the die surface using a microscope Origin Origin

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30 correlated to the results of the Actel tool. Figure 8 discloses that there are 105 blocks horizontally, which are organized in groups of 2 sequential and 2 combinatorial with 1 combinatorial left over and 18 blocks vertically. This correlates well to microscope observations. Details of how each cell in the Actel representation of the FPGA was mapped to a physical location on the die are provided in Chapter 4. 3.15 Test Procedure The FPGA was exposed to the laser in a systematic manner that was designed to maximize the likelihood of observing an upset. From the estimated starting location, the X position was increased, between exposures, in 10-micron increments until 200 microns had been traversed. At this point, the Y position was increased in a single 10-micron increment. After the Y position increment the FPGA was exposed. Then the X position decreased, between exposures, in 10-micron increments until the original X position was reached. A block diagram detailing the test procedure used is presented in Figure 13.

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31 Figure 13. Test Procedure Block Diagram Select a Test Node Determine Approx. XY Coordinates Expose Chip Upsets Observed? Reset Test Equipment Decrease Step Size Increase X Coordinate X Coord at Min/Max? Change X Step Direction Increase Y Coordinate Y Coordinate at Max? End Test No No No Yes Yes Yes

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32 Chapter 4 Experiment Results Laser fault injection testing was performed on an Actel A42MX series FPGA. Four individual bits were targeted for upset. Actel was unable to provide precise coordinates for the cells containing these bits. Therefore, an estimation of each cells location was made based on a correlation of the Exceed tools visual representation of the specific cells location and a photograph that was taken of the physical die. Once a location estimate for a particular cell was made, the surrounding area was exposed to the laser systematically while the output was monitored for an upset. The systematic exposure procedure moved the laser in an open rectangular pattern. Starting at a prescribed X coordinate the laser was moved in 10-micron increments in the X direction for approximately 200 microns. Next the laser was moved in the orthogonal Y direction for a single 10-micron increment. Then the laser was again moved orthogonally, in the negative X direction, in 10-micron increments until the original X coordinate was reached. This procedure was continued until an upset condition was observed. Once an upset condition was observed, the step size in both directions was decreased to 1 micron and the pattern continued until a boundary was established that produced a repeatable upset to the same bit.

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33 4.1 Word A Bit 2 The first bit targeted with the laser was the second most significant bit in the first word, which was labeled Word A Bit 2. This bit was targeted since the cell containing this bit was the most isolated of all the cells and provided the greatest chance of exposing it without striking another bit. The isolation of Word A Bit 2 is revealed in Figure 14. After reviewing the Exceed tools representation of the bits location and the physical picture of the die, it was determined that this cell was located at approximately coordinates X = +4200 microns and Y = +200 microns from the defined origin. Figure 14. Exceed Diagram Showing the Location of Word A Bit 2

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34 Figure 15. Estimate of Physical Location of Word A Bit 2 4.1.1 Word A Bit 2 Procedure Testing was initiated with the laser power set to 0.62 Watt and focused to approximately 2 microns. Exposure proceeded in a systematic manner as previously described, advancing +10-microns in the X-axis between each exposure until the X-axis position had been advanced by +200 microns. Next the Y-axis was advanced by +10microns and the part again exposed to the laser. Then the X-axis was decreased in 10micron intervals between exposures until the X-axis location was again at +4200 microns. The first location that yielded repeatable upsets to the same output bit while following this procedure was at X = +4240 microns and Y = +190 microns from the origin. As anticipated, an exposure in this region yielded an upset to the second bit of word A. However, in addition to forcing an upset to the specified bit, the laser exposure caused the FPGA to enter a latched up state. Latchup caused the maximum compliance

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35 current to be drawn from the Agilent E3633A power supply. This latchup condition did not permanently damage the device since the supply current had been limited to 50.0 mA. The FPGA continued to functionally operate during the latched condition. However, the parts output drive capability was decreased, which manifested itself as a dimming of the LEDs that were used. This location yielded a consistent upset of the second bit of word A during multiple exposures regardless of the input sequence or the expected state of the bit. Once the upset occurred, the X-axis and Y-axis movements were refined to + 1micron and the testing continued as described above in an effort to better define the sensitive region. After numerous exposures, it was determined that the sensitive region for the second bit of Word A was defined by the borders X = +4236 microns to X = +4240 microns and Y = +189 microns to Y = +192 microns from the defined origin. A summary of the results of the upset testing for Word A Bit 2 is presented in Tables 2 and 3. Testing was performed numerous times in the region of the second bit of Word A and each laser exposure produced an upset as well as a latchup. Next, the laser power was decreased in 0 .02 watt increments and the part re-exposed to determine the minimum power needed to induce an upset and/or latchup. The results, as summarized in Table 4, revealed that all exposures, which were equal to or above a laser power of 0.58 watt induced both an upset and a latchup. Exposures performed at a laser power of 0.56 watt produced intermittent upsets and latchups. At 0.54 watt and below, neither upsets nor latchups were observed. Additionally, it should be noted that latchups were always observed when the bit was upset.

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36 Table 2. Word A Bit 2 Upset Results with Expected Output = 0000 Clock Cycle # Laser Exposure Laser Power Data Input Output Word A Output Word B Output Word C Output Word FT Latchup Upset 1 No 0.62 0000 0000 0000 0000 0000 No No 2 No 0.62 0000 0000 0000 0000 0000 No No 3 No 0.62 0000 0000 0000 0000 0000 No No 4 Yes 0.62 0000 0000 0000 0000 0000 No No 5 No 0.62 1111 0011 0011 0011 0011 Yes No 6 No 0.62 1111 0 0 11 0111 0111 0111 Yes Yes 7 No 0.62 1111 1011 1011 1011 1011 Yes No 8 No 0.62 1111 1 0 11 1111 1111 1111 Yes Yes Figure 16. Word A Bit 2 Upset Results with Expected Output = 0000 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0011 0011 1011 1011 0000 0000 0000 0000 0011 0111 1011 1111 0000 0000 0000 0000 0011 0111 1011 1111 0000 0000 0000 0000 0011 0111 1011 1111 Clock Laser Input Output A Output B Output C Output FT

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37 Table 3. Word A Bit 2 Upset Results with Expected Output = 1111 Clock Cycle # Laser Exposure Laser Power Data Input Output Word A Output Word B Output Word C Output Word FT Latchup Upset 1 No 0.62 1111 0011 0011 0011 0011 No No 2 No 0.62 1111 0111 0111 0111 0111 No No 3 No 0.62 1111 1011 1011 1011 1011 No No 4 Yes 0.62 1111 1111 1111 1111 1111 No No 5 No 0.62 0000 1011 1011 1011 1011 Yes No 6 No 0.62 0000 0111 0 0 11 0111 0111 Yes Yes 7 No 0.62 0000 0011 0011 0011 0011 Yes No 8 No 0.62 0000 0000 0000 0000 0000 Yes No Figure 17. Word A Bit 2 Upset Results with Expected Output = 1111 1111 1111 1111 1111 0000 0000 0000 0000 0011 0111 1011 1111 1011 0011 0011 0000 0011 0111 1011 1111 1011 0111 0011 0000 0011 0111 1011 1111 1011 0111 0011 0000 0011 0111 1011 1111 1011 0111 0011 0000 Clock Laser Input Output A Output B Output C Output FT

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38 Table 4. Word A Bit 2 Latchup Results with Decreasing Power Exposure # Laser Exposure Laser Power Data Output Expected Output Word A Output Word B Output Word C Output Word FT Latchup Upset 1 Yes 0.62 1111 1 0 11 1111 1111 1111 Yes Yes 2 Yes 0.62 1111 1 0 11 1111 1111 1111 Yes Yes 3 Yes 0.62 1111 1 0 11 1111 1111 1111 Yes Yes 4 Yes 0.60 1111 1 0 11 1111 1111 1111 Yes Yes 5 Yes 0.60 1111 1 0 11 1111 1111 1111 Yes Yes 6 Yes 0.60 1111 1 0 11 1111 1111 1111 Yes Yes 7 Yes 0.58 1111 1 0 11 1111 1111 1111 Yes Yes 8 Yes 0.58 1111 1 0 11 1111 1111 1111 Yes Yes 9 Yes 0.58 1111 1 0 11 1111 1111 1111 Yes Yes 10 Yes 0.56 1111 1111 1111 1111 1111 Yes Yes 11 Yes 0.56 1111 1111 1111 1111 1111 No No 12 Yes 0.56 1111 1 0 11 1111 1111 1111 Yes Yes 13 Yes 0.56 1111 1111 1111 1111 1111 No No 14 Yes 0.56 1111 1 0 11 1111 1111 1111 No No 15 Yes 0.54 1111 1 0 11 1111 1111 1111 No Yes 16 Yes 0.54 1111 1111 1111 1111 1111 No No 17 Yes 0.54 1111 1111 1111 1111 1111 No No 18 Yes 0.54 1111 1111 1111 1111 1111 No No 19 Yes 0.54 1111 1111 1111 1111 1111 No No 20 Yes 0.52 1111 1111 1111 1111 1111 No No 21 Yes 0.52 1111 1111 1111 1111 1111 No No 22 Yes 0.52 1111 1111 1111 1111 1111 No No 23 Yes 0.50 1111 1111 1111 1111 1111 No No 24 Yes 0.50 1111 1111 1111 1111 1111 No No 25 Yes 0.50 1111 1111 1111 1111 1111 No No 4.1.2 Word A Bit 2 Summary More than 25 test sequences were performed in this region under numerous input and output conditions. All exposures produced the same results. Each exposure produced an upset of Word A Bit 2 that was a logic low 100% of the time, which was accompanied by a high-current latchup condition. Simply cycling power to the FPGA and then re-loading the test software resolved all of the latchups. Since the device was fabricated using one-time programmable anti-fuse technology, no software or firmware had to be reloaded to the test device. For the upsets that were observed, the logic state of the affected output bit could not be altered by performing additional filtering operations

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39 or by adjusting the output loading of the pin. The inability of the output bit to be rewritten, without first powering down the FPGA, signified that the observed upsets were not of the traditional nature but rather the latchup of an output buffer cell. 4.2 Word B Bit 2 The second bit that was targeted for laser fault injection testing was the second most significant bit of word B. Once again this cell was isolated from the other active cells that were used in the filters design. The isolation of Word B Bit 2 is illustrated in Figure 18. Based on the results of the correlation between the chips layout in Exceed and the view of the de-lidded chip, it was estimated that a starting location of X = +500 microns and Y = +2500 microns from the origin should be used. Figure 19 presents a physical picture with the estimated position of Word B Bit 2 highlighted Figure 18. Exceed Diagram Showing the Location of Word B Bit 2

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40 Figure 19. Estimate of Physical Location of Word B Bit 2 4.2.1 Word B Bit 2 Procedure Following the test procedure established for Word A Bit 2, the laser power was set to 0.62 Watt, the beam focused to approximately 2 microns and a systematic exposure pattern used to locate the sensitive region. Exposure proceeded in a systematic manner as previously described, advancing +10-microns in the X-axis between each exposure until the X-axis position had been advanced by +200 microns. Next the Y-axis was advanced by +10-microns and the part again exposed to the laser. Then the X-axis was decreased in 10-micron intervals between exposures until the X-axis location was again at its original location. The exposure pattern was repeated until an upset was observed, which occurred at location X = +870 and Y = +2630 from the origin. As estimated, the upset was observed in the second bit of Word B. Using the same procedure as described for Word A Bit 2 previously for determining the borders of the sensitive region, the step size

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41 was once again decreased to 1-micron and the testing repeated. The sensitive region for Word B Bit 2 was defined by borders from +865 to +870 microns in the X direction and +2626 to +2630 microns in the Y direction. The laser exposure was repeated with various input conditions to determine if the input data pattern or the expected state of the cell had any affect on the results. After completing four different input patterns it was determined that the upset condition was not based on an input pattern or the state of bit. However, in every case, the laser exposure forced the output bit into a zero state. A summary of the results of the upset testing for Word B Bit 2 is presented in Tables 5 and 6. Next, the laser power was decreased in 0 .02 watt increments and the part reexposed to determine the minimum power needed to induce an upset and/or latchup. The results, as summarized in Table 7, revealed that all exposures, which were equal to or above a laser power of 0.60 watt induced both an upset and a latchup. At 0.58 watt and below, neither upsets nor latchups were observed. Additionally, it should be noted that latchups were always observed when the bit was upset. Table 5. Word B Bit 2 Upset Results with Expected Output = 0000 Clock Cycle # Laser Exposure Laser Power Data Input Output Word A Output Word B Output Word C Output Word FT Latchup Upset 1 No 0.62 0000 0000 0000 0000 0000 No No 2 No 0.62 0000 0000 0000 0000 0000 No No 3 No 0.62 0000 0000 0000 0000 0000 No No 4 Yes 0.62 0000 0000 0000 0000 0000 No No 5 No 0.62 1111 0011 0011 0011 0011 Yes No 6 No 0.62 1111 0111 0 0 11 0111 0111 Yes No 7 No 0.62 1111 1011 1011 1011 1011 Yes No 8 No 0.62 1111 1111 1 0 11 1111 1111 Yes Yes

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42 Figure 20. Word B Bit 2 Upset Results with Expected Output = 0000 Table 6. Word B Bit 2 Upset Results with Expected Output = 1111 Clock Cycle # Laser Exposure Laser Power Data Input Output Word A Output Word B Output Word C Output Word FT Latchup Upset 1 No 0.62 1111 0011 0011 0011 0011 No No 2 No 0.62 1111 0111 0111 0111 0111 No No 3 No 0.62 1111 1011 1011 1011 1011 No No 4 Yes 0.62 1111 1111 1111 1111 1111 No No 5 No 0.62 0000 1011 1011 1011 1011 Yes No 6 No 0.62 0000 0111 0 0 11 0111 0111 Yes Yes 7 No 0.62 0000 0011 0011 0011 0011 Yes No 8 No 0.62 0000 0000 0000 0000 0000 Yes No 0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0011 0111 1011 1111 0000 0000 0000 0000 0011 0011 1011 1011 0000 0000 0000 0000 0011 0111 1011 1111 0000 0000 0000 0000 0011 0111 1011 1111 Clock Laser Input Output A Output B Output C Output FT

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43 Figure 21. Word B Bit 2 Upset Results with Expected Output = 1111 Table 7. Word B Bit 2 Latchup Results with Decreasing Power Exposure # Laser Exposure Laser Power Data Output Expected Output Word A Output Word B Output Word C Output Word FT Latchup Upset 1 Yes 0.62 1111 1111 0 0 11 1111 1111 Yes Yes 2 Yes 0.60 1111 1111 0 0 11 1111 1111 Yes Yes 3 Yes 0.58 1111 1111 1111 1111 1111 No No 4 Yes 0.56 1111 1111 1111 1111 1111 No No 5 Yes 0.54 1111 1111 1111 1111 1111 No No 6 Yes 0.52 1111 1111 1111 1111 1111 No No 7 Yes 0.50 1111 1111 1111 1111 1111 No No 4.2.2 Word B Bit 2 Summary The results observed for Word B Bit 2 corresponded to the results that were observed for Word A Bit 2. An upset of Word B Bit 2 resulted in a logic zero 100% of the time and a high-current latchup condition. Once again, the latchups were nondestructive since the supply current was limited to 50 mA and were resolved by cycling power and then re-loading the test software. For the upsets that were observed in the 1111 1111 1111 1111 0000 0000 0000 0000 0011 0111 1011 1111 1011 0111 0011 0000 0011 0111 1011 1111 1011 0011 0011 0000 0011 0111 1011 1111 1011 0111 0011 0000 0011 0111 1011 1111 1011 0111 0011 0000 Clock Laser Input Output A Output B Output C Output FT

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44 Word B Bit 2 region, the affected output buffer could not be corrected by changing the input sequence to the part or by adjusting the output loading of the pin. 4.3 Word C Bit 2 Unlike the previous two bits that were targeted for exposure, Word C Bit 2 was located near several other cells that were being used in the design. Based on the same location assessment that was performed for the first two output cells, a starting point for this cell was estimated at X = +500 microns and Y = +2800 microns from the origin. The isolation of Word C Bit 2 is illustrated in Figure 22. Figure 23 presents a physical picture with the estimated position of Word C Bit 2 highlighted Figure 22. Exceed Diagram Showing the Location of Word C Bit 2

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45 Figure 23. Estimate of Physical Location of Word C Bit 2 4.3.1 Word C Bit 2 Procedure Using the same laser power, beam diameter and systematic approach described for bit 2 of Words A and B the FPGA was subjected to laser fault injection testing. However, unlike the results that were obtained for Word A Bit 2 and Word B Bit 2, the upsets that were observed did not correspond to those predicted for Word C Bit 2. With as many as six different upset patterns logged, the testing of Word C Bit 2 did not produce a repeatable upset condition. Upsets ranged from single errors in Word A and Word FT to the complete upset of Word C. However, latchup of the FPGA was exhibited in each upset condition.

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46 4.3.2 Word C Bit 2 Summary Due to the 10 minutes required to power down the FPGA and reload the test software, it was not practical to continue searching for the location that caused an upset to Bit 2 of Word C. It is possible that this location was buried under a metalization layer or was not exposed to the laser. This bit is one where manufacture specified coordinates of the specific cell would have been very valuable. 4.4 Word FT Bit 2 The final bit that was individually targeted was the second bit of the fault tolerant output. Like Word A Bit 2 and Word B Bit 2 this bits location was fairly isolated from other used cells. Using the same procedure as was used to estimate the location of the first three bits, it was estimated that Word FT Bit 2 was located at X = +950 microns and Y = +2200 microns from the designated origin. The isolation of Word FT Bit 2 is illustrated in Figure 24. Figure 25 presents a physical picture with the estimated position of Word FT Bit 2 highlighted

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47 Figure 24. Exceed Diagram Showing the Location of Word FT Bit 2 Figure 25. Estimate of the Physical Location of Word FT Bit 2

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48 4.4.1 Word FT Bit 2 Procedure Once again, the laser power was set to 0.62 Watt, the beam focused to approximately 2 microns and a systematic approach used to locate a sensitive region. Exposure proceeded in a systematic manner as previously described, advancing +10microns in the X-axis between each exposure until the X-axis position had been advanced by +200 microns. Next the Y-axis was advanced by +10-microns and the part again exposed to the laser. Then the X-axis was decreased in 10-micron intervals between exposures until the X-axis location was again at its original location. The exposure pattern was repeated until it was no longer feasible to continue. As observed with Word C Bit 2, numerous upset and latchup locations were discovered. However, the time required for resetting the test sample and the test computer prevented further testing. 4.4.2 Word FT Bit 2 Summary Similar to the results observed for Word C Bit 2, numerous upsets and latchups were observed in the area of Word FT Bit 2. None of the observed upsets affected only Word FT Bit 2. This series of testing continued for several hours and did reveal several locations that produced repeatable upsets and latchups. However, most of these upsets affected multiple bits and in some cases multiple bits in multiple words. Without knowing specifically what cells were being targeted with the laser due to the inability to obtain the X-Y coordinates from the manufacturer, it was not possible to determine why the upset testing did not produce the output data patterns that were expected. It is possible that either the correct location was not found during the time allotted or that the

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49 sensitive area for this output cell was covered by a metalization layer and thus not accessible to the laser. 4.5 Other Injection Locations Numerous other locations were targeted throughout the testing in mostly a random fashion. The purpose of this testing was to attempt to catch an upset condition and then go back and study it in more detail. This testing was performed numerous times in different areas of the chip. Some of the areas were heavily populated and some only lightly populated. However, no locations were isolated that produced significant repeatable upsets. Many of the locations produced single and multiple bit errors in multiple output words, which indicated that a control portion of the FPGA had most likely been targeted.

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50 Chapter 5 Issues Observed/Future Work Numerous issues were discovered during the course of the development and testing of the FPGA. The issues identified as major that should be addressed in future testing are: Determination of the cause for the extreme latchup sensitivity of the FPGA and the reason the devices latchup sensitivity is dependent on output loading. Perform a complete investigation into the effect of using the frequency doubler in LFI experiments. Obtain the X-Y coordinates for the sensitive cells from the manufacturer or determine which manufacturers are willing to provide coordinate information Determine the best method for removing the backside of the die and expose the FPGA through the backside in order to avoid the metalization layers. 5.1 Latchup Sensitivity Determination It was discovered during testing that the Actel A42MX series of FPGA is a highly latchup sensitive device. During testing, there were numerous times that the device exhibited a significant increase in the amount of current it was drawing. The current drawn by the test device ranged from approximately 10 mA to over 50 mA with each

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51 latchup condition. In order to keep from damaging the few test samples that were available, the power supply current was limited to 50 mA for most exposures to assure that the device would not burn out. The induction of a latchup condition was not totally unexpected since there is a great deal of literature exists showing that bulk CMOS can exhibit the latchup condition. However, the frequency of occurrence, during this research, was significantly greater than was anticipated. Additionally, it was discovered during testing that the devices latchup susceptibility was dependent on the output loading structure. When all red LEDs were used the device latched up approximately once in every 10 exposures regardless of the output states of the filter I/O pins. However, when the red LEDs were replaced with yellow, green and/or blue LEDs the devices latchup susceptibility decreased to less than once in every 100 exposures. 5.2 Frequency Doubler Another issue that warrants further investigation is the use of the frequency doubler in LFI experiments. It was reported earlier that the use of a frequency doubler decreases the effectiveness of a Nd :YAG laser on silicon devices. It is possible that performing the same experiment at the same locations using a laser with a longer wavelength may produce different results. Elimination of the frequency doubler could potentially provide upsets without associated latchup conditions. 5.3 Critical Cells Location Determination During the course of the testing reluctance on the part of the manufacturer to provide the necessary X-Y coordinates for critical cells was encountered. Manufacturer

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52 reluctance surfaced even though they had committed to provide the information before their chip was selected. This issue definitely needs to be addressed before a part is selected for laser fault injection testing since failure to obtain critical cell coordinates severely limits the usefulness of the data. It is possible that a contractual teaming arrangement could be established. 5.4 Back Side Die Lapping Significant research is currently being performed within the radiation effects community to address the issue of metalization layers covering critical elements in highly complex designs. More research is needed to determine the most effective way to perform thinning of the backside layer while maintaining the devices functionality. One concern with this procedure is that removing a majority of the die causes the FPGA to run much warmer than normal since this is the pathway that most of the heat generated by the part is dissipated.

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53 Chapter 6 Conclusion In summary, portions of a fault tolerant 4-bit filter implemented in a commercial FPGA were verified using laser fault injection. Two separate locations, from four that were targeted, produced an upset to a single bit while not affecting the other output bits. These two upset locations yielded predictable and repeatable upsets when exposed to a laser with a beam diameter of 2 m m and a power of 0.62 Watt. In all cases, the upsets to these two bits were observed and recorded as a logic low when a logic high condition was expected. Additionally, a significant number of other locations were identified that produced upsets to multiple bits as well as upsets to bits contained in different words. However, many of these upsets were not repeatable and without precise X-Y coordinates it was not possible to determine the exact cell that produced the upset. This research also demonstrated that the Actel A42MX FPGA could be latched up using laser fault injection without causing permanent damage to the device. Several hundred locations were identified that induced a non-destructive latchup condition within the FPGA when exposed to a 2 m m diameter laser set to a power of 0.62 Watt. Once the FPGA was latched up power had to be removed from the FPGA and the software had to be reset for all locations in order to recover from the latchup condition.

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54 Numerous issues need to be addressed before laser fault injection can be used as the sole method for verifying a fault tolerant design implemented in an FPGA or an ASIC. However, the results presented in this thesis demonstrate that the spatial and temporal qualities associated with laser fault injection testing make it an attractive verification tool when compared to other verification techniques. Once the major issues discussed in this thesis are overcome, laser fault injection will probably become a much more utilized tool for the prediction and verification of upsets and latchups in fault tolerant designs.

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55 References [1] Aerospace Corporation Website, World Wide Web URL: http://www.aero.org/facilities/spaceEnvironment.html [2] Mavis, David G and Eaton, Paul H., SEU and SET Mitigation Techniques for FPGA Circuit and Configuration Bit Storage Design, World Wide Web URL: http://klabs.org/richcontent/MAPLDCon00/Abstracts/mavis_a.pdf [3] Carreira, Joao, Madeira, Henrique and Silvia, Joao Gabriel, Xception: Software Fault Injection and Monitoring in Processor Functional Units, World Wide Web URL: http://dsg.dei.uc.pt/Papers/dcca95.ps.Z [4] Habling, D. H., Use of Lasers to Simulate Radiation Induced Transients in Semiconductors and Circuits, IEEE Transactions on Nuclear Science Vol NS-12, No 6, pp 91-100, Dec. 1965. [5] Binder, D., et al. Satellite Anomalies from Galactic Cosmic Rays IEEE Transactions on Nuclear Science Vol 22, pp 2675-2680, 1975. [6] Samson, J. R. Jr., Moreno, W. A. and Falquez, F. J., A Technique For Automated Validation Of Fault Tolerant Designs Using Laser Fault Injection (LFI), Proceedings, IEEE Symposium on Fault Tolerant Computing Munich, Germany, June 1998. [7] Duzellier, Sophie, Falguere, Didier, Guibert, Laurent, Pouget, Vincent, Fouillat, Pascal and Ecoffet, Robert, Application of Laser Testing in Study of SEE Mechanicms in 16-Mbit DRAMs, IEEE Transactions on Nuclear Science Vol 47, No 6, pp 2392-2399. [8] Aerospace Crosslink Article, World Wide Web URL: http://www.aero.org/publications/crosslink/summer2003/04.html [9] Skorobogatov, P. K., Nikiforov, A. Y., Demidov, A. A. and Levin, V. V., Influence of Temperature on Dose Rate Laser Simulation Adequacy IEEE Transactions on Nuclear Science Vol 47, No 6, Dec 2000, pp 2442-2446. [10] Lewis, Dean, Pouget, Vincent, Beaudoin, Felix, Perdu, Philippe, Lapuyade, Herve, Fouillat, Pascal and Touboul, Andre, Backside Laser Testing of ICs for SET Sensitivity Evaluation, IEE Transactions on Nuclear Science Vol 48, no 6, pp 21932201.

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56 [11] Pouget, V., Fouillat, P., Lewis, D., Lapuyade, H., Darracq, F. and Touboul, A., Laser Cross Section Measurement for the Evaluation of Single-Event Effects in Integrated Circuits, Microelectronics Reliability Vol 40, pp 1371-1375, 2000. [12] Pouget, V., Fouillat, P., Lewis, D., Lapuyade, H. and Buchner, S., Theoretical Investigation of an Equivalent Laser LET in ESREF 2001, submitted for publication. [13] Melinger, J. S., Buchner, S., McMorrow, D., Stapor, W. J., Weatherford, T. R. and Campbell, A. B., Critical Evaluation of the Pulsed Laser Method for Single Event Effects Testing and Fundamental Studies, IEEE Transactions on Nuclear Science Vol 41, pp 2574-2584, Dec. 1994. [14] University of Bath Optoelectronics Group Website, World Wide Web URL: http://www.bath.ac.uk/physics/groups/opto/lasers.html [15] Zhu, Xiaowei, Bhuva, Bharat, Cirba, Claude R., Massengill, Lloyd, Buchner, Stephen and Dodd, Paul E., A Methodology for Identifying Laser Parameter for Equivalent Heavy Ion Hits, IEEE Transactions on Nuclear Science Vol 48, No 6, pp 2174-2179. [16] Johnston, A. H., Charge Generation and Collection in p-n Junction Excited with Pulsed Infrared Lasers, IEEE Transactions on Nuclear Science Vol 40, No 6, pp 16941702, 1993.

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57 Appendices

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58 Appendix A Fault Tolerant FPGA VHDL Code entity four_bit_four_value_filter is port( data_in_bv:in bit_vector (3 downto 0); error _out:out bit; clk ,reset:in bit; data _out_A_bv,data_out_B_bv,data_out_C_bv,data_out_ft_bv:out bit_vector (3 downto 0)); end four_bit_four_value_filter; architecture behave of four_bit_four_value_filter is type history is array (0 to 3) of natural; type history_bv is array (0 to 3) of bit_vector (3 downto 0); begin process( clk, reset, data_in_bv) --------------------------------------------------------------------------------------------------variable declarations variable history_A_bv,history_B_bv,history_C_bv:history_bv; variable sum_A,sum_B,sum_C,average_A,average_B,average_C:natural := 0; variable sum,add:natural := 0; variable nat_A,nat_B,nat_C,nat_bit2int,add_A,add_B,add_C,add_bit2int:natural:=0; variable temp_A_bv,temp_B_bv,temp_C_bv:bit_vector(3 downto 0); variable current_sum_A,current_sum_B,current_sum_C:natural:=0; variable average_output_A,average_output_B,average_output_C:bit_vector (3 downto 0); -------------------------------------------------------------------------------------------------begin if(clk='1' and clk'event) then if(reset='1') then for i in 0 to 3 loop --clears all three history vectors if reset = '1' history _A_bv( i) := "0000"; history _B_bv( i) := "0000"; history _C_bv( i) := "0000"; error _out <= '0'; end loop; else for i in 3 downto 1 loop --shifts all history values up 1 in the vector history _A_bv( i) := history_A_bv(i-1); history _B_bv( i) := history_B_bv(i-1); history _C_bv( i) := history_C_bv(i-1); end loop; history _A_bv(0) := data_in_bv; --the next three lines sample the input data and history _B_bv(0) := data_in_bv; --place it in the 0 position of the three history history _C_bv(0) := data_in_bv; --vectors end if;

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59 Appendix A (Continued) ----------------------------------------------------------------------------------------------------------this section adds up the previous 4 readings so that the average can be found sum _A := 0; sum _B := 0; sum _C := 0; nat _A := 0; nat _B := 0; nat _C := 0; add _A := 0; add _B := 0; add _C := 0; for k in 0 to 3 loop --this loop is for the number of previous values temp _A_bv := history_A_bv(k); --that need to be summed, which is permanently set temp _B_bv := history_B_bv(k); --to the last 4 values temp _C_bv := history_C_bv(k); for l in 0 to 3 loop --this loop converts the bitvectors that if temp_A_bv(l) = '1' then --are stored in gr oup A into a natural number add _A := 2**l; --to add else add _A := 0; end if; nat _A := nat_A + add_A; end loop; for l in 0 to 3 loop --this loop converts the bitvectors that if temp_B_bv(l) = '1' then --are stored in group B into a natural number add _B := 2**l; --to add else add _B := 0; end if; nat _B := nat_B + add_B; end loop; for l in 0 to 3 loop --this loop converts the bitvectors that if temp_C_bv(l) = '1' then --are stored in group C into a natural number add _C := 2**l; --to add else add _C := 0; end if; nat _C := nat_C + add_C;

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60 Appendix A (Continued) end loop; sum _A := sum_A + nat_A; --the next three lines actually accumulate the integer values sum _B := sum_B + nat_B; --converted above sum _C := sum_C + nat_C; nat _A := 0; --the next six lines reset the variables used to convert the nat _B := 0; -bitvectors stored in the history array from a bitvector to nat _C := 0; --an integer add _A := 0; add _B := 0; add _C := 0; end loop; --------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------this section actually finds the average for the numbers that were summed above and sets the variables -that will be used to convert the number back to a bitvector for output average _A := sum_A / 4; average _B := sum_B / 4; average _C := sum_C / 4; current _sum_A := average_A; current _sum_B := average_B; current _sum_C := average_C; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------convert the average for output A from integer to binary for i in 3 downto 0 loop if( current_sum_A/(2**i)) >= 1 then current _sum_A := current_sum_A (2**i); average _output_A( i) := '1'; else average _output_A( i) := '0'; end if; end loop; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------convert the average for output B from integer to binary for i in 3 downto 0 loop if( current_sum_B/(2**i)) >= 1 then current _sum_B := current_sum_B (2**i); average _output_B( i) := '1'; else average _output_B( i) := '0'; end if;

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61 Appendix A (Continued) end loop; ---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------convert the average for output C from integer to binary for i in 3 downto 0 loop if( current_sum_C/(2**i)) >= 1 then current _sum_C := current_sum_C (2**i); average _output_C( i) := '1'; else average _output_C( i) := '0'; end if; end loop; -------------------------------------------------------------------------------------------------this section produces the fault tolerant output by checking the values of each of the three averages -and taking the two that match. for i in 0 to 3 loop if (( average_output_A( i) /= average_output_B( i)) or ( average_output_A( i) /= average_output_C( i)) or ( average_output_B( i) /= average_output_C( i))) then error _out <= '1'; else error _out <= '0'; end if; data _out_ft_bv( i) <= (( average_output_A( i) and average_output_B( i)) or ( average_output_B( i) and average_output_C( i)) or ( average_output_C( i) and average_output_A( i))); end loop; data _out_A_bv <= average_output_A; data _out_B_bv <= average_output_B; data _out_C_bv <= average_output_C; end if; end process; end behave;

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62 Appendix B LabWindows Test Software Code ASIC 42MX Support.h File // ------------------------------------------------------------------------// // Filename: ASIC 42MX support.h // // Description: This file co ntains functions to support the main program // "ASIC 42MX.c". // // Created by : Paris Wiley 5/24/01 // // ------------------------------------------------------------------------# include < visa.h> # include < nivxi.h> # include "Tkvx4801.h" # include < utility.h> # include < gpib.h> # include < ansi_c.h> # include // LOCAL VARIABLE DECLARATIONS extern int panelHandle; ViSession VXI4801; ViUInt32 byte_ctr; FILE output_data; extern FILE output_data; // BEGINNING OF FUNCTIONS void Testing_Init(char the_file[40]) { ViUInt32 byte_ctr; // bytes return by a viWrite operation char date_ptr; char time_ptr; char suffix_name[20]="ASIC42MX_output.xls"; // Get the current date and time, and create a new file for output b ases on this data. // example: date=4/15/99, time=11:13:26am, so filename="041599_111326_am3output.txt" date _ptr = DateStr (); time _ptr = TimeStr (); date _ptr[2]= date_ptr[3];

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63 Appendix B (Continued) date _ptr[3]= date_ptr[4]; date _ptr[4]= date_ptr[6]; date _ptr[5]= date_ptr[7]; date _ptr[6]= date_ptr[8]; date _ptr[7]= date_ptr[9]; date _ptr[8]='\0'; time _ptr[2]= time_ptr[3]; time _ptr[3]= time_ptr[4]; time _ptr[4]= time_ptr[6]; time _ptr[5]= time_ptr[7]; time _ptr[6]='\0'; strcat( the_file,date_ptr); strcat( the_file, "_"); strcat( the_file,time_ptr); strcat( the_file, "_"); strcat( the_file,suffix_name); output _data = fopen ( the_file, "w"); // Insert file header information here... fputs(" ASIC 42MX Test\n",output_data); fputs("(The file name is the date/time created)\ n\n",output_data); //Setup Labels in the data file fprintf(output_data,"COMMENTS\tINPUT_DATA\tOUTPUT_DATA_A\tOUTPUT_DATA_B\t OUTPUT_DATA_C\tOUTPUT_DATA_FT\n"); fclose( output_data); } initialize_4801(void) { tkvx4801_init ("GPIB-VXI0::128::INSTR", INIT_SKIP_QUERY, INIT_DO_RESET, &VXI4801); // set the byte direction of communication tkvx4801_setByteMode (VXI4801, tkvx4801_BYTE0, tkvx4801_INPUT_MODE, tkvx4801_TRUE_LOGIC_HIGH); tkvx4801_setByteMode (VXI4801, tkvx4801_BYTE1, tkvx4801_INPUT_MODE, tkvx4801_TRUE_LOGIC_HIGH); tkvx4801_setByteMode (VXI4801, tkvx4801_BYTE2, tkvx4801_INPUT_MODE, tkvx4801_TRUE_LOGIC_HIGH); tkvx4801_setByteMode (VXI4801, tkvx4801_BYTE3, tkvx4801_INPUT_MODE, tkvx4801_TRUE_LOGIC_HIGH); tkvx4801_setByteMode (VXI4801, tkvx4801_BYTE4, tkvx4801_INPUT_MODE, tkvx4801_TRUE_LOGIC_HIGH);

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64 Appendix B (Continued) tkvx4801_setByteMode (VXI4801, tkvx4801_BYTE5, tkvx4801_OUTPUT_MODE, tkvx4801_TRUE_LOGIC_HIGH); // Untristate all Bytes tkvx4801_setTristateMode (VXI4801, tkvx4801_BYTE0, tkvx4801_TRI_STATE_OFF); tkvx4801_setTristateMode (VXI4801, tkvx4801_BYTE1, tkvx4801_TRI_STATE_OFF); tkvx4801_setTristateMode (VXI4801, tkvx4801_BYTE2, tkvx4801_TRI_STATE_OFF); tkvx4801_setTristateMode (VXI4801, tkvx4801_BYTE3, tkvx4801_TRI_STATE_OFF); tkvx4801_setTristateMode (VXI4801, tkvx4801_BYTE4, tkvx4801_TRI_STATE_OFF); tkvx4801_setTristateMode (VXI4801, tkvx4801_BYTE5, tkvx4801_TRI_STATE_OFF); return 0; } // -----------------------------------------// // Function: VXI4801_GetByte // // Arguments: byte the byte to read // // Returns: byte_val the integer value of the byte // // Description: This function returns the integer value of a byte on the // VXI 4801 DIO. // int VXI4801_GetByte( enum byte_enum byte) { ViChar read_ in [20]={'\0'}; int byte_val; tkvx4801_readInputs (VXI4801, tkvx4801_NORMAL_COMMAND, tkvx4801_NORMAL_INPUT, tkvx4801_NORMAL_INPUT, tkvx4801_NORMAL_INPUT, tkvx4801_NORMAL_INPUT,

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65 Appendix B (Continued) tkvx4801_NORMAL_INPUT, tkvx4801_NORMAL_INPUT, read _in); tkvx4801_readByteData (VXI4801, read_in); switch (byte) { case 0: byte _val = Convert_ASCII_to_Decimal(0, read_in); break; case 1: byte _val = Convert_ASCII_to_Decimal(1, read_in); break; case 2: byte _val = Convert_ASCII_to_Decimal(2, read_in); break; case 3: byte _val = Convert_ASCII_to_Decimal(3, read_in); break; case 4: byte _val = Convert_ASCII_to_Decimal(4, read_in); break; case 5: byte _val = Convert_ASCII_to_Decimal(5, read_in); break; } // end switch (byte) return ( byte_val); } // -----------------------------------------// // Function: Set_Bit_Pattern // // Arguments: data the 8-bit number in decimal(0-255) to set a byte to // byte the decimal byte to set(0-5) on the tkvx4801 // // Returns: (none) // // Description: This function allows the user to set the bit pattern of any byte of the 4801. // void Set_Bit_Pattern( int byte, int data) { tkvx4801_setOutputData (VXI4801, byte, tkvx4801_SPECIFIC_DATA, data);

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66 Appendix B (Continued) switch (byte) { case 0: tkvx4801_outputData (VXI4801, tkvx4801_OVERRIDE_COMMAND, tkvx4801_MASKED_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT); break; case 1: tkvx4801_outputData (VXI4801, tkvx4801_OVERRIDE_COMMAND, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT); break; case 2: tkvx4801_outputData (VXI4801, tkvx4801_OVERRIDE_COMMAND, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT); break; case 3: tkvx4801_outputData (VXI4801, tkvx4801_OVERRIDE_COMMAND, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT); break; case 4: tkvx4801_outputData (VXI4801, tkvx4801_OVERRIDE_COMMAND,

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67 Appendix B (Continued) tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT, tkvx4801_NO_OUTPUT); break; case 5: tkvx4801_outputData (VXI4801, tkvx4801_OVERRIDE_COMMAND, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT); break; } //end switch } //end Set_Bit_Pattern int Convert_ASCII_to_Decimal( int byte_no, ViChar value[20]) { int temp; int upper_nibble; int lower_nibble; switch ( byte_no) { case 0: upper_nibble=0; lower_nibble=1; break; case 1: upper_nibble=2; lower_nibble=3; break; case 2: upper_nibble=4; lower_nibble=5; break; case 3: upper_nibble=6; lower_nibble=7; break; case 4: upper_nibble=8; lower_nibble=9; break; case 5: upper_nibble=10; lower_nibble=11; break;

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68 Appendix B (Continued) } // end switch ( byte_no) switch (value[ upper_nibble]) { case '0': temp=0; break; case '1': temp=1; break; case '2': temp=2; break; case '3': temp=3; break; case '4': temp=4; break; case '5': temp=5; break; case '6': temp=6; break; case '7': temp=7; break; case '8': temp=8; break; case '9': temp=9; break; case 'A': temp=10; break; case 'B': temp=11; break; case 'C': temp=12; break; case 'D': temp=13; break; case 'E': temp=14; break; case 'F': temp=15; break; } // end switch ( read_in[6])

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69 Appendix B (Continued) temp =temp<<4; switch (value[ lower_nibble]) { case '0': temp=temp+0; break; case '1': temp=temp+1; break; case '2': temp=temp+2; break; case '3': temp=temp+3; break; case '4': temp=temp+4; break; case '5': temp=temp+5; break; case '6': temp=temp+6; break; case '7': temp=temp+7; break; case '8': temp=temp+8; break; case '9': temp=temp+9; break; case 'A': temp=temp+10; break; case 'B': temp=temp+11; break; case 'C': temp=temp+12; break; case 'D': temp=temp+13; break; case 'E': temp=temp+14; break; case 'F': temp=temp+15; break; } // end switch ( read_in[6])

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70 Appendix B (Continued) return temp; } UC1846 Support.h File // ------------------------------------------------------------------------// // Filename: UC1846 support.h // // Description: This file is used to store commonly-used types and variables // for use in UC1846.c // // Created by : Paris Wiley, Test Engineer, 2/04/01 // // ------------------------------------------------------------------------// GLOBAL FUNCTION DECLARATIONS enum byte_enum { BYTE0, BYTE1, BYTE2, BYTE3, BYTE4, BYTE5, ALL }; enum bit_enum { BIT0, B IT1, BIT2, BIT3, BIT4, BIT5, BIT6, BIT7, }; void Set_Bit_Pattern( int data, int byte); int VXI4801_GetByte( enum byte_enum byte); int Convert_ASCII_to_Decimal( int byte_no, ViChar value[20]); void Testing_Init(char the_file[40]); # include < ansi_c.h> # include < utility.h>

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71 Appendix B (Continued) # include < cvirte.h> /* Needed if linking in external compiler; harmless otherwise */ # include < userint.h> # include ASIC.h" # include "Tkvx4801.h" # include //Variable Declarations ViSession VXI4801; int INPUT[16]; //Array INPUT to store Data from front panel FILE output_data; // the FILE handle of the output data file char COMMENTS[50]; // Test Sequence/Comments int i,data, TEMP, error_flag, stop_flag=0; int OUTPUT_DATA_A, OUTPUT_DATA_B, OUTPUT_DATA_C, OUTPUT_DATA_FT =0; char filename[40]={'\0'}; //Function Declarations int initialize_4801(void); //Declares the initialization function for 4801 int Convert(void); //function to convert data (0000=>1111) void Clock(void); //Function to Clock the part static int panelHandle; int main ( int argc, char argv[]) { if ( InitCVIRTE (0, argv, 0) == 0) /* Needed if linking in external compiler; harmless otherwise */ return -1; /* out of memory */ if (( panelHandle = LoadPanel (0, ASIC.uir", PANEL)) < 0) return -1; Testing_ Init (filename); //setup data file initialize_4801(); //calls initialize_4801 to initialize the 4801 DisplayPanel ( panelHandle); RunUserInterface (); tkvx4801_reset (VXI4801); //reset the 4801 before qu itting return 0; } int CVICALLBACK start ( int panel, int control, int event, void callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: // reset error variables and counter i i=0; stop_flag=0; error_flag=0; SetCtrlVal ( panelHandle, PANEL_LED_16, 0); //end of reset variables

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72 Appendix B (Continued) output _data=fopen(filename, "a"); GetTextBoxLine ( panelHandle, PANEL_COMMENTS, 0, & COMMENTS[0]); fprintf( output_data, "% s",COMMENTS); fclose( output_data); SetCtrlAttribute ( panelHandle, PANEL_Start, ATTR_DIMMED, 1); SetCtrlAttribute ( panelHandle, PANEL_Stop, ATTR_DIMMED, 0); SetCtrlAttribute ( panelHandle, PANEL_Reset, ATTR_DIMMED, 1); SetCtrlAttribute ( panelHandle, PANEL_COMMANDBUTTON, ATTR_DIMMED, 1); ProcessSystemEvents (); // dimm start button GetCtrlVal ( panelHandle, PANEL_INPUT_1, & INPUT[0]); GetCtrlVal ( panelHandle, PANEL_INPUT_2, & INPUT[1]); GetCtrlVal ( panelHandle, PANEL_INPUT_3, & INPUT[2]); GetCtrlVal ( panelHandle, PANEL_INPUT_4, & INPUT[3]); GetCtrlVal ( panelHandle, PANEL_INPUT_5, & INPUT[4]); GetCtrlVal ( panelHandle, PANEL_INPUT_6, & INPUT[5]); GetCtrlVal ( panelHandle, PANEL_INPUT_7, & INPUT[6]); GetCtrlVal ( panelHandle, PANEL_INPUT_8, & INPUT[7]); GetCtrlVal ( panelHandle, PANEL_INPUT_9, & INPUT[8]); GetCtrlVal ( panelHandle, PANEL_INPUT_10, & INPUT[9]); GetCtrlVal ( panelHandle, PANEL_INPUT_11, & INPUT[10]); GetCtrlVal ( panelHandle, PANEL_INPUT_12, & INPUT[11]); GetCtrlVal ( panelHandle, PANEL_INPUT_13, & INPUT[12]); GetCtrlVal ( panelHandle, PANEL_INPUT_14, & INPUT[13]); GetCtrlVal ( panelHandle, PANEL_INPUT_15, & INPUT[14]); GetCtrlVal ( panelHandle, PANEL_INPUT_16, & INPUT[15]); Convert(); //Convert data to inverse while (stop_flag==0) { for (i=0; i<=15; i++) { ProcessSystemEvents (); //if stop is pushed stop GetCtrlVal ( panelHandle, PANEL_INPUT_1-i, &data); SetCtrlVal ( panelHandle, PANEL_LED_1-i, 1); if ( i>=1) { SetCtrlVal ( panelHandle, PANEL_LED_1i +1, 0); } if (i==0) { SetCtrlVal ( panelHandle, PANEL_LED_16, 0); }

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73 Appendix B (Continued) fopen(filename, "a"); fprintf( output_data, "\ t%i\t",data); Set_Bit_ Pattern (5, INPUT[ i]); //Send data to VXI4801 Clock(); //Read Data and Write to front panel and Data File OUTPUT_DATA_A=VXI4801_ GetByte(BYTE0); //get data on byte 0 OUTPUT_DATA_A=VXI4801_ GetByte(BYTE0); //get data on byte 0 SetCtrlVal ( panelHandle, PANEL_OUTPUT_A, OUTPUT_DATA_A); fprintf( output_data, "% i\t",OUTPUT_DATA_A); OUTPUT_DATA_B=VXI4801_ GetByte(BYTE1); //get data on byte 1 SetCtrlVal ( panelHandle, PANEL_OUTPUT_B, OUTPUT_DATA_B); fprintf( output_data, "% i\t",OUTPUT_DATA_B); OUTPUT_DATA_C=VXI4801_ GetByte(BYTE3); //get data on byte 3 SetCtrlVal ( panelHandle, PANEL_OUTPUT_C, OUTPUT_DATA_C); fprintf( output_data, "% i\t",OUTPUT_DATA_C); OUTPUT_DATA_FT=VXI4801_ GetByte(BYTE4); //get data on byte 4 SetCtrlVal ( panelHandle, PANEL_OUTPUT_FT, OUTPUT_DATA_FT); fprintf( output_data, "% i\t",OUTPUT_DATA_FT); fprintf( output_data, "\n"); fclose( output_data); //Compare data to see if an error ; if error beep if ((OUTPUT_DATA_A == OUTPUT_DATA_B) && (OUTPUT_DATA_B==OUTPUT_DATA_C) && (OUTPUT_DATA_C == OUTPUT_DATA_FT)) { error_flag=0; } else { error_flag=1; } if (error_flag==1) { Beep(); MessagePopup ("Upset", "There has been an upset");

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74 Appendix B (Continued) } } } break; } return 0; } int CVICALLBACK quit ( int panel, int control, int event, void callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: SetCtrlAttribute ( panelHandle, PANEL_Start, ATTR_DIMMED, 1); SetCtrlAttribute ( panelHandle, PANEL_Stop, ATTR_DIMMED, 1); SetCtrlAttribute ( panelHandle, PANEL_Reset, ATTR_DIMMED, 1); stop_flag=1; QuitUserInterface (0); break; } return 0; } int CVICALLBACK stop ( int panel, int control, int event, void callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: SetCtrlAttribute ( panelHandle, PANEL_Start, ATTR_DIMMED, 0); SetCtrlAttribute ( panelHandle, PANEL_Stop, ATTR_DIMMED, 1); SetCtrlAttribute ( panelHandle, PANEL_Reset, ATTR_DIMMED, 0); SetCtrlAttribute ( panelHandle, PANEL_COMMANDBUTTON, ATTR_DIMMED, 0); //Reset LED's SetCtrlVal ( panelHandle, PANEL_LED_1, 0); SetCtrlVal ( panelHandle, PANEL_LED_2, 0); SetCtrlVal ( panelHandle, PANEL_LED_3, 0); SetCtrlVal ( panelHandle, PANEL_LED_4, 0); SetCtrlVal ( panelHandle, PANEL_LED_5, 0); SetCtrlVal ( panelHandle, PANEL_LED_6, 0); SetCtrlVal ( panelHandle, PANEL_LED_7, 0); SetCtrlVal ( panelHandle, PANEL_LED_8, 0); SetCtrlVal ( panelHandle, PANEL_LED_9, 0); SetCtrlVal ( panelHandle, PANEL_LED_10, 0); SetCtrlVal ( panelHandle, PANEL_LED_11, 0); SetCtrlVal ( panelHandle, PANEL_LED_12, 0);

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75 Appendix B (Continued) SetCtrlVal ( panelHandle, PANEL_LED_13, 0); SetCtrlVal ( panelHandle, PANEL_LED_14, 0); SetCtrlVal ( panelHandle, PANEL_LED_15, 0); SetCtrlVal ( panelHandle, PANEL_LED_16, 0); stop_flag=1; //exit loop i=15; //set so pr ogram will stop break; } return 0; } int CVICALLBACK reset ( int panel, int control, int event, void callbackData, int eventData1, int eventData2) { switch (event) { case EVENT_COMMIT: Set_Bit_ Pattern (5, 60); //Send data to VXI4801 to set outputs to all 0 for (i=0; i<=4; i++) { Clock(); //clock 4 times to clear output to all ZERO's } i=0; //reset variable i to 0 break; } return 0; } int Convert(void) { //This function converts 0-15 to 15-0 and SLL 2 places for (i=0; i<=15; i++) { switch (INPUT[ i]) { case 0: INPUT[ i]=60; break; case 1: INPUT[ i]=56; break; case 2: INPUT[ i]=52; break;

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76 Appendix B (Continued) case 3: INPUT[ i]=48; break; case 4: INPUT[ i]=44; break; case 5: INPUT[ i]=40; break; case 6: INPUT[ i]=36; break; case 7: INPUT[ i]=32; break; case 8: INPUT[ i]=28; break; case 9: INPUT[ i]=24; break; case 10: INPUT[ i]=20; break; case 11: INPUT[ i]=16; break; case 12: INPUT[ i]=12; break; case 13: INPUT[ i]=8; break; case 14: INPUT[ i]=4; break; case 15:

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77 Appendix B (Continued) INPUT[ i]=0; break; default: break; } } return 0; } void Clock(void) { //CLOCK THE PART : Change bit 0 of Byte 5 others left alone tkvx4801_setOutputData (VXI4801, tkvx4801_BYTE5, tkvx4801_SET_BIT_LOW, 0); tkvx4801_outputData (VXI4801, tkvx4801_NORMAL_COMMAND, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT); tkvx4801_setOutputData (VXI4801, tkvx4801_BYTE5, tkvx4801_SET_BIT_HIGH, 0); tkvx4801_outputData (VXI4801, tkvx4801_NORMAL_COMMAND, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT); tkvx4801_setOutputData (VXI4801, tkvx4801_BYTE5, tkvx4801_SET_BIT_LOW, 0); tkvx4801_outputData (VXI4801, tkvx4801_NORMAL_COMMAND, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_NO_OUTPUT, tkvx4801_MASKED_OUTPUT); //END CLOCK THE PART return; } [Project Header] Version = 501 Platform Code = 4 Pathname = "/c/Paris/ASIC 42MX/ASIC 42MX.prj" CVI Dir = "/c/ cvi"

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78 Appendix B (Continued) VXIplug&play Framework Dir = "/C/VXIPNP/win95" Number of Files = 6 Sort Type = "No Sort" Target Type = "Executable" Flags = 17 Drag Bar Left = 232 Window Top = 69 Window Left = 49 Window Bottom = 378 Window Right = 605 [File 0001] File Type = "Include" Path = "/c/Paris/ASIC 42MX/ASIC.h" Res Id = 1 Exclude = False Disk Date = 3074018746 Project Flags = 0 Window Top = 71 Window Left = 30 Window Height = 0 Window Width = 0 Source Window State = "1,0,0,0,0,0,0,0,0,65,0,0,0,0,0,18,0,0,0,0," [File 0002] File Type = "User Interface Resource" Path = "/c/Paris/ASIC 42MX/ASIC.uir" Res Id = 2 Exclude = False Disk Date = 3074018746 Project Flags = 0 Window Top = 94 Window Left = 42 Window Height = 309 Window Width = 556 [File 0003] File Type = CSource" Path = "/c/Paris/ASIC 42MX/ASIC 42MX.c" Res Id = 3 Exclude = False Disk Date = 3074098788 Project Flags = 0 Window Top = 23 Window Left = 0 Window Height = 0 Window Width = 0 Source Window State = "1,214,214,214,0,2032,0,1,0,76,0,1,0,1,0,18,76,0,84,0," Header Dependencies = "1,2,3,4,5,6,7,9,18,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35," [File 0004] File Type = CSource"

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79 Appendix B (Continued) Path = "/c/Paris/ASIC 42MX/ASIC 42MX support.c" Res Id = 4 Exclude = False Disk Date = 3073994964 Project Flags = 0 Window Top = 23 Window Left = 0 Window Height = 0 Window Width = 0 Source Window State = "1,0,0,0,0,0,0,0,0,76,0,0,0,0,0,18,100,0,109,23," Header Dependencies Line0001 = "1,2,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31," Header Dependencies Line0002 = "32,33,34,35," [File 0005] File Type = "Include" Path = "/c/Paris/ASIC 42MX/ASIC 42MX support.h" Res Id = 5 Exclude = False Disk Date = 3073994526 Project Flags = 0 Window Top = 30 Window Left = 30 Window Height = 0 Window Width = 0 Source Window State = "1,0,0,0,0,0,0,0,0,65,0,0,0,0,0,18,0,0,13,50," [File 0006] File Type = "Function Panel" Path = "/c/VXIPNP/Win95/Tkvx4801/Tkvx4801.fp" Res Id = 6 Exclude = False Disk Date = 2977141450 Project Flags = 0 Window Top = 0 Window Left = 0 Window Height = 0 Window Width = 0 [Compiler Options] Default Calling Convention = cdecl" Max Number Of Errors = 10 Require Prototypes = True Require Return Values = True Enable Pointer Mismatch Warning = False Enable Unreachable Code Warning = False Track Include File Dependencies = True Prompt For Missing Includes = True Stop On First Error File = False Bring Up Err Win For Warnings = True Show Build Dialog = False

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80 Appendix B (Continued) [Run Options] Stack Size = 250000 Debugging Level = "Standard" Save Changes Before Running = "Ask" Break On Library Errors = True Hide Windows = False Unload DLLs After Each Run = True Check Disk Dates Before Each Run = True Break At First Statement = False [Build Options] DLL Debugging Level = "None" [Compiler Defines] Compiler Defines = "/DWIN32_LEAN_AND_MEAN" [Command Line Args] Command Line Args = "" [Included Headers] Header 0004 = "/c/Paris/ASIC 42MX/ASIC.h" Header 0035 = "/c/Paris/ASIC 42MX/ASIC 42MX support.h" Header 0001 = "/c/ cvi/include/ cvirte.h" Header 0002 = "/c/ cvi/include/ cvidef.h" Header 0003 = "/c/ cvi/include/ userint.h" Header 0005 = "/c/VXIPNP/Win95/Include/Tkvx4801.h" Header 0006 = "/c/ cvi/include/ vpptype.h" Header 0007 = "/c/ cvi/include/ visatype.h" Header 0008 = "/c/ cvi/include/ visa.h" Header 0009 = "/c/ cvi/include/ ansi/ stdarg.h" Header 0010 = "/c/ cvi/include/ nivxi.h" Header 0011 = "/c/ cvi/include/ datasize.h" Header 0012 = "/c/ cvi/include/ busacc.h" Header 0013 = "/c/ cvi/include/ devinfo.h" Header 0014 = "/c/ cvi/include/ sysint.h" Header 0015 = "/c/ cvi/include/ trig.h" Header 0016 = "/c/ cvi/include/ vxiint.h" Header 0017 = "/c/ cvi/include/ ws.h" Header 0018 = "/c/ cvi/include/ utility.h" Header 0019 = "/c/ cvi/include/ gpib.h" Header 0020 = "/c/ cvi/include/ ansi_c.h" Header 0021 = "/c/ cvi/include/ ansi/ assert.h" Header 0022 = "/c/ cvi/include/ ansi/ ctype.h" Header 0023 = "/c/ cvi/include/ ansi/ errno.h" Header 0024 = "/c/ cvi/include/ ansi/ float.h" Header 0025 = "/c/ cvi/include/ ansi/ limits.h" Header 0026 = "/c/ cvi/include/ ansi/ locale.h" Header 0027 = "/c/ cvi/include/ ansi/ math.h" Header 0028 = "/c/ cvi/include/ ansi/ setjmp.h" Header 0029 = "/c/ cvi/include/ ansi/ signal.h" Header 0030 = "/c/ cvi/include/ ansi/ stddef.h" Header 0031 = "/c/ cvi/include/ ansi/ stdio.h"

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81 Appendix B (Continued) Header 0032 = "/c/ cvi/include/ ansi/ stdlib.h" Header 0033 = "/c/ cvi/include/ ansi/ string.h" Header 0034 = "/c/ cvi/include/ ansi/ time.h" Max Header Number = 35 [Create Executable] Executable File = "" Icon File = "" Application Title = "" DLL Exports = "Include File Symbols" DLL Import Library Choice = Gen Lib For Current Mode" Use VXIPNP Subdirectories for Import Libraries = False Use Dflt Import Lib Base Name = True Where to Copy DLL = "Do not copy" Add Type Lib To DLL = False Include Type Lib Help Links = False Type Lib FP File = "" Type Lib Guid = "" Instrument Driver Support Only = False [External Compiler Support] Create UIR Callbacks File = False Using LoadExternalModule = False Create Project Symbols File = True UIR Callbacks Obj File = "" Project Symbols H File = "" Project Symbols Obj File = "" [DLL Debugging Support] External Process Path = "" User Interface Resource (UIR) Include File /**************************************************************************/ /* LabWindows/CVI User Interface Resource (UIR) Include File */ /* Copyright (c) National Instruments 2001. All Rights Reserved. */ /* */ /* WARNING: Do not add to, delete from, or otherwise modify the contents */ /* of this include file. */ /**************************************************************************/ # include < userint.h> # ifdef __ cplusplus extern "C" { # endif /* Panels and Controls: */ # define PANEL 1

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82 Appendix B (Continued) # define PANEL_COMMENTS 2 # define PANEL_INPUT_16 3 # define PANEL_INPUT_15 4 # define PANEL_INPUT_14 5 # define PANEL_INPUT_13 6 # define PANEL_INPUT_12 7 # define PANEL_INPUT_11 8 # define PANEL_INPUT_10 9 # define PANEL_INPUT_9 10 # define PANEL_INPUT_8 11 # define PANEL_INPUT_7 12 # define PANEL_INPUT_6 13 # define PANEL_INPUT_5 14 # define PANEL_INPUT_4 15 # define PANEL_INPUT_3 16 # define PANEL_INPUT_2 17 # define PANEL_INPUT_1 18 # define PANEL_Start 19 /* callback function: start */ # define PANEL_Stop 20 /* callback function: stop */ # define PANEL_OUTPUT_FT 21 # define PANEL_OUTPUT_C 22 # define PANEL_OUTPUT_B 23 # define PANEL_OUTPUT_A 24 # define PANEL_Reset 25 /* callback function: reset */ # define PANEL_COMMANDBUTTON 26 /* callback function: quit */ # define PANEL_LED_16 27 # define PANEL_LED_15 28 # define PANEL_LED_14 29 # define PANEL_LED_13 30 # define PANEL_LED_12 31 # define PANEL_LED_11 32 # define PANEL_LED_10 33 # define PANEL_LED_9 34 # define PANEL_LED_8 35 # define PANEL_LED_7 36 # define PANEL_LED_6 37 # define PANEL_LED_5 38 # define PANEL_LED_4 39 # define PANEL_LED_3 40 # define PANEL_LED_2 41 # define PANEL_LED_1 42 /* Menu Bars, Menus, and Menu Items: */ /* ( no menu bars in the resource file) */ /* Callback Prototypes: */ int CVICALLBACK quit( int panel, int control, int event, void callbackData, int eventData1, int eventData2);

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83 Appendix B (Continued) int CVICALLBACK reset( int panel, int control, int event, void callbackData, int eventData1, int eventData2); int CVICALLBACK start( int panel, int control, int event, void callbackData, int eventData1, int eventData2); int CVICALLBACK stop( int panel, int control, int event, void callbackData, int eventData1, int eventData2); # ifdef __ cplusplus } # endif


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Fault tolerant design verification through the use of laser fault injection
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by Paris D. Wiley.
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[Tampa, Fla.] :
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2004.
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Thesis (M.S.E.E.)--University of South Florida, 2004.
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ABSTRACT: Laser Fault Injection (LFI) testing has been demonstrated to be a useful tool in the prediction of single event upset rates in microcircuits. In addition LFI has contributed to the basic understanding of the mechanisms that cause single event upsets. However, very little research has been performed on the viability of LFI as a tool for verifying fault tolerant designs incorporated in ASICs, FPGAs, microprocessors and embedded systems. Current fault tolerant design verification techniques such as simulation and test have several significant limitations that prevent the complete verification of a fault tolerant design. However, LFI possesses spatial, temporal and financial advantages related to its use, which are very beneficial. This thesis presents results of the fault tolerance verification tests that were performed using laser fault injection on a four-bit fault tolerant filter that was implemented in a commercial FPGA.
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