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High level VHDL modeling of a low-power ASIC for a tour guide

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High level VHDL modeling of a low-power ASIC for a tour guide
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Kailasam, Umadevi
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Subjects / Keywords:
translators
leakage power
behavioral synthesis
location-aware computing
navigator
Dissertations, Academic -- Computer Engineering -- Masters -- USF   ( lcsh )
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government publication (state, provincial, terriorial, dependent)   ( marcgt )
bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

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Summary:
ABSTRACT: We present the high level (VHDL) modeling and high level synthesis of an ASIC (TOUR NAVIGATOR) for a portable hand held device - a tour guide. The tour guide is based on location-aware mobile computing, which gives the information of the current location to the user. The TOUR NAVIGATOR designed in this work is interfaced with off-the-shelf components to realise the tour guide system. The current location is given by an on-board GPS receiver chip. The TOUR NAVIGATOR is a search and play module which interfaces with the flash memory, GPS receiver and the audio codec. The functionality of the TOUR NAVIGATOR is to search the flash memory for audio data corresponding to the current GPS co-ordinate, which is an input to the TOUR NAVIGATOR. The look-up table containing the GPS coordinates and the corresponding audio files are loaded into the flash memory, where in each GPS entry in the table is indexed by the co-ordinates, and an audio file that contains information about the locations is associated with it. When there is a match, the audio file is streamed to the codec. The functionality of the interface of the TOUR NAVIGATOR with the memory module is verified at the RTL using Cadence-NCLaunch. The layout implementation of the TOUR NAVIGATOR is done using an automatic place and route tool (Silicon Ensemble), which uses standard cells for the entire design. Leakage power reduction is done by introducing sleep transistors in the standard cells. The TOUR NAVIGATOR is put into a "sleep" mode when there is no operation of the tour guide, thus giving significant power savings.
Thesis:
Thesis (M.S.Cp.E.)--University of South Florida, 2004.
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Includes bibliographical references.
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by Umadevi Kailasam.
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Document formatted into pages; contains 102 pages.

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High level VHDL modeling of a low-power ASIC for a tour guide
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ABSTRACT: We present the high level (VHDL) modeling and high level synthesis of an ASIC (TOUR NAVIGATOR) for a portable hand held device a tour guide. The tour guide is based on location-aware mobile computing, which gives the information of the current location to the user. The TOUR NAVIGATOR designed in this work is interfaced with off-the-shelf components to realise the tour guide system. The current location is given by an on-board GPS receiver chip. The TOUR NAVIGATOR is a search and play module which interfaces with the flash memory, GPS receiver and the audio codec. The functionality of the TOUR NAVIGATOR is to search the flash memory for audio data corresponding to the current GPS co-ordinate, which is an input to the TOUR NAVIGATOR. The look-up table containing the GPS coordinates and the corresponding audio files are loaded into the flash memory, where in each GPS entry in the table is indexed by the co-ordinates, and an audio file that contains information about the locations is associated with it. When there is a match, the audio file is streamed to the codec. The functionality of the interface of the TOUR NAVIGATOR with the memory module is verified at the RTL using Cadence-NCLaunch. The layout implementation of the TOUR NAVIGATOR is done using an automatic place and route tool (Silicon Ensemble), which uses standard cells for the entire design. Leakage power reduction is done by introducing sleep transistors in the standard cells. The TOUR NAVIGATOR is put into a "sleep" mode when there is no operation of the tour guide, thus giving significant power savings.
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HighLevelVHDLModelingofaLow-PowerASICforaTourGuide by UmadeviKailasam Athesissubmittedinpartialfulllment oftherequirementsforthedegreeof MasterofScienceinComputerEngineering DepartmentofComputerScienceandEngineering CollegeofEngineering UniversityofSouthFlorida MajorProfessor:SrinivasKatkoori,Ph.D. MuraliVaranasi,Ph.D. SanjuktaBhanja,Ph.D. DateofApproval: March29,2004 Keywords:Location-awarecomputing,BehavioralSynthesi s,Leakagepower,Translators, NAVIGATOR cCopyright2004,UmadeviKailasam

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DEDICATION Tomyparents,family,andfriends

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ACKNOWLEDGEMENTS IwouldliketothankDr.SrinivasKatkooriforprovidingmet heopportunitytobeapart ofhisresearchteam.Hisconstantencouragementandsuppor tprovidedmethecondencetodo thisthesisworkefciently.IwouldliketothankDr.Murali VaranasiandDr.SanjuktaBhanja forbeingonmycommittee.Iwouldliketoextendmyspecialth ankstoViswanathSairaman, NarenderHanchate,andRanganathGopalanforhelpingmewhe neverIwasstuckupwithsome problem.IwouldliketothankmyfriendsintheVCAPPgroupan doutside,forprovidingmethe encouragementtodothisgoodpieceofwork.

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TABLEOFCONTENTS LISTOFTABLES iii LISTOFFIGURES iv ABSTRACT vi CHAPTER1INTRODUCTION 1 1.1Motivation 1 1.2Context-AwareMobileComputing 2 1.3Location-awareComputing 3 1.4DesignFlowofanASIC 4 1.5PowerDissipationisCMOSCircuits 6 1.5.1DynamicPowerDissipation 7 1.5.2ShortCircuitPowerDissipation71.5.3LeakagePowerDissipation 8 1.5.4ProposedApproach 8 1.5.5ThesisOrganization 10 CHAPTER2LOCATION-AWAREMOBILECOMPUTINGANDPOWEROPTIMI ZATIONINASICS 11 2.1Location-awareMobileComputing 11 2.1.1PersonalShoppingAssistant 11 2.1.2Location-basedAgentAssistance122.1.3comMotion 13 2.1.4ElectronicTouristGuide 14 2.1.5CyberGuide 15 2.2PowerOptimizationTechniques 17 2.2.1DynamicPowerOptimization 17 2.2.1.1ClockGating 17 2.2.1.2Precomputation 19 2.2.1.3GuardedEvaluation222.2.1.4Retiming 24 2.2.1.5MultipleClocking 25 2.2.2LeakagePowerOptimization 27 2.2.2.1InputVectorControl272.2.2.2PowerGating 28 2.2.2.3TransistorStacking 30 2.3Summary 32 i

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CHAPTER3MOBILEINTERACTIVEGUIDE 33 3.1HighLevelModelingofNAVIGATOR 33 3.1.1GPSReceiver 35 3.1.2USBPort 35 3.1.3FlashMemory 35 3.1.4AudioCODEC 35 3.2BriefDescriptionoftheFlashMemory 35 3.2.1FAT16Drive 38 3.3FunctionalityofTOURNAVIGATOR 39 3.4NAVIGATORDesign 40 3.5DesignofMemoryModule 44 3.6ToolsUsed 44 3.6.1HighLevelModelinginVHDL443.6.2AUDI 45 3.6.3SIS 46 3.6.4SiliconEnsemble 48 3.6.5CadenceVirtuosoLayoutEditor493.6.6Translators 49 3.6.6.1VHDLtoKISSTranslator503.6.6.2BDNETtoVerilogTranslator503.6.6.3VHDLtoVerilogTranslator503.6.6.4StepstoGeneratetheLayout513.6.6.5FunctionalityofBack-endTool51 3.7LeakageReductionUsingLow-LeakageStandardCells54 3.7.1Leakage-DelayTradeoff 56 3.7.2Summary 57 CHAPTER4EXPERIMENTALRESULTS 58 4.1DesignFlow 58 4.1.1BehavioralLevelSimulationResultsfortheASICDesi gn59 4.1.2Low-LeakageStandardCells 60 4.2RealWorldApplications 60 4.3LayoutsGeneratedbyBackEndTool 64 4.4Summary 64 CHAPTER5CONCLUSIONSANDFUTURERESEARCH68 5.1FutureResearch 68 REFERENCES 69 APPENDICES 71 AppendixABehavioralVHDLCodeofNAVIGATOR72 ii

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LISTOFTABLES Table2.1.ComparisonofProposedApproachwithPreviousAp proaches16 Table4.1.LeakagePowerSavingsinStandardCells63Table4.2.DelayOverheadDuetoSleepTransistorinStandar dCells63 Table4.3.LeakagePowerSavingsinRealWorldApplications 63 Table4.4.AreaOverheadinRealWorldApplications64 iii

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LISTOFFIGURES Figure1.1.ASICDesignLifeCycle 5 Figure1.2.ProposedTourGuide 9 Figure1.3.ModelofInterfacebetweenNAVIGATORandFlashM emory9 Figure2.1.PersonalShoppingAssistantService.Reproduc edFrom[1]12 Figure2.2.AgentInteractionDiagram.ReproducedFrom[2] 13 Figure2.3.ArchitectureofcomMotionShowingtheThreeDif ferentModules.ReproducedFrom[3] 14 Figure2.4.Gated-ClockArchitecture 18 Figure2.5.OriginalCircuit 20 Figure2.6.FirstPrecomputationArchitecture 20 Figure2.7.SecondPrecomputationArchitecture 21 Figure2.8.CircuitwithoutGuardLatches 22 Figure2.9.CircuitwithGuardLatches 23 Figure2.10.Flip-opAdditiontoCircuit 24 Figure2.11.RepositioningtheFlip-opsinaPipeline25Figure2.12.OriginalCircuit 25 Figure2.13.PartitionedCircuit 26 Figure2.14.MultipleClockingScheme 26 Figure2.15.ModiedLatcheswithOptimumSleepValues(0an d1)28 Figure2.16.MTCMOSLatchCircuit 29 Figure2.17.TwoInputNANDGate.Turning“off”M1andM2rais estoPositive ValueCausingthe“StackingEffect” 31 Figure2.18.LECTORTechnique 32 Figure3.1.MobileInteractiveCampusTourGuide 34 iv

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Figure3.2.OverallBlockDiagramoftheSystemDesign34Figure3.3.CompactFlashMemoryCardBlockDiagram36Figure3.4.DiagramshowingthePinInterfaceofNAVIGATORw ithFlashMemoryCard40 Figure3.5.FlowchartwithStepsinvolvedintheNAVIGATORD esign41 Figure3.6.SignalsthatInterfacebetweenNAVIGATORandFl ashMemoryCard42 Figure3.7.RTLevelDesigngivenbyAUDI 45 Figure3.8.ControllerStateMachineinAUDI 46 Figure3.9.SteptoDesignandSynthesizeaLowPowerSystem5 2 Figure3.10.OverallDataFlowDiagramofSynthesisofDesig n53 Figure3.11.StandardCellwithSleepTransistor 55 Figure3.12.LeakagePowerVsTransistorWidth 56 Figure3.13.DelayVsTransistorWidth 56 Figure4.1.BehaviorofASICwhen`go'SignalisAsserted61Figure4.2.SerialAudioDataOutputwhenthereisaMatch62Figure4.3.GeneratedLayoutforIIRFilter 65 Figure4.4.GeneratedLayoutforDCTApplication 66 Figure4.5.GeneratedLayoutforFFTApplication 67 v

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HIGHLEVELVHDLMODELINGOFALOW-POWERASICFORATOURGUIDE UmadeviKailasam ABSTRACT Wepresentthehighlevel(VHDL)modelingandhighlevelsynt hesisofanASIC(TOUR NAVIGATOR)foraportablehandhelddevice-atourguide.The tourguideisbasedonlocationawaremobilecomputing,whichgivestheinformationofthec urrentlocationtotheuser.The TOURNAVIGATORdesignedinthisworkisinterfacedwithoffthe-shelfcomponentstorealise thetourguidesystem.ThecurrentlocationisgivenbyanonboardGPSreceiverchip.The TOURNAVIGATORisasearchandplaymodulewhichinterfacesw iththeashmemory,GPS receiverandtheaudiocodec.ThefunctionalityoftheTOURN AVIGATORistosearchtheash memoryforaudiodatacorrespondingtothecurrentGPSco-or dinate,whichisaninputtothe TOURNAVIGATOR.Thelook-uptablecontainingtheGPScoordi natesandthecorresponding audiolesareloadedintotheashmemory,whereineachGPSe ntryinthetableisindexedbythe co-ordinates,andanaudiolethatcontainsinformationab outthelocationsisassociatedwithit. Whenthereisamatch,theaudioleisstreamedtothecodec.ThefunctionalityoftheinterfaceoftheTOURNAVIGATORwit hthememorymoduleisveried attheRTLusingCadence-NCLaunch.Thelayoutimplementati onoftheTOURNAVIGATORis doneusinganautomaticplaceandroutetool(SiliconEnsemb le),whichusesstandardcellsforthe entiredesign.Leakagepowerreductionisdonebyintroduci ngsleeptransistorsinthestandard cells.TheTOURNAVIGATORisputintoa“sleep”modewhenther eisnooperationofthetour guide,thusgivingsignicantpowersavings. vi

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CHAPTER1 INTRODUCTION Inrecenttimesmobileapplicationssuchashand-helddevic es,PDA,etc.havegainedwide acceptanceallowingtheusertomovearoundwithcomputingc apabilityandnetworkresources. Manydevicesthatarerecentlydevelopedareconceivedwith mobilecapabilityastheirprimary objective.Performanceisthemainfocusoftheseapplicati ons,whereresponsetimeisthemajor objective.Suchisthecasewithprocessorswhicharemainly builtforspeedandperformance.Other applicationssuchasinexpensivemobilechipsthatarewide lyusedmainlyfocusonfunctionality ratherthanperformance.Thespecicfunctionperformedby thedevicenottypicallyfoundin processorsordevicesbasedonperformance,becomesthenee dfortheuser.Inthecontextof context-awarecomputing,wedevelopanapplicationthatis focusedonfunctionalitydesiredbythe userbytradingoffwithperformance.1.1Motivation Mobilecomputingisarapidlyevolvingeldthatgivestheus erthepowerandpotentialto accessanyinformationonthemove.Nowadayswebbrowsingis carriedoutviamobiledevices. Thereductionintheuseofapplicationsandcomputersinast aticenvironmenthasledtoaenormous changeintrendinthedomainofmobilecomputing.Dynamicen vironmenthasbecomeamajor areaofresearchtoimprovethequalityofmobileapplicatio nsthatenableuserstoaccessanykind ofinformationfromanylocation.Insuchanenvironment,th ephysicalconnectionsbetweenthe hostandthenetworktobeconnectedshouldbeconstantlyrec omputed.Today'stechnologyand softwareprogressesmustadapttosuchaconstantlychangin gbehaviorofthesystem. Allthemobileapplicationsarebasedontheconceptofconte xt-awarecomputing,whichis characterizedbytheabilityofanapplicationtoadaptitsb ehaviortotheconstantlychangingenvironmentalfactorswithleastcontroloverthem.Today'simp rovementandadvancesintechnology 1

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andsoftwareisenablingeasieradaptationtothechangingu ser'srequestsandenvironment.The contextualinformationthatisexploitedinsuchapplicati onsaretheuser'slocation,thephysical factorsandinformationssurroundingtheuser,theuser'sc urrentactivityandthetimeoftheday. Howeverthereisaconstraintontheuser'srequesttoobtain informationpertainingtotheuser's locationandwirelesscommunication. VLSIdesigntechnologyhasadvancedatahighlevelintheimp lementationofmobiledevices, withhighperformanceandlowpowerdissipationatanoptima lcost.Itprovidestheabilityto integratemixed,analoganddigitalsignalsonasinglechip .Thereisscopeforanentiremobile applicationtoberealizedonasinglechip.Torealizethese applications,itisimportanttohavea systemtoconvertalargenumberofbehavioraldescriptiono fthesemobiledeviceswithvarious user'sneedsandrequests,intoitsphysicalimplementatio nwithoutmuchofuserinterventionin themiddlestages. Hencethemotivationofthiswork,istoprovidetheuserwith aspecicfunctionalitythatis basedonlyonhislocationandtorealizethephysicalimplem entationofitwithnouserintervention.Thefollowingsectionsgiveanoverviewoftheconcept sandfeaturesusedindevelopingthis application.1.2Context-AwareMobileComputing Portablecomputersandwirelesscommunicationdeviceshav ebecomeamajorpartofourdayto-daylifeenablingpeopletoaccesstheirpersonalinform ation,publicresources,andcorporate dataatanytimeinanylocation.Context-awarecomputingis amobilecomputingparadigm[4] inwhichapplicationscandiscoverandtakeadvantageofcon textualinformation.Thecontextual informationthatisprimarilyavailablefordesigningsyst emsare,entity,location,time,andactivity oftheuser.Theseinformationsenablestheapplicationsto predictthepresentsituationandsurroundingenvironmentoftheusertoprovidehimwithmoreser vices.Schilit[5]givesdenitions forcontext-awareapplicationsasfollows: 1. n:Thisisatechniqueofuser-interfacewherethelocationof nearby objectsareemphasized. 2

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2. n :Thisisaprocess,wherenewcomponentsare addedbyremovingtheexistingcomponentsorbyalteringthe connectionsbetweencomponents duethechangeincontext. 3. n :Thisdependsonthecontextinwhichtheyare issuedandproducesdifferentresultsaccordingly. 4. :Thesearesimpleruleswhichemphasizeonhowthecontextawaresystemshouldadapttothecontext. Chengivesadifferentperspectiveonhowamobileapplicati onshouldtakeadvantageofavailablecontextandgivestwodenitionsofcontextawarecompu ting[4]: :anapplicationautomaticallyadaptstodiscoveredcontex t,by changingtheapplication'sbehavior. :anapplicationpresentstheneworupdatedcontexttoanint eresteduserormakesthecontextpersistentfortheusertoret rievelater. Givenacontext,whetheractiveorpassive,itdependsonhow thecontextisusedintheapplication.Efcientuseofthecurrentavailablecontextua linformationinapplicationsisstilla challengingproblemindevelopingapplications.Activeco ntext-awarecomputingisinteresting andimportantasitpaveswayforthedesignofnewmobiledevi cesthatrequiremoreinfrastructure support.Inthiswork,wefocusondesigninganapplicationt hatprovidesservicesbysensingthe location(activecontext)oftheuser1.3Location-awareComputing Theuser'slocationplaysasignicantroleinimplementing suchportabledevices.Location awarenessisanemergingtrendinmobilecomputing.Locatio nisanimportantcontextthathasto beupdatedwhenevertheusermakesamove.Thisleadstoaneed forareliableposition-tracking systemwhichisacriticalcomponentofmanycontext-awarea pplications. Locationawarenessistakenadvantagebysystemsthatareaw areofwheretheyarelocated. Therearetwotypesoftechniquestoobtainlocationawarene ss[6],namely, n ,andn positioning.Applicationsusingabsolutepositioningare awareoftheactuallocation:eitherthecoordinatesorthebuilding,city,orcountryoftheuser.GPS( GlobalPositioningSystem),GSM 3

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(GlobalSystemforMobilecommunicationtogetherwithMPS( MobilePositioningSystem)[6]are sometechnologiesusedforabsolutepositioning.Relative locationontheotherhand,isawareof whatotherobjectsareincloseproximity.Whenusingrelati vepositioninginanapplication,the objectscanbemovedaround.Thesystemshouldrecognizeoth erobjectswithoutdependingon wherethedeviceislocated. Thelocationoftheusermustbedecipheredbysensingonwhet hertheuserisoutdoororindoor. Themostcommonchoiceforoutdoorpositioningsystemisthe GlobalPositioningSystem(GPS). TheGPSsignaldoesnotworkindoorasthesignalstrengthist oolowtopropagatethroughthe buildings.Itisachallengingproblemtobuildanindoorloc ationsensorthatprovidesne-grain informationatahighupdaterate.Fewapplicationssuchast hePersonalShoppingAssistant[1] developedattheHewlett-PackardLaboratories,isbasedon theRadioFrequencyIdentication (RFID)technologywhichallowsthereadingofspeciclabel sattachedtoproductsandpackages bymeansofradiosignals.TheCyberGuideproject[7]hasbui ltanindoortrackingsystembased oninfrared(IR).1.4DesignFlowofanASIC ThemainstagesinthedesigncycleforanASICaredesignentr y,functionalsimulation,physicallayout,testsimulation,anddesignvericationbefore releasingthedesignforfabrication.These stagesarethesameirrespectiveofthetechnologyusedinth eASICdesign.ACADsystemprovidesasuiteoffacilities[8]andstepsthatareintegrated tosupportallthesestageswithaproper combinationofautomaticanduser-controlledprocessinga teachstage.TheCADsystemhasdefaultoptionsatmanystages,whichthedesignermaychooseo rignoreifnecessaryateachstage. TheentryformatgivenforadesigntotheCADsystemiscompil edtoasetofschematicsoraprograminahardwaredescriptionlanguage(HDL),toaninterme diatedesignlanguage(IDL)thatis usedforsimulationandphysicalplacement.Thephysicalpl acementprocesscomprisesofseveral stepsthatleadstoalayer-by-layerdescriptionoftheASIC network. Powerconsumptionhasbecomeanimportantparameteralongw itharea,speedandtestability inthedesignofVLSIcircuits.Today'sASICDesignersarefa cingacommondilemmawiththe productspecicationinonehandthatstatesthatthedesign mustconsumetheminimumpower 4

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Figure1.1.ASICDesignLifeCycle requirementssoastomeetthegoalsofreliability,costand energyefciency,andthefunctional specicationontheotherhandwhichimpliesthattheASICsm ustintegratemorecircuitryand thespeedshouldbefastertoimplementthedesiredfunction ality,thatincreasestheoverallpower consumption.Adecadeago,whenpowerconsumptionwasnotth emajorconstraintASICswere designedwithmoreimportancetospeedanddesignconstrain tsaslargepackages,coolingfansand nshavebeencapableenoughtodissipatethegeneratedheat .Thedifcultyinprovidingthenecessarycoolingduetotheincreaseinchipdensityandchipsize mayresultinsignicantcostoverhead orlimitthesystemfunctionalitythatcanbeprovided.This makestheneedofahigh-throughput, low-powerdigitalsystemsveryevident.Today'sdesigners ,duetotheunavoidablenecessitytoreducepowerconsumptionadoptdesignmethodologiesandtech niquesatdifferentabstractionlevels toreducepowerconsumption.Theseabstractionlevelsarea ttechnology,circuit,logic,architectureandsystem.Substantialminimizationofpowerconsump tionrequirespower-awaredecisions thataremadeateachlevelofdesignabstraction.MOStechno logyhasscaleddownto0.2micro minimumfeaturesizethatincreasesthepossibilityofplac ing1Xtransistorsinanareaof8 5

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inx10inifahigh-densitytechnologyisused[9].Forhigh-p erformancemicroprocessor,anincreaseintheamountofon-chipmemorywouldbestutilizethe increasedcapabilityoftransistors. Theproliferationofpersonaldigitalassistantsandporta bledeviceshasincreasedthedemandof designinglowpowerASICs.Highperformanceandlow-powerc onsumptionhasbecomeamajor problemconfrontedbymostportabledevices.Energyminimi zationisoneofthemostimportant metricsinthedesignofaportablesystem.Thebatterycapac ityplaysamajorroleinthepower consumptionofportablesystems.Ithasimprovedataverysl owerrate(afactoroftwoorfour)in thepast35yearswherethecomputationaldemandshaveincre aseddrasticallyoverthesametime. Henceportablesystemsarehighlypower-constrainedwitha nefforttoincreasethebatterylifeand reducethebatteryweight.Anotherimportantconsideratio nthatshouldbetakenintoaccountin portableapplicationsisthatmanycomputationtasksarere al-timesuchasspeechrecognitionthat alwaysrequiresthecomputationsatnear-peakrates.Theco nventionalwayofshuttingdownthe powerisnotanappropriatesolutionforsuchapplicationst hatalwaysrequireactivecomputations. Thedegreeoffreedomindesignthatisavailableinimplemen tingthesefunctionsisthatasthereal timerequirementsoftheseapplicationsaresatised,ther eisnoeffectinincreasingthecomputationalthroughput.Thisfactalongwiththeunlimitednumbe roftransistorsthatcanbeused,leads todevelopinganarchitecturaldesignthatcanshowsignic antsavingsinpowerdissipation. 1.5PowerDissipationisCMOSCircuits ThethreemajorsourcesofpowerdissipationinCMOScircuit sarerepresentedbythefollowing equation: n r r (1.1) (1.2) Thersttermdenotestheswitchingcomponentofpower,whic hisduetotheswitchingtransientcurrentandthecharginganddischargingofloadcapac itances. istheloadingcapacitance, istheclockfrequency, isthesupplyvoltage,Visthevoltageswingthatisthesamea sthat ofthesupplyvoltage,and istheactivityfactorthatgivestheprobabilitythatapowe rconsuming transitionoccurs.Thesecondtermdenotesthedirect-path shortcircuitcurrent whichiscurrent 6

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thatowsfromthesupplytogroundwhenboththePMOSandtheN MOStransistorsaresimultaneouslyturnedON.Thethirdtermdenotestheleakagecurren t,,whichisduetothereverse biasleakagebetweendiffusionregionsandthesubstrate,a ndsub-thresholdconduction.Therst termcontributestodynamicpowerdissipationandthesecon dandthirdtermscontributetostatic powerdissipation.1.5.1DynamicPowerDissipation TheswitchingactivityinaCMOScircuitthatgivesrisetoth edynamiccomponentofpower consumptioniswhenthePMOStransistorschargetheloadcap acitance tomakeatransition from0to whichisthehighestvoltagelevel.Ontheviceversa,forthe to0transition attheoutput,thereisnochargethatisdrawnfromthesupply ,thestoredenergyinthecapacitor isdissipatedinthepull-downNMOStransistor.Thepowerdr awnfromthesupplyisgivenby ifthetransitionsoccurforaclockfrequencyof Fromtheequation(1.2),itisseenthatpowerdissipatedisp roportionaltothesquareofthe supplyvoltage.Hencethemostdirectwaytoreducepowerisb yreducingthesupplyvoltage.A reductioninthevoltagebyafactoroftworesultsintheredu ctionofpowerbyafactoroffour.The disadvantageinthismethodisthatthecircuitdelayincrea sesconsiderably. 1.5.2ShortCircuitPowerDissipation Thereisadirectcurrentpathbetweenthesupplyandgroundd uringniteriseandfalltimes thatexistsforashortperiodoftimeduringswitching.This conditionariseswhenboththeNMOS andPMOSdevicesaresimultaneouslyONcreatingaconductiv epathbetweenthe andGND. Thiscurrentissignicantwhentheinputriseorfalltimeat agateisgreaterthantheoutputrise orfalltime.Duetothis,theshortcircuitpathwillbeactiv eforalongtimeperiod.Toreducethe shortcircuitcurrent,itisdesirabletomaketheinputrise orfalltimeequaltotheoutputriseorfall time.Thisreducestheshortcircuitpowerconsumptiontobe lessthan10%ofthetotaldynamic powerofthecircuit.Theshortcircuitcurrentcanbeelimin atedbyloweringthesupplyvoltage lowerthanthesumofthethresholdsofthetransistors,asbo ththeNMOSandPMOSdeviceswill notbeinthe“ON”stateforanyinputvalues. 7

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1.5.3LeakagePowerDissipation Theleakagecurrentisduetothereverse-biasdiodeleakage onthedrainofthetransistorandthe sub-thresholdleakagecurrentthatowsthroughthechanne lofanoffdevice.Consideraninverter whichisgivenainput`1'.ThisturnsontheNMOStransistorg iving`0'asoutput.Thoughthe PMOStransistorwillbeturnedoff,thebulkofPMOSwillbeat andthedrain-to-bulkvoltage willbeequalto.Thisleadstoacurrentthatistheproductoftheareaofthed raindiffusionand theleakagecurrentdensityandlessdependentonthesupply voltage.Theleakagecurrentdueto diodeleakagebecomessignicantwhenthesystemisidlefor alongtimeasthispowerisdissipated thoughthereisnoswitching.Theleakagepowerduetosub-th resholdleakagecurrentoccurswhen thegatetosourcevoltageisgreaterthantheweakinversion point,butbelowthethresholdvoltage ,thereisacarrierdiffusionbetweenthesourceanddrain.H ence,anoptimal ischosenfor lowvoltageapplicationsthatcontrolsthesub-thresholdv oltage. 1.5.4ProposedApproach Theproposedapproachisthedesignofalocation-awarebase dtourguidewhichhastheinformationaboutallthelocationsofatourplan.TheGlobalP ositingSystem(GPS)isusedas thetrackingcomponenttolocatethecurrentpositionofthe user.Thesystemdoesnotdependon communicationwithanyexternalserver.Thedeviceshownin gure1.2.isbuiltbyintegratingoffthe-shelfcomponentslike,GPSreceiver,Flashmemory,ASI C,USBinterface,andaudioCODEC. ThesearchandplaymoduleisimplementedasanASICwhichint erfacesallthesecomponentsto performthefunctionality.DependingontheGPSco-ordinat esofthecurrentlocation,theASIC searchestheaudiodatacorrespondingtothatlocationinth eFlashmemorycardtoplayoutthe audioinformationtotheoutput. ThebehavioroftheASICandtheFlashmemoryismodeledinthe highlevelusingVHDL toensurethecorrectnessofthefunctionalityasshowning ure1.3..Thedatatobeaccessed inasimilarfashionasinasolidstateashmemorythatusesF AT16lesystem.Thisdesignis synthesizedusingAUDI(AutomaticDesignInstantiation)s ynthesissystemwhichisabehavioral synthesissystem,capableofsynthesizingsuchcontrolint ensiveapplicationsintothecorresponding RTleveldesign. 8

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USB Interface AUDIO START Memory Flash ASIC Codec Audio Receiver GPS Figure1.2.ProposedTourGuide NAVIGATOR (VHDL) FLASH MEMORY (VHDL) DATA IN TEXT FORMAT Figure1.3.ModelofInterfacebetweenNAVIGATORandFlashM emory 9

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ThevalidationofthisdesignisdoneattheRTLusingCadence NCLaunch.Abackendtoolis builttoconverttheRTLsynthesizedoutputgivenbyAUDItot hetransistorlevelphysicalimplementationofthedesign. Leakagepowerforthismobiledeviceiscontrolledbyuseofs leeptransistors.Introductionof sleeptransistorsinthestandardcellsinthestandardcell library,thatisusedtoplaceandroutethe design,theleakagepoweroftheentiredesignisminimizedc onsiderablywithminimaldelay.A techniquetoreducetheleakagepowerbyuseofsleeptransis torsinthecontrollerdesigngenerated byAUDIisalsoproposed.1.5.5ThesisOrganization InChapter2,therelatedworkareaintheareaofcontext-awa recomputingandlogiclevelpower optimizationisdiscussed.InChapter3,theapproachtodes ignandimplementationofASICwith leakagepowerreductionispresentedindetail.InChapter4 ,theexperimentalresultsisdiscussed. InChapter5,theconclusionofthesiswithfutureworkisdis cussed. 10

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CHAPTER2 LOCATION-AWAREMOBILECOMPUTINGANDPOWEROPTIMIZATIONIN ASICS Wepresentadetailedsurveyofsomeofthepriorworkdoneinl ocation-awaremobilecomputing,logiclevelandRTLpoweroptimization(Dynamicpowera ndLeakagepower)techniquesthat havebeenproposedtoreducepowerdissipationinthelogicl evelandRTLlevel.Wealsopresent indetailthenoveltyoftheproposedapplicationinmobilec omputingincomparisontotheexisting applications.Thepoweroptimizationtechniquethatischo sentoobtainthebestpowersavingsfor theproposedapplicationisdiscussedinthenextchapter.2.1Location-awareMobileComputing Mobilecomputinghasstimulatedaradicalrevolution,chan gingourday-to-dayliveswiththe useofpopularsmallhandhelddevicessuchasPDAs,PocketPC setc,whichareembeddedwith substantialprocessingcapabilities.Locationisaveryim portantcontextinmostofthemobile applications.Inthefollowingsection,wedescribesomeof theapplicationsthatarebasedon location-awarecomputing.2.1.1PersonalShoppingAssistant ThePSA[1]isahand-heldwirelesscommunicationdevicewhi chthecustomerowns(provided bytheshoppingcenter)andacentralizedserverlocatedint heshoppingcentertowhichthecustomerscancommunicate.Theservermaintainsthestoreandp roductdatabase,customerprole, andprovidesaudioandvisualoutputforthecustomer'sinqu iriesoverawirelessnetwork. ThePSAconsistsoftwocomponents,namely,thePSAunitwhic hisasmallandlow-cost deviceactingasaterminalforcommunicationandthePSAser verwhichistheheartofthePSA system. 11

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RF CEILING NODES PSA UNIT PSA UNIT Corporate IQ Other Stores and SERVER ASSISTANT SHOPPING USER USER Figure2.1.PersonalShoppingAssistantService.Reproduc edFrom[1] 1. :ThePSAisdifferentfromthePDAnotonlyinitssetofinput/ outputinterfacesbutalsoinitsfunctionalitythatisentirelydepende ntonitsserver.ThePSArelays informationtoandfromthePSAserver.Themicroprocessoro fPSAprocessestheprotocols thatisinvolvedinsettingupavirtualcircuitwiththeserv er,directsmessagestotheoutput devices,performcompression/decompressiononaudioinpu t/output,tagsmessagesfromthe inputdevicesbeforetransmittingtothewirelessinterfac e. 2. :ThePSAservertakestheresponsibilitytoprovidethefunc tionalityofanswering tothequeriesplacedtothePSAunit.Oncetheconnectionise stablished,theserverusesthat identiertoretrievethecustomer'sprolefromitsdataba seandaidinthequeriesplacedby thecustomer.Thetransmitterandreceiverformthewireles snetworksubsystemthatsends andreceivesvoiceandimagestoandfromthePSAunits. 2.1.2Location-basedAgentAssistance Thisapplicationapproacheslocation-basedcomputing[2] bycommunicationwithfourcomponents,namely,theUserAgent,theWherehooserver,Provi derAgents,andProviders.TheUser Agentissuesaqueryconsistingofthelocation,searchradi usandkeywordsrepresentingtheuser's interestandinteractswiththeProviderAgents,theWhereh ooserverisasearchserverthatsearches usingthelocationasitsprimaryinputandthekeywordsasit ssecondaryinput.Businesses,ser12

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vices,attractionsetc.,registeredwiththeWherehooserv erandhaveinternetpresenceformthe Providers.TheProviderAgentsarecontrolledbytheProvid ersandinteractwithUserAgents. Wherehoo server ABC ABC Provider AgentsProviders User Agent residing inthe hand-held device USER Figure2.2.AgentInteractionDiagram.ReproducedFrom[2] ThedisplaydeviceusedbytheUserisa computingappliancethatisequipped withGPSreceiver.IthasawirelessInternetconnection.An agentinthedevicekeepsconstructingqueriesinthebackgrounddependingontheuser'sneeds, queriesandcommunicateswiththe Wherehooserver.TheProviderAgents,dependingontheuser 'swants,retrieveandlterdata accordingtotheuser'swants.Theuser'squeriesareobtain edfromtheuserthroughform-based applicationsonthePalmdevice.Seriesofalertsandplacel istingisusedbytheagenttointeract withtheuser.TheWherehooserverisasearchenginethatret urnsXMLdocumentstakingthe GPScoordinates,searchradius,andkeywordsasinputfromt heuser,geographiclocationofeach Provider'sserviceandadescriptionofhowtoprocessthequ eryofeachoftheProviderAgents. TheUserissuesdirectqueriesafterselectingtheProvider thatmatcheshisinterestintheformof URL's.2.1.3comMotion comMotion[3]isalocation-awarecomputingenvironment,w hichremindstheuseroftheir dutiesdependingontheuser'scurrentlocation,providing bothgeographicalandspeechinterfaces. comMotiontakesintheGPScoordinates(latitudeandlongit ude)andtranslatesthemintopositions 13

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thatarerelevanttotheuser.Ithasato-dolistfortheuserd ependingonthelocationintheformof voiceandtextentries.Onobtainingthelocationfromtheus er,theto-dolistisassociatedwithit whichalertstheuserthathehasitemstobeperformedinthec urrentlocation. Receiver GPSCDPDModem physical messages virtuallocation direct and indirect feedback GPS satellite system main message server map server info server Internet position queryposition info location context-relatedmessage USER Query Engine Location Learning Agent Message Engine Figure2.3.ArchitectureofcomMotionShowingtheThreeDif ferentModules.ReproducedFrom [3] ThehardwareofcomMotionincludesaGPSreceiver,aportabl ePC,aCDPDmodem,anda Jabraearphonespeakerwithamicrophone.Theclientsideus esbothgraphicalandspeechinterface.Speechrecognitionandtext-to-speechsynthesiswas developedusingAT&T'sWatsonSDK (SoftwareDevelopmentKit).AutomaticSpeechRecognition (ASR)andText-to-Speech(TTS) synthesissysteminintegratedintotheWatsonproductwhic husesphoneme-basedsub-wordanalysissupportingspeakerindependenceandcontinuousspeec h.TCP/IPsocketsareusedonthe clientsidetocommunicatetoallthedifferentserverproce sses,toprovideeasytransferofthese processtotheclientdevicewithWeb-servercapabilities.2.1.4ElectronicTouristGuide TheGUIDESystem[10]developedbythedistributedmultimed iaresearchgroupinLancaster University,supportsnavigationandinformationneedsofv isitorstothecityofLancasterusing wirelesscommunications,context-awareness,andadaptiv ehyper-media.Itusesacellbasedwirelesscommunicationinfrastructuretobroadcastpositioni nginformationanduser'sneedstoportable 14

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GUIDEunitsthatrunacustomizedwebbrowser.TheGUIDEunit sobtainpositioninginformation byreceivinglocationmessagesthataretransmittedfromst rategicallypositionedbasestations. TheGUIDEsystemisbasedondistributedanddynamicinforma tionmodelthatissentto portablehand-heldGUIDEunits.Consideringtheendsystem stobeusedintheGUIDEunit aspen-basedtabletPCsandPDAs,thegray-scaletransecti veversionofFujitsuTeampadwas selected,whichisbasedonPentium166MMXprocessor.Theci tycontainsanumberofWaveLAN cells,whichconformtoIEEE802.11standardandeachcellpr ovesasharedbandwidthwhichis supportedbyaGUIDEserver.Theinformationmodelrepresen tsthegeographicinformationby includingspecialnavigationpointobjectsthatareusedin conjunctionwiththelocationobjectsto determinethebestroutebetweenasourceandadestination. EachGUIDEunitcanlocallycache partsoftheinformationmodelandthereforeoperateevenwh enthenetworkisdisconnected. 2.1.5CyberGuide TourismistheapplicationdomainofCyberGuide[7]develop edbyGeorgiaInstituteofTechnology.Themainobjectiveistoknowwherethetouristis,gi veinformationandanswerthetourist's queriesaboutthelocationbyuseofPDAsandpen-basedPCsus ingRFforindoorpositioningand GPSforoutdoorpositioning. Thesystemisdividedintoseveralindependentcomponentss oastomakeitusefulforthe touristsintermsofgenericfunction.Overallthesystemgi vestheappearanceofasingleunitasa tourguide.AppleMessagePad100withNewton1.3isusedandp en-basedPCsrunningWindows forPenComputing1.0.Letustakealookatthedifferentcomp onentsofCyberGuide. 1. :Thisisthemapcomponentofthesystem.Thiscomponenthask nowledge aboutthephysicalsurroundingslikethelocationofbuildi ngsorrouteswhichthetouristscan access.Thissystemrealizesthiscomponentbyamapoftheph ysicalenvironmentvisitedby thetourist. 2. :Thisistheinformationcomponentofthesystemwhichgives alltheinformation aboutthesightsthatatouristmightencounterduringtheir visitsuchasdescriptionsofthe building.Thisisconsideredasthestructuralrepositoryo finformation. 15

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3. :Thisisthepositioningcomponentofthesystemtoshowthei mmediatenearby surroundingsonthemapandgivesanswersaboutthesesurrou ndings.Thiscomponentis realizedbyapositioningmodulethatgivesexactinformati onaboutthecurrentlocationof thetouristsothatnavigatorcanchartthenearbylocations closetothecurrentlocation. 4. :Thisisthecommunicationcomponentofthesystemfortheto uristtosend andreceiveinformationactinglikeamessengerservice.Th etouristcancommunicatewith thecentralservicelocatetheothers.Thiscomponentisrea lizedusingasetofwireless communicationservices. InTable2.1.weprovidethecomparisonofourproposedworkw iththeapplicationsdiscussed inthepreviouswork. Table2.1.ComparisonofProposedApproachwithPreviousAp proaches Application Purpose Context User External Components Mobility Communication Used Cyberguide Guidancefor Tourist Within Yes PDAandGPS (Georgia fortourist location GeorgiaTech unit Tech) inlabsand andtime campus comMotion Guidancefor Tourist Within Yes PortablePC, fortourist location exhibition GPSreceiver, inexhibition andtime DPDmodem Impulse Answerqueries User Anywhere Yes Palmwith (MITlab) toexplore location GPSreceiver physicalworld Personal Servicesto Customer Shopping Yes PlesseyARM610, Shopping customerin location center andSparc10s Assistant shoppingcenter Electronic Guidefor Tourist Lancester Yes FujitsuTeampad Tour Touristsin location City 7600 Guide LancesterCity Tour Guidancefor Tourist Anywhere No Off-the-shelf Guide pre-stored location components(GPS Tourplanas receiver,Flash desiredbyUser memory,Audio desiredbyUser codeandASIC) 16

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2.2PowerOptimizationTechniques Extendingthebatterylifetimeofthebatteriesusedforthe mobiledevicesisthemajorchallenge.Powerisacriticalandsharedsystemresource.Optim izationtechniquesforobtaininglow powercanbeappliedatmanydifferentlevelsofthedesignhi erarchy.Optimizationatthelogic levelhasbeenshowntohaveaverysignicantimpactonthedi ssipationofpowerofcombinational logiccircuits.Inthissection,wereviewsomeofthepowero ptimizationtechniquesthatareapplied atthelogiclevel.2.2.1DynamicPowerOptimization Inthefollowingsectionswediscusssomeofthetechniquesu sedfordynamicpoweroptimization.2.2.1.1ClockGating Insynchronouscircuits,selectivelystoppingtheclockin portionsofthecircuitwherethere isnoactivecomputationisaveryefcienttechniquetoredu cepowerdissipation.Beniniand DeMicheli[11]haveproposedthistechniquetoreducethesw itchingactivityofthecircuitthat leadstopowerdissipationduringtheidleperiods.Themain ideabehindthisworkistodetectthe idleperiodofthecircuitfromthestatediagram.Inthecase ofMooremachines,theidleperiod isidentiedbydetectingtheself-loops.In[11],thelimit ationtoMoorenite-statemachines hasbeenremovedbyproposinganewmethod.Itdealswithaver ygeneralmodelofsequential circuit,theincompletelyspeciedMealymachineandanove lprobabilisticapproach,thatcan selectivelyseparateandexploittheidleconditionsthato ccurwithhighprobability.Thisisdone bytransformingtheMealymachineintoanequivalentMoorem achine. Localclocksthatareconditionallyenabledarecalledgate dclocks,becauseasignalfromthe environmentisusedtoqualifytheglobalclocksignal[11]. Anedge-triggeredip-opfollowedby acombinationallogicwithasingleclockisassumedintheFi gure2.4.(a).Ithasbeenmodiedwith agatedclockimplementationinFigure2.4.(b)withanewsig nalcalledtheactivationfunction whosesolepurposeistostoptheclockwhenthereisnostatet ransitioninthenitestatemachine andthemachineisinanidlestate.TheblockLinFigure2.4.( b)isusedtolterouttheglitches 17

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OUT CLK STATE IN Logic CombinationalRegisters (a)Combinational LogicRegistersSTATE CLK OUT IN GCLK L&af (b) Figure2.4.Gated-ClockArchitecture 18

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on toensureacorrectbehavior.Whentheactivationfunction becomeshigh,thenitestate machineisnotclocked.Theauthorshaveproposedatechniqu e[11]thatautomaticallygenerates theactivationfunctioninformofacombinationallogicblo ckthatusesasitsinputstheprimary inputINandthestatelinesSTATEofthenitestatemachine. Thistechniqueisstronglydependent ontwofactors-howmuchofstatesplittingisneededtotrans formthemachinetoalocallyMoore machine.Italsodependsontheselfloopconditions,thetim eforwhichthenitestatemachine willbeintheself-loopconditionandtogeneratetheactiva tionfunctionthatisnotminimal.In thistechnique[11],byshuttingdownthelocalclockinport ionsofthecircuitthatareidlereduces thepowerconsumptionasnopowerisconsumedinthenitesta temachine,combinationallogic andthesequentialcircuits.Thedrawbackofthistechnique isthattheadditionalcircuitryforthe computationoftheactivationfunction isanoverheadandincreasesthedelayifitisinthe criticalpathofthecircuit.Andformachinesthathaveaver ysmallnumberofselfloops,thearea ofimprovementisalmostnull[11].Thegated-clocktechniq ueisveryadvantageousforcircuits thatareidleforalongtimeandgetactivatedbySTARTsignal s.Toimplementthistechnique, knowledgeoftheenvironmentisrequiredintermsofactivit ysoastoindicateiftheactivation functionshouldbehighorlow.2.2.1.2Precomputation Thismethoddealswiththeproblemofreducingthepowerbyop timizinglogic-levelsequential circuits.Alidina n[12]proposedapowerfulsequentiallogicoptimizationmet hodtoreduce powerthatisbasedonselectivelyprecomputingtheoutputl ogicvaluesofthecircuitoneclock cyclebeforetheyarerequired,andusingtheprecomputedva luestoreduceinternalswitching activityinthesucceedingclockcycle.Themainobjectiveo fthistechniqueistosynthesizethe precomputationlogic,whichpredictstheoutputofasubset ofinputsforthenextvalue.The originallogiccircuitcanbeswitchedoffinthenextclockc yclebyusingalatchiftheoutputscan beprecomputedusingtheprecomputationlogic.Theprecomp utationlogictakesasitsinputsthe currentinputsofthecircuitandcomputestheoutputvalue. Theimportantfactorinthismethod isthatthepowersavingsthatareachievedbyimplementingt histechniqueshouldovercomethe 19

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powerthatisdissipatedbytheadditionalcircuitrythatis addedfortheprecomputationlogicto selecttheinputsforwhichtheoutputisprecomputed. f n x x2 x1 A R1 R2 Figure2.5.OriginalCircuit Tworegistersseparatedbyacombinationallogicblockisgi veninFigure2.5..Itisassumed thatblockAcomputesandoutputsaBooleanfunction.Thetwopredictorfunctionsg1andg2 predicttheoutputvalueofthecombinationalblockAforthe nextclockcycleasgivenbelow: (2.1) (2.2) Duringtheclockcyclet,ifg1evaluatesto1,theinputtothe registerR2inthesucceedingclock cycleisa1andifg2evaluatestoa1,thentheinputtotheregi sterR2inthesucceedingclockcycle isa0.Ifeitherg1org2evaluatesto1,theregisterR1isdisa bledi.e,thatinthesucceedingclock cycletheinputstoblockAdonotchange. n n n g1g1 g2 FF FF R2 R1 x1x2xn A f LE Figure2.6.FirstPrecomputationArchitecture 20

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Theauthorsof[12]hasproposedtwoprecomputationarchite ctures.Intherstprecomputation architectureseeninFigure2.6.,thepredictorfunctionis evaluatedbyasubsetoftheinputswhich predictstheoutputvalueofthecircuitinthenextclockcyc le.Iftheoutputvalueispredictedthen theinputstothecombinationalblockAdonotchangeandthis outputvalueisusedinthenext clockcycle,thusreducingtheswitchingactivityinthecom binationalblockA.Themainobjective ofthismethodistousetheminimumnumberofinputstopredic ttheoutputinordertoavoid theduplicationofthecombinationalblockAandtoavoidthe increaseinpowerduetothearea overhead.Atthesametime,thechancesofpredictingtheout putshouldalsobemaximized.This leadstothesecondprecomputationarchitectureasshownin Figure2.6. A R3 R1 f g1 g2 x1x2 xn R2 LE Figure2.7.SecondPrecomputationArchitecture Inthesecondprecomputationarchitecture[12],theinputs tothecombinationalblockhavebeen splitintotwosetsthatcorrespondtotheregistersR1andR2 .ThecombinationalblockAisfed continuouslybytheregisterR1withtheinputsthatareused topredicttheoutputvalueforthenext clockcycle.Ifthepredictorlogicpredictstheoutputvalu eforthenextclockcycle,theRegister R2isblockedandthereisnoswitchingactivityamongtheinp utstothecombinationalblockA. Thisreducessomeswitchingactivityintheinternalnodeso fblockA. Precomputationtechniqueaimsatreducingtheswitchingac tivityinthecircuitintheconsecutiveclockcyclesbypredictingtheoutput.Thistechni queincreasesthecircuitareaandcan affectthecircuitperformanceresultinginanincreasedcl ockperiodduetothedelaycausedby thepredictorlogiccircuit.Andmoreoverthistechniqueis dependentonpreviousinputhistory. 21

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Thistechniqueisapplicableforcircuitsthatarespecico napplicationwiththeirenvironment informationknownpriorly.2.2.1.3GuardedEvaluation VivekTiwari n[13]proposedamethodforpoweroptimizationinasimilarma nnerasclock gatingandprecomputation.Themethodisanapplicationofp owermanagementatthelogiclevel. Thetechniquedetermines,thepartsofthecircuitthatperf ormusefulanduselesscomputationand shutsdownthepartsofthecircuitperforminguselesscompu tationperclockcycle.Transparent latchesareusedwithENABLEsignalisusedtodisabletheclo ckofthecomponentsthatperform uselesstransitions.TheENABLEsignaliscalculatedfroma subsetofexistinginputsignalsthat doesnotaffecttheprimaryoutputofthemodulewhenblocked Data RegisterData Register Shifter Adder MUXc 01 Figure2.8.CircuitwithoutGuardLatches InFigure2.8.,theALUperformsbothshiftingandadditiono perationseveryclockcycle.The resultofoneoftheseisselectedusingamultiplexer.Theev aluationofboththeoperationsis unnecessaryeveryclockcycleastheresultofonlyoneofthe operationsistakentotheoutput.If thedecisionismadeastowhichoftheresultsofthetwoopera tionsisneeded,thecomputation ofresultbytheothercomponentcanbeavoidedleadingtosig nicantpowersavings.InFigure 22

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2.9.,guardswhicharetransparentlatcheswithanenablein putareplacedattheinputsofthose partsofthecircuitsthatneedtobeselectivelyturnedoff. Ifthemodulehastobeactive,theenable signalintheguardallowsinputstopropagatethroughthetr ansparentlatchespermittingnormal operation.Ifthemodulehastobeinactive,thetransparent latchretainsitspreviousvalueand thereisnocomputationortransitionperformedinthemodul e.Onanabstractlevel,inaCMOS circuit,theprimaryinputcausestheprimaryoutputtochan gewhichistheresultofswitchingofa largenumberofgateswherealltheswitchingactivityisunn ecessary.Forexample,inthecaseof atwo-inputANDgatewithoneoftheinputsalreadysetto0,an yswitchingactivityintheother inputdoesnotaffecttheoutput.Hencetheswitchingactivi tyonthesecondinputisuselessand canbeblocked. Shifter Adder MUXc 01 Data RegisterData Register L1L2 Guard Logic c=0 c=1 Figure2.9.CircuitwithGuardLatches Theauthorstatesthattheirtechniqueisdifferentfrompre computationinthattheentirecircuit neednotbere-synthesisedtondoutthepossibilitiesasto whenthecircuithastobeshutdown. Theevaluationofthesub-circuitthatisusedtoshutdownth emodulesisguardedbytheexisting inputsignalsofthecircuit.Inotherwordsthecircuitisne verclockedOFF.Hencethereisnonecessitytoresynthesisethecircuit.Thepoweroptimalinpu tstothecircuitareobtainedbyincluding atransformationcircuitrytotheoriginalcircuit. 23

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2.2.1.4Retiming Monteiro nproposesatechniquein[14]toreducepowerdissipationins equentialcircuits suchaspipelines.Apipelinedsequentialcircuitcanbeacy cliccorrespondingtoblocksofcombinationallogicthatareseparatedbyipops.Theintrodu ctionofaipoptoacombinational blockreducestheswitchingactivityattheoutputoftheblo ckleadingtolowerpowerdissipation. G C L (a) G R C L (b) Figure2.10.Flip-opAdditiontoCircuit InFigures2.10.(a)and2.10.(b)thepowerdissipatedbythe circuitisgivenby and where istheaverageswitchingactivityattheoutputofthegateGa nd istheloadcapacitance. Whenaip-opRisintroducedattheoutputofgateG,thepowe rdissipatedbythegateGisgiven by r r ,where risthecapacitanceattheinputoftheip-opand risthe switchingactivityattheoutputoftheipop.Theobservat ionhereisthat r astheoutput oftheipopmakesatmostonlyonetransitionperclockcycl ewhereasgateGmaymakethree transitionsforthesame.Hencetheadditionofip-opstoa circuitdecreasespowerdissipation.In asimilarway,repositioningofaip-opinapipelineaccor dingtotheamountofspuriousactivity atvariousstagesofapipeline,leadstoreductioninpower. Theauthorsproposeanalgorithmtoplaceaip-opattheout putofaselectedsetofnodes asshowninFigure2.11..Thisleadstoreducedswitchingact ivityreducingthepowerdissipation inapipelinedcircuit.Theselectionofnodesisdonebasedo ntheamountofglitchingactivityat theoutputofthesenodes.Acostfunctionisgivenbyestimat ingtheaverageswitchingactivityof thecombinationalnetworkbothwithzerodelayandactualde layforeachgate,thuscalculatingthe amountofglitchingattheoutputofthenodesandtheprobabi lity[5]thatatransitionateachgate propagatesthroughitstransitivefanout.Thismethodredu cestheconsumptionofpowerwithout anylossinperformance. 24

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P0P1P2 FF P0 FF P1 P2 Figure2.11.RepositioningtheFlip-opsinaPipeline 2.2.1.5MultipleClocking Papachristou nproposesatechniquein[15]todesignlow-powerregister-t ransfer-level datapaths.Acircuitispartitionedintodisjointmodulesandeachmoduleisassignedadistinct clock.Thetechniqueusesnon-overlappingclocksbydividingthefrequencyofasingleclock intocycles.Inthiswayeachmoduleoperateonlyduringitsdutyc ycleandpowerisreducedas theclockingfrequencyofeachmoduleis .Theoverallfrequencyofthecircuitremainsthe singleclockfrequency.Thiswaythemodulesthatareinactiveareturnedoffduring theiroff dutycyclereducingthepowerdissipation. adcb x y z e x y z u v w + + Figure2.12.OriginalCircuit 25

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ThedifferencesinthecircuitsFigures2.12.and2.13.are( 1)circuit1needslessresources thancircuit2.(2)ThetwoALUsincircuit1useasingleclock andworkconcurrently.Whereas incircuit2,thecircuitispartitionedinawaythattherst sub-circuitworksduringtheoddtime stepsandthesecondsub-circuitworksduringtheeventimes teps.Allocatingthenodesateven andoddtimestepspartitionthecircuitintoseparatesub-c ircuitsthatareactiveatnon-overlapping timeintervals,makingtheuseofnon-overlappingclocks. + + d eba c x u y v z w CLOCK1 CLOCK2CLOCK3 T1 T3 T5T2 T4 .....T1 T3 T5 Figure2.13.PartitionedCircuit Figure2.14.showsthetwonon-overlappingclockswhosefre quencyis ,whereisthe frequencyoftheoriginalcircuit.Thoughtheseparatecomp onentsofcircuit2areclockedathalf thefrequencyoftheoriginalfrequency,thereisnolossinp erformanceastheeffectivefrequency isthesame,reducingthepoweratthesametime. Single Clock (freq = f)Clock 1(freq = f/2)(freq = f/2) Clock 2 Multiple clocking scheme Figure2.14.MultipleClockingScheme 26

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Theauthorsproposeanalgorithmin[15]forallocationofmu ltipleclocksforpowerreduction. Thealgorithmemphasizesonholdingthepreviousinputvalu esforthelongesttimepossibleto reducethespurioustransitionsontheinputportsoftheALU s.Theyalsoproposeamethodto decreasethevoltage,astheoperatingfrequencyofeachclo ckpartitionislowerthanthesingle clockfrequencytoachievemorepowerreduction.Partition ingthecircuitcarefullyduringtheRTL designassuressameperformanceasinthesingleclockdatap ath. 2.2.2LeakagePowerOptimization Inthefollowingsectionswediscusssomeofthetechniquesu sedforleakagepoweroptimization.2.2.2.1InputVectorControl Thisapproachisbasedoncircuit-leveloptimizationmetho dswitharchitecturalsupportthatis appliedduringrun-timetoachievereductioninleakagepow er.TheauthorsBorkarandDepropose atechniquethatisbasedon[16]standbyleakagecontrolsch emewhichsimultaneouslyturnsoff morethanonetransistorinnMOSorpMOSstacksbetweensuppl yandground.Thisismade effectivebygivinganinputvectorthatmaximizesthenumbe rofstacksinthePMOSandNMOS transistorsbyswitchingoffmorethanonetransistor.Henc ethegoalinthismethodistondthe inputvectorpatternthatmaximizesthenumberoftransisto rsthatcanbeintheoffstateinallthe stacksacrossthedesign.Anexhaustivesimulationofallth einputvectorsisdonetondtheinput vectorthatgivesthelowestleakagepowerortouseaprobabi listictheorytominimizethenumber oftrialsgivingafunctionwitherrortoleranceanddesired functionality. Implementationofthistechniquerequiresminimalarchite cturesupportwhichenablesordisablestheunitdependingonthesleepsignalasshowningure 2.15..Theactualleakagepower savingsdependstronglyontheunittowhichthetechniqueis applied[16],withthelogicdesign styleandlogicdepthbeingthemostinuentialfactors.The savingsaresignicantinsuchlogic unitsasthesavingsisdirectlyproportionaltothecontrol labilityofthestackingeffectbytheinput vectors.Allthedesignsareassumedtobefront-endedbythe latchshowninFigure2.15.,mostlyin pipelineddata-paths.Theinputvectorcausingminimumlea kageishardwiredtotheinputsofthe 27

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latchwhichincursverylessareaoverhead.Thesleepsignal isusedtoactivate/deactivatetheinput ofthelatcheswithinatimeperiodofoneclockcycle.Thesig nicantoverheadinpower,isthe transitionfromthestateinwhichthemodulewastothestate ofminimumleakagecausedbylow leakageinputvector.Thetimeforwhichtheunitisidlemust belongenoughsothatthedynamic powerdissipatedinswitchingtothelow-leakageinputisle ssthantheleakagepowerconsumed duringthesametimeifthereisnotransitiontolow-leakage input.Hencetheminimumidletime oftheunitthatovercomesthedynamicpowerdissipationtoo btainactualsavingsisestimatedby thefollowingformula[16]: (2.3) r r r r r r(2.4) A_ext A_int Sleep VDD Sleep Sleep A_ext A_int Sleep GND Figure2.15.ModiedLatcheswithOptimumSleepValues(0an d1) where isthepowerwastageifnoleakagetechniqueisused, istheleakagepower obtainedafterapplyingthetechnique, r and r givetheenergydissipatedbytheadditional circuitryduring r and r ,respectively. 2.2.2.2PowerGating Lowpowercircuittechnologyisveryessentialtominimizet hesizeofportabledevicesand toreducethebatterylife-time.Insuchdevices,powersupp lyshouldbereducedduetothelow breakdownvoltageofsource-drain.Reductioninsupplyvol tageleadstoanincreaseindelay. Toavoidthedelayandincreasethecircuitspeed,thethresh oldvoltage isdecreased.Though 28

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lowering reducesthedelayandincreasestheoperationspeed,thesta ndbyleakagecurrentdue tothesub-thresholdcharacteristicsincreasedrasticall y.High MOStransistorstocutoffleakage pathsbecauseoftheirlowleakagecurrent. MutohandMatsuya[17]proposetheMTCMOScircuittechnolog ythatpreservesdataduring sleepmodetoachievelowerthresholdvoltageandasmallers tandbyleakagecurrent.Thistechnologyusesbothhighandlowthresholdvoltagesonthesamec hip.Thelogicgatesaredesigned tohavelow MOStransistorswhicharenotconnectedtotheVDDandGNDdir ectlybuttoa virtualVDDVandGNDV.Thesetransistorsarecalledpowertr ansistors. VDD VDDV SLQ (High V t ) Low V Logic t GNDV SLQ GND (High V ) t Figure2.16.MTCMOSLatchCircuit Therearetwooperatingmodesinthesetransistorscalledac tiveandsleep.Intheactivemode, thepowertransistorsareon.TheVDDVandGNDVfunctionasVD DAndGNDrespectively.In thismode,thelowlogicgatesfunctionathighspeed.Inthesleepmode,thepow ertransistors arecutoff.InFigure2.16.,thetransistorQhasahigh andhencealowleakagecurrentfromthe lowMOStransistorswhichisalmostsuppressed.Thisleadstoad ramaticreductionofstandby leakagecurrentduringthesleepmode. Inthesleepmode,inordertoreducethestandbyleakagecurr entthepowersuppliesarecutoff thelogiccircuitsbyusingthehigh MOStransistorsresultingindataloss.Toensurecontinuou s circuitoperation,thedatainthecircuitshouldbepreserv edduringthesleepmode.Toovercome thisdifculty,theauthorshavedevelopedanMTCMOSlatchc ircuitforpreservingdatawhenin 29

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thesleepmode.TheFigure2.16.showstheMTCMOSlatchcircu itinwhichthelatchpathL, consistsofhighMOSinvertersthatarepowereddirectlybyVDDandGNDtopres ervedata duringthesleepmode.TG1inthecriticalpathisthetransmi ssiongatecomposedofhightransistorstocutoffthestandbyleakagecurrentpath.Q1Q4,high powertransistorsforsleep controlareconnectedtolowdatapathinvertersindependentlytocutoffthestandbylea kage path. Thedrawbackofthislatchcircuitisthatthesedata-pathin vertersdoesnothavethespeedof thecapacitanceofthevirtualpowerlines.Inordertoobtai nthespeedoftheordinarylatch,the powertransistorQ1-Q4havetobeenlarged.Hencethiscircu itisabottleneckduringhigh-speed operationsbecauseofthehightransistorsinthecriticalpath.Thehugesizesoftransist ors Q1-Q4takeuplargerarealeadingtomorewastageofpower.2.2.2.3TransistorStacking Sub-thresholdcurrent[18],whichincreasesduetotheshor tchanneleffectbecomesthemajor factorofleakageinCMOSdeviceswiththickeroxides.Trans istorstackingisaveryefcient techniqueinloweringthesub-thresholdleakageduringthe standby-modeofanoperationina circuit.Anextratransistor[19]isplacedbetweenthesupp lylineandthepull-uptransistorforthe driver.Whenboththetransistorsareswitchedoff,aslight reversebiasiscausedbetweenthegate andsourceofthepull-uptransistor.Aconsiderableleakag ecurrentreductionisobtainedbasedon thefactthatthesub-thresholdcurrentisexponentiallyde pendentonthegatebias.Henceleakage currentthatowsthroughatransistorstackdependsonthen umberof“off”transistorsinthestack. Figure2.17.[18]illustratesanexampleofatwo-inputNAND gate,inwhichbothM1andM2 areturnedoff.Thisraisestheintermediatenodevoltage()toapositivevalueduetoasmall draincurrent.Therearethreeeffectsduetothepositivepo tentialattheintermediatenode: 1.gate-to-sourcevoltageofM1( )becomesnegative; 2.Bodyeffectbythenegativebody-to-sourcepotential( )ofM1; 3.Lessdrain-inducedbarrierlowering(DIBL)duetodecrea seofdrain-to-sourcepotential ( )ofM1; 30

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AB AB V M M M 2 1 VDD V B = 0 GND Figure2.17.TwoInputNANDGate.Turning“off”M1andM2rais estoPositiveValueCausing the“StackingEffect” Thesub-thresholdcurrent[18]owingthrough“off”transi storisgivenby n n nr (2.5) whereA= ,and arethegate-tosource,drain-tosource andthebulk-to-sourcevoltagesrespectively.andaretheDIBLcoefcientandthebodyeffect respectively. isthezero-biasthresholdvoltage. isthegate-oxidecapacitance. isthe zero-biasmobility,andnisthesub-thresholdswingcoefc ient.Itisobservedfromtheequation abovethat,withanegative ,andincreaseinthebodyeffect(negative ),andareductionin ,thesub-thresholdcurrentisreducedexponentially. NarenderandRanganathan[20]proposeatechniquecalledLE CTORtoreduceleakagepower byeffectivestackingoftransistorsinthepathfromsupply voltagetoground.Theyintroducetwo leakagecontroltransistorsineachCMOSgatesuchthatonle oftheleakagecontroltransistoris nearitscutoffregionofoperation. Figure2.18.[20]showstwoleakagecontroltransistors (PMOS)and (NMOS) betweenthenodes and ofthepull-upandpull-downnetworkoftheNANDgate.Thedra in nodesofthetransistors and areconnectedtogethertoformtheoutputnodeofthe NANDgate.Thesourcenodesofthetransistorsareconnected tonodes and ofpull-upand 31

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A M N M N LCT LCT N M M Vdd Out Additional circuitry in in Gnd 4 3 3 2 2 1 1 2 1 B Figure2.18.LECTORTechnique pull-downlogic,respectively.Thevoltagepotentialsatn odes and controltheswitchingof transistors and .Thiscongurationensuresthatirrespectiveoftheinputv ectorapplied totheNANDgate,oneoftheLCTsisalwaysnearitscutoffregi onresultinginthereductiongof leakagepower.2.3Summary Inthischapter,weoutlinedveapplicationsthatarebased oncontext-awaremobilecomputing andpoweroptimizationtechniquesatthelogicandRTlevels .Wealsooutlinedthenoveltyofour approachascomparedtotheexistingapplicationsbasedonc ontext-awaremobilecomputing. 32

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CHAPTER3 MOBILEINTERACTIVEGUIDE Futuremobilecomputingenvironmentpromisestoremovethe constraintsofstationarydesktop computingfromusers.Mobileenvironmentapplicationssho uldmakeuseofcontextualinformation,liketheuser'slocation,user'sactivity,timeofthe day,user'snearbyobjects,toprovidemore servicestotheuser.Informationofpositionimprovestheu tilityofatourguideapplication. WepresentanovelMobileInteractiveCampusTourGuideproj ect,inwhichwearebuilding theprototypesofamobilecontext-awaretourguide.Thegoa lofthisapplicationistoprovide theuserwithallthefeaturesandfunctionalitieswithoutu singwirelesscommunicationunlikethe existingapplications.Thereisnocentralserverforthisa pplication.Allcomputationsnecessary forprovidingtheoutputrespectivetotheuser'sinputisdo nebytheportabledevice.Thisreduces costandcommunicationoverheadonanymobiledevice.Depen dingontheuser'smobility,the currentlocationoftheuserisobtainedbyusingapositiont rackingsystem.Thecoordinatesofthe positionalinformationandtheuser'schoicebecomethepri maryinputforthedevice.Theaudio lecorrespondingtothislocationissearchedfromtheon-b oardFlashmemoryandplayedout, givinginformationaboutthecurrentlocationtotheuser.T heapplicationdomainwhichhasdriven thedevelopmentofthmobiletourguideismobilityforstude ntswithoutacentralserverthathas tobecommunicated.Inthischapter,wediscussthearchitec tureandfeaturesoftheCampustour guide,thehigh-levelmodeling,andhigh-levelsynthesiso ftheASIC(NAVIGATOR). 3.1HighLevelModelingofNAVIGATOR Themobileinteractivecampustourguideisahand-helddevi cewithascreenandapushbutton interface,accesstostorageresources(memorymodule)tos toreinformationaboutspeciclocations,anaudiooutputinterfacewithspeechgeneration,aP CinterfacethroughanUSB(Universal SerialBus)portandatextoutputinterface. 33

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TOUR GUIDE CAMPUS INTERACTIVE MOBILE GPS COORDINATES GPS SATELLITES AUDIO START USER Figure3.1.MobileInteractiveCampusTourGuide Figure3.1.givestheblockdiagramforthesystemdesign.Th eoverallsystemcanbeconsidered asonewholeunitwithpositioningcomponent,searchingcom ponent,andinformationcomponent. Thehighlevelviewofthesystemandtheinterfaceofcompone ntsisgiveningure3.2..The requiredfunctionalityofeachofthesecomponentsusedfor providingthefunctionarediscussed below: GPS ASIC MEMORYMODULE AUDIO INTERFACE USB POWER PC GPS SATELLITE RECEIVER 'START' Figure3.2.OverallBlockDiagramoftheSystemDesign 34

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3.1.1GPSReceiver Thisisthepositioningcomponentofthesystem.TheGlobalP ositioningSystem(GPS)isused, whichgivestheX,Y,andZcoordinatesofthecurrentlocatio noftheuser.TheoutputoftheGPS moduleisthelatitudeandlongitudegivenasa64bytevalue, whichisaninputtothesystem. 3.1.2USBPort Thisistheinterfacingcomponentofthesystemthatcommuni cateswiththeexternaldeviceto getthedatathathastobeprocessedandprovidedtotheuser. TheUSBportisusedasaninterface betweenthePCandthishand-helddevice.Thedataisdown-lo adedfromthelookuptabletothe memorymodulebyusingaMemoryCardWriterthatisinstalled inthePC.Thisistheonlysource ofexternalcommunicationinthehand-helddevice.3.1.3FlashMemory Thisisthestoragecomponentofthesystem,thatstoresallt hedataandinformationaboutthe specicphysicallocationsaroundthecampus.Itstoresthe lookup-tableandaudiolesofthese locations.Theashmemorychosenforthisdesignhasacapac ityof32MB.Theashmemory interfaceswiththeNAVIGATORwhichreadsthecorrespondin gaudioleandplaysitouttothe audioCODEC.Aashmemoryischosenconsideringlaterversi onsofthisdevicewillhavetext displaysaboutthecurrentlocationthatmightneedmoremem ory. 3.1.4AudioCODEC Thisistheaudiooutputcomponentofthesystem,thatplayso uttheserialdatasenttoitbythe NAVIGATOR.Itcompressestheserialdataandplaysouttheau dioforthecurrentlocation,when thereisamatchbetweentheGPScoordinatesobtainedasanou tputfromtheGPSreceiverandthe GPScoordinatesstoredinthememory.3.2BriefDescriptionoftheFlashMemory TheSandiskCompactFlashMemoryCard(CF)[21]isahighcapa citysolidstateashmemory. ItsupportsthetrueIDEmodewhichiselectricallycompatib lewithandIDEdiskdrive.Ithas 35

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anintelligenton-cardcontrollerthatefcientlymanages datastorage,interfaceprotocols,data retrieval,powermanagementand,clockcontrol.Interfaci ngthehostcomputerwiththememory cardenablestheusertoaccesstheashmemorycardlikeasta ndarddiskdrive.Thesizeofthe sectoris512byteswhichisthesameasthatinanIDEmagnetic diskdrive.Thehostcomputer issuesaReadorWritecommandtoreadorwriteasector(ormul tiplesectors).Thiscommand containstheaddressandthenumberofsectorstoread/write .Theintelligenton-boardcontroller performsallthenecessaryoperationsandprovidestheoutp uttothehostsoftware'srequest.This reducestheinterventionofthehostsoftwarefromgettingi ntothedetailsofprogramming,erasing, orreadingtheashmemory. SanDisk CompactFlash Control In/Out Data Host Interface Controller Chip Single SanDisk MODULES SANDISK FLASH Figure3.3.CompactFlashMemoryCardBlockDiagram Figure3.3.showsthehostinterfacewiththeSanDiskCompac tFlashMemoryCardandthe Read/Writetimingdiagram.TheCompactFlashmemoryCardis conguredintheTrueIDEMode inthisdesign.Thisisdonebygroundingthe-OEsignalwhenp owerisappliedtothecard.Inthis mode,inputandoutputoperationsareallowedonlytotheTas kFileRegistersandDataRegister. Thereisnoaccesstothememoryortheattributeregistersby thehost.TheTaskFileRegisters 36

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providestatusandcontrolinformationwhichisdonebyseve nregistersaccessedusinga3-bit addressbus.Eachoftheregistersisdescribedindetailbel ow: 1. :Thisisa16-bitregisterusedtotransferblocksofdatafro m/totheCompact FlashMemoryCarddatabufferandtheHost.Thisregisteriso verlappedwiththeErrorRegister whichgivesinformationaboutthesourceofanerror.Thisre gisterisaccessedtoread/writedata usingtheaddress“000”andasanerrorregisterusingtheadd ress“001”. 2. :Thisregistercontainsthenumberofsectorsofdatareques tedbya readorwriteoperationtobetransferredbetweenthehostan dtheCompactFlashMemoryCard. Avalueofzeroindicatesthat256sectorswillbetransferre datthecompleteoftherequest.Ifthis commandiscompletedsuccessfully,zerovalueisavailable inthisregisteratcommandcompletion. Ifunsuccessful,theregistercontainsthenumberofsector sthatneedtobetransferredinorderto completetherequest.3. :Thisregistercontainsthestartingofthesectornumberfo rany CompactFlashMemoryCarddataaccessforthesubsequentcom mand. 4. n :Thisregistercontainstheloworder8bitsofthestartingc ylinder address.5. n :Thisregistercontainsthehighorder8bitsofthestarting cylinder address.6. :Thisregisterisusedtoselectthedriveandhead.Itisalso usedtoselectthe LBAmodeorCHSmodeofaddressingbysettingtheD6bitto1/0r espectively. 7. / n :ThisregisterreturnsthestatusoftheCompactFlash MemoryCardwhenreadbythehost.ThebitsD7andD3arechecke dconstantlyfromthisstatus registerwhendataisreadfromtheCompactFlashMemory.Bit 7isthebusybitwhichissetwhen theCompactFlashMemoryCardhasaccesstothecommandbuffe randregistersandthehostis lockedoutfromaccessingthecommandregisterandbuffer.W henthisbitissetto1,theother bitsinthisregisterareinvalid.Bit3istheDataRequestbi twhichissetwhentheCompactFlash MemoryCardrequiresthatinformationbetransferredeithe rtoorfromthehostthroughtheData register.Thisregisterisusedasacommandregisterduring theWritecycle,towritethecommand indicatingtheCompactFlashaboutwhatoperationtoperfor m,forexample,readsectorsorread longsectorsetc.Wegivethevalue20Hforcommandregisteri ndicatingittoreadsectors. 37

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8. :TherearetwomodestoaccesstheCompactFlashMemoryCard, CHS (Cylinder/Head/Sector)addressingandLBA(LogicalBlock Address)mode.CHSaddressing modeisthenormalordefaultmode.Inthismode,thereisnotr anslationdoneattheBIOSlevel, andthelogicalgeometrypresentedbythediskisusedbytheB IOSdirectly.WhiletheLBA,insteadofreferringadrivebyitscylinder,headandsectornu mbergeometryinordertoaccessit, eachsectorisgivenauniquesectornumber.Thedriveisacce ssedbylinearlyaddressingsector addressesbeginningatsector1ofhead0andcylinder0asLBA 0andproceedingoninasequence tothelastphysicalsectoronthedrive.TouseLBAaddressin gmode,itmustbesupportedbyboth theBIOSandtheoperatingsystem. TheCompactFlashMemoryCardusestheabovedescribedeight registersforbothCHSand LBAaddressingmodes.Theaddressingmodechosenforthisde signistheCHSaddressingmode. 3.2.1FAT16Drive The32MBCompactFlashMemoryCard,thatisusedinthisappli cationusestheFATtable. ThestructureoftheFAT16[22]driveisgivenbelow:1. :TheMasterBootRecordislocatedattherstsectoratCylin der0,Head 0andSector1.ItistherstpieceofcodethatMemoryCardrun swhenthesystemisswitched “on”.2. :TheBootRecordislocatedintherstsectorofeverypartit ionandgivesuseful informationaboutthediskthatitson.Themostusefulinfor mationstoredintheBootRecordis thesizeofeachsector(usually512bytes)andthetotalnumb erofsectors.Ittypicallystartswith a3bytejumpinstructiontowherethebootstrapcodeisstore dwhichisfollowedbyan8byte longstringset.Itsuppliesinformationonthelocationsof theFATtableandtheRootDirectory. TheotherusefulinformationstoredintheBootRecordarenu mberofbytespersector,numberof sectorspercluster,numberofrootentries,numberofsecto rsperFAT,numberofsectorspertrack, numberofheads,numberofhiddensectors,thevolumename,a ndtheserialnumber. 3. n:TheFileAllocationTable(FAT)containslinkedlistsofl esinthelesystem. Anyleordirectoryentryinadirectorylistcontainsaclus ternumberfortherstchunkofthe 38

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leordirectory.Foreveryclusteronthedisk,thereisanen tryintheleallocationtablewhich occupiesthenumberofbitsthatareused(12,16or32).Atthi sentryintheFATasinglewordvalue eitherpointstothenextcluster/chunkoritcontainsanend -of-levalue.IftheFATentryis0,then thereisnodatainthatcluster.IftheFATEntryisFFFFh,the nitisthelastentryinthechain.The FATentry0001h-0002hindicatesthattheseclusternumbers arenotused,Fatentry0003h-FFEFh indicatesthattheclustersareusedandgivesthenumberoft henextclusterandFATentryFFF7h indicatesabadsectorinthecluster. 4. :Thisisaspeciallethatcontainsthenames,attributes,l ast modiedtimesandotherdetailsconcerningthelesandsubdirectoriescontainedinit.Eachentry inthedirectorylistis32bytelong.Rootdirectoryistheon lydirectorywhichisinaxedlocation. ByreadingtheFATtable,wecanfollowthroughthelechains butwedonotknowwherethele begins.Thedirectoryentryholdsthenumberoftherstclus terofthele.Toreadale,therst clusterfromthedirectoryentryisreadandindexedintheda taarea.Thenextclusterforthele islookeduponintheFAT.TheothervaluesstoredintheRootd irectoryarethenameofthele whichis8byteslonganditsextensionwhichis3byteslong,i tsattributes,thetimethatthele wascreated,thedatethatthelewascreated,thedatethatt helewaslastaccessed,thetimethat thelewaslastmodied,thedatethatthelewaslastmodie dandthesizeofthele. 3.3FunctionalityofTOURNAVIGATOR Amoduleisnecessarytosearch,retrieve,andplayoutdataf romthememory.Thesearch moduleactsasaninterfacetoallthecomponentsofthesyste m.Theinputstothemoduleare,a 64byteGPSlatitudeandlongitudeoftheuser'scurrentloca tionanda`GO'signalfromtheuser. Whenthe`GO'signalisasserted,theNAVIGATORstartscompa ringtheinputGPSco-ordinates withtheGPScoordinatesstoredinthelookuptablestoredin theashmemory.Ifthereisamatch, thenthesearchmodulereadstheaddressoftheaudiolecorr espondingtothatcurrentlocation andsendstheaudiodataasaserialdatastreamtotheaudioCO DEC.TheaudioCODEC,takesin theserialdataandgeneratestheaudiooutput.IftheGPScoo rdinatesintherstlocationdonot matchwiththeGPScoordinatesofthecurrentuser'slocatio n,thenthecontrolintheNAVIGATOR 39

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jumpstotheaddressoftheGPScoordinatesofthenextlocati onandtheprocessuntilamatchis found.Ifthereisnomatchwithanyofthelocationsintheloo kuptablethenitexitsoutoftheloop. GND DASP PDIAG INPACK A0A1A2 IORD IORW D0D1D2D3D4D5D7D8D9D10D11D12D13D14 ATA SEL CSEL CD1CD2CS0CS1 INTRQ D8D9 D10 D15D14D13D12 D11 STARTCLEARCLOCKFINISHSDOUTG0G1G2G3G4G5G6G7 FLASH MEMORY CARD D7 REG REST VCC VS1 VS2 WE IORDY IOCS16 D15 COMPACT ASIC A0A1A2RDWRD0D1D2D3D4D5 D6D6 Figure3.4.DiagramshowingthePinInterfaceofNAVIGATORw ithFlashMemoryCard 3.4NAVIGATORDesign Thedesignofthesearchmoduleisdescribedatthebehaviorl evelwithtimingdiagramsto interfacewiththeashmemory.Theinterfaceofpinsbetwee ntheNAVIGATORandtheash memoryisgiveningure3.5.,andtheinterfaceofsignalsbe tweentheNAVIGATORandthe ashmemoryisshowningure3.6..Theaddressingmodesused toaccessthedatafromtheash memoryaretheCHS(CylinderHeadSector)modeandLBAmode.A 16bitbidirectionaldatabus isusedtointerfacewiththeashmemorymoduletoreadandwr itedataintotheeightregisters.A 3bitaddressbusisusedtoselectoneoftheseeightregister s.Theoutputisasinglebittobesentas aserialdataoutput.Whenthe`GO'signalisasserted,thema sterbootrecordisreadfromtheash memory.Themasterbootrecordislocatedattheveryrstsec torgivenbytheCHSaddress(C=0, H=0,S=1)orLBAaddress(LBA=0).TheCHS/LBAaddressiswrit tenontotheTaskFiles(also knownastheCommandBlock)whicharetheeightregisterstow ritethecylinder,headandsector addressesrespectivelyinashmemory.Thesectorcountreg isteriswrittenavalueof1specifying tothecontrolleroftheashmemorytoreadonlyonesectorat atime.Thecommandregisteris 40

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writtenavalueof20Hwhichisacommandforreadingsectorsi ntheashmemory.Theminimum writecycleneededtowriteontotheseregistersis120ns.On cethesevaluesarewrittenintothe eightregisters,thestatusregisterispolledconstantlyt ocheckthestatusofthedataavailableon thedatabuffer.Avalueof`1'ontheseventhbitofthestatus registerindicatestheashcontroller isbusyreadingdatafromtheashmemory.Whenthevalueofth ebusyis`0',the512bytesofthe rstsectorarereadontothelocalmemoryon-boardintermso f16bitsputintoaloopof256times whilethevalueofthethirdbitis`1'.Thethirdbitofthesta tusregisterbecomes`0'afterthe512 bytesareread.Theminimumreadcycletimeis120ns. Read root directory entry and Data area directory table, FAT table Obtain starting address of root partition into the local memory Read Boot record of Obtain address of first partition into the local memory Read Master boot record Task file registers for sector 0 into the Write CHS address Start into local memory Play audio as serial output Search audio file name in the root directory table file name Get the corresponding audio Play error message Match? A A lookuptable.txt with those stored in the Compare the input GPSlatlong root directory table Search for lookuptable.txt in Figure3.5.FlowchartwithStepsinvolvedintheNAVIGATORD esign TheCHS/LBAaddressoftheFATbootrecordisobtainedfromth erst512bytes.Thisaddressisagainwrittenontotheeightregistersandthevalue sofbytespersector,sectorspercluster, reservedsectors,maximumrootdirectoryentriesandsecto rsperFATareobtained.Usingthese 41

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values,theCHS/LBAaddressoftheFATtable,theRootdirect orytableandthedataareaarecalculatedusingtheformulagivenbelow: FLASH MEMORY NAVIGATOR DATA WRITE READ ADDRESS ADDRESS READ WRITE DATA 16 3 Figure3.6.SignalsthatInterfacebetweenNAVIGATORandFl ashMemoryCard n (3.1) TheFATtableisstoredlocallysoastogettherequiredclust ernumbersofthedataarea.The rootdirectorytableisalsostoredlocallytoobtainthesta rtingclusternumberofarequiredlocation ofalebyusingthelename.Thelenameofthelookuptablei sxed,namedaslookuptable.txt. ThislenameiscomparedwiththeentriesintheRootdirecto rytable.Whenthereisamatch,the startingclusternumberofthelecontainingthelookuptab leisobtained.Usingtheclusternumber, assumingthatthereare32sectorsperhead,thecorrespondi ngCHS/LBAaddressisfound.The pseudo-codetondthecorrespondingCHSaddressandLBAadd resswithagivenclusternumber isshowninAlgorithm1andAlgorithm2respectively. 42

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1.ClustersPerHead=SectorsPerTrack/SectorsPerCluster ; 2.SectoraddressofDataArea=ClusterNumber*SectorsPerC luster; 3.Offset=SectoraddressofDataArea-SectorsPerTrack;4. while OffsetNumberofHeads do Offset=Offset-SectorsPerTrack; endwhile 5.ClusterNumber=ClusterNumber-2;6.ClusterNumber=ClusterNumber/ClustersPerHead;7. if ClusterNumberNumberofHeads then HeadAddressofDataArea=ClusterNumber; else while ClusterNumberNumberofHeads do CylinderaddressofDataArea=CylinderaddressofDataArea +1; ClusterNumber=ClusterNumber-NumberofHeads; endwhile endif Algorithm1: Pseudo-codeforTranslationofClusterNumberintoCHSAddr ess Therstsectorofclusterisreadontothelocalmemory.Thec omparisonofGPSco-ordinates isdonethe512bytesonboard.Ifthereisamatch,theaudiol eissearched.Ifthereisnomatch, 512bytesofnextsectorisread,andcomparisonofGPSco-ord inatesiscontinued. 1.Offset=(ClusterNumber-2)*SectorsPerCluster;2.LBAaddressofDataAreapointedbyClusterNumber=LBAadd ressofbeginningofDataArea+Offset; Algorithm2: Pseudo-codeforTranslationofClusterNumberintoLBAAddr ess UsingtheformulaementionedinFigure1andFigure2,theCHS /LBAaddressoftheaudio leisobtainedandwrittenontotheeightregistersoftheFl ashmemory.Thevalueofsectorcount registerissettothevalueofsectorspercluster,indicati ngtheashmemorytofetchthedataofall thesectorsinthatparticularcluster.Whena16-bitdatais readfromthedataregisteroftheash memory,the16-bitdataisshiftedrightonebyoneandgivent otheoutput.Hencetheoutputofthe searchmoduleisaserialdatathatisinterfacedwiththeaud ioCODEC. 1.Cylinder=LBA/(HeadsperCylinder*SectorsperTrack);2.Temp=LBAmod(HeadsperCylinder*SectorsperTrack);3.Head=Temp/SectorsperTrack;4.Sector=TempmodSectorsperTrack; Algorithm3: Pseudo-codeforTranslationofCHSAddressintoLBAAddress 43

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3.5DesignofMemoryModule AmemorymoduleismodeledinbehavioralVHDLtosimulatethe behavioroftheFlashmemory.ThisisdonetoverifythefunctionalityoftheNAVIGATO Rdesign.Thetimingfortheread andwritecyclesaremodeled.Dataisstoredinalesimilart otheFlashmemorywitheachsector containing512bytes.Thememorymodulehastheabovementio nedeightregistersoftheFlash memory.Dependingonthevaluesontheseregisters,theappr opriatesectorisreadfromthedata leandgivenasoutputtotheNAVIGATOR.InthecaseofCHSadd ressingmode,thevaluesof cylinder,headandsectorregistersareusedtoindextothea ppropriatesector.InthecaseofLBA addressingmode,LBA(7downto0)iswrittentothesectornum berregister,LBA(15downto8) iswrittentothecylinderlowregister,LBA(23downto16)is writtentothecylinderhighregister andLBA(27downto24)iswrittentotheheadregister.Atrans lationalgorithmgiveninFigure3 iswrittentotranslatethevaluesintheseregisterstothec orrespondingCHSaddress,toaccessthe necessarysectorfromthedatale.3.6ToolsUsed Thissectiongivesabriefdetailonthetoolsthatareusedto generatethelayoutofthedesign. 1.HighLevelModelinginVHDL2.BehavioralSynthesisusingAUDI3.LogicSynthesisofcontrollerusingSIS4.LayoutSynthesisinSiliconEnsemble5.CadenceVirtuosoLayoutEditor6.Translators3.6.1HighLevelModelinginVHDL TheHardwareDescriptionLanguagesthatareusedforthisde signareVHDLandVerilog. Theycanbeusedfordocumentation,verication,andsynthe sisoflargedigitaldesigns.They canbeusedinthreedifferentapproachestodescribinghard warenamely,thestructural,dataow, andbehavioralmethodsofhardwaredescription.ThisNAVIG ATORisdescribedbehaviorallyin VHDL.ThebehavioraldescriptionissubmittedtoAUDIwhich synthesizesastructuraldescrip44

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tionofthedesigninVHDL.ThestructuralVHDListranslated intostructuralVerilogforfurther synthesisandsimulationofthedesigninCADENCElayoutsyn thesisenvironment. 3.6.2AUDI AUDIisabehavioralsynthesissystememployedtosynthesiz eaRTleveldesign.TheAUDI systemtakesbehavioraldataowgraph(DFG)representatio nasinputandgivesastructuralVHDL output.SeveralschedulingalgorithmssuchasASAP(as-soo n-as-possible),ALAP(as-last-aspossible),FDS(ForceDirectedScheduling)andsimultaneo usscheduling,allocation,andmapping algorithmareimplementedinAUDIgivingtheuservariousop tionstosynthesizehis/herdesign. Acliquepartitioningheuristic[23]isusedforallocation andbinding.Itgeneratesaminimal setofmaximalsizedcliquesresultinginmaximumsharingbe tweentheallocatedcomponents. ThisheuristicisusedforFunctionalUnit(FU)mappingandR egisterMapping.Forfunctional unitmapping,thecompatibilitygraphoftheoperationsint hescheduledDFGisgivenasinput. Forregistermapping,lifetimeanalysisoftheregistersis donebeforemapping.Twoedgesare compatibleifandonlyiftheyhavenon-overlappinglifetim es.Acompatibilitygraphoftheedges intheDFGisformed.Multiplexersorbusesareusedforshari ngfunctionalunitsandregisters.A characterizedstandardcelllibraryisusedtosynthesizet hedatapath. OUTPUTS INPUTS CLOCK CLEAR FINISH START CONTROLLER DATA-PATH Figure3.7.RTLevelDesigngivenbyAUDI Thetopleveldesigninstantiates[23]adatapathandacontr ollerasgiveninFigure3.8..Control signalsandagsareusedforcommunicationbetweenthecont rolleranddatapath.Thedatapath 45

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operatesaccordingtothecontrolsignalsandagsgenerate dbythecontroller.Thecontrollerisa FiniteStateMooreMachineshownasingure3.8..Asinglecl ocksignaldrivesboththedatapath andthecontroller.Thecontrollerallowthefunctionaluni tstoperformcomputationfortherst halfoftheclockcycleandgeneratescontrolsignalsduring theremaininghalfoftheclockcycle. DuringtheIDLE(State0)state,thecircuitwaitsforaninpu tvectoronitsprimaryinputsduring whichtheCLEARsignalclearstheregistersbeforestartofo peration.Oncenewinputsarriveat theprimaryinputs,theSTARTsignalisasserted.Thistakes thecontrollerfromtheIDLEstateto State1,generatingcontrolsignalstothedatapathatevery state.Theprimaryinputsarestoredin registers.Oncethecontrollergoessequentiallytoallthe states,aFINISHsignalisgeneratedatthe endoflaststateandtheprimaryoutputsarestoredinregist ers. Finish = 1 St_art =1 St_art =0 N STATE 1 STATE 0 STATE Figure3.8.ControllerStateMachineinAUDI SynthesizeddesigngivenbyAUDIissimulatedusingCadence VHDLSimulatorattheRTL Level.LayoutsfordesignsweregeneratedusingCadenceVir tuosoLayoutandfunctionallyveriedusingHSPICE.3.6.3SIS SIS(SequentialInteractiveSynthesis)systemisanintera ctivetoolforsynthesisandoptimization[24]ofsequentialcircuits.Ifastatetransitiontabl e,signaltransitiongraph,oralogic-level descriptionofasequentialcircuitisgiven,SISproducesa noptimizednetlistinthetargettechnol46

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ogywhilepreservingthesequentialinput-outputbehavior .Theoutputcanbestoredasanitestate machineorasanimplementationconsistingoflogicgatesan dmemoryelements.Theprogramincludesalgorithmsforminimizingthearearequiredtoimple mentthelogicequation,algorithms forminimizingdelay,andatechnologymappingsteptomapan etworkintoauser-speciedcell library.ThemostcommoninputtoSISisintheformofnet-lis tofgatesandanite-statemachine instate-transitiontableform. Inourdesign,weuseatranslatortotranslatethecontrolle rofthedesignfromtheVHDL formattotheKISSformatwhichisaformattospecifyastatet ransitiontableforanite-state machinetobegivenasinputtoSIS.KISSformatisusedextens ively[24]instateassignment andstateminimizationprograms.Astateisrepresentedsym bolically,thenextsymbolicstateand outputbit-vectorisindicatedinatransitiontablegivena currentstateandinputbit-vector.Missing transitionsindicatedon'tcareconditionswhichdenotest hatapresentstateorinputcombination hasnospeciednextstateoroutput.A`-'intheoutputbitin dicatestheparticularoutputcanbe either0or1. Stateassignmentisdoneonthestatetransitiongraphtomap itontoanetlist.Stateassignment isdoneusingstateassignmentprogramsthatstartwithasta tetransitiontableandobtainoptimum binarycodesforeachsymbolicstate.Alogiclevelimplemen tationisobtainedfromthesebinary codesbysubstitutingthemforsymbolicstates.Alatchiscr eatedforeachbitofthebinarycode. JEDIandNOVAaretwostateassignmentprogramsdistributed withSIS.NOVAisusedforPLAbasednite-statemachines.JEDIisageneralsymbolicenco dingprogram[24]forencodingboth inputsandoutputs,thatcanbeusedformorespecicstateen codingproblem,targetedformultilevelimplementations.WeusedJEDIforstateassignmentfo rourdesign. TheresultingnetlistiswrittenintoaBLIF(BerkeleyLogic InterchangeFormat)whichconsistsofinterconnectedsingle-outputcombinationalgate sandlatches.TheBLIFformatallows specicationoflatchesandcontrollingclocks.Thelatche sspeciedinBLIFaresimplegeneric delayelementswhicharemappedtoactuallatchesinthetech nologylibrary.BLIFalsoaccepts user-specieddon'tcareconditions. TheresultingBLIFleisreadintoSISagainandmappedwitht helibrarygatesmentionedin theGENLIB,whichislibrarycontainingthedescriptionofl ogicgatesandlatches.Theinputs, outputs,pinnames,pinloads,input-load,max-load,riseblock-delay,rise-fanout-delay,fall-block47

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delay,fall-fanout-delayofthecomponentsarespeciedin thelibrary.Thelibrarygatecreatesan instanceofatechnology-dependentlogicgateandassociat esitwithanodethatgivestheoutputof thelogicgate. TheresultantmappedoutputiswrittenintoBDNETformatwhi chisusedtoconnectcombinationallogicandregisters.Theleconsistsofinstanc esoflogicgatesandlatcheswiththe actualinputsandoutputsmappedwiththeformalinputsando utputs.Thislegivesthestructural descriptionofthestatetransitiongraphwhichisinputtoS IS. 3.6.4SiliconEnsemble SiliconEnsembleisanautomaticplaceandroutetool[25]by CADENCEthatcanperformall thecomplextasksneededtocreatethephysicallayoutofani ntegratedcircuit.Itisdesignedto placedigitalblocksquicklyandefciently.Itperformso orplanning,cellplacement,andinterconnectroutingoperationsforstandardcell-basedintegr atedcircuitandsub-circuitdesigns.The oorplannerallowssettinguprowsforplacingthecomponen ts.Theplacersincludecommands forgroupingcellsbasedonconnectivity,placingcellsaut omatically,placingcellsincrementally andoptimizingplacement.Thedifferentfunctionsthatare supportedbySiliconEnsembleare 1.Multi-layermetalrouting:Youcanroutemulti-layermet aldesigns,includingdual-layer channeledandtriple-layerchanneledandchannel-lessdes igns.Therouterssupportoverthe-cellroutingthatavoidsroutingobstructions.Therou terscanalsohandleoff-gridpins. 2.Mixedlibrarysupport:Librariescanincluderectilinea rblocksaswellasstandardcells andmacros.Thisreducesthearticialconstraintsonblock designsandincreasesdesign exibility. 3.Correct-by-constructionlayout:Algorithmsvalidatet helayoutduringconstructiontoensure thatdesignrulesaresatisedbythephysicaldesign 4.Automaticparametertuning:Thesystemautomaticallyad justssignicantoperationalparametersaccordingtothedesigndatatoproducethebestlay outwhilereducingtheruntime. Manualadjustmentscanbedonetosomeoperationalparamete rstooptimizethelayoutfor fewlargedesigns. 48

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5.Engineeringchangeoption:Theseareminorchangestothe completeddesigns.Thesystem makesthesechangeswithoutrequiringthecompletedesignc ycle. 3.6.5CadenceVirtuosoLayoutEditor VirtuosoLayoutEditoristheindustry-standardbase-leve lcustomphysicallayouttoolofthe Virtuosocustomdesignplatform.Itsupportsthephysicali mplementationofcustomdigital,mixedsignal,andanalogdesignsatthedevice-cell-and-blockle vels.TheVirtuosocustomdesignplatform isacomprehensivesystemforfast,silicon-accuratedesig n,andisoptimizedtosupportadvanced designmethodologiessuchascustomdesign.Virtuosoinclu destheindustry'sonlyspecicationdrivenenvironment,multi-modesimulationwithcommonmod elsandequations,vastlyaccelerated layout,advancedsiliconanalysisfor0.13micronsandbelo w,andafull-chip,mixed-signalintegrationenvironment. Customlayoutisenhancedwithasetofuser-congurableand easy-to-usepurepolygonlayout featureswithinamulti-windowenvironmentinVirtuosoLay outEditor.Parameterizationofcells andapowerfulscriptinglanguagecalledSKILLgivesmoreac celerationprovidingdirectdatabase access,toolconguration,andinter-operabilitywithoth ertools.TheadvantagesofVirtuosoLayoutEditorareeasycreationandnavigationofcomplexdesig nswithunlimitedhierarchysupport alongwithamulti-windoweditingenvironment,accelerate dlayoutentryusingtheeasilyaccessed editingfunctions,increaseddesignoptimizationandprod uctivityusingPcells,andefcienthandlingoflargedesignsusingtheOpen-Accessdatabase.3.6.6Translators ThissectionexplainsthepathforgenerationoflayoutinCa denceVirtuosoLayoutEditorwith threeVHDLlesgeneratedfromAUDI.ThethreeVHDLlesthat areoutputfromAUDIare thecontroller,datapathand,thetop-leveldesignle,tha tconcatenatesthecontrollerandthedata pathofadesign.Ascriptincludingallthetranslatorsiswr ittentogenerateaverilogleforthe wholedesignwhichisimportedintoSiliconEnsembleforaut omaticplaceandroute.Theoutput ofSiliconEnsembleisaDEFle,thatisimportedintoCadenc eVirtuosoLayoutEditortogenerate thelayout.Thestepsandthetranslatorswillbediscussedi ndetailbelow. 49

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3.6.6.1VHDLtoKISSTranslator NAME:vhd2kiss SYNOPSIS:vhd2kisslenameDESCRIPTION:Thelenameisthecontrollerlewhichisofth eextensionlename con.vhd Thistranslatortakesinthecontrollerleofthedesignand givestheoutputintheKISSformat.The KISSformatistakenasinputbySIStogeneratetheBDNETlef orthecontroller.Thetranslator wasdesignedusinglexandyacccompilertools.3.6.6.2BDNETtoVerilogTranslator NAME:bdnet2verilog SYNOPSIS:bdnet2verilogdesignnameDESCRIPTION:Thedesignnameisthenameofthedesignforwhichthelayoutisgeneratedwithnoextensions.ThistranslatortakesintheBDNE TlethatisgeneratedbySISasinput andgeneratesaverilogleforthecontrollerofthedesign. TheBDNETlehastheinputsand outputsofthecontrollerandthegatesmappedwiththesigna lsofthecontrollerastheinputsand outputsaccordingtothefunctionality.3.6.6.3VHDLtoVerilogTranslator NAME:vhd2vl SYNOPSIS:vhd2vldesign dp.vhddesign des.vhd DESCRIPTION:Thedesign dp.vhdisthenameofthelecontainingthedescriptionof datapathinVHDLanddesignlenameisthenameoflecontainingthetop-levelofthe designinVHDL.Thistranslatortakesinthedesign dp.vhdandthedesign des.vhdas inputsandgeneratesthreeverilogleswiththeprimaryinp utsandoutputsofthedesignandthe datapathforthedesign.Itgeneratesadesign dp.vwhichhasallthecomponentsusedforthe datapathandtheirmappingofinputsandoutputs,adesign des.vwhichhasthenameofthe designasthemodule,theprimaryinputsandoutputsandadesign dp.interwhichcontainsall theintermediatesignalsthatareusedinthedatapathtomap theinputsandoutputstotheinstances ofthegates. 50

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3.6.6.4StepstoGeneratetheLayout STEP1:ObtainthethreeVHDLles(controller,datapath,an ddesign)fromAUDI. STEP2:Givethecontrollerleastheinputtothevhd2kisstr anslatortogeneratetheKISS le. STEP3:GivetheKISSleasinputtothescriptforSIStogetth eBDNETleasoutput. STEP4:GivetheBDNETleasaninputtothebdnet2verilogtra nslatortogettheverilogle ofthecontroller. STEP5:GivethedatapathleandthedesignlefromAUDItoth evhd2vltranslatorwhich willgivetheveriloglesforthedatapathandthedesignle STEP6:Concatenateallthefourverilogles(verilogdesig nle,verilogintermediatele, verilogcontrollerle,andverilogdatapathle)togetthe nalverilogleforthedesign. STEP7:Replacethenameofthenalverilogleinthese.ini lewhichisreadwhenSilicon Ensembleisinvoked. STEP8:InvokeSiliconEnsemble. Steps1-6areautomatedbywritingascriptwiththeexecutab lenamed n and givingthethreeVHDLlesasinput.3.6.6.5FunctionalityofBack-endTool Thissectiongivesafullexplanationofwhyandhoweachtool isusedinthisdesignprocess. Thehigherlevelowtodesignandsynthesizealowpowerimpl ementationofanydesignisgiven ingure3.9..TheVHDLmodelofthedesignisdone.AUDIisuse dtoforgeneratingtheRT leveldesignfromtheVHDL(Behavioral)modelthatisdescri bedasacontroller,datapathand design.Thecontrollerisanitestatemachinewithseveral statetransitionsdependingoninputs andsignals.SISisusedtogeneratethecontrollerdesignas alogicandmapthislogictostandard celllibrary.SIStakesKISSleasinputle.TheKISSformat givesthenumberofinputs,outputs, statesandthetransitionsofthestatesfromoneanother.SI SreadstheKISSleanddoesstate assignmentusingaprogramcalledjeditoassignvaluestoth estatesandprovidesthelatchesto changefromonestatetoanother.Thisstateassignmentiswr ittenintoaBLIFle.TheBLIF leisreadagaininSISandastandardcelllibraryisalsorea dandmapped.Theresultingleis 51

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theBDNETlewhichhasthealltheprimaryinputsandoutputs andthegatesmappedfromthe standardlibraryforthelogic.ThisBDNETleisgivenasinp uttothebdnet2verilogtranslatorthat translatestheleintoaverilogle.Figure3.10.explains theabovementionedsteps. Functional Verification of Design Low-power feature implementation Logic and Layout Synthesis RT Level Synthesis Behavioral Design Specifications Synthesis Figure3.9.SteptoDesignandSynthesizeaLowPowerSystem TheVHDLlesforthedatapathandthedesignaregivenasinpu tstothevhd2vltranslator.It translatestheselesintotwointermediatelesinverilog les.Thedesign dp.vlehasallthe datapathinverilogformat.Thedesign des.vlehastheprimaryinputsandoutputsofthe designinverilogformattranslatedfromthedesign des.vhd.Thedesign dp.interlehas alltheintermediatesignalsthatareusedformappingthein stancesofthecomponentsinthedata pathtobeincludedinthemainverilogle. Allthefourveriloglesobtainedabovenamelythecontroll er,datapath,design,andtheintermediatesignalleareconcatenatedintoasinglele.These .inilehasallcommandstoautomat52

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Low Leakage Non-Low Leakage or Flow2 Flow1 Recovery Performance and Power Management Binding Selective Binding Automatic (Clique Partitioning) Allocation Scheduling (DFG) Data Flow Graph (VHDL) Behavioral code LIBRARY CELL STANDARD RT-Level AUDI LIBRARY CELL STANDARD Datapath(Verilog) RT-Level Automatic Place and Route Silicon Ensemble Power Leakage NANOSIM Spice Netlist and Cadence Layout HSPICE Power Leakage Translator Translator VHDL2Verilog BDNET2Verilog Translator VHDL2KISS Datapath (VHDL) Figure3.10.OverallDataFlowDiagramofSynthesisofDesig n 53

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icallyplaceandroutethedesigninSiliconEnsemble.Thena meofthedesignisreplacedinthe se.iniwhichreferstothelibrarywhichhastheabstractand layoutofthestandardcellsandSilicon Ensembleisinvokedwhichrstreadsallthecontentsofse.i nitoautomaticallyplaceandroutethe entiredesignwhoseoutputisgiventoaDEFle.ThisDEFlei simportedintocadenceandthe layoutisdonewhichissimulatedandtested.3.7LeakageReductionUsingLow-LeakageStandardCells Leakagepowerconsumptionhasbecomeaverysignicantpart ofthetotalpowerconsumption duetoanincreaseinthechipspeedanddensityinsubmicrons cale.Avetimeincreaseinleakage powerhasbeenobserved,leadingittobeequaltothedynamic powerofthecircuit.Leakagepower becomesamajorcomponentofpowerdissipationinportablea ndwirelessapplicationsduetothe increasedidletimeofthecircuits. ThedatapathobtainedfromAUDIcomprisesofcomponentsfro maparameterizedmacro-cell library,developedbytheUniversityofCincinnati[23].Th elibraryconsistsofadders,subtractors, multipliers,registers,multiplexers,andbuses. Weuseautomaticplaceandrouteofstandardcellstobuildth edesign.Theentiredesignis presentedintermsofstandardcellsensuringtheeaseofaus ertoobtainthelayoutofhisdesign withthebasicleafgates.Acharacterizedstandardcelllib raryconsistingoflayoutsofalltheabove functional,storageandinterconnectunitsisbuiltusingt hedeepsub-microntechnology.Eachof thesemacrocellsaretransformedintermsoftheirstandard cells.Themacrocellcomponentsin thedatapathsynthesizedbyAUDI,instantiatesthestandar dcellstoformamacrocelllayout. TheauthorsJayakumarandKhatri[ ? ]haveproposedthedesignofstandardcellswithpredictablylowleakagecurrentsdependingontheinputsofaga te.Iftheinputstoacellduring standbymodeofoperationaresuchthattheoutputhasahighv alue,thentheleakageisminimized inthepull-downnetworkbyintroducingahigh NMOSdeviceconnectedtothe signal. Similarly,iftheinputsofacellduringstandbymodeissuch thattheoutputhasalowvalue,then theleakageisminimizedinthepull-upnetworkbyintroduci ngahigh PMOSdeviceconnected tothestandbysignal. 54

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Theinputstoourdesigncannotbepredictedaprioriduetoth euncertaintyoftheuser'slocation.Hence,weextendtheaboveconceptofleakage-immunes tandardcellsbyintroducingsleep transistorstocutoffthepowersupplyorground[26]ofthel eafcellsinthestandard-celllibrary.A lowsleeptransistor(PMOSorNMOS)isintroducedforeverycomp onentbetweenthepower supplyorgroundandthepowerterminalofthecircuit,thusa ctingasavirtualVdd.Thesignal SLEEPisconnectedtothesleeptransistortoswitchbetween the`active'and`sleep'modes.In theactivemode,theSLEEPsignalissetto`0',thusturningo nthesleeptransistor.Withavery smallonresistancethesleeptransistoractsasarealpower line.Hence,thegateoperatesinthe normalmode.Inthesleepmode,theSLEEPsignalissetto`1', turningoffthesleeptransistor,so thatthevirtualVddlineisoatingandviceversaforthe signal.Onesleeptransistoris sufcienttoreduceleakagepowerineachstandardcell.The SLEEPsignalisaglobalsignalthat isconnectedtoalltheSLEEPsignalofalltheleafcellsinth edatapathofthedesign.Onenabling theglobalSLEEPsignal,theentiredatapathofthedesignis puttosleep. SLEEP STANDARD CELL VDD GND SLEEP VDD CLEAR GND REGISTER Figure3.11.StandardCellwithSleepTransistor Ourstandardcelllibrarywithsleeptransistorsconsistso fthefollowingcells:INV,AND2, OR2,NAND2,NOR2,XOR2,COMPARATOR2,SRAM,1-BITMUX,1-BIT FULLADDER, 1-BITREGISTER.WhenthereisaCLEARsignal,theregistersn eedtobeactive.Henceforthis purpose,anadditionalparalleltransistorasshowninthe gure3.13..Tofurtherreducetheleakage powerinregisters,theclockoftheregistersiscutdowndur ingthesleepmodeusingtheconcept ofclockgating[11].Whenthesleepsignalisactive,theclo cktotheregistersareshutdown,soas toreducetheswitchingactivityduringthesleepmode,lead ingtomoreleakagepowerreduction. 55

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3.7.1Leakage-DelayTradeoff Eachofthestandardcellswithsleeptransistorsexhibitdi fferentleakagepowercharacteristics dependingonthewidthofthesleeptransistor.Duringthesl eepmode,thepull-uporpull-down networkisisolatedfromthesupplylineseitherbyalow PMOSsleeptransistororlow NMOS transistorrespectively.Theleakagepowerdissipateddur ingthesleepmodeismajorlyduetothe sleeptransistor.Thestandardcelllibraryhasbeencharac terizedforleakagepowerasafunction ofthesleeptransistorwidthduringthesleepmode.Itisobs ervedthat,asthewidthofthesleep transistorincreases,theleakagepowerdissipatedbythes leeptransistorincreases.Thisisdueto thefactthatthesub-thresholdleakagecurrentdependsont he(W/L)ratioofthetransistor.But withandecreaseinwidthofthesleeptransistor,thedelayo fthegateincreases.Hence,theleakage powersavingsanddelayareinverselyproportionaltothewi dthofthesleeptransistor.Power characterizationisdoneusingHSPICE. Figure3.12.LeakagePowerVsTransistorWidth Figure3.13.DelayVsTransistorWidth 56

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3.7.2Summary Inthischapter,wehavegivenadetaileddescriptionofthed esignandsynthesisoftheNAVIGATOR (ASIC),designedforthesearch-and-playmoduleofthetour guide.Wehavedesignedthetour guidetoprovideservicetotheuserdependingonlyhislocat ionofapre-decidedtourplanandhas nocommunicationwithaservertoaccessdata.Wehavealsode scribedthetechniquechosenfor thetourguidetoreduceleakagepowerdissipation.Experim entalresultsarepresentedinChapter 4. 57

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CHAPTER4 EXPERIMENTALRESULTS WepresentadetaileddescriptionofthesynthesisofASICan dthesynthesisenvironment.The resultsobtainedbyusingtheleakagereductiontechniquea realsopresented.Thebackendtool, developedtogeneratethelayoutfromRTLdesignisvalidate dusingbenchmarks. 4.1DesignFlow ThedesignstepstosynthesizetheASICareexplainedbelow: 1.BehaviorofASICcodedinVHDL.2.VHDLcodeistranslatedintotheAIF(Dataowgraph),inte rmediateformat. 3.AIFformatisgivenasinputtoAUDI.4.TheRTLleveldesignobtainedasaresultfromAUDIisgiven asinputtothebackendtool developedthussynthesizingtheCadencelayoutusingstand ardcelswithsleeptransistors. 5.ThedesignisextractedusingtheextractcommandinCaden ce. 6.Thenetlistleisobtainedfromtheextracteddesign.7.TheleakagepowerofthedesignismeasuredusingHSPICEus ingascriptcodedinshell scripttakingintoaccounttheleakagepowerofthetransist orsthatareinthe“off”state. 8.Steps4-7arerepeatedagainusingthestandardcelllibra rywithsleeptransistors. 9.ThesameinputsequencegiveninStep7aregiventothislow powercircuitandsimulated andthepowerismeasured. Thefollowingaretheresultspresentedforthisdesign, 58

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1.TheinputandoutputwaveformsfortheASICdesign.2.Effectofleakagepowerinindividualstandardcellswith sleeptransistors 3.Implementationofreal-worldapplicationssuchasDCTmo dule,IIR,andFIRltersusing theabovementionedbackendtoolandsleeptransistortoill ustratethereductioninleakage powerusingthistechnique. 4.ThelayoutsgeneratedbythebackendtoolthattakestheRT LVHDLdesignasinputand producesatransistorleveldesign. 4.1.1BehavioralLevelSimulationResultsfortheASICDesi gn Wepresentthesimulationresultsofthehigh-levelmodelin goftheNAVIGATOR.Theash memoryismodeledtocheckthefunctionalityoftheASIC.The datathatisstoredintheash memoryiswrittenasatextle.ThedataiswrittenintheCHSf ormatsimilartothedatastoredin aCompactFlashMemory.Eachsectorcontains512bytesofdat a. TherstsectorcontainstheMasterBootrecordwhichcontai nsinformationaboutthestartof thepartition.TheRootdirectoryandtheFATtablearestore dwiththeircorrespondingvaluesin theconsecutivesectors.TheGPSlatitudeandlongitudedat awiththecorrespondingaudiolesare storedinthesectorrepresentingthedataareafollowingth eRootDirectoryentries.Theremaining sectorscontaintheaudiodataofthedifferentlocations. ThetoplevelmodelintegratestheASICmoduleandtheFlashm emorymodule,thuspresenting thefunctionalityofthetourguide.Wheninputsaregivento thetoplevelmodel,theASICmodule sendsoutsignalsanddatatotheashmemorymodule.Theash memorymodulereadsinthe datafromthetextlecorrespondingtotheaddressreceived ,andsendbackthedatatotheASIC module.Theaudioinformationisplayedoutseriallybitbyb it,tobeplayedtotheuserbythe audiocodec. The`go'and`GPSlatlong'signalsaretheprimaryinputstot hetoplevelmodule.`RD',`WR' and`address'signalsaretheoutputsignalsoftheASICmodu leandtheinputsignalsfortheFlash memorymodule.The`data'signalisabidirectionalsignalt oreadandwritedataintoboththe 59

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ASICandtheFlashmemorymodulesrespectively.The`sdout' signalistheprimaryoutofthetop levelmodulewhichoutputstheserialaudiodata. Figure4.1.showstheresults,whentheASICinterfaceswith theashmemorymoduleto searchforamatch.TheCHS/LBAaddressestobewrittenontot heTaskleregistersappearon the`data'bus.Figure4.2.showstheoutputserialaudiodat astreamwhenthereisamatchofGPS co-ordinates.4.1.2Low-LeakageStandardCells Inthissection,wepresenttheresultsobtainedforreducti oninleakageinstandardcellswhen asleeptransistorisintroducedintheP-network.Whena“HI GH”gatevoltageisappliedacrossthe sleeptransistor,thecircuitisgatedfromtheVDDsupply.G atingtheVDD,reducestheleakage currentowingthroughthepull-upnetworkwhenoneormoret ransistorsareinthe“OFF”state. Thesleeptransistorsinourstandardcelllibraryaresized threetimesthesizeofthetransistorsin thepull-upnetwork.Hencetheworst-caseoutputdelaypena ltyoverallthegateinputtransistions isnotlargerthan15%.Byincreasingthesizeofthesleeptra nsistorevenmore,willresultinmore reductioninleakageanddelay.Thestandardheightofthece llsinthestandardcelllibrary,used forplaceandrouteofthedesignusingSiliconEnsemble,and increaseinareaoverhead,becomea limitingfactortothewidthofthesleeptransistor.Sizing ofthesleeptransistorthreetimesthesize ofthepull-upnetwork,showsignicantleakagepowersavin gsandasmallincreaseindelayfor allinputcombinationsofeachofthestandardcells.Table4 .1.showstheleakagevaluesofallthe standardcellsinthelibrarywithandwithoutsleeptransis tors.Table4.2.showsthedelayoverhead incurredduetotheadditionofthesleeptransistor.Thelay outsforthestandardcellswithsleep transistorsarealsogiven.4.2RealWorldApplications Thestandardcelllibrarywithleakageanddelayoptimizati onspresentedaboveisusedinthe synthesisofsomerealworldapplicationssuchasDSPlters suchasIIR,FIR,andbenchmarks 60

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Page 1 of 1 Printed by SimVision from Cadence Design Systems, Inc. Printed at 14:08:41 on Tue, Mar 23, 2004 Cursor-Baseline = 486,036,563,813fs Baseline = 0 Cursor = 486036.563813ns Figure4.1.BehaviorofASICwhen`go'SignalisAsserted 61

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Page 1 of 1 Printed by SimVision from Cadence Design Systems, Inc. Printed at 14:10:02 on Tue, Mar 23, 2004 Cursor-Baseline = 486,036,563,813fs Baseline = 0 Cursor = 486036.563813ns Figure4.2.SerialAudioDataOutputwhenthereisaMatch 62

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Table4.1.LeakagePowerSavingsinStandardCells Gate Leakagewithout Leakagewith PowerSavings sleep(nF) sleep(nF) (%) NOR 19.186 4.5779 76.13 NAND 1.835 1.0217 44.30 AND 36.143 3.9287 89.13 OR 38.842 9.6520 75.15 XOR 7.068 1.1894 83.17 1-bitADDER 194.670 31.9410 83.59 Dlatch 61.440 7.2620 88.18 Table4.2.DelayOverheadDuetoSleepTransistorinStandar dCells Gate Delaywithout Delaywith Overhead sleep(ns) sleep(ns) (%) NOR 0.283 0.292 3.18 NAND 0.067 0.074 10.44 AND 0.109 0.133 22.01 OR 1.775 1.927 8.56 XOR 2.024 2.253 11.31 1-bitADDER 7.455 8.235 10.46 Dlatch 0.211 0.317 50.23 suchasFFTandDCT.Theleakagepowerfortheseapplications isshowninTable4.3..Thearea overheadincurredduetotheadditionofsleeptransistorsi sgiveninTable4.4.. Table4.3.LeakagePowerSavingsinRealWorldApplications Application Leakagewithout Leakagewith PowerSavings sleep(nF) sleep(nF) (%) IIR 36590 9710 73.40 FIR 23120 9479 59 DCT 33360 13330 60.04 FFT 45930 1375 68 ELLIP 33290 13480 59.50 FromTable4.3.,weobservethatthereisanaverage65%leaka gepowersavingswithanaverageareaoverheadof21%. 63

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Table4.4.AreaOverheadinRealWorldApplications Application Areawithout Areawith Overhead sleep( ) sleep( ) (%) IIR 400725.18 508628.98 26.90 FIR 495039.47 594757.32 20.26 DCT 717974.60 870332.51 21.22 FFT 300869.44 349845.36 16.28 ELLIP 598371.84 657935.77 9.95 4.3LayoutsGeneratedbyBackEndTool Thissectiongivestheresultsfromthebackendtooldevelop edtoobtainthelayoutofthesynthesizeddesigns.ThelayoutsforFIRlter,DCT,andFFTben chmarksareshowninFigures4.3., 4.4.,and4.5..4.4Summary Experimentalresultsandwaveformsareshownforthedesign andsimulationoftheNAVIGATOR (ASIC).Theback-endtooldevelopedisvalidatedbyusingth eseveralbenchmarks.Theleakage standardcelllibrarywithGatedVddstyleisshowntobeeffe ctive 64

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Figure4.3.GeneratedLayoutforIIRFilter 65

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Figure4.4.GeneratedLayoutforDCTApplication 66

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Figure4.5.GeneratedLayoutforFFTApplication 67

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CHAPTER5 CONCLUSIONSANDFUTURERESEARCH Wepresentedanovelapproachinlocation-awarecomputingb ydesigningatourguidethatis dependentonlyontheuser'scurrentlocation.Otherapplic ationsdevelopedinthisareadepend oncommunicationwithanexternalserver,whichrestrictst hemobilityoftheuserwithingthe rangeoftheserver.Thereisalsoanoverheadofcommunicati ononthedeviceandthecostof implementingwirelessnetworkwiththeserver.Oursystemd oesnotsufferfromtheseoverheads. Itgivestheusertheinformationabouteverylocationandth enearbylocationinthepre-planned tour,enablinghimtokeeptrackofhislocationcorrespondi ngtothetourplan.Thefunctionalityof searchingandplayingtheaudioinformationoftheuser'scu rrentlocationismodeledinbehavioral VHDLasalowpowerASIC.Tofacilitatethegenerationofphys icallayout,abackendtoolis developed.Thevalidationofthebackendtoolisdoneusings everalbenchmarks.Thisleadstothe physicalimplementationoftheASICwithverylessuserinte rventionusingautomaticplaceand route.Leakagepowerisreducedbyintroducingsleeptransi storsthatgatetheVddinthestandard cells,thatareusedinplaceandroute5.1FutureResearch Thefollowingarethemostpossibleextensionstothepropos edapproach: 1.Incorporatetextualdisplayforthecurrentlocationtog iveanoptionofaudioortextoutput totheuser. 2.Incorporateanindoorpositioningsystemtoprovideserv icetotheuser. 3.Inclusionofmoreuseroptions,suchasrepeat,scrolling themenu,etc. 4.Synthesisoftheentirefunctionalityofthesystemonasi nglechip(SystemonaChip). 5.Automaticallyretrieveaudio/textdataastheGPSco-ord inateschange. 6.Implementsleeptransistorsandsleepsignalforthecont rollerofthedesign. 68

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REFERENCES [1]M.CravattsA.AsthanaandP.Krzyzanowski.Anindoorwir elesssystemforpersonalized shoppingassistance.In IEEEWorkshoponMobileComputingSystemsandApplications SantaCruz,CA,US,1994. [2]J.Youll,J.Morris,R.Krikorian,andP.Maes.“Impulse: Location-basedAgentAssistance ”. MITMediaLab [3]N.Marmasse,C.Schmandt.“Location-awareinformation deliverywithcomMotion”. MIT MediaLaboratory [4]G.ChenandD.Kotz.“surveyofcontext-awaremobilecomp utingresearch”.Technical ReportTR2000-381,Dept.ofComputerScience,DartmouthCo llege,November2000. [5]B.Schilit,N.Adams,andR.Want.“Context-awarecomput ingapplications”. Proceedings ofIEEEWorkshoponMobileComputingSystemsandApplicatio ns ,pages85–90,December 1994. [6]J.Bergqvist,P.Dahlberg,H.Fagrell,andJ.Redstrom.“ LocationAwarenessandLocalMobility”. [7]G.Abowd,C.Atkeson,J.Hong,S.Long,R.KooperandM.Pin kerton.“Cyberguide:A mobilecontext-awaretourguide”. WirelessNetworks ,3:421–433,October1997. [8]“http://iroi.seu.edu.cn/books/asics/ASICs.htm/an chor11320”. [9]A.P.Chandrakasan,S.Sheng,andR.W.Brodersen.“Low-P owerCMOSDigitalDesign”. IEEEJournalofSolid-StateCircuits ,27:473–484,April1992. [10]K.Cheverst,N.Davies,K.Mitchell,A.Friday,C.Efstr atiou.“DevelopingaContext-aware ElectronicTouristGuide:SomeIssuesandExperiences”. DistributedMultimediaResearch Group,DepartmentofComputing,LancasterUniversity [11]L.Benini,G.DeMicheli.“Transformationandsynthesi sofFSMsforlowpowergatedclock implementation”. InProceedingsofthe1995ACM/IEEEInternationalSymposiu monLow PowerDesign ,pages21–26,1994. [12]M.Alidina,J.Monteiro,S.Devadas,A.GhoshandM.Papa efthymiou.“Precomutationbasedsequentiallogicoptimizationforlowpower”. InProceedingsofthe1994International ConferenceonComputerAidedDesign ,pages398–402,November1993. [13]V.Tiwari,S.Malik,andP.Ashar.“Guardedevaluation: Pushingpowermanagementto logicsynthesis/design”. InProceedingsofthe1995InternationalSymposiumonLowPo wer Design ,pages221–226,November1995. 69

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[14]J.Monteiro,S.Devadas,andA.Ghosh.“Retimingsequen tialcircuitsforlowpower”. In ProceedingsoftheIEEEInternationalConferenceonComput erAidedDesign ,pages398– 402,November1993. [15]C.Papachristou,M.Nourani,andM.Spining.“AMultipl eClockingSchemeforLow-Power RTLDesign”. IEEETransactionsonVeryLargeScaleIntegration(VLSI)Sy stems ,7:266– 276,June1999. [16]Y.Ye,S.Borkar,andVivekDe.“ANewTechniqueforStand byLeakageReductioninHighPerformanceCircuits”. SymposiumonVLSICircuitsDigestofTechnicalPapers ,10,1998. [17]S.Mutoh,S.Shigematsu,Y.Matsuya,Y.Tanabe,J.Yamad a.“A1-VHigh-SpeedMTCMOS CircuitSchemeforPower-DownApplicationCircuits”. IEEEJournalofSolid-StateCircuits 32(11):861–869,June1997. [18]S.Muhkopadhyay,C.Neau,R.T.Cakici,A.Agarwal,C.H. Kim,K.Roy.“GateLeakage ReductionforScaledDevicesUsingTransistorStacking”. IEEETransactionsonVeryLarge ScaleIntegration(VLSI)Systems ,11(12):716–730,August2003. [19]Z.Chen,M.Johnson,L.WeiandK.Roy.“EstimationofSta ndbyLeakagePowerinCMOS CircuitsConsideringAccurateModelingofTransistorStac ks”. ProceedingsonLowPower ElectronicsandDesign ,(13):239–244,August1998. [20]N.HanchateandN.Ranganathan.“LECTOR:ATechniquefo rLeakageReductioninCMOS Circuits”. IEEETransactionsonVeryLargeScaleIntegration(VLSI)Sy stems ,12:196–205, February2004. [21]SANDISK,editor. “CompactFlashMemoryCardProductManual” .SANDISKCorporation,2002. [22]“http://www.maverickos.dk/FileSystemFormats/FAT 16 FileSystem.html”. [23]C.Gopalakrishnan.“http://80-purl.fcla.edu.proxy .usf.edu/fcla/etd/SFE0000147”. [24]E.M.Sentovich,K.J.Singh,L.Lavagno,C.Moon,R.Murg ai,A.Saldanha,H.Savoj,P.R. Stephan,R.K.Brayton,andA-SVincentelli,editor. “SIS:ASystemforSequentialCircuit Synthesis” .UniversityofCalifornia,Berkeley,1992. [25]CadenceDesignSystems,editor. “Envisia-SiliconEnsemblePlaceandRouteReference” Cadence,2000. [26]N.Jayakumar,S.P.Khatri.“AnASICDesignMethodology withPredictablyLowLeakage, usingLeakage-immuneStandardCells”.In ISLPED ,August,2003. 70

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APPENDICES 71

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AppendixABehavioralVHDLCodeofNAVIGATOR-------------------------------------------------------------------------------Navigator.vhd----Author:Uma--Created:Nov2003--LastModified:March2004----Interfacestheoff-the-shelfcomponentsoftheTourGuid etocompare --theinputGPSco-ordinatesfromGPSreceiverwiththeGPSc o-ordinates --storedinthelookuptable.txt.Ifthereisamatch,thecor responding --audiofilenameisreadandthedatastoredintheaudiofile isplayed --outasaserialstream.-----------------------------------------------------------------------------libraryIEEE;useIEEE.numeric_std.all;useIEEE.std_logic_arith.all;useIEEE.std_logic_1164.all;useIEEE.std_logic_unsigned.all;useSTD.TEXTIO.all;entityflashis port( go:instd_logic;GPSlatlong:instd_logic_vector(511downto0);address:outstd_logic_vector(2downto0);data:inoutstd_logic_vector(15downto0);sdout:outbit;RD:outstd_logic;WR:outstd_logic);endflash;architecturebehaviorofflashis functionbits_to_int(input:std_logic_vector)returnIN TEGERis variableret_val:INTEGER:=0; begin foriininput'RANGEloop ifinput(i)='1'then ret_val:=2**i+ret_val; endif; endloop;returnret_val; endbits_to_int; signalcyl_lowaddr:std_logic_vector(15downto0);signalcyl_highaddr:std_logic_vector(15downto0);signalhead_addr:std_logic_vector(15downto0);signalsect_countaddr:std_logic_vector(15downto0) :="0000000000000001"; signalsect_numberaddr:std_logic_vector(15downto0) :="0000000000000001"; signalcmd_addr:std_logic_vector(15downto0) :="0000000000100000"; typememoryisarray(0to255)ofstd_logic_vector(15downt o0); signalRootDir_mem:memory;signalFAT_mem:memory;beginprocessvariablestatus:std_logic_vector(15downto0);variablecheck:std_logic_vector(15downto0);variableplayout:bit_vector(15downto0);variableplaydata:std_logic_vector(15downto0); 72

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AppendixA(Continued)variablecylsec,temproot:std_logic_vector(15downto0) ; variablecylsectemp:std_logic_vector(7downto0);variableshifttemp:std_logic_vector(7downto0);variablehead_concat:std_logic_vector(11downto0);variablebootcylinderaddr:std_logic_vector(15downto0 ); variablebootheadaddr:std_logic_vector(3downto0);variablebootsectoraddr:std_logic_vector(15downto0);variablefatcylinderaddr:std_logic_vector(15downto0) ; variablefatheadaddr:std_logic_vector(3downto0);variablefatsectoraddr:std_logic_vector(15downto0);variableincfatcylinderaddr:std_logic_vector(15downt o0); variableincfatheadaddr:std_logic_vector(3downto0);variableincfatsectoraddr:std_logic_vector(15downto0 ); variablerootdircylinderaddr:std_logic_vector(15down to0); variablerootdirheadaddr:std_logic_vector(3downto0);variablerootdirsectoraddr:std_logic_vector(15downto 0); variabledatacylinderaddr:std_logic_vector(15downto0 ); variabledataheadaddr:std_logic_vector(3downto0);variabledatasectoraddr:std_logic_vector(15downto0);variableincdatacylinderaddr:std_logic_vector(15down to0); variableincdataheadaddr:std_logic_vector(3downto0);variableincdatasectoraddr:std_logic_vector(15downto 0); variableincdatasectoroffset:std_logic_vector(15down to0); variablesectorspercluster:std_logic_vector(7downto0 ); variablesectorsperclustertemp1:std_logic_vector(7do wnto0); variablebytespersector:std_logic_vector(15downto0);variablereservedsectors:std_logic_vector(15downto0) ; variablerootdirentries:std_logic_vector(15downto0);variablesectorsperFAT:std_logic_vector(15downto0);variablemaxrootdirentries:std_logic_vector(15downto 0); variablelookupentry:std_logic_vector(15downto0);variableloopvar:std_logic_vector(15downto0);variabletempfatentry:std_logic_vector(15downto0);variabletempfatentrycopy:std_logic_vector(15downto0 ); variabletemproot1:std_logic_vector(31downto0);variableFATtable:std_logic_vector(4095downto0);variableclustersperhead:std_logic_vector(7downto0);---integerdeclarations-variableRDctr:INTEGER:=0;variablefile_ctr,file1,file2,file3,file4:INTEGER:=0 ; variableRootDir_Ctr:Integer;variableFAT_Ctr:INTEGER;variablesectorsperclustervar1:INTEGER:=0;variableplaybit:INTEGER:=0;variablebitcount:INTEGER:=0;variabletempfatvar:INTEGER:=0;variableflag:INTEGER:=1;----thesevariablesaretovalidatethefullarithmeticope ration variabledtemp1:std_logic_vector(31downto0);variabledtemp2:std_logic_vector(31downto0);variablelookupfilename:std_logic_vector(87downto0);--testdatasvariableltemp0:std_logic_vector(15downto0);variableltemp1:std_logic_vector(31downto0);variableltemp2:std_logic_vector(47downto0);variableltemp3:std_logic_vector(63downto0);variableltemp4:std_logic_vector(79downto0);variableltemp5:std_logic_vector(95downto0);variableltemp6:std_logic_vector(111downto0);variableltemp7:std_logic_vector(127downto0);variableltemp8:std_logic_vector(143downto0);variableltemp9:std_logic_vector(159downto0);variableltemp10:std_logic_vector(175downto0); 73

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AppendixA(Continued)variableltemp11:std_logic_vector(191downto0);variableltemp12:std_logic_vector(207downto0);variableltemp13:std_logic_vector(223downto0);variableltemp14:std_logic_vector(239downto0);variableltemp15:std_logic_vector(255downto0);variableltemp16:std_logic_vector(271downto0);variableltemp17:std_logic_vector(287downto0);variableltemp18:std_logic_vector(303downto0);variableltemp19:std_logic_vector(319downto0);variableltemp20:std_logic_vector(335downto0);variableltemp21:std_logic_vector(351downto0);variableltemp22:std_logic_vector(367downto0);variableltemp23:std_logic_vector(383downto0);variableltemp24:std_logic_vector(399downto0);variableltemp25:std_logic_vector(415downto0);variableltemp26:std_logic_vector(431downto0);variableltemp27:std_logic_vector(447downto0);variableltemp28:std_logic_vector(463downto0);variableltemp29:std_logic_vector(479downto0);variableltemp30:std_logic_vector(495downto0);variableltemp31:std_logic_vector(511downto0);beginwaituntilgo='1';------------------------------------------------------------------------------------Writingthecylinderlowregisterintheflas h -----------------------------------------------------------------------RD<='1';WR<='1';cyl_lowaddr<="0000000000000000";cyl_highaddr<="0000000000000000";head_addr<=head_concat&"0000";sect_countaddr<="0000000000000000";sect_numberaddr<="0000000000000000";cmd_addr<="0000000000100000";waitfor25ns;Address<="100";data<=cyl_lowaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecylinderhighregisterinthefla sh -----------------------------------------------------------------------Address<="101";data<=cyl_highaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingtheheadregisterintheflash-----------------------------------------------------------------------Address<="110";data<=head_addr;waitfor25ns;WR<='0';waitfor70ns; 74

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AppendixA(Continued)WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectorcountregisterintheflas h -----------------------------------------------------------------------Address<="010";data<=sect_countaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectornumberregisterinthefla sh -----------------------------------------------------------------------Address<="011";data<=sect_numberaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecommandregisterintheflash-----------------------------------------------------------------------Address<="111";data<=cmd_addr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Readingthestatusregisterintheflash-----------------------------------------------------------------------RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;while(status(7)/='0')loopRD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;RootDir_Ctr:=0;endloop;while(status(3)/='0')loopAddress<="000";waitfor25ns;RD<='0';waitfor70ns;RootDir_mem(RootDir_Ctr)<=data;ifRootDir_Ctr=223then bootheadaddr:=data(3downto0); elsifRootDir_Ctr=224then 75

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AppendixA(Continued) cylsec:=data; endif;RootDir_Ctr:=RootDir_Ctr+1;RD<='1';waitfor25ns;Address<="111";waitfor25ns;RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;endloop;-------------------------------------------------------------------------------computingthecylinderaddressfromcylsecvalue-----------------------------------------------------------------------------cylsectemp:=cylsec(7downto0)AND"11000000";shifttemp:=cylsectemp;cylsectemp(7downto2):=shifttemp(5downto0);cylsectemp(1downto0):="00";bootcylinderaddr(7downto0):=cylsec(15downto8)ORcyls ectemp; -------------------------------------------------------------------------------computingthesectoraddressfromcylsecvalue-----------------------------------------------------------------------------bootsectoraddr(7downto0):=cylsec(7downto0)AND"00111 111"; -------------------------------------------------------------------------------AccessingtheBootRecord-----------------------------------------------------------------------------------------------------------------------------------------------------------------Writingthecylinderlowregisterintheflas h -----------------------------------------------------------------------RD<='1';WR<='1';waitfor25ns;Address<="100";data<=bootcylinderaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecylinderhighregisterinthefla sh -----------------------------------------------------------------------Address<="101";data<="0000000000000000";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingtheheadregisterintheflash-----------------------------------------------------------------------Address<="110";data<=head_concat&bootheadaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns; 76

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AppendixA(Continued)data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectorcountregisterintheflas h -----------------------------------------------------------------------Address<="010";data<="0000000000000001";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectornumberregisterinthefla sh -----------------------------------------------------------------------Address<="011";data<=bootsectoraddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecommandregisterintheflash-----------------------------------------------------------------------Address<="111";data<=cmd_addr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Readingthestatusregisterintheflash-----------------------------------------------------------------------RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;while(status(7)/='0')loopRD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;RootDir_Ctr:=0;endloop;while(status(3)/='0')loopAddress<="000";waitfor25ns;RD<='0';waitfor70ns;RootDir_mem(RootDir_Ctr)<=data; ifRootDir_Ctr=5then bytespersector(7downto0):=data(15downto8); elsifRootDir_Ctr=6then bytespersector(15downto8):=data(7downto0);sectorspercluster:=data(15downto8); elsifRootDir_Ctr=7then 77

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AppendixA(Continued) reservedsectors:=data; elsifRootDir_Ctr=8then maxrootdirentries(7downto0):=data(15downto8); elsifRootDir_Ctr=9then maxrootdirentries(15downto8):=data(7downto0); elsifRootDir_Ctr=11then sectorsperFAT:=data; endif;RootDir_Ctr:=RootDir_Ctr+1;RD<='1';waitfor25ns;Address<="111";waitfor25ns;RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;endloop;-------------------------------------------------------------------------------findingthestartingoftheFATtable-----------------------------------------------------------------------------fatcylinderaddr:=bootcylinderaddr;fatheadaddr:=bootheadaddr; fatsectoraddr:=bootsectoraddr+reservedsectors; iffatsectoraddr>"0000000000100000"then iffatheadaddr<"0010"then fatheadaddr:=fatheadaddr+"0001"; fatsectoraddr:="0000000000000001"; else fatcylinderaddr:=fatcylinderaddr+"0000000000000001" ; fatheadaddr:="0000"; fatsectoraddr:="0000000000000001"; endif; endif; incfatcylinderaddr:=fatcylinderaddr;incfatheadaddr:=fatheadaddr;incfatsectoraddr:=fatsectoraddr; -------------------------------------------------------------------------------findingthestartingaddressoftheRootdirectoryentry-----------------------------------------------------------------------------rootdircylinderaddr:=fatcylinderaddr;rootdirheadaddr:=fatheadaddr;temproot1:=sectorsperFAT*"0000000000000010"; rootdirsectoraddr:=fatsectoraddr+temproot1(15downto 0); ifrootdirsectoraddr>"0000000000100000"then ifrootdirheadaddr<"0010"then rootdirheadaddr:=rootdirheadaddr+"0001"; rootdirsectoraddr:="0000000000000001"; else rootdircylinderaddr:=rootdircylinderaddr+"000000000 0000001"; rootdirheadaddr:="0000";rootdirsectoraddr:="0000000000000001"; endif; endif; -------------------------------------------------------------------------------AccessingtheRootDirectoryTable------------------------------------------------------------------------------------------------------------------------------------------------------Writingthecylinderlowregisterintheflash-----------------------------------------------------------------------RD<='1'; 78

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AppendixA(Continued)WR<='1';waitfor25ns;Address<="100";data<=rootdircylinderaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecylinderhighregisterinthefla sh -----------------------------------------------------------------------Address<="101";data<="0000000000000000";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingtheheadregisterintheflash-----------------------------------------------------------------------Address<="110";data<=head_concat&rootdirheadaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectorcountregisterintheflas h -----------------------------------------------------------------------Address<="010";data<="0000000000000001";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectornumberregisterinthefla sh -----------------------------------------------------------------------Address<="011";data<=rootdirsectoraddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecommandregisterintheflash-----------------------------------------------------------------------Address<="111";data<=cmd_addr;waitfor25ns;WR<='0';waitfor70ns;WR<='1'; 79

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AppendixA(Continued)waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Readingthestatusregisterintheflash-----------------------------------------------------------------------RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;while(status(7)/='0')loopRD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;RootDir_Ctr:=0;endloop;while(status(3)/='0')loopAddress<="000";waitfor25ns;RD<='0';waitfor70ns;RootDir_mem(RootDir_Ctr)<=data;RootDir_Ctr:=RootDir_Ctr+1;RD<='1';waitfor25ns;Address<="111";waitfor25ns;RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;endloop;-------------------------------------------------------------------------------findingthestartingofthedataarea-----------------------------------------------------------------------------datacylinderaddr:=rootdircylinderaddr;dataheadaddr:=rootdirheadaddr;dtemp1:=maxrootdirentries*"0000000000100000";dtemp2:=dtemp1; forjin0to8loop foriin30downto0loop dtemp2(i):=dtemp2(i+1);endloop; dtemp2(30):='0'; endloop; datasectoraddr:=rootdirsectoraddr+dtemp2(15downto0) ; ifdatasectoraddr>"0000000100000000"then datasectoraddr:=datasectoraddr-"0000000100000000"; ifdatasectoraddr>"0000000000100000"then ifdataheadaddr<"0010"then dataheadaddr:=dataheadaddr+"0001"; datasectoraddr:="0000000000000001"; else datacylinderaddr:=datacylinderaddr+"000000000000000 1"; dataheadaddr:="0000";datasectoraddr:="0000000000000001"; endif; endif; endif; incdatacylinderaddr:=datacylinderaddr; 80

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AppendixA(Continued) incdataheadaddr:=dataheadaddr;incdatasectoraddr:=datasectoraddr; -----------------------------------------------------------------------------------------comparingthegivenGPSlatitudelongitudewiththeGPSco ordinatesmentionedinthe --lookuptable.txt-------------------------------------------------------------------------------------lookupfilename:=; ------------------------------------------------------------------------------Searchingforthelocationofthelookuptable.wavinther ootdirectorytable ----------------------------------------------------------------------------file_ctr:=0;ltemp0:=RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp1:=ltemp0&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp2:=ltemp1&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp3:=ltemp2&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp4:=ltemp3&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp5:=ltemp4&RootDir_mem(file_ctr);iflookupfilename=ltemp5(95downto8)then file_ctr:=file_ctr+8;lookupentry:=RootDir_mem(file_ctr); else foriin1tomaxrootdirentriesloop file_ctr:=file_ctr+13; ltemp0:=RootDir_mem(file_ctr); file_ctr:=file_ctr+1; ltemp1:=ltemp0&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp2:=ltemp1&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp3:=ltemp2&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp4:=ltemp3&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp5:=ltemp4&RootDir_mem(file_ctr);iflookupfilename=ltemp5(95downto8)then file_ctr:=file_ctr+8;lookupentry:=RootDir_mem(file_ctr); endif; exitwhenlookupfilename=ltemp5(95downto8);endloop; endif; -------------------------------------------------------------------------------incrementingthedataareaaddresstoplaythesectorpoin tedbythe --firstclusteroftheRootdirectoryentry-----------------------------------------------------------------------------clustersperhead:="00010000";sectorsperclustertemp1:=sectorspercluster;---ShiftingRighttofindthepowerofsectorspercluster: whilesectorsperclustertemp1/="00000001"loop foriin0to6loop sectorsperclustertemp1(i):=sectorsperclustertemp1(i +1); endloop;sectorsperclustervar1:=sectorsperclustervar1+1;sectorsperclustertemp1(7):='0'; endloop; --Shiftingrighttodivide32/sectorsperclustertofindth eno.ofclustersperhead 81

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AppendixA(Continued) forjin1to3loop foriin0to6loop clustersperhead(i):=clustersperhead(i+1); endloop;clustersperhead(7):='0'; endloop; incdatasectoraddr:=lookupentry(7downto0)*sectorsper cluster; --lookupentry:=lookupentry-"0000000000000010"; --Shiftingrighttwicetodivideby4 forjin0to4loop foriin0to14loop lookupentry(i):=lookupentry(i+1); endloop; lookupentry(15):='0'; endloop; iflookupentryclustersperheadloop incdatacylinderaddr:=incdatacylinderaddr+"000000000 0000001"; lookupentry:=lookupentry-clustersperhead; endloop; incdataheadaddr:=lookupentry(3downto0); endif;-----------------------------------------------------------------Readingthelookuptableintolocalmemory---------------------------------------------------------------------------------------------------------------------------------------------------Writingthecylinderlowregisterintheflas h -----------------------------------------------------------------------RD<='1'; WR<='1';waitfor25ns;Address<="100";data<=incdatacylinderaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecylinderhighregisterinthefla sh -----------------------------------------------------------------------Address<="101";data<="0000000000000000";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingtheheadregisterintheflash-----------------------------------------------------------------------Address<="110";data<=head_concat&incdataheadaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ"; 82

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AppendixA(Continued)------------------------------------------------------------------------------------Writingthesectorcountregisterintheflas h -----------------------------------------------------------------------Address<="010";data<="0000000000001000";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectornumberregisterinthefla sh -----------------------------------------------------------------------Address<="011";data<=incdatasectoraddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecommandregisterintheflash-----------------------------------------------------------------------Address<="111";data<=cmd_addr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Readingthestatusregisterintheflash-----------------------------------------------------------------------whilecounter/=sectorsperclusterloop RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;while(status(7)/='0')loop RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;FAT_Ctr:=0; endloop;while(status(3)/='0')loopAddress<="000";waitfor25ns;RD<='0';waitfor70ns;FAT_mem(FAT_Ctr)<=data;FAT_Ctr:=FAT_Ctr+1;RD<='1';waitfor25ns;Address<="111";waitfor25ns;RD<='0';waitfor70ns; 83

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AppendixA(Continued)status:=data;RD<='1';waitfor25ns;endloop;------------------------------------------------------------------------------------------------ComparingtheinputGPSwiththeGPSvaluesinthelookupta ble -----------------------------------------------------------------------------------------------file_ctr:=0;ltemp0:=FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp1:=ltemp0&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp2:=ltemp1&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp3:=ltemp2&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp4:=ltemp3&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp5:=ltemp4&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp6:=ltemp5&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp7:=ltemp6&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp8:=ltemp7&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp9:=ltemp8&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp10:=ltemp9&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp11:=ltemp10&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp12:=ltemp11&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp13:=ltemp12&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp14:=ltemp13&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp15:=ltemp14&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp16:=ltemp15&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp17:=ltemp16&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp18:=ltemp17&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp19:=ltemp18&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp20:=ltemp19&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp21:=ltemp20&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp22:=ltemp21&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp23:=ltemp22&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp24:=ltemp23&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp25:=ltemp24&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp26:=ltemp25&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp27:=ltemp26&FAT_mem(file_ctr); 84

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AppendixA(Continued) file_ctr:=file_ctr+1;ltemp28:=ltemp27&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp29:=ltemp28&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp30:=ltemp29&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp31:=ltemp30&FAT_mem(file_ctr);file1:=file_ctr;ifGPSlatlong=ltemp31thenfile_ctr:=file_ctr+1; file2:=file_ctr; ltemp0:=FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp1:=ltemp0&FAT_mem(file_ctr);file_ctr:=file_ctr+1; ltemp2:=ltemp1&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp3:=ltemp2&FAT_mem(file_ctr); file_ctr:=file_ctr+1;ltemp4:=ltemp3&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp5:=ltemp4&FAT_mem(file_ctr); lookupfilename:=ltemp5(95downto8); else file_ctr:=file_ctr+7; file3:=file_ctr; ltemp0:=FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp1:=ltemp0&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp2:=ltemp1&FAT_mem(file_ctr); file_ctr:=file_ctr+1;ltemp3:=ltemp2&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp4:=ltemp3&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp5:=ltemp4&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp6:=ltemp5&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp7:=ltemp6&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp8:=ltemp7&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp9:=ltemp8&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp10:=ltemp9&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp11:=ltemp10&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp12:=ltemp11&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp13:=ltemp12&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp14:=ltemp13&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp15:=ltemp14&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp16:=ltemp15&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp17:=ltemp16&FAT_mem(file_ctr); 85

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AppendixA(Continued) file_ctr:=file_ctr+1;ltemp18:=ltemp17&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp19:=ltemp18&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp20:=ltemp19&FAT_mem(file_ctr);file_ctr:=file_ctr+1; ltemp21:=ltemp20&FAT_mem(file_ctr); file_ctr:=file_ctr+1;ltemp22:=ltemp21&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp23:=ltemp22&FAT_mem(file_ctr);file_ctr:=file_ctr+1; ltemp24:=ltemp23&FAT_mem(file_ctr); file_ctr:=file_ctr+1;ltemp25:=ltemp24&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp26:=ltemp25&FAT_mem(file_ctr);file_ctr:=file_ctr+1; ltemp27:=ltemp26&FAT_mem(file_ctr); file_ctr:=file_ctr+1;ltemp28:=ltemp27&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp29:=ltemp28&FAT_mem(file_ctr);file_ctr:=file_ctr+1; ltemp30:=ltemp29&FAT_mem(file_ctr); file_ctr:=file_ctr+1;ltemp31:=ltemp30&FAT_mem(file_ctr);ifGPSlatlong=ltemp31then file_ctr:=file_ctr+1; file4:=file_ctr; ltemp0:=FAT_mem(file_ctr);file_ctr:=file_ctr+1; ltemp1:=ltemp0&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp2:=ltemp1&FAT_mem(file_ctr); file_ctr:=file_ctr+1;ltemp3:=ltemp2&FAT_mem(file_ctr);file_ctr:=file_ctr+1;ltemp4:=ltemp3&FAT_mem(file_ctr); file_ctr:=file_ctr+1; ltemp5:=ltemp4&FAT_mem(file_ctr); lookupfilename:=ltemp5(95downto8); endif; endif; ------------------------------------------------------------------------------comparingthefilenameinlookuptablewithoneintheroot dirtablelocally ----------------------------------------------------------------------------file_ctr:=0;ltemp0:=RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp1:=ltemp0&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp2:=ltemp1&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp3:=ltemp2&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp4:=ltemp3&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp5:=ltemp4&RootDir_mem(file_ctr); iflookupfilename=ltemp5(95downto8)then file_ctr:=file_ctr+8; 86

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AppendixA(Continued) tempfatentry:=RootDir_mem(file_ctr); else foriin1tomaxrootdirentriesloop file_ctr:=file_ctr+13;ltemp0:=RootDir_mem(file_ctr); file_ctr:=file_ctr+1; ltemp1:=ltemp0&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp2:=ltemp1&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp3:=ltemp2&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp4:=ltemp3&RootDir_mem(file_ctr);file_ctr:=file_ctr+1;ltemp5:=ltemp4&RootDir_mem(file_ctr);iflookupfilename=ltemp5(95downto8)then file_ctr:=file_ctr+8;tempfatentry:=RootDir_mem(file_ctr); endif; exitwhenlookupfilename=ltemp5(95downto8); endloop;endif; incdatacylinderaddr:=datacylinderaddr;incdataheadaddr:=dataheadaddr;incdatasectoraddr:=datasectoraddr; ---------------------------------------------------------------------------------------------Readingalltheentriesofthefirstsectorintoatemporar yFATtable -------------------------------------------------------------------------------------------incfatcylinderaddr:=fatcylinderaddr;incfatheadaddr:=fatheadaddr;incfatsectoraddr:=fatsectoraddr;loopvar:="0000000010000000";-------------------------------------------------------------------------------StoringtheFATTablelocally------------------------------------------------------------------------------------------------------------------------------------------------------Writingthecylinderlowregisterintheflash-----------------------------------------------------------------------RD<='1';WR<='1';waitfor25ns;Address<="100";data<=incfatcylinderaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecylinderhighregisterinthefla sh -----------------------------------------------------------------------Address<="101";data<="0000000000000000";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingtheheadregisterintheflash-----------------------------------------------------------------------87

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AppendixA(Continued)Address<="110";data<=head_concat&incfatheadaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectorcountregisterintheflas h -----------------------------------------------------------------------Address<="010";data<="0000000000000001";waitfor25ns; WR<='0'; waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectornumberregisterinthefla sh -----------------------------------------------------------------------Address<="011";data<=incfatsectoraddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecommandregisterintheflash-----------------------------------------------------------------------Address<="111";data<=cmd_addr;waitfor25ns; WR<='0'; waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Readingthestatusregisterintheflash-----------------------------------------------------------------------RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;while(status(7)/='0')loopRD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;FAT_Ctr:=0;endloop;while(status(3)/='0')loopAddress<="000";waitfor25ns;RD<='0';waitfor70ns;FAT_mem(FAT_Ctr)<=data; 88

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AppendixA(Continued)FAT_Ctr:=FAT_Ctr+1;RD<='1';waitfor25ns;Address<="111";waitfor25ns;RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;endloop;whileflag=1loop iftempfatentry>loopvarthen incfatsectoraddr:=incfatsectoraddr+"000000000000000 1"; loopvar:=loopvar+"0000000010000000";ifincfatsectoraddr>="0000000000010000"then ifincfatheadaddr<"0010"then incfatheadaddr:=incfatheadaddr+"0001";incfatsectoraddr:="0000000000000001"; else incfatcylinderaddr:=incdatacylinderaddr+"0000000000 000001"; incfatheadaddr:="0000";incfatsectoraddr:="0000000000000001"; endif; endif; -------------------------------------------------------------------------Writingthecylinderlowregisterintheflash----------------------------------------------------------------------RD<='1'; WR<='1'; waitfor25ns; Address<="100"; data<=incfatcylinderaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecylinderhighregisterinthefla sh -----------------------------------------------------------------------Address<="101";data<="0000000000000000";waitfor25ns;WR<='0';waitfor70ns; WR<='1'; waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingtheheadregisterintheflash-----------------------------------------------------------------------Address<="110";data<=head_concat&incfatheadaddr; waitfor25ns; WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ"; 89

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AppendixA(Continued)------------------------------------------------------------------------------------Writingthesectorcountregisterintheflas h -----------------------------------------------------------------------Address<="010";data<="0000000000000001";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectornumberregisterinthefla sh -----------------------------------------------------------------------Address<="011";data<=incfatsectoraddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecommandregisterintheflash-----------------------------------------------------------------------Address<="111";data<=cmd_addr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Readingthestatusregisterintheflash-----------------------------------------------------------------------RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;while(status(7)/='0')loop RD<='0'; waitfor70ns;status:=data;RD<='1';waitfor25ns;FAT_Ctr:=0;endloop; while(status(3)/='0')loop Address<="000";waitfor25ns;RD<='0';waitfor70ns;FAT_mem(FAT_Ctr)<=data;FAT_Ctr:=FAT_Ctr+1;RD<='1';waitfor25ns;Address<="111";waitfor25ns;RD<='0';waitfor70ns;status:=data; 90

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AppendixA(Continued)RD<='1';waitfor25ns;endloop;endif; tempfatentrycopy:=tempfatentry;incdatasectoraddr:=tempfatentrycopy(7downto0)*secto rspercluster; incdatasectoroffset:=incdatasectoraddr-"00000000001 00000"; whileincdatasectoroffset>="0000000000100000"loop incdatasectoroffset:=incdatasectoroffset-"000000000 0100000"; endloop; forjin0to4loop foriin0to14loop tempfatentrycopy(i):=tempfatentrycopy(i+1);endloop; tempfatentrycopy(15):='0'; endloop;iftempfatentrycopyclustersperheadloop incdatacylinderaddr:=incdatacylinderaddr+"000000000 0000001"; tempfatentrycopy:=tempfatentrycopy-clustersperhead; endloop;incdataheadaddr:=tempfatentrycopy(3downto0); endif; ifincdatasectoraddr>="0000000000100000"then ifincdataheadaddr<"0010"then incdataheadaddr:=incdataheadaddr+"0001"; incdatasectoraddr:=incdatasectoroffset; else incdatacylinderaddr:=incdatacylinderaddr+"000000000 0000001"; incdataheadaddr:="0000";incdatasectoraddr:=incdatasectoroffset; endif; endif; ------------------------------------------------------------------------------Playingoutthenextclusterfromdataareaandfindingthe nextcluster ----------------------------------------------------------------------------foriin1tosectorsperclusterloop------------------------------------------------------------------------------------Writingthecylinderlowregisterintheflas h -----------------------------------------------------------------------RD<='1';WR<='1';waitfor25ns;Address<="100";data<=incdatacylinderaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecylinderhighregisterinthefla sh -----------------------------------------------------------------------Address<="101";data<="0000000000000000";waitfor25ns;WR<='0';waitfor70ns; 91

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AppendixA(Continued)WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingtheheadregisterintheflash-----------------------------------------------------------------------Address<="110";data<=head_concat&incdataheadaddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectorcountregisterintheflas h -----------------------------------------------------------------------Address<="010";data<="0000000000000001";waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthesectornumberregisterinthefla sh -----------------------------------------------------------------------Address<="011";data<=incdatasectoraddr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Writingthecommandregisterintheflash-----------------------------------------------------------------------Address<="111";data<=cmd_addr;waitfor25ns;WR<='0';waitfor70ns;WR<='1';waitfor25ns;data<="ZZZZZZZZZZZZZZZZ";------------------------------------------------------------------------------------Readingthestatusregisterintheflash-----------------------------------------------------------------------RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns;while(status(7)/='0')loop RD<='0';waitfor70ns;status:=data;RD<='1';waitfor25ns; endloop;while(status(3)/='0')loop 92

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AppendixA(Continued) Address<="000";waitfor25ns;RD<='0';waitfor70ns;playdata:=data;RD<='1';waitfor25ns;Address<="111";waitfor25ns;RD<='0';waitfor70ns;status:=data;RD<='1'; waitfor25ns;playout:=TO_BITVECTOR(playdata); forjin0to15loop sdout<=playout(0);waitfor1ns;playout:=playoutsrl1; endloop; endloop; incdatasectoraddr:=incdatasectoraddr+"0000000000000 001"; ifincdatasectoraddr>="0000000001000000"then ifincdataheadaddr<"0010"then incdataheadaddr:=incdataheadaddr+"0001"; incdatasectoraddr:="0000000000000000"; else incdatacylinderaddr:=incdatacylinderaddr+"000000000 0000001"; incdataheadaddr:="0000";incdatasectoraddr:="0000000000000000"; endif; endif; endloop;incdatacylinderaddr:=datacylinderaddr;incdataheadaddr:=dataheadaddr;incdatasectoraddr:=datasectoraddr; ----------------------------------------------------------------------------------------FindingthenexttempfatentryfromtheFATt able---------------------------------------------------------------------------------------tempfatvar:=bits_to_int(tempfatentry);tempfatentry:=FAT_mem(tempfatvar); exitwhentempfatentry="0000000011111111"; endloop;endprocess;endbehavior; 93