USF Libraries
USF Digital Collections

Broad-band space conservative on wafer network analyzer calibrations with more complex SOLT definitions

MISSING IMAGE

Material Information

Title:
Broad-band space conservative on wafer network analyzer calibrations with more complex SOLT definitions
Physical Description:
Book
Language:
English
Creator:
Padmanabhan, Sathya
Publisher:
University of South Florida
Place of Publication:
Tampa, Fla.
Publication Date:

Subjects

Subjects / Keywords:
error correction
cal comparison
complex models
TRL
cSOLT
Dissertations, Academic -- Electrical Engineering -- Masters -- USF   ( lcsh )
Genre:
government publication (state, provincial, terriorial, dependent)   ( marcgt )
bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

Notes

Summary:
ABSTRACT: An improved Short-Open-Load-Thru (SOLT) on-wafer vector network calibration method for broad-band accuracy is proposed. Accurate measurement of on-wafer devices over a wide range of frequency, from DC to high frequencies with a minimum number of space conservative standards has always been desirable. Therefore, the work is aimed at improving the existing calibration methods and suggesting a best "practice" strategy that could be adopted to obtain greater accuracy with a simplified procedure and calibration set. Quantitative and qualitative comparisons are made to the existing calibration techniques. The advantages and drawbacks of each calibration are analyzed. Prior work done at the University of South Florida by an improved SOLT calibration is briefed. The presented work is a culmination and refinement of the prior USF work that suggested that SOLT calibration improves with more complex definitions for the calibration standards. Modeling of the load and thru standards is shown to improve accuracy as the frequency variation of the two standards can be significant. The load is modeled with modified equivalent circuit to include the high frequency parasitics. The model is physically verified on different substrates. The relation of load impedance with DC resistance is verified and its significance in SOLT calibrations is illustrated. The thru equation accounts for the losses in a transmission line reflections and phase shift including dielectric and conductor losses. The equations used are important for cases where a non-zero length of thru is assumed for the calibration. The complex definitions of the calibration standards are included in the calibration algorithm with LabView and tested on two different VNA's -- Wiltron 360B and Anritsu Lightning. The importance of including the forward and reverse switch terms error correction in the algorithm is analyzed and measurements that verify the improvement are shown. The concept using same foot size calibration standards to simplify the calibration process is highlighted with results to verify the same. The proposed technique thus provides for calibration strategy that can overcome the low frequency problems of TRL, retain TRL accuracy at high frequencies while enabling the use of a compact common footprint calibration set.
Thesis:
Thesis (M.S.E.E.)--University of South Florida, 2004.
Bibliography:
Includes bibliographical references.
System Details:
System requirements: World Wide Web browser and PDF reader.
System Details:
Mode of access: World Wide Web.
Statement of Responsibility:
by Sathya Padmanabhan.
General Note:
Title from PDF of title page.
General Note:
Document formatted into pages; contains 171 pages.

Record Information

Source Institution:
University of South Florida Library
Holding Location:
University of South Florida
Rights Management:
All applicable rights reserved by the source institution and holding location.
Resource Identifier:
aleph - 001469416
oclc - 55731375
notis - AJR1170
usfldc doi - E14-SFE0000318
usfldc handle - e14.318
System ID:
SFS0025013:00001


This item is only available as the following downloads:


Full Text

PAGE 1

Broad-Band Space Conservative On Wafer Network Analyzer Calibrations With More Complex SOLT Definitions by Sathya Padmanabhan A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Lawrence P. Dunleavy, Ph.D. Thomas Weller, Ph.D. Stephen E. Saddow, Ph.D. Date of Approval: March 29, 2004 Keywords: cSOLT, TRL, complex models, error correction, cal comparison Copyright 2004 Sathya Padmanabhan

PAGE 2

DEDICATION To my parents who mean the world to me and have been on my side in making my dreams come true

PAGE 3

ACKNOWLEDGEMENTS I would like to thank my major professor, Dr. Lawrence Dunleavy for having given me the opportunity to work as a part of his research team and for the motivation and guidance through the course of the work. I would also like to thank my committee members, Dr. Thomas Weller and Dr. Stephen Saddow for the assistance provided for the thesis work. I thank M/A-Com and Anritsu, who funded the project and for the technical discussions and suggestions provided throughout the work. My special thanks to M/A-Com for fabricating the custom calibration standards designed for the work. I thank John Daniel, Alberto Rodriguez and Balaji Lakshminarayanan for their valuable suggestions and assistance at various stages of the work. I also thank all my friends and colleagues at ENB 412 who have been of great support as I progressed with my work. Finally, I thank my wonderful parents, sister and Abishek who have been an integral part of success.

PAGE 4

TABLE OF CONTENTS LIST OF TABLES iv LIST OF FIGURES v ABSTRACT xv CHAPTER 1 INTRODUCTION 1 1.1 Overview 1 1.2 Available Calibration Techniques 2 1.3 Summary of Contributions 5 1.4 Thesis Organization 6 CHAPTER 2 REVIEW OF AVAILABLE VNA CALIBRATION TECHNIQUES 8 2.1 Introduction 8 2.2 VNA Architecture 9 2.3 Error Correction and Related Terminology 10 2.3.1 Directivity 11 2.3.2 Source Match 11 2.3.3 Load Match 11 2.3.4 Isolation 12 2.3.5 Frequency Tracking 12 2.4 Error Correction and Models 12 2.4.1 One-port Calibration 13 2.4.2 Two-port Calibration Methods 14 2.5 Calibration Techniques 15 2.5.1 SOLT Calibration 15 2.5.2 TRL Calibration 18 2.5.3 LRM and LRRM Calibration 21 2.5.4 16-Term Error Model for TRL and SOLT Calibration 22 2.6 Prior Work 23 2.6.1 mSOLT Calibration 23 2.6.2 SOLT Calibration with More Complex Load and Thru Models 24 2.7 Chapter Summary 25 i

PAGE 5

CHAPTER 3 ACCURATE MODELS FOR SOLT CALIBRATION STANDARDS 27 3.1 Introduction 27 3.2 Issues with SOLT Calibration 28 3.3 Verification Substrates 29 3.4 Complex Models for Calibration Standards 30 3.4.1 Open and Short Standards 30 3.4.2 Load Standard Model 34 3.4.2.1 NIST Load Model 34 3.4.2.2 Proposed Complex Load Model 35 3.4.2.3 R DC Variation with RF Performance of Load 39 3.4.2.4 Verification of Proposed Model on Other Substrates 46 3.5 Thru Model Equations 52 3.6 Chapter Summary 59 CHAPTER 4 CALIBRATION COMPARISON TECHNIQUES 60 4.1 Introduction 60 4.2 Calibration Comparison Method 61 4.2.1 Comparison with Two-tier Calibrations 61 4.2.2 Calibration Comparison with One-tier Calibrations 63 4.3 Determination of Worst Case Deviations 64 4.4 Implementation and Verification of Comparison Algorithm 66 4.5 Chapter Summary 68 CHAPTER 5 COMPLEX SOLT (cSOLT) CALIBRATION IMPLEMENTATION AND ACCURACY VERIFICATION GaAs MMIC SUBSTRATES 69 5.1 Introduction 69 5.2 Complex SOLT Calibration and Verification of Accuracy 70 5.3 ITT GaAs Microstrip Substrate 71 5.3.1 TRL Calibration Data Verification ITT GaAs Microstrip Substrate 72 5.3.2 cSOLT TRL Calibration Data Comparison 74 5.3.3 Upper Bound Error Comparison ITT GaAs Microstrip Substrate 77 5.3.4 Device Measurements w.r.t TRL and cSOLT Calibrations 80 5.3.5 Accuracy Verification with Multiple Copies of Calibration Sets R DC Variability 82 5.4 M/A-Com GaAs Microstrip Standards 84 5.4.1 Half the Thru SOLT Standards M/A-Com Die 85 5.4.1.1 Upper Bound Error between Calibrations 88 5.4.2 Equal Foot Print SOLT Standards 89 5.4.2.1 Upper Bound Error between Calibrations 92 5.5 Chapter Summary 93 ii

PAGE 6

CHAPTER 6 COMPLEX SOLT (cSOLT) CALIBRATION VERIFICATION ON COMMERCIAL AND HYBRID (FR4) SUBSTRATES 95 6.1 Introduction 95 6.2 Hybrid FR-4 14mil Microstrip Substrate 95 6.2.1 Upper Bound Error between Calibrations 99 6.2.2 Device Measurements w.r.t TRL and cSOLT Calibrations 101 6.3 GGB CS5 Calibration Substrate 103 6.4 Jmicro 5mil Microstrip Substrate 106 6.5 Chapter Summary 108 CHAPTER 7 CONCLUSIONS AND RECOMMENDATIONS 110 7.1 Conclusions 110 7.2 Recommendations for Future Work 112 REFERENCES 114 APPENDICES 117 Appendix A: Verification Substrates for Accuracy of CSOLT Calibration 118 A.1 ITT GaAs Microstrip Substrate 118 A.2 Jmicro 5mil Calibration Substrate 120 A.3 GGB CS5 Substrate 121 A.4 FR4 14mil Microstrip Substrate 122 Appendix B: Design of Broad-band GaAs Calibration Standards 124 Appendix C: Complex Load and Thru Model Data Jmicro 5mil & M/A-Com GaAs Substrates 127 C.1 Complex Load Model Verification 127 C.2 Complex Thru Model Verification 131 Appendix D: BullCal V2.0 Implementation of cSOLT and Cal Compare with LabVIEW 133 D.1 cSOLT Calibration Program 133 D.2 Cal Compare Program 140 Appendix E: Calibration Verification Data and Comparison of Measured Standards 141 E.1 GGB CS5 Calibration Substrate 141 E.2 Jmicro 5mil Calibration Substrate 145 E.3 Custom M/A-Com GaAs Substrate 149 E.4 FR4 14mil Substrate 151 iii

PAGE 7

LIST OF TABLES Table 2.1 Error Model Description. 16 Table 3.1 Tabulation of Load Model Parameters and their Values from Simulation for Load Measured on ITT GaAs Microstrip Substrate. 38 Table 3.2 Tabulation of Load Model Parameters and Their Values from Simulation for Load Measured at Probe Tip Plane (75um Offset Length) on GGB CS5 Substrate. 48 Table 3.3 Tabulation of Load Model Parameters and Their Values from Simulation for Load Measured on 14mil FR4 Microstrip Substrate. 50 Table A.1 List of Calibration Structures used for ITT GaAs Calibrations. 118 Table A.2 List of Calibration Structures used for Jmicro Calibrations. 121 Table A.3 List of Calibration Structures used for GGB CS5 Calibrations. 121 Table A.4 List of Calibration Structures used for 14mil FR4 Calibrations. 123 Table B.1 Line Lengths and Quarter Wavelengths. 125 Table C.1 Tabulation of Load Model Parameters and their Values from Simulation for Load Measured on Jmicro 5mil Substrate. 128 Table C.2 Tabulation of Load Model Parameters and their Values from Simulation for Load Measured on M/A-Com GaAs Microstrip Substrate. 128 iv

PAGE 8

LIST OF FIGURES Figure 1.1 Block Diagram of Actual Measurement of DUT When Connected to VNA. 3 Figure 2.1 Typical Block Diagram of Vector Network Analyzer. 9 Figure 2.2 IF Section of Typical VNA. 10 Figure 2.3 One-port Error Model. 13 Figure 2.4 12-Term Error Model Forward Direction. 15 Figure 2.5 12-Term Error Model Reverse Direction. 16 Figure 2.6 8-Term Error Model. 20 Figure 2.7 16-Term Error Model. 23 Figure 3.1 Equivalent Circuit Model of Open Standard (Probe Tip Reference). 30 Figure 3.2 Equivalent Circuit Model of Short Standard (Probe Tip Reference). 31 Figure 3.3 Magnitude of Measured versus Equivalent Model of Open Referenced at Probe Tip on GGB CS5 Substrate. 32 Figure 3.4 Phase of Measured versus Model Equivalent Model of Open Referenced at Probe Tip on GGB CS5 Substrate. 32 Figure 3.5 S11 Magnitude of Measured Data versus Equivalent Model of Short Referenced at Probe Tip on GGB CS5 Substrate. 33 Figure 3.6 S11 Phase of Measured Data versus Equivalent Model of Short Referenced at Probe Tip on GGB CS5 Substrate. 33 Figure 3.7 Equivalent Circuit NIST Model for CPW Load Standard. 34 Figure 3.8 Equivalent Circuit Model for CPW Load Standard Suggested in [6]. 35 v

PAGE 9

Figure 3.9 An Improved Equivalent Circuit Model for Load Standard (Microstrip). 36 Figure 3.10 Picture of GaAs Microstrip Load, Which the Complex Model Represents. 37 Figure 3.11 Real Impedance of Measured Load vs. Complex Load Model at Center of Thru Reference. 38 Figure 3.12 Imaginary Impedance of Measured Load vs. Complex Load Model at Center of Thru Reference. 39 Figure 3.13 Reflection Co-Efficients Of Loads for the 10 GaAs Loads Used, with Varying Dc Resistances Between 49.5 To 52.5 on Smith Chart (Markers on 50.256 Load). 40 Figure 3.14 Real Part of Measured (Left) and Model (Right) Load Impedance of 10 GaAs Microstrip Loads with Varying DC Resistances between 49.5 To 52.5. 40 Figure 3.15 Imaginary Part of Load Impedance of 10 GaAs Microstrip Loads with Varying DC Resistances Between 49.5 To 52.5. 41 Figure 3.16 Real Impedance of Measured Load vs. Load Model with Adjusted R DC of 52.045 at Center of Thru Reference. 42 Figure 3.17 Imaginary Impedance of Measured Load vs. Load Model with Adjusted R DC of 52.045 at Center of Thru Reference. 42 Figure 3.18 Real Impedance of Measured Load vs. Load Model with Adjusted R DC of 50.045 at Center of Thru Reference. 43 Figure 3.19 Imaginary Impedance of Measured Load vs. Load Model with Adjusted R DC of 50.045 at Center of Thru Reference. 43 Figure 3.20 Vector Error Difference of Loads Measured on the Whole Wafer and the Optimized R DC Compensated Model. 44 Figure 3.21 Average Vector Magnitude Error of 15 Loads Comparing the Different Load Model Conditions. 45 Figure 3.22 Comparison of Vector Error Difference between the Measured and Model With and Without Compensation for Varying R DC 46 vi

PAGE 10

Figure 3.23 Real Impedance of GGB CS5 Load with RDC of 49.9 vs. Load Model at Probe tip Reference. 48 Figure 3.24 Imaginary Impedance of GGB CS5 Load with RDC of 49.9 vs. Load Model at Probe Tip Reference. 49 Figure 3.25 Real Impedance of 14mil FR4 Load with R DC of 49.75 vs. Load Model at Center of Thru Reference. 49 Figure 3.26 Imaginary Impedance of 14mil FR4 Load with R DC of 49.75 vs. Load Model at Center of Thru Reference. 50 Figure 3.27 Real Impedance of Microstrip Parallel Load with R DC of 48.4 Measured at Center of Thru Reference. 51 Figure 3.28 Imaginary Impedance of Microstrip Parallel Load with R DC of 48.4 Measured at Center of Thru Reference. 51 Figure 3.29 Reflection Co-efficient of 8390um Probe Tip Measured Delay on ITT GaAs Microstrip Substrate. 55 Figure 3.30 S21 (dB) of 8390um Probe Tip Measured Delay on ITT GaAs Microstrip Substrate. 55 Figure 3.31 S21 Phase of 8390um Probe Tip Measured Delay on ITT GaAs Microstrip Substrate. 56 Figure 3.32 Reflection Co-Efficient of 500um Probe Tip Measured Delay on GGB CS5 Substrate. 56 Figure 3.33 S21 (dB) of 500um Probe Tip Measured Delay on GGB CS5 Substrate. 57 Figure 3.34 S21 Phase of 500um Probe Tip Measured Delay on GGB CS5 Substrate. 57 Figure 3.35 Return Loss (S11) (dB) and S21 (dB) for a 14mil FR4 Delay Line of Length 1.1252cm Measured at the Center of Thru Reference. 58 Figure 3.36 S21 Phase of 1.1252cm Center of Thru Referenced Delay on 14mil FR4 Substrate. 58 Figure 4.1 Cascade Matrix Representation of Instrument and DUT State during Measurements. 61 vii

PAGE 11

Figure 4.2 Screen Shot of Cal Compare Program Implemented in LabVIEW. 66 Figure 4.3 Upper Bound Error Graph for TRL, SOLT, Sliding Load SOLT (SLSOLT) Calibrations Performed on OS-50 Co-axial Standards. 68 Figure 5.1 Screen Shot of cSOLT Calibration Algorithm Implemented with LabVIEW. 71 Figure 5.2 Effective Phase Delay of Delay Lines on the ITT GaAs Microstrip Substrate after TRL Calibration. 73 Figure 5.3 Effective Dielectric Constant (eff) of ITT GaAs Microstrip Substrate in Real Imaginary after Center of Thru TRL Calibration (Z0=50.9 @ 10GHz). 73 Figure 5.4 Characteristic Impedance of ITT GaAs Microstrip Substrate in Real Imaginary, after Center of Thru TRL Calibration. 74 Figure 5.5 Reflection Co-Efficient (S11 in dB) of Load Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 75 Figure 5.6 Reflection Co-efficient of Thru Line Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 76 Figure 5.7 Transmission Co-efficient of Thru Line Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 76 Figure 5.8 S21 Phase of Thru Line Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 77 Figure 5.9 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL as Reference on ITT GaAs Microstrip Substrate with Center of Thru Reference. 78 Figure 5.10 Upper Bound Error Difference between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL on ITT GaAs Microstrip Substrate with Center of Thru Reference. 79 Figure 5.11 S11 of 0.03pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S11 from TRL and cSOLT (Right). 80 viii

PAGE 12

Figure 5.12 S21 of 0.03pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S21 from TRL and cSOLT (Right). 81 Figure 5.13 S11 of 0.3pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S11 from TRL and cSOLT (Right). 81 Figure 5.14 S21 of 0.3pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S21 from TRL and cSOLT (Right). 82 Figure 5.15 Upper Bound Error Difference for cSOLT Calibration vs. TRL on Multiple Die from ITT GaAs Microstrip Substrate using cSOLT as the Reference Calibration. 83 Figure 5.16 Magnitude of S11 (dB) of Load Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 86 Figure 5.17 Magnitude (dB) and Phase of S11 of Open Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 86 Figure 5.18 Magnitude (dB) and Phase of S11 of Short Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 87 Figure 5.19 Magnitude of S11 (dB) and S21 (dB) of Thru Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 87 Figure 5.20 Upper Bound Error Difference between cSOLT, mSOLT, SOLT with Respect to TRL Calibration on M/A-Com GaAs Microstrip Substrate. 88 Figure 5.21 Upper Bound Error Difference between cSOLT, mSOLT, SOLT with Respect to cSOLT Calibration on M/A-Com GaAs Microstrip Substrate. 89 Figure 5.22 Magnitude of S11 (dB) of Load Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. 90 ix

PAGE 13

Figure 5.23 S11 Magnitude and Phase of Open Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. 91 Figure 5.24 S11 Magnitude and Phase of Short Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. 91 Figure 5.25 S21 Magnitude and Phase of Thru Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. 92 Figure 5.26 Upper Bound Error between cSOLT (Equal Length SOLT Standards) and TRL Calibration Referenced at Probe Tips on M/A-Com GaAs Microstrip Substrate. 93 Figure 6.1 S11 Magnitude and Phase of Open Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 96 Figure 6.2 S11 Magnitude and Phase of Short Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 97 Figure 6.3 Magnitude of S11 for Load Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 98 Figure 6.4 Magnitude of S11 and S21 of Thru Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 98 Figure 6.5 Upper Bound Error between cSOLT, mSOLT, SOLT with Respect to TRL Calibration on 14mil FR4 Microstrip Substrate. 99 Figure 6.6 Upper Bound Error between cSOLT, mSOLT, SOLT with cSOLT Calibration on 14mil FR4 Microstrip Substrate. 100 Figure 6.7 S11 and S21 of 0.2pF Capacitor w.r.t cSOLT and TRL Calibrations Referenced at the Center of Thru on 14mil FR4 Microstrip Substrate. 101 x

PAGE 14

Figure 6.8 Vector Difference between the S-parameters of 0.2pF Capacitor Measured on 14mil FR4 Microstrip Substrate with Respect to cSOLT and TRL Calibrations. 102 Figure 6.9 S11 of 0.2pF Capacitor When Port 2 is Shorted during Simulation w.r.t cSOLT and TRL Calibrations Referenced at the Center of Thru. 102 Figure 6.10 S11 and S21 of 0.4pF Capacitor Measured with respect to TRL and cSOLT Calibrations. 103 Figure 6.11 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL on GGB CS5 Substrate. 105 Figure 6.12 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL on GGB CS5 CPW Substrate. 106 Figure 6.13 Upper Bound Error Between TRL, cSOLT, mSOLT and SOLT with Respect to TRL at the Center of Thru Reference on Jmicro 5mil Microstrip Substrate. 107 Figure 6.14 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT with Respect to cSOLT at the Center of Thru Reference. 108 Figure A.1 Layout of the ITT GaAs Microstrip Substrate [5]. 119 Figure A.2 Layout of Jmicro 5mil Calibration Substrate with Calibration Structures for up to 20GHz, 40GHz and 80GHz [34]. 120 Figure A.3 Layout of GGB CS5 Calibration Substrate [27]. 122 Figure A.4 Layout of the hybrid FR4 14mil microstrip substrate [35]. 123 Figure B.1 Layout of TRL and SOLT Calibration Standards on 100um Thick GaAs Substrate. 126 Figure C.1 Real Impedance of Measured Load Vs. Complex Load Model on Jmicro 5mil Microstrip Substrate at Center of Thru Reference. 127 Figure C.2 Imaginary Impedance of Measured Load vs. Complex Load Model on Jmicro 5mil Microstrip Substrate at Center of Thru Reference. 128 Figure C.3 Real Impedance of Measured Load Vs. Complex Load Model on M/A-Com 4mil Microstrip Substrate at Center of Thru Reference. 129 xi

PAGE 15

Figure C.4 Imaginary Impedance of Measured Load Vs. Complex Load Model on M/A-Com 4mil Microstrip Substrate at Center of Thru Reference. 129 Figure C.5 Real Impedance of Measured Load vs. Complex Load Model for Equal Foot Print Load Standard on M/A-Com 4mil Microstrip Substrate at Center of Thru Reference. 130 Figure C.6 Imaginary Impedance of Measured Load vs. Complex Load Model for Equal Foot Print Load Standard on M/A-Com 4mil Substrate at Center of Thru Reference. 130 Figure C.7 S11 in dB for Measured Data vs. Thru Model for 1168um Delay Line on Jmicro 5mil Substrate at Center of Thru Reference. 131 Figure C.8 S21 in dB for Measured Data vs. Thru Model for 1168um Delay Line on Jmicro 5mil Substrate at Center of Thru Reference. 131 Figure C.9 S11 Magnitude of Measured Data vs. Thru Model for 500um Line on M/A-Com GaAs Substrate at Probe Tip Reference. 132 Figure C.10 S21 Magnitude and Phase of Measured Data vs. Model for 500um Thru on M/A-Com GaAs Substrate at Probe Tip Reference. 132 Figure D.1 Screen Capture of the Main Screen in cSOLT Program to Perform Complex-SOLT Calibrations. 133 Figure D.2 Screen Capture of Edit/View Calibration Standard Definitions Section. 134 Figure D.3 Dialog Box for Short Standard Definitions at Port 1 and Port 2. 135 Figure D.4 Dialog Box for Open Standard Definitions at Port 1 and Port 2. 135 Figure D.5 Dialog Box for Load Standard Definitions at Port 1 and Port 2. 136 Figure D.6 Dialog Box for Thru Line Definitions. 136 Figure D.7 Calibration Standard Definitions Section. 137 Figure D.8 Measurements Section where Raw Data of Calibration Standards are Measured. 138 Figure D.9 Embedding or De-embedding Reference Plane Shifting Section. 138 xii

PAGE 16

Figure D.10 Calculation of Error Co-efficients Before Sending to Network Analyzer. 139 Figure D.11 Screen Shot of the Cal Compare Program that Generates the Upper Bound Error between Two Calibrations. 140 Figure E.1 Effective Dielectric Constant of GGB CS5 Calibration Substrate after TRL Calibration at Probe Tip Reference Plane. 141 Figure E.2 Characteristic Impedance of Standards on GGB CS5 Calibration Substrate after TRL Calibration at Probe Tip Reference Plane (Z0=49.82 @ 10GHz). 142 Figure E.3 Effective Phase Delay of Delay Lines on GGB CS5 Calibration Substrate after TRL Calibration at Probe Tip Reference Plane. 142 Figure E.4 S11 Magnitude and Phase of Short Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 143 Figure E.5 S11 Magnitude and Phase of Open Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 143 Figure E.6 S11 Magnitude and Phase of Load Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 144 Figure E.7 S11 Magnitude of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 144 Figure E.8 S21 Magnitude and Phase of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 145 Figure E.9 Effective Dielectric Constant of Jmicro 5mil Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 145 Figure E.10 Effective Phase Delay of Delay Lines on Jmicro 5mil Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 146 Figure E.11 Characteristic Impedance of Standards on Jmicro 5mil Calibration Substrate after TRL Calibration at Center of Thru Reference Plane (Z0=50.2 @ 10GHz). 146 xiii

PAGE 17

Figure E.12 S11 Magnitude and Phase of Short Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 147 Figure E.13 S11 Magnitude and Phase of Open Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 147 Figure E.14 S11 Magnitude and Phase of Load Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 148 Figure E.15 S11 Magnitude of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 148 Figure E.16 S21 Magnitude of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 149 Figure E.17 Effective Dielectric Constant of Custom M/A-Com GaAs Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 149 Figure E.18 Effective Phase Delay of Delay Lines on Custom M/A-Com GaAs Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 150 Figure E.19 Characteristic Impedance of Standards of Custom M/A-Com GaAs Calibration Substrate after TRL Calibration at Center of Thru Reference Plane (Z0=49.9 @ 10GHz). 150 Figure E.20 Effective Dielectric Constant of Custom 14mil FR4 Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 151 Figure E.21 Effective Phase Delay of Delay Lines on Custom 14mil FR4 Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 151 Figure E.22 Characteristic Impedance of Standards of Custom 14mil FR4 Calibration Substrate after TRL Calibration at Center of Thru Reference Plane (Z0 = 49.3 @ 10GHz). 152 xiv

PAGE 18

BROAD-BAND SPACE CONSERVATIVE ON-WAFER NETWORK ANALYZER CALIBRATIONS WITH MORE COMPLEX SOLT DEFINITIONS Sathya Padmanabhan ABSTRACT An improved Short-Open-Load-Thru (SOLT) on-wafer vector network calibration method for broad-band accuracy is proposed. Accurate measurement of on-wafer devices over a wide range of frequency, from DC to high frequencies with a minimum number of space conservative standards has always been desirable. Therefore, the work is aimed at improving the existing calibration methods and suggesting a best practice strategy that could be adopted to obtain greater accuracy with a simplified procedure and calibration set. Quantitative and qualitative comparisons are made to the existing calibration techniques. The advantages and drawbacks of each calibration are analyzed. Prior work done at the University of South Florida by on improved SOLT calibration is briefed. The presented work is a culmination and refinement of the prior USF work that suggested that SOLT calibration improves with more complex definitions for the calibration standards. Modeling of the load and thru standards is shown to improve accuracy as the frequency variation of the two standards can be significant. The load is modeled with modified equivalent circuit to include the high frequency parasitics. The model is xv

PAGE 19

physically verified on different substrates. The relation of load impedance with DC resistance is verified and its significance in SOLT calibrations is illustrated. The thru equation accounts for the losses in a transmission line reflections and phase shift including dielectric and conductor losses. The equations used are important for cases where a non-zero length of thru is assumed for the calibration. The complex definitions of the calibration standards are included in the calibration algorithm with LabView and tested on two different VNAs Wiltron 360B and Anritsu Lightning. The importance of including the forward and reverse switch terms error correction in the algorithm is analyzed and measurements that verify the improvement are shown. The concept using same foot size calibration standards to simplify the calibration process is highlighted with results to verify the same. The proposed technique thus provides for calibration strategy that can overcome the low frequency problems of TRL, retain TRL accuracy at high frequencies while enabling the use of a compact common footprint calibration set. xvi

PAGE 20

CHAPTER 1 INTRODUCTION 1.1 Overview An accurate microwave S-parameter measurement of a Device Under Test (DUT) with a Vector Network Analyzer (VNA) depends on the accuracy of the calibration done to eliminate the inherent errors with the measurement system and setup. A calibration procedure characterizes errors in the system before measurement of the DUT. The error model calculated from calibration is used to correct for the actual parameters of the device. It is important that the VNA calibration algorithm adopted is able to calibrate for the errors in the system for the entire operating frequency range. The work presented here includes a study of the different VNA calibration techniques available. The choice of a particular calibration is determined with respect to the working frequency range and the accuracy required for DUT measurement. When the devices are on-wafer as in the case of monolithic microwave integrated circuits (MMIC); it becomes necessary to consider a few other issues. Due to the cost involved in fabricating the circuit, the real estate used for calibration standards should be minimal. A calibration technique is sought with minimum number of standards that can provide maximum accuracy over a broad-band of frequencies. 1

PAGE 21

The goal of this work is to thus suggest a calibration strategy that provides the desired broadband accuracy with minimum number of space conservative standards. Further for on-wafer probing it is best if all the calibration standards have the exact same probe contact pad layout (or foot print). The work presented analyzes the advantages and disadvantages of the different calibration methods and suggests an improved technique for broad-band calibrations with a compact standard set. 1.2 Available Calibration Techniques The most popular calibration methods available are Thru-Reflect-Line (TRL) and Short-Open-Load-Thru (SOLT) methods. There are other calibration methods like Line-Reflect-Match (LRM) and Line-Reflect-Reflect-Match (LRRM) that combine advantages and attempts to eliminate the disadvantages of TRL and SOLT techniques. It is important that the significance of a calibration routine is understood. Prior to a calibration the measurement of the DUT includes loss and phase delay of cables, transitions from vector network analyzer (VNA) port to cable and cable to DUT. It also includes losses that are innate in the system that cannot be corrected for. Figure 1.1 shows in a block diagram the actual measurement of the DUT when connected to the ports of the VNA. 2

PAGE 22

Error BoxA[S1] Device underTest (DUT)[S] Error BoxB[S2] a1 [Smeas] [SDUT]ReferencePlace @ VNAPort 1ReferencePlace @ VNAPort 2ReferencePlace @ DUTPort 2ReferencePlace @ DUTPort 1b1b2a2 Figure 1.1 Block Diagram of Actual Measurement of DUT When Connected to VNA. The error box A and B with S-parameters (S1) and (S2) are the error co-efficients that are calculated with calibration. When measuring a DUT, the measured data (S meas ) is data as seen between the reference planes at VNA ports 1 and 2. Once calibrated, the actual S-parameters (S DUT ) are determined with the help of the two error boxes. The different calibration methods use a unique approach to calculate the error co-efficients. TRL calibration [1] uses a thru, reflect and delay line with minimum information for the standards (ex.-physical dimensions). NIST developed a powerful multi-line TRL calibration [2] that enables broad-band accurate calibration by using more than one delay line to calculate error co-efficients over a wide frequency bandwidth. TRL is considered to be the most accurate calibration at high frequencies. With decrease in frequencies, longer lines are needed to account for those frequency bandwidths which results in more real estate. Due to the fact that it is practically not always possible to construct a very long line, TRL often fails at the lower frequencies typically less than 1GHz. 3

PAGE 23

An alternative to TRL at lower frequencies is the SOLT calibration routine [3]. The method relies on the electrical model definitions for the standards. With good definitions of the calibration standards, it is possible to obtain accurate calibration results. The advantages of this calibration are that it occupies very little wafer or board space when compared to TRL standards. The process of calibration is also simplified in terms of time and repeatability of measurements with the help of automatic prober systems when the standards have the same foot prints. However, if the definitions do not accurately model for the standards behavior throughout the operating bandwidth it can result in erroneous data. Another risk is that when the definitions are not accurate enough, the outcome of the calibration can be deceiving; in the sense that the results after calibration might match well with the definitions but will produce inaccurate S-parameter measurement of DUT. The Line-Reflect-Match (LRM) calibration [4] evolved combining the advantages of TRL and SOLT algorithms. The reference impedance of the calibration is the impedance of the match standard. This results in an accurate low frequency calibration. But with increase in frequencies the accuracy deteriorates if the complex behavior of load is not well defined. It is verified from both SOLT and LRM where the calibration accuracy depends on the definition of standards, the main error factor with increasing frequency is because of the load standard. The load is usually modeled as a resistor circuit. Some loads however exhibit more complex behavior with increase in frequencies. Hence it is becomes important that the load is well defined over the entire desired frequency range. NIST suggested LRM* to compensate for the variations of the load based on the TRL measurement of the load. This improves the accuracy of the 4

PAGE 24

calibration at higher frequencies but retains the low frequency problems of TRL. Another calibration algorithm with similar problem with the load was the Line-Reflect-Reflect-Match (LRRM) algorithm. The method automatically calculates the inductance of the load, but assumes that the load is a simple RL model and hence is still inadequate at higher frequencies. Other attempts to increase the accuracy of calibration prior to the work presented here are mSOLT [5] and complex model SOLT [6]. The mSOLT method which uses the measured files after a TRL calibration as the standard definitions was verified to have TRL level accuracy at higher frequencies. But it carries over the low frequency problem of TRL as the definitions are basically measured files from TRL. As an alternative to this problem, and a precursor to the work presented here is cSOLT method. The method suggests that with complex models for the load and thru standards, the accuracy of the SOLT calibration could be made comparable to TRL calibration. 1.3 Summary of Contributions The work documented here suggests that more (or rigorous) complex models for the lumped element calibration standards improve the accuracy of SOLT calibration over a broad-band frequency range. The proposed complex load model is a modification of a previously proposed NIST model. Its significance is verified from 40MHz 65GHz. It has been verified that the RF performance of the load directly depends on the DC resistance of the load. This is utilized to SOLT calibrate multiple dies on a whole wafer without having to model for the load performance on each die on the wafer. The 5

PAGE 25

importance of a thru line model that includes attenuation losses for calibration referenced at the probe tips has been verified. The thru equations suggested provide a fitting equation that compensates for the conductor and dielectric losses. The load and thru models have been verified on substrates with different dielectrics for validation. A custom LabVIEW TM program (cSOLT) which includes the complex models for load and thru in the SOLT calibration routine has been implemented as a modification of prior work. The fact that the calibration standards short, open and load could have some variations port to port is accommodated in the LabView program. The cSOLT algorithm can presently be done on two VNAs, the Wiltron 360B and Anritsu Lightning. The program can also be used to shift reference planes after probe tip SOLT calibrations. A calibration comparison routine (Cal Compare) has also been implemented in the program where any two calibrations with similar frequency setup can be compared. The program is simple when compared to the NIST VERIFY which requires two tier calibrations to generate the upper bound error graph. The proposed improved SOLT calibration is compared with TRL, conventional SOLT and mSOLT calibrations. 1.4 Thesis Organization The thesis starts with a brief introduction of VNA architecture in Chapter 2. The chapter elaborates on the different error correction algorithms. Prior USF work to that presented here is also briefly introduced. The advantages and disadvantages to competing calibration methods are described. The 3 rd chapter illustrates the significance to SOLT 6

PAGE 26

calibration method and the reason as to why the SOLT method is selected for improvement. The complex models used for the standard definition are explained, with results that validate the models. The R DC variation with load and RF performance relation to R DC is illustrated. Chapter 4 explains on the custom calibration comparison method implemented in LabView to generate the upper bound error graph between any two calibrations. Verification of the proposed cSOLT is exemplified with probe tip and center of thru calibrations. The calibration is compared with TRL, ideal SOLT, mSOLT and LRM calibration techniques. Finally chapter 6 discusses conclusions and recommendations for future work. 7

PAGE 27

CHAPTER 2 REVIEW OF AVAILABLE VNA CALIBRATION TECHNIQUES 2.1 Introduction A two-port vector network analyzer (VNA) measures the ratio of the power levels of a signal transmitted from the input port to that reflected back to input and the power received at the output port. Frequency range of operation can vary from near DC to high millimeter wave frequency ranges. VNA measurement errors may be random, drift or systematic errors. While random and drift errors cannot be removed from the system due to their innate nature, systematic errors can be removed. This is because, they are repeatable imperfections in the measurement system like impedance mismatch, leakage (or crosstalk), phase shift and loss caused by cable networks, and errors caused by the non-ideal directivity of couplers used in the VNA system. Therefore it is important to calibrate out systematic errors before device measurement. This chapter briefs on the different calibration techniques available and error models used for correction to minimize the systematic errors. The primary interest is in techniques applicable to on-wafer calibrations (broadly defined to include hybrid board as well as semiconductor wafer calibrations) which is the focus of this thesis. 8

PAGE 28

2.2 VNA Architecture S-parameters of active or passive devices under test are measured with a vector network analyzer. Figure 2.1 is a typical block diagram of a four channel VNA designed to process the magnitude and phase of transmitted and reflected waves from the analyzer. b1a2 RF Sourcea0a3DUT LO Sourcea1b2 Port 1Port 2 b3 IF IFMixerMixer Forward / ReverseSwitch Network IFb0 IF MixerMixer Figure 2.1 Typical Block Diagram of Vector Network Analyzer [7]. 9

PAGE 29

The RF source is set to sweep over a specified bandwidth and it can switch between the forward and reverse paths to excite port 1 or port 2 of the VNA. The switch network provides Z 0 termination for the output port when one port is being excited. The incident, reflected and transmitted signals are separated from each other in forward and reverse directions with directional couplers. The four dual conversion channels convert the RF into fixed low frequency IF. Since these signals are in analog form, they are then detected and digitized using A/D converters [8]. IF Section Proc.Display BPF A/D Figure 2.2 IF Section of Typical VNA [7]. The digitized data is then used to calculate the magnitude and phase of the S-parameters of the DUT. It is evident that with the errors induced due to directional coupler mismatch, imperfect directivity, losses and variations in frequency response, it is imperative that these errors are compensated using some error correction method. 2.3 Error Correction and Related Terminology It is understood from the previous section that calibration and error correction algorithms are required to accurately measure a DUT. These algorithms are based on error model diagrams that represent the losses present in the measurement set-up. The vector error correction procedure accounts for the systematic errors present in the system. Calibration characterizes the systematic error terms by measuring known calibration standards and stores the data which is finally used for calculation of an error model that 10

PAGE 30

relates to the inaccuracies in the system. Error correction uses the calibrated error model to mathematically remove systematic errors from raw measured data sets. There are six different systematic errors for reflection and transmission that are taken care of in any error model diagram. They are directivity, source and load match, isolation and frequency tracking errors. 2.3.1 Directivity 2.3.2 2.3.3 It is defined as the vector sum of all leakage signals that appear at the input of the network analyzer. The leakage signals are induced due to the fact that there is not enough isolation between the incident and reflected waves. It also includes the residual effects of cables and adapters between the measurement plane and instrument and affects the reflection measurements of the DUT. Referring to Fig. 1, imperfect directivity accounts for the fact that there will be a signal at port b 0 even if a perfect non-reflecting load is connected as the DUT. Source Match It is defined as the vector sum of signals present at the input of the network analyzer due to its inability to maintain a constant power at the input of the test device. The uncertainty is created when the impedance of the source does not match the required input impedance of the ports to be connected to the DUT (e.g. 50 ohms). Load Match It is the vector sum of all signals present at the input to the analyzer when there are impedance mismatches between the output of the DUT and the input to the VNA. 11

PAGE 31

These errors are significant when the device under test is highly reflective resulting in transmission errors. 2.3.4 Isolation 2.3.5 It is the vector sum of signals appearing at the network analyzer detectors due to crosstalk between the reference and test signal paths. It also includes the signal leakage between the RF and IF sections and results in lossy transmission measurements. Frequency Tracking It is defined as the vector sum of measurement variations in magnitude and phase of the frequency response of the signal. This error results in losses in both reflection and transmission measurements. The error correction procedure involves correcting for the error co-efficients defined above and thus measure the actual S-parameters of the device under test. The correction algorithm is designed according to the number of ports in the DUT. Accordingly, there are one port, two port and four port calibration algorithms available. The work described here focuses on two port calibration algorithms. 2.4 Error Correction and Models This section briefly discusses the different calibration techniques available to measure devices under test with the error models they use for correction. There are two types of error correction; one port and two port calibration algorithms. Multi-port calibrations use the same type of calibration methods as the two ports. Since there is an 12

PAGE 32

n*n (where n is the number of ports of DUT) S-parameter matrix a total of 3*n 2 error terms to be corrected. 2.4.1 One Port Calibration A one port calibration method is used to obtain the reflection only S-parameters of a test device or to measure a one port device. This type of error correction corrects for three systematic errors, namely the directivity, source match and reflection tracking [9]. The correction strategy adopted is to measure three known calibration standards, such as the short, open and load and generate three simultaneous equations to solve for the three errors. The equations are obtained from the error model diagram (signal flow graph) for the one port measurement setup (Figure 3). a11ESETEDS11aS11mb1 Figure 2.3 One Port Error Model. E D Directivity error; E S Source match error; E T Reflection Tracking; S 11 a ( a ) Actual S-parameters of the device; S 11 m ( m ) Measured S-parameters of the device Solving the signal flow graph for b, three equations with three unknowns are obtained. The error so-efficients are then calculated and the measured data is corrected. 1/1a 13

PAGE 33

ED1a1mESE1a1m ED2a2mESE2a2m ED3a3mESE3a3m where, EEDESET 2.4.2 Two Port Calibration Methods A two port calibration corrects for the major systematic errors in both forward and reverse directions. The calibration algorithms developed account for these systematic errors using two port error models. According to the number of the systematic errors, that is six terms each on forward and reverse directions, a 12-term error model accounts for all the errors in a measurement system. However, it is not essential that all these 12 terms be used for correction; because the error co-efficients defined with a reduced error model (8-term) can take care of the most important errors in a measurement system with a few assumptions. When the switching network is assumed to be a perfect switch, the 12-term model can be reduced to an 8-term error model, by eliminating the leakage terms. This condition is valid, when it is assumed that all the four measurement channels are on the DUT side of the switch. Apart from the standard set of systematic errors, leakage and coupling associated with microwave probes also exists. The 16-term error model is an elaborate model that accounts for all these errors. Since the VNA does not support 16 error terms it is required that it is converted back to 12 terms before being to sent to the VNA after an offline calibration. Each of the error models is used for different calibration techniques according to the number of error co-efficients it can compensate. 14

PAGE 34

2.5 Calibration Techniques 2.5.1 SOLT Calibration A Short-Open-Load-Thru (SOLT) calibration uses 12-term error models to correct for error co-efficients. The technique uses known calibration standards with the short, open and load taking care of the reflection measurements and the thru line for the transmission measurements. The comparison of the measured and the ideal data for each standard result in calibrating out the errors present in the system. A total of 12 error terms with six on forward and reverse directions complete the calibration [3]. The error models account for all the systematic errors discussed in section 2.3. The error co-efficients are listed in Table 1. The signal flow graphs (error model diagram) are solved for the error co-efficients, and with the solutions the actual S-parameters of the test device are characterized. Figures 4 and 5 show the error models in the forward and reverse directions. DUTEXFa0b01EDFERFESFa1b1a2b2S21S11S12S22ELFETFb3Port 1Port 2 Figure 2.4 12-Term Error Model Forward Direction. 15

PAGE 35

EXR1EDRERRESRa'1S21S11S12S22ELRETRb'1b'2a'2Port 1Port 2b'0a'3b'3 Figure 2.5 12-Term Error Model Reverse Direction. The error terms directivity, reflection tracking and source and load match are calculated from the equations quoted in section 2.4.1 with the short, open and load measurements. Table 2.1 Error Model Description. Forward Error Terms Reverse Error Terms E DF Directivity E DR Directivity E SF Port 1 Source Match E SR Port 1 Load Match E RF Reflection Tracking E RR Reflection Tracking E LF Port 2 Load Match E LR Port 1 Load Match E TF Transmission tracking E TR Transmission tracking E XF Isolation E XR Isolation The transmission error terms are calculated from the thru line measurement. Often, the isolation term is ignored with the assumption that the network analyzer has a switch with perfect isolation. For on-wafer calibrations, it is common that the cross-talk between the probes is more significant than the leakage through the internal switch. Because the probe-to-probe crosstalk varies, in general, with probe horizontal spacing and the structure of the device-under-test, it is usually recommended that the isolation correction be omitted for on-wafer calibrations [7]. 16

PAGE 36

It is also due to the fact that since the cross talk measurements are carried out near the network analyzers noise floor, it is very likely that noise could be introduced into the system [10]. But when included in the calibration, it is carried out by placing test devices on each of the ports of the VNA and terminating the devices on the other end with loads. Despite the wide-spread popularity of the TRL calibrations discussed below, SOLT calibration has some real advantages for on-wafer calibrations [11]. The main advantage is that it can use a compact set of space conservative standards that can reduce the cost and time required to fabricate and calibrate with. When the standards are designed with the same footprint size, an automatic probe station can further simplify the calibration process. Since this calibration technique is available in the firmware of almost all the vector network analyzer families, it can be performed with any commercial analyzer. It is accurate at low frequencies where the standards are well defined and with better definition (i.e. models) of standards, the frequency bandwidth of the calibration could be extended to higher range. The major drawback of a SOLT calibration is that it may not be accurate at higher frequency ranges. This is because the models used to represent the SOLT standards in common firmware are not always adequate. Hence, it is important that the models used for the standards describe its behavior up to the desired frequency range. In addition to the short, open and load models, this statement applies also to the thru standard, when it is of non-zero length It is therefore required that there is a complete knowledge of the standards used prior to calibration. 17

PAGE 37

2.5.2 TRL Calibration Thru-Reflect-Line (TRL) calibration is a 2-port calibration algorithm that uses a thru line, open/short and a line standard to perform the error correction [1]. The calibration came as a solution to problems encountered with terminating two six ports with equal impedances, in the case of TSD algorithm [12][13] and the procedure where the characteristic impedance of the calibration depended only on the dimensions of the transmission line [14]. It also eliminates the need for a known reflection (short) as the reflection standard. The remaining requirement is that the reflect standard must be the same on each of the two ports. The requirements for a TRL calibration are 1. Thru line a piece of transmission line that will help set the reference plane. It could be a zero or non-zero length line. 2. Reflect reflection co-efficient magnitude need not be known, but symmetric at both the ports and the phase known to within 90 degrees. 3. Line characteristic impedance of the line establishes the reference impedance (Z 0 ) of the calibration. The optimal length of the line is 90 degrees relative to the thru line. 4. Knowledge of the Z 0 of the line standard This can be obtained in multiple ways. One method, developed by NIST, uses a combination of the effective dielectric constant (a byproduct of TRL calibration), and low frequency measurement of a pair of load standards [15]. With the calibration standards defined as above, the useable bandwidth of the calibration [16] is approximately the ratio 8:1 (frequency span/start frequency). Multiple delay lines can be used to cover more than one such bandwidth, and accommodation for 18

PAGE 38

same is typically available in built-in VNA calibration algorithms. Because the user specifies the frequency range for which each delay line is to be used, there are often noticeable bumps or discontinuities at the break points. A much-improved multi-line TRL algorithm (MultiCal) was developed at NIST [16]. Implemented in a program called MultiCal the algorithm used a weighted averaging of calibration coefficient calculations from the multiple delay lines and determines a linear covariance matrix that reduces the overall error when computing the calibration co-efficients. With each of the calibration constants determined in a linear manner, the method provides an optimal, minimum variance estimate of the constants with assumptions based on the nature of the errors and their correlation [17]. The NIST algorithm also accommodates reference plane translation, using a knowledge of the complex propagation constant (calculated by MultiCals TRL algorithm), and reference impedance correction, given a knowledge of the complex Z 0 The original TRL algorithm uses the 8-term error model (Figure 6) for correction. The 8-term model can be converted into the 12-term model that is in-built in the VNA, by adding switch term measurements. The switch term measurement aids in measuring the response of the entire system from the within the network analyzer; thus accounting for the forward and reverse model constants of the 12-term error model [17]. Once the switch terms are measured, the 8-term model is converted to the 10-term model without isolation. The fact that multi-line TRL calibration uses multiple delay lines to account for a wide frequency bandwidth and presents the best estimate of calibration constants makes it 19

PAGE 39

the most accurate TRL algorithm available. However, it has some limitations that prevent broadband measurements of devices after calibration. DUTa3a1b1a2b2S21S11S12S22b3a0b0e10e00e11e01e32e22e33e23 Figure 2.6 8-Term Error Model. The design rule for delay lines is that the electrical lengths of the lines should be around 90 for the frequency band of the line and never approach 0 and 180. As a rule of thumb, it is designed to be between 20 and 160 [18]. The requirement of multiple delay lines to cover a broad band of frequencies can result in a lengthy calibration procedure and, for on-wafer probing that require footprint contact, the horizontal spacing of the probes (contact footprint) changes during calibration. This horizontal movement is not ideal for auto-probing systems and also results in cable flexure that can cause phase induced calibration errors at high frequencies. Another disadvantage is that at lower frequencies, such as less than 2GHz, the line lengths become too large for practical wafer fabrication and probe station use. The result is that without appropriately long lines there are usually low frequency ambiguities in TRL-based measurement of devices. In effect, the characteristic impedance of the line cannot be determined accurately, thus leading erroneous reference impedance for measurement of the test devices. Compounding the long line requirement is that, due to the skin effect, the characteristic impedance often becomes complex (i.e. has a 20

PAGE 40

significant reactance) and increases rapidly at low frequency with the thin films typically used in planar microwave circuits [15]. 2.5.3 LRM and LRRM calibration The Line-Reflect-Match (LRM) calibration evolved to circumvent the disadvantages of both TRL and SOLT algorithms. It uses the same principle of error correction and error model (8-term) as that of TRL [4]. It differs from TRL in the fact that it uses an impedance match standard (assumed perfect in original method) on each of the ports instead of the line standards. The thru and reflect standards are similar to that used in TRL. The main advantage to LRM is the number of standards required for the calibration [19]. Since there is not much variation with the length of the standards used, the probe placement error with immovable probes is minimized. With fewer standards, accuracy comparable to TRL could be obtained. The major advantage of LRM is the higher accuracy of LRM at lower frequency ranges. This is due to the fact that, at these frequencies, the match which sets the reference impedance is accurately defined. But as frequency increases, this turns out to be the disadvantage. This is because, the match standard is ideally set to the DC resistance of the load; but with increase in frequencies, the loads become more complex (more on this later in this thesis) and hence do not define the standard well resulting in high frequency ambiguities. As a solution to this problem, modified LRM (LRM*) was developed at the NIST. LRM* uses a Z 0 corrected TRL measurement of the load match standards, which define the Z 0 of the LRM calibration, to correct the LRM calibration for the non-ideal 21

PAGE 41

nature of the load match standards [20]. In doing so the loads are assumed symmetrical; which is often, but not always a good assumption. The algorithm fails at whatever low frequency the TRL calibration used to measure the load standards fails. The LRRM calibration was a slightly different version of LRM. It used a line, two unknown reflects and a match standard. The match standard is defined at one of the ports and is not required to be a perfect match. With the load measured and defined at one port, it was predicted that any errors that can arise with misalignment of the match standards at both ports and any discrepancies in load resistance (deviation from 50 ohms) could be eliminated [21]. The calibration uses both the open and short as reflect standards for the error correction. The downsides to this technique are that the match was modeled with a simple RL model and hence may not represent the load at higher frequencies. Also, it is assumed that the loads connected to ports 1 and 2 are identical which is not always true. It was verified in the work presented that DC resistance of the load can vary from port to port for MMIC and hybrid MIC fabricated loads. 2.5.4 16-Term Error Model for TRL and SOLT Calibrations The 8-term error model assumes that there is no leakage between the test ports and other components in the measurement setup. The 16-term error model (Figure 7) can be used for both TRL and SOLT calibrations, but the calibration usually has to be carried out with an offline calibration program that can extract the measured data to process the error co-efficients and send it back to the VNA as in the case of MultiCal for example. Once the co-efficients are calculated, they have to be converted to the 12-term model implemented in most current VNAs. The error terms that are accounted for include 22

PAGE 42

cross-talk, switch leakage, reflection leakage from DUT back to the transmission port, common mode inductance and others. DUTa3a1b1a2b2S21S11S12S22b3a0b0e10e00e11e01e32e22e33e23 e30e12e31e02e20e13 e03e21 Figure 2.7 16-Term Error Model. 2.6 Prior Work Prior to the work presented here, there were two variations of SOLT calibration algorithm worked on by the authors research group and discussed next that was advanced to improve broadband on-wafer VNA calibration accuracy. 2.6.1 mSOLT Calibration The measurement-based SOLT calibration routine advanced by Michael Imparato [5] depends on measurement based definitions of standards for calibration. For this method, the approach is to measure the SOLT standards, based on an accurate Z 0 23

PAGE 43

corrected TRL calibration. SOLT calibration is accomplished using the measured data for the standards used as calibration definitions. One problem with this calibration is that since it depends on the TRL calibration data for definition of standards, the low frequency errors of TRL is transferred to the SOLT calibration. However at higher frequencies, the accuracy is comparable to TRL. Another problem with this method is the inconvenience of storing and retrieving measured data file definitions for standards. Hence the calibration process could become unwieldy when dealing with large number of calibration sets. The calibration is accomplished with software supplied from Anritsu. In this prior work, the characterization file was generated from a program called Wafer characterization 1 and the calibration itself was completed Wafercal 1 The present work implements mSOLT along with cSOLT (described next) in a new LabVIEW [22] program. 2.6.2 SOLT Calibration with More Complex Load and Thru Models With the problems encountered with mSOLT, an easier approach to accurate calibrations was suggested with equivalent models for the calibration standards. The most important error inducing factor in a SOLT calibration is the load standard. This topic was taken on by Peter Kirby [6] in his thesis that further proved the validity of mSOLT, and developed a new software routine that tried to overcome the shortcomings of mSOLT related to its cumbersome measurement file definitions for calibration standards. Kirby 24 1 The Wafer characterization and WaferCal programs were initially implemented by Dr. Don Metzger, an Anritsu Consultant.

PAGE 44

suggested and proved that with accurate modeling of the load standard in a SOLT calibration, the accuracy could improve. The accuracy of SOLT calibration was thus improved and was better than TRL at lower frequencies. However, it was not comparable to the same at higher frequencies in all cases where non-zero thru lines was involved. Hence it was suggested that with a thru model that accounts for the losses in the transmission line, the accuracy could improve. The importance of thru modeling was demonstrated with examples, but stopped short of implementing a thru model in the very useful LabVIEW program BullCal developed to implement the SOLT algorithm, with improved load standard modeling. One of the contributions of the present thesis is adding the modeling of non-zero length thru lines to the algorithm previously developed. Another contribution is demonstration of another idea suggested by Kirby, that the adjustment of load model resistance using a dc measurement can account for unavoidable fabrication variations in load resistance due to wafer processing. The LabVIEW program begun by Peter Kirby has been enhanced in a number of other ways to be discussed in future chapters. The resulting calibration algorithm that allows for more complex load and thru models to be used is called cSOLT in this thesis. 2.7 Chapter Summary The basics of vector network analyzer were discussed with a block diagram. The concept behind error correction and related terminologies were briefly reviewed with an introduction to types of error corrections. The different calibration techniques like SOLT, 25

PAGE 45

TRL, LRM and LRRM were discussed, with the error models they apply for correction. The advantages and disadvantages of each technique were analyzed with suggestions to improve on the drawbacks. TRL is generally considered most accurate high frequency calibration. LRM and LRRM are derived TRL and allows a compact calibration set but may not adequately represent the load standard. mSOLT reproduces TRL using compact set of transfer standards but also carries the low frequency problems of TRL and is cumbersome to use due to measured data file representation of standards. Finally the prior USF work that leads to the work presented here was discussed briefly. The complex model SOLT algorithm overcomes the drawbacks of these standards. The present work builds on and refines the prior USF work and the associated LabVIEW software program. 26

PAGE 46

CHAPTER 3 ACCURATE MODELS FOR SOLT CALIBRATION STANDARDS 3.1 Introduction This chapter explains the proposed accurate complex models that represent the SOLT calibration standards over a broad-band frequency range. The reason as to why SOLT calibration algorithm was chosen for improvement was explained in the previous chapter. Of the different error correction procedures, though TRL is considered to be the benchmark high frequency calibration, its accuracy at the lower frequency range (typically less than 1GHz) is questionable. It is augmented by the fact that it requires more than one delay line to account for the broadband frequency bandwidth results in a time consuming calibration. Also, more number of standards entails a significant amount of real estate. Other calibration techniques like SOLT and LRM are not as accurate as TRL at higher frequencies because the calibrations depend on ideal or symmetric standard definitions even though they use a compact set of standards and are easy to calibrate. Nevertheless, it has been suggested that the SOLT calibrations can have TRL accuracy with accurate modeling of the calibration standards. This chapter illustrates the complex models used in SOLT calibration to improve broad-band accuracy. 27

PAGE 47

3.2 Issues with SOLT Calibration It is known that the SOLT calibration routine depends on definitions of the standards. Almost all the VNA firmware has the SOLT calibration option loaded internally. The VNA provides conventional models for the definition of the calibration standards. The open is described with a capacitance, inductance a short, the load a series RL model and the thru line with a lossless ideal transmission line. At lower frequency ranges where these definitions are appropriate, it is verified that the calibration is very accurate. However as the frequency bandwidth of the calibration extends to higher frequencies, the ideal models used may no longer be good enough to account for the behavior of these standards. Thus, although the calibration technique has quite a few advantages in terms of space conservative standards and a calibration that is easy to perform, the technique required improvement to obtain a broadband accurate calibration. As an effort to increase the accuracy of the calibration, there has been prior work at the USF. The first one used measured data files from a TRL calibration for the definitions (by Mike Imparato [5]). This has the TRL limitations at the lower frequencies as it uses TRL data to define standards. Hence an improved SOLT calibration with complex models that account for the high frequency behavior of the standards was suggested previously by Peter Kirby [6]. The work was done as far as implementing a complex load model and emphasized on the need for a thru model. However the model needed more improvement, which is dealt with in this chapter in detail. The following sections in the chapter illustrate the complex models used for the calibration standards. 28

PAGE 48

3.3 Verification Substrates The accuracy of the models and calibration is verified on five substrates. The verification has been established on different substrates, to validate the calibration with complex models for any substrate. The substrates however have either CPW or microstrip lines with typical transmission line design. Substrates modified essentially for low loss or with non-typical transmission lines have not been analyzed and is beyond the scope of the thesis. The substrates used for the thesis are briefly explained below and the respective substrate diagrams are illustrated in Appendix A. 1. ITT (now M/A-Com) GaAs microstrip 100um thick microstrip substrate. The design was basically done by Mike Imparato as a part of his Masters thesis. The substrate has both TRL and SOLT standards with center of thru lines and an offset from half thru. The center of thru lines have been explored for the work presented here. The frequency range of measurements is from 0.04-65GHz. 2. GGB CS5 635um thick Co-planar waveguide (CPW) substrate. The calibration substrate has true probe tip transmission lines for calibration. The frequency range of interest is 0.04-65GHz. 3. Jmicro 125um thick microstrip substrate. The calibration substrate is analyzed on the center of thru line plane and the frequency range of operation is 0.04-40GHz. 4. FR4 14mil thick microstrip substrate. The FR4 substrate is particularly chosen to illustrate the compatibility of the complex model SOLT with on-chip resistors. The frequency range of concern is between 0.04-18GHz. 5. M/A-Com Custom 100um thick microstrip substrate. The calibration lines have 29

PAGE 49

been designed in interest of demonstrating one of the highlights of the work presented. It helps to illustrate the accuracy of SOLT calibration with equal footprint standards over a broad-band frequency range (0.04-50GHz). 3.4 Complex Models for Calibration Standards The concept of using complex models has been suggested before [6] and has been implemented in SOLT calibration algorithms. The models suggested however, needed more improvement. This section analyzes the inadequacy of the available models and hence validates the proposed complex load and thru models. The models were fit with Z 0 corrected TRL calibrated data taken over the desired frequency range using Agilent ADS [23]. These models were tested for verification for best fit over a broad-band frequency range on the different substrates described in the previous section. 3.4.1 Open and Short Standards C Z0,,l Figure 3.1 Equivalent Circuit Model of Open Standard (Probe Tip Reference). 30

PAGE 50

L Z0,,l Figure 3.2 Equivalent Circuit Model of Short Standard (Probe Tip Reference). The open and short standards are modeled with the ideal capacitance and inductance definitions. It has been verified with measurements referenced to the center of thru and probe tip planes that these models can define the standards well over a broad band of frequencies. When the measured data is with respect to the probe tip plane, then the models include an offset line length L and impedance Z 0 as seen in figures 3.1 and 3.2. The ideal models (Figure 3.1, 3.2 without line) fit the phase variations of the measured standards adequately over the frequency range. This is evident in the figures 3.3 3.6 that show results of open and short after a probe tip TRL calibration on a GGB CS5 substrate. In the case of GGB CS5, where the offset length is 75um, the line length is neglected since it is a small length of line and a direct optimization of C and L is chosen. The variations in the magnitude of the standards were considered negligible. However, this did not affect the accuracy of the calibration and hence the simple model for the open and short were assumed. 31

PAGE 51

0 10 20 30 40 50 60Frequency [GHz] -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15Reflection Co-efficient (S11) [dB] Measured S11Model S11 Figure 3.3 Magnitude of Measured versus Equivalent Model of Open Referenced at Probe Tip on GGB CS5 Substrate. 0 10 20 30 40 50 60Frequency [GHz] -14 -12 -10 -8 -6 -4 -2 0 2Reflection Co-efficient (S11) [Deg] Model OpenMeasured Open Figure 3.4 Phase of Measured versus Model Equivalent Model of Open Referenced at Probe Tip on GGB CS5 Substrate. 32

PAGE 52

0 10 20 30 40 50 60Frequency [GHz] -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1Reflection Co-efficient (S11) [dB] Model ShortMeasured Short Figure 3.5 S11 Magnitude of Measured Data versus Equivalent Model of Short Referenced at Probe Tip on GGB CS5 Substrate. 0 10 20 30 40 50 60Frequency [GHz] 166 168 170 172 174 176 178 180Reflection Co-efficient (S11) [Deg] Model ShortMeasured Short Figure 3.6 S11 Phase of Measured Data versus Equivalent Model of Short Referenced at Probe Tip on GGB CS5 Substrate. 33

PAGE 53

3.4.2 Load Standard Model After a careful study on the variations of a load (resistor), it was realized that it was important that a more complex model be used instead of the commonly used series RL model for many popular applications. Thus the need for a more complex model that accounts for the variations with frequency was emphasized after analyzing the existing models. The existing NIST model is illustrated and compared with the suggested model which is verified with CPW, microstrip and on-chip resistors fabricated on various substrates. 3.4.2.1 NIST Load Model NIST proposed a complex model for the load standard used in the SOLT calibration [24]. The model (Figure 3.7) originally demonstrated for CPW loads included the capacitance to ground effect (C) that is significant at higher frequencies along with the series RL model ideally used. C RDC L Figure 3.7 Equivalent Circuit NIST Model for CPW Load Standard. 34

PAGE 54

It is verified that the model fit the real part of the load impedance quite well though there are a few discrepancies towards DC due to the reason that TRL fails at lower frequencies. However, the imaginary impedance (Figure 3.11) of the model did not track well with the measured data as frequency increased. The graphs (Figure 3.10, 3.11) shown are center of thru TRL measured load data on the ITT microstrip GaAs substrate. 3.4.2.2 Proposed Complex Load Model The previously suggested model (Peter Kirby [6]), provided a good model in terms of the fit with the measured data. However the model is questionable with respect to physical plausibility. The resistance R added in series with the capacitance to ground (figure 3.8) did not have a physical significance and hence an improved model with better physical significance was sought. C RDC L R Figure 3.8 Equivalent Circuit Model for CPW Load Standard Suggested in [6]. The alternative load model suggested [25] in this work accounts well for the high frequency parasitic effects in the load. The load models are derived such that they fit high frequency TRL data, but smoothly transition to the DC resistance at low frequencies. The 35

PAGE 55

model is also used to fit each of the ports separately since the dc resistances of the ports varied independently as in some cases like the ITT GaAs substrates. The advantage of this complex model is that though most of the commercial substrates are laser trimmed and well fabricated (hence negligible variation in load impedance with frequency), there are many cases where the load is not so well behaved. Figure 3.9 shows the proposed complex load model. The model is essentially an improved variation of the existing NIST model. The DC resistance of the load is represented as R DC ; the series inductance of the load L and capacitance from signal to ground C. Apart from these parameters, it also includes the gap capacitance that exists between the signal line to the via pad and inductance to the ground through the via. Figure 3.10 shows a microphotograph of an ITT GaAs microstrip load. When modeling a CPW load, the via inductance is zeroed in the model since the CPW transmission line structure does not have a via. C RDC L CgLvia Figure 3.9 An Improved Equivalent Circuit Model for Load Standard (Microstrip). 36

PAGE 56

The load model was first verified with ITT GaAs microstrip loads (Figure 3.11, 3.12). Table 3.1 gives the simulated values of the parameters used in the model for ITT GaAs loads under test. To validate the physical significance of the model, the values obtained after simulation were tested mathematically. The inductance of the load and capacitance to ground were calculated with LINPAR (program that calculates matrix parameters for transmission lines). The parameters are calculated treating the load as a transmission line. The load inductance and capacitance to ground are found to be 48pH and 18.3fF respectively. The gap capacitance is a low value as expected. This capacitance represents the combined coupling through the air to the pad on top of the ground via, as well as coupling through the substrate to the conical shaped via below the load (which is more significant). When the load is optimized with a series RL model, the value of the series inductance is about 30pH. It is verified and illustrated (Section 3.4.2.3) that since the load impedance varies widely with frequency; the series RL model is not adequate to model the load. Figure 3.10 Picture of GaAs Microstrip Load, Which the Complex Model Represents. 37

PAGE 57

Table 3.1Tabulation of Load Model Parameters and their Values from Simulation for Load Measured on ITT GaAs Microstrip Substrate. Parameters Significance Values Rdc DC Resistance of load 50.256 L Series Inductance 56.82pH C Capacitance from signal to ground 11.7fF Cg Gap capacitance 20.65fF Lvia Via Inductance 124.52pH 0 10 20 30 40 50 60Frequency [GHz] 40 50 60 70 80 90 100 110 120Real Impedance [] Measured DataProposed Load ModelNIST Load ModelSeries RL Model Figure 3.11 Real Impedance of Measured Load vs. Complex Load Model at Center of Thru Reference. 38

PAGE 58

0 10 20 30 40 50 60Frequency [GHz] -20 -15 -10 -5 0 5 10 15 20 25Imaginary Impedance [] Measured DataProposed Load ModelNIST Load ModelSeries RL Model Figure 3.12 Imaginary Impedance of Measured Load vs. Complex Load Model at Center of Thru Reference. 3.4.2.3 R DC Variation with RF Performance of Load The advantage of the proposed complex model is that when compared to the available models, is its ability to track the DC resistance of the load at lower end and at the same time follow the load behavior at higher frequencies more accurately. It has been verified [26] that the RF performance of the load is directly related to the DC resistance of the load. The availability of a whole wafer (ITT GaAs microstrip) with multiple sites of the same die is utilized to perform this verification test. Different loads were measured on multiple sites of the wafer after a Z 0 corrected center of thru TRL calibration. It was observed that the load impedances were not uniform with a DC resistance of 50. Ideally, it is expected that the loads were all 50. However due to various fabrication 39

PAGE 59

issues (for example, resistivity and thickness tolerances), the load impedances had some reliability problems from die to die on the wafer (Figure 3.13). m2freq=240.0MHzS(2,2)=0.004 / -4.645impedance = Z0 (1.009 j6.968E-4) m3freq=40.00GHzS(2,2)=0.227 / 30.059impedance = Z0 (1.441 + j0.346) freq (40.00MHz to 40.00GHz)Reflection co-eff m2 m3 Figure 3.13 Reflection Co-Efficients of Loads for the 10 GaAs Loads Used, with Varying DC Resistances Between 49.5 To 52.5 on Smith Chart (Markers on 50.256 Load). 0 10 20 30 40 50 60Frequency [GHz] 40 50 60 70 80 90 100 110Real Impedance of Varying RDC Loads [] 0 10 20 30 40 50 60Frequency [GHz] 40 50 60 70 80 90 100 110Real Impedance of Models for Varying RDC Loads [] Figure 3.14 Real Part of Measured (Left) and Model (Right) Load Impedance of 10 GaAs Microstrip Loads with Varying DC Resistances between 49.5 To 52.5. 40

PAGE 60

0 10 20 30 40 50 60Frequency [GHz] -40 -30 -20 -10 0 10 20 30Imaginary Impedance of Varying RDC Loads [] 0 10 20 30 40 50 60Frequency [GHz] -25 -20 -15 -10 -5 0 5 10 15 20Imaginary Impedance of Models for Varying RDC Loads [] Figure 3.15 Imaginary Part of Load Impedance of 10 GaAs Microstrip Loads with Varying DC Resistances Between 49.5 To 52.5. The real and imaginary load impedance of 10 GaAs microstrip loads in terms of measured and model data are plotted in Figures 3.14 and 3.15. It is clear from the graphs that the load impedance is influenced by the DC resistance which is seen to varying from die to die. The measured loads are fit with the load model shown in the previous section, adjusting for the respective DC resistances but making no changes to the other model parameters. This is shown in figures 3.16 and 3.17 where a load with DC resistance of 52.045 is measured and matched with the R DC compensated model. Figures 3.18 and 3.19 augment the fact that the load model can track well with RF performance of the load at both DC and the higher end. As a reminder, the model parameters are values obtained when optimizing for a 50.3 load. It is seen that the model can fit well with 52 and 49.8 loads that are at least 1.5 different from the simulated load. 41

PAGE 61

0 10 20 30 40 50 60Frequency [GHz] 50 55 60 65 70 75 80 85 90 95 100 105Real Impedance [] 52ohm Load MeasuredComplex Load Model Figure 3.16 Real Impedance of Measured Load vs. Load Model with Adjusted R DC of 52.045 at Center of Thru Reference. 0 10 20 30 40 50 60Frequency [GHz] -30 -25 -20 -15 -10 -5 0 5 10 15 20Imaginary Impedance [] 52ohm Measured LoadLoad Model Data Figure 3.17 Imaginary Impedance of Measured Load vs. Load Model with Adjusted R DC of 52.045 at Center of Thru Reference. 42

PAGE 62

0 10 20 30 40 50 60Frequency [GHz] 40 50 60 70 80 90 100 110Real Impedance [] 49.8ohm Measured LoadLoad Model Data Figure 3.18 Real Impedance of Measured Load vs. Load Model with Adjusted R DC of 50.045 at Center of Thru Reference. 0 10 20 30 40 50 60Frequency [GHz] -25 -20 -15 -10 -5 0 5 10 15 20 25Imaginary Impedance [] 49.8ohm Measured LoadLoad Model Data Figure 3.19 Imaginary Impedance of Measured Load vs. Load Model with Adjusted R DC of 50.045 at Center of Thru Reference. 43

PAGE 63

0 10 20 30 40 50 60Frequency [GHz] 0 1 2 3 4 5 6 7Vector Error Difference(Meas_Model) 49.8ohm Load50.5ohm Load52.0ohm Load50.03ohm Load Figure 3.20 Vector Error Difference of Loads Measured on the Whole Wafer and the Optimized R DC Compensated Model. The vector error difference between the measured loads and the respective R DC compensated models is plotted in figure 3.20. It is seen that the maximum worst case difference between the measured and model at 65Hz is about 5.5. For a more complete analysis, 14 different loads were measured and the average vector error difference between the measured and model is plotted (Figure 3.21). This is compared with the series RL model that is available in the commercial VNA firmware as the equivalent model for the load standard. 44

PAGE 64

0 10 20 30 40 50 60Frequency [GHz] 0 10 20 30 40 50 60 70 80Avg(Zmodel Zmeas) [] Proposed Complex Load ModelNIST Load ModelSeries RL Model Figure 3.21 Average Vector Magnitude Error of 15 Loads Comparing the Different Load Model Conditions. The vector error from the proposed model is also compared with the NIST model. It is seen in the graph (Figure 3.15) that the proposed load model has an average error less than 4 throughout the frequency range. Though the NIST model can predict closely with varying DC resistance with a vector error difference is about 14 at 65GHz. The error through most of the bandwidth is about 8. The series RL model however had the maximum error because the model is basically a straight with little variation with frequency. Thus the graph again highlights the fact that the complex model proposed is able to very closely the RF performance of the load even with increase in frequencies. As a final note, the importance of the adjusting for R DC is highlighted again with the figure 3.22. The plot shows the vector error differences for model versus measured data for the R DC varying and non varying cases. It is clear from the graph that if the load 45

PAGE 65

is assumed to be 50 with no variation die to die, then the error between the measured and model is much more significant. The fact that the 50 model does not track with the lower frequency data towards DC is shown in the figure. It also highlights the validity of the improved load model by comparing the average deviation of the measured data with the NIST model. 0 10 20 30 40 50 60Frequency [GHz] 0 2 4 6 8 10 12 14 16Avg(Zmodel Zmeas) [] Complex Load Model with RDC CorrectionComplex Load Model with No RDC CorrectionNIST Model with no RDC CorrectionNIST Load Model with RDC Correction Figure 3.22 Comparison of Vector Error Difference between the Measured and Model With and Without Compensation for Varying R DC 3.4.2.4 Verification of Proposed Model on Other Substrates The complex load model was also verified with measured loads on other substrates. The versatility of the model is proved with measured loads on different dielectric substrates. The figures 3.16, 3.17 show results of measured load data on GGB CS5 wafer versus the model. It is seen in the graphs that there is not much variation of 46

PAGE 66

load impedance with increase in frequency. This is because the GGB loads have been well fabricated and laser trimmed thus producing a god 50 load. The on-chip resistor loads measured on 14mil FR4 boards are shown in figures 3.18 and 3.19. It is clear from the graphs that there is a good agreement between measured data and model. Tables 3.2 and 3.3 give the values obtained after optimizing the model with the measured data for GGB CS5 and FR4 substrates. The compatibility of the model is also verified with microstrip parallel loads available on a GaAs substrate. The results (Figures 3.20, 3.21) indicate that the model is able to trace well with the measured data though they are different in physical structure. The discrepancies found towards the 40GHz in figure 3.20 is because the substrate did not have enough delay lines to account for the entire frequency bandwidth. The measured load with respective model data on the Jmicro 5mil and M/A-Com GaAs substrates are shown in Appendix A. Well fabricated and well behaved loads like that on GGB (Figure 3.23-24) Jmicro (illustrated in Appendix C) substrates where the real part of the load does not vary too much and the imaginary part varies linearly with frequency, can be modeled with simpler complex load model. In most cases, the NIST load model can be used to model the measured load data. The series RL model was used to optimize the measured loads on all the substrates. In case of the commercial substrates, GGB CS5 and Jmicro where the loads have been well fabricated (close to 50), the simple RL model could predict the load behavior over the frequency range. The inductance of the GGB load is about the same value as predicted by the specifications from GGB [27], which is -4pH. 47

PAGE 67

Table 3.2 Tabulation of Load Model Parameters and Their Values from Simulation for Load Measured at Probe Tip Plane (75um Offset Length) on GGB CS5 Substrate. Parameters Significance Values Rdc DC Resistance of load 49.9 L Series Inductance 10.99pH C Capacitance from signal to ground 6.4fF Cg Gap capacitance 0.19fF Lvia Via Inductance 0pH 0 10 20 30 40 50 60Frequency [GHz] 48.5 49 49.5 50 50.5 51Impedance (Real) ] Measured DataLoad Model Figure 3.23 Real Impedance of GGB CS5 Load with R DC of 49.9 vs. Load Model at Probe tip Reference. 48

PAGE 68

0 10 20 30 40 50 60Frequency [GHz] -2 -1.5 -1 -0.5 0 0.5Impedance (Imaginary) [] Measured DataLoad Model Figure 3.24 Imaginary Impedance of GGB CS5 Load with R DC of 49.9 vs. Load Model at Probe Tip Reference. 0 2 4 6 8 10 12 14 16 18Frequency [GHz] 40 50 60 70 80 90 100 110 120 130Real Impedance [] Measured DataLoad Model Figure 3.25 Real Impedance of 14mil FR4 Load with R DC of 49.75 vs. Load Model at Center of Thru Reference. 49

PAGE 69

Table 3.3 Tabulation of Load Model Parameters and Their Values from Simulation for Load Measured on 14mil FR4 Microstrip Substrate. Parameters Significance Values Rdc DC Resistance of load 49.75 L Series Inductance 689.05pH C Capacitance from signal to ground 28.4fF Cg Gap capacitance 18.4fF Lvia Via Inductance 0.829pH 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -10 0 10 20 30 40 50 60 70 80Imaginary Impedance [] Measured DataLoad Model Figure 3.26 Imaginary Impedance of 14mil FR4 Load with R DC of 49.75 vs. Load Model at Center of Thru Reference. 50

PAGE 70

0 5 10 15 20 25 30 35 40Frequency [GHz] 48 48.5 49 49.5 50 50.5 51 51.5Real Impedance [] Measured DataComplex Load ModelDC Resistance Figure 3.27 Real Impedance of Microstrip Parallel Load with R DC of 48.4 Measured at Center of Thru Reference. 0 5 10 15 20 25 30 35 40Frequency [GHz] -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1Imaginary Impedance [] Measured DataLoad Model Figure 3.28 Imaginary Impedance of Microstrip Parallel Load with R DC of 48.4 Measured at Center of Thru Reference. 51

PAGE 71

3.5 Thru Model Equations The VNA calibration algorithms like SOLT or LRM assume an ideal lossless transmission line model for the thru line standard. In reality, the thru line is lossy and the attenuation loss varies with respect to the substrate and conductor properties. With increase in frequency, issues such as radiation and surface wave effects become more significant, thereby increasing the attenuation constant at those frequencies. Thus it becomes necessary that the thru line be well modeled in terms of the propagation constant over the design frequency range. Prior to this work, [6] illustrates the importance of a complex thru line. The thru line behavior was illustrated with a TLINP model from Agilent ADS. In the work presented here, a set of equations that predict the nature of a thru line is derived and compared with the TLINP model. It is observed that the equations are able to trace well with the measured data and the model equations have been verified up to 65GHz. The thru line equations treats the transmission line as a lossy line and thus compensates for the losses. It is known that the propagation constant of a transmission line is represented as i where A is the attenuation constant (dB/unit length) of the transmission line. The dielectric loss of the substrate and conductor loss of the metal are the two main factors that are generally significant in a thru line measurement. The other losses are either not too significant or cannot be modeled directly. The attenuation constant equation was thus designed to be dependant on the aforementioned losses. 52

PAGE 72

The conductor loss of a transmission line is represented by the sheet resistivity of the line and is given by, Rsf where Relative permeability (H/m) Conductivity of the metal (S/m) f Frequency (GHz) The dielectric loss is represented by the equation [28], dfQtanDeff c where Qeff1r1 tanD Loss tangent of the metal c Velocity of light (m/sec) eff effective dielectric constant r dielectric constant The propagation constant of the line is given by, 2freqeff C 53

PAGE 73

The total attenuation constant (in nepers) is represented as the following equation, )(*dca The above equation includes a fitting factor a, which is multiplied with the total attenuation. This is because the equation uses simple approximations to estimate the losses and hence the total loss is underestimated. The objective while modeling for the thru loss was a simple equation, which can predict both microstrip and CPW losses. A complex equation that accounts the losses more specifically can accurately predict the losses. But this also increases the complexity of the SOLT algorithm when implemented in LabVIEW by increasing the computation time and memory to execute such equations. Thus an equation has been modeled to predict the behavior of the thru over a frequency range with minimum computation. It should also be noted that the thru equations are a good approximation for typical transmission lines and substrates. The propagation constant of the thru line thus estimated is used to calculate the ABCD parameters which are then converted to S-parameters. The thru equation fit is verified on substrates with different dielectrics. It is suggested from verification that the thru equation holds good for typical microstrip and CPW substrates. The results on GGB CS5 and microstrip GaAs are shown in figures 3.22 3.29. The S-parameter measurements with their respective model fits with other substrates (M/ACom GaAs, Jmicro 5mil) are listed in Appendix A. It is clear from the graphs that the equations fit the measured data well throughout the frequency range. 54

PAGE 74

0 10 20 30 40 50 60Frequency [GHz] -60 -55 -50 -45 -40 -35 -30 -25S11 Maginitude [dB] Measured DataThru Model Figure 3.29 Reflection Co-efficient of 8390um Probe Tip Measured Delay on ITT GaAs Microstrip Substrate. 0 10 20 30 40 50 60Frequency [GHz] -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0S21 Magnitude [dB] Measured DataThru Model Figure 3.30 S21 (dB) of 8390um Probe Tip Measured Delay on ITT GaAs Microstrip Substrate. 55

PAGE 75

0 10 20 30 40 50 60Frequency [GHz] -200 -150 -100 -50 0 50 100 150 200S21 Phase [Deg] Measured DataThru Model Figure 3.31 S21 Phase of 8390um Probe Tip Measured Delay on ITT GaAs Microstrip Substrate. 0 10 20 30 40 50 60Frequency [GHz] -100 -90 -80 -70 -60 -50 -40 -30 -20S11 Thru [dB] Measured ThruThru Model Figure 3.32 Reflection Co-Efficient of 500um Probe Tip Measured Delay on GGB CS5 Substrate. 56

PAGE 76

0 10 20 30 40 50 60Frequency [GHz] -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05S21 [dB] Measured ThruThru Model Figure 3.33 S21 (dB) of 500um Probe Tip Measured Delay on GGB CS5 Substrate. 0 10 20 30 40 50 60Frequency [GHz] -90 -80 -70 -60 -50 -40 -30 -20 -10 0S21 Phase [Deg] Measured ThruThru Model Figure 3.34 S21 Phase of 500um Probe Tip Measured Delay on GGB CS5 Substrate. 57

PAGE 77

0 2 4 6 8 10 12 14 16 18Frequency [GHz] -70 -60 -50 -40 -30 -20 -10 0S11 Maginitude [dB] -2 -1.8 -1.6 -1.4 -1.2 -1 -0.8 -0.6 -0.4 -0.2 0S21 Magnitude [dB] Measured DataThru Model Figure 3.35 Return Loss (S11) (dB) and S21 (dB) for a 14mil FR4 Delay Line of Length 1.1252cm Measured at the Center of Thru Reference. 0 2 4 6 8 10 12 14 16 18 20Frequency [GHz] -200 -150 -100 -50 0 50 100 150 200S21 Phase [Deg] Measured DataThru Model Figure 3.36 S21 Phase of 1.1252cm Center of Thru Referenced Delay on 14mil FR4 Substrate. 58

PAGE 78

It is evident from the above graphs that the thru line equations that are used to represent a lossy transmission line follow the behavior the measured data very well over a broad-band frequency range. It is also clear from Figure 3.23, that the TLINP model does not adequately model the losses on the GaAs transmission line. The accurate definition of the transmission line when used in a SOLT calibration, improves the accuracy of the calibration to a great extent which would be elaborated in the next chapter. 3.6 Chapter Summary Rigorous models are described for improving accuracy in a SOLT calibration. The models were validated with measured data after TRL calibrations referenced at both center of thru and probe tip. The open and short standards were modeled with simple capacitance and inductance; while the load has a more complex model that can relate to the DC resistance of the load at the lower end and at the same time track with the high frequency parasitics. The fact that the thru line is lossy with increase in frequencies was highlighted and a lossy thru equation that compensates for the conductor and dielectric losses has been modeled. Finally, it is shown that the RF performance changes due to load fabrication variation can be addressed by calibrating or adjusting the load model with the measured DC resistance for a particular load with the proposed complex load model. 59

PAGE 79

CHAPTER 4 CALIBRATION COMPARISON TECHNIQUES 4.1 Introduction The difference between S-parameter measurements made with respect to two VNA calibrations that are similar to each other is quite helpful in comprehending the advantages of one method over the other. The importance of the calibration comparison method is highlighted when the accuracy of calibrations have to be verified. Herein, where an improved SOLT calibration algorithm has been suggested, it becomes essential that the proposed method is compared with respect to the available techniques. This chapter expounds on the calibration comparison methods suggested by NIST [29, 31]. The two methods compute the difference between the error co-efficients of the calibrations of interest. The upper bound graph generated by the methods gives the maximum worst case difference between two calibrations when S-parameters of a device is measured after calibration. The theory behind the two tier calibration comparison and direct comparison of two calibrations are discussed. It also discusses the implementation of the latter method [31] in LabVIEW for the work presented with demonstration of an example result. 60

PAGE 80

4.2 Calibration Comparison Methods 4.2.1 Comparison with Two-tier Calibrations D.F. Williams and R.B. Marks of NIST [29] proposed a method to compare on-wafer calibrations. The method uses TRL calibration as the benchmark calibration. The calibration whose accuracy is to be verified is the working calibration and is performed initially before the benchmark calibration. VNA Port 1 [X]Error Box 1 [T]DUT Parameters [Y]Error Box 2 VNA Port 2 Figure 4.1Cascade Matrix Representation of Instrument and DUT State during Measurements. The S-parameter measurement of any DUT with two-port VNA (M i ) is given by the product of three cascaded matrices as shown in Figure 4.1. MiXTiY (1) The Error box 2 or [Y] is represented as a reverse cascade matrix and is given by Y0110 Y10110 (2) The error box 1 [X] and 2 [Y] are calculated with measurements on calibration standards. T i the cascade matrix of a device i, is thus determined through the calibration procedure. Assuming T A is the cascade matrix of a device measured with respect to calibration A, T B is the cascade matrix for the device measured with respect to the 61

PAGE 81

benchmark calibration and T D is the actual cascade matrix of the device then a relation between the cascade matrices of the device can be derived. The cascade matrix from the initial calibration to be verified for accuracy should be ideally equal to the actual cascade matrix of the device if it as accurate as the benchmark calibration and is given the following relation, TAXBTBYB XDTDY D (3) The process of calibration comparison is based on determining the X B and Y B matrices. The calibration whose accuracy is to verified is the initial calibration A. The benchmark TRL calibration is then performed with respect to the calibration A. The two-tier calibration is performed with the help of multi-line TRL calibration [2] implemented in software MultiCAL. The error boxes X B and Y B are determined at the end of the step. It has been illustrated in [30] that TRL calibration generally provides the most accurate representation of the device under test, when the lines and transitions used for calibration are also applied for the DUT, and when the reference plane is established at the center of the thru line. Hence, it results in the approximations, T B = T D for all matrices of T D and X B = X D and Y B = Y D The matrices X D and Y D thus represent the differences between measurements performed with respect to the working calibration and the benchmark calibration. In practice there are some differences between two TRL calibrations. This is the result of random and repeatability errors present in the measurement system. The difference between the two calibrations under study is verified by plotting the upper bound error graphs that represent the worst case deviations [S ij S ij ]. The difference 62

PAGE 82

between the error co-efficients can be equated for maximum difference between the S-parameters (explained in Section 4.3). 4.2.2 Calibration Comparison with One-tier Calibrations The comparison method discussed in the previous section requires two-tier calibrations to establish the comparison. As implemented by NIST, it also requires that TRL calibration be the benchmark calibration for comparison. Thus when the focus is on comparing calibration methods other than TRL, the two-tier procedure does not produce a solution. R.B. Marks and others [31] at the NIST presented a technique for comparing any two similar calibrations with respect to each other. As quoted in the previous section, cascade matrix T 1 of the device is calculated from the error matrices X and Y with enough number of measurements M i for calculation. 11111)(**)(YMXT (4) Assuming 12 term error models, X 1 and Y 1 is calculated from the calibration error co-efficients. 1*1EsfEdfEsfEdfErfX (5) and 1**)*1(*21EsrEdrEsrEdrErrErrEdrEtfY (6) where, 63

PAGE 83

)(*2EsrElfEdrErrEsrElf (7) When a second calibration is performed, the cascade matrix T 2 is given by a similar relation as that of equation (4). 12122)(**)(YMXT (8) Combining equations (4) and (8), YTXYYTXXT **])(*[**]*)[(211222111 (9) The above equation (9) is the relation between the two cascade matrices that represent two different calibrations. The error box X and Y give the differences between the two calibrations and is the deviation between the measurements. When the two calibrations are identical, it is noted that the cascade matrices are equal with X and Y equal to the identity matrix. This is however the ideal case and two repeatability calibrations differ by a small degree due to the random errors induced into the system. The difference in calibrations is presented by the equation, )(**)(2211ITIT (10) where, IX1 ; are the deviations from the identity matrix (I). IY2 4.3 Determination of Worst Case Deviations Upper bound error data is defined by the difference in S-parameters of a passive device that is measured with respect to two calibrations and is given by the worst case deviation between the measured S-parameters S 1 ij (with respect to the cascade matrix T 1 ) 64

PAGE 84

and S-parameters S 2 ij (with respect to cascade matrix T 2 ). The worst case deviation is computed from two methods discussed above in a similar manner. The equations in the previous section (4.2.2) can be simplified by assuming an error less than 1. The assumption reduces the equation (10) to 221221**TTTT (11) The cascade T-parameters are then represented in terms of S-parameter to generate the error bound data. The conversion leads to the following set of equations which characterize the error bound for each of the S-parameters. )**1(*111212222121112221121SSSS (12) Equation (12) is modified to for 11ij and 12ij The inequality for the error bounds is then given by, 12111221221222112121121**SSSSS (13) 12111221222221111212112**SSSSS (14) 12121122121122221111111211111****SSSSSS (15) 22122212121121222112221222122****SSSSSS (16) The error bounds can be further simplified when the DUT under consideration is a passive device with max|S ij |1 and when the reference impedance of calibration is real at each port. 121221122211212121121SSS (17) 65

PAGE 85

121221222111121212112SSS (18) 1212212221111121111111SS (19) 2211211222112122222122SS (20) 4.4 Implementation and Verification of Comparison Algorithm Figure 4.2 Screen Shot of Cal Compare Program Implemented in LabVIEW. The need to compare the proposed cSOLT calibration with TRL and other existing calibrations led to implementing the calibration comparison method discussed in Section 4.2.2. The method has been implemented with the help of LabVIEW. The 66

PAGE 86

program can be used to compare any two calibrations directly from the network analyzer or read from the error co-efficients that are saved in a file. Figure 4.2 is a screen shot of the comparison algorithm implemented. The program also allows calculation of error bounds for passive or active device under test after calibration. The Cal Compare algorithm is verified with co-axial calibrations on co-axial OS-50 calibration standards. Front panel TRL, SOLT and sliding load SOLT calibrations were performed on the standards for verification of accuracy from 0.2 50GHz. The upper bound error graph that shows the maximum error for [S ij S ij ] was plotted to compare the three calibrations. The availability of airlines that covered the frequency bandwidth for TRL calibration made it the most accurate calibration. Since the load in the SOLT calibration was not a broadband load, it exhibits the highest upper bound error. Nevertheless, with sliding load in SOLT calibration, the error was greatly reduced when compared to the ideal SOLT algorithm. The sliding SOLT (represented as SLSOLT in the Figure 4.3) calibration describes the load much better than the simple load. The load is measured at different positions and the reflection co-efficient at different points on the Smith chart is determined. Thus the load behavior is predicted more accurately when compared to a series RL model. However, after about 40GHz the sliding load also fails and the error becomes closer to ideal SOLT. The Figure 4.3 clearly shows the upper bound error data for the three calibrations with TRL repeatability as the reference for minimum error in the measurement system. 67

PAGE 87

0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18Upper Bound Error [Sij S'ij] TRL RepeatTRL vs. SOLTTRL vs. SLSOLT Figure 4.3 Upper Bound Error Graph for TRL, SOLT, Sliding Load SOLT (SLSOLT) Calibrations Performed on OS-50 Co-axial Standards. 4.5 Chapter Summary The chapter reviews the calibration comparison methods for analyzing the accuracy of S-parameter measurements of a DUT. Two types of calibration comparison methods are explained for upper bound error data calculations. The first method discusses the comparison of TRL algorithm with any other calibration whose accuracy is to be verified. The second method discusses comparison of any two calibration algorithms. Since in the work presented, there is need to compare the proposed calibration with the calibrations other than TRL, it led to the implementation of the LabVIEW program with the help of the second algorithm. An example graph illustrates results obtained for verification of different co-axial calibrations on OS-50 calibration standards. 68

PAGE 88

CHAPTER 5 COMPLEX SOLT (cSOLT) CALIBRATION IMPLEMENTATION AND ACCURACY VERIFICATION GaAs MMIC SUBSTRATES 5.1 Introduction In this chapter the improved SOLT (cSOLT) calibration is implemented with the complex load and thru models that have been discussed in Chapter 3. A significant improvement in the accuracy of SOLT calibration over a broad-band frequency range is achieved and this is attributed to use of the complex models. The improved SOLT algorithm is compared with TRL, measured SOLT (mSOLT) [5] and the conventional front panel SOLT calibrations. The term SOLT henceforth in this chapter refers to the conventional SOLT calibration. In this chapter, the comparison for verification of accuracy is established on the two custom GaAs MMIC microstrip substrates that were available ITT GaAs designed at USF in 1999 and M/A-Com GaAs designed at USF in 2003. The importance of the complex load and thru models in a SOLT calibration is highlighted with upper bound error graphs for center of thru and probe tip reference plane calibrations. This chapter deals with the two GaAs MMIC substrates that have been used for verification of accuracy in detail. 69

PAGE 89

5.2 Complex SOLT Calibration and Verification of Accuracy As explained in the earlier chapters the disadvantage of SOLT when performed with presently available VNA calibration algorithms is due to the limitations with the models used to define the calibration standards. This may reduce the accuracy of the calibration at higher frequencies where the models do not adequately define the RF performance for commonly used planar standards. The fact that the definitions of the standards can vary from port to port particularly for the load is also not accounted for in the most calibration routines. Thus an offline calibration algorithm that accounts for the models and variations between the ports is required in order to improve the accuracy of SOLT calibrations. A LabVIEW program (an extension of the work done by former USF Student [6]) has been implemented for the purpose. The program also includes reference plane shifting after calibration to set the reference plane at any desired position while measuring a DUT. The calibration can be performed with Wiltron 360B (DC-65GHz) and Anritsu Lightning (DC-65GHz) VNAs. The Figure 5.1 shows the screen shot of the program. The program also allows using measured data files for standard definitions as in the case of mSOLT calibration method. The calibrations on the ITT GaAs substrates illustrated in this chapter are performed with the Anritsu Lightning. The improvement in accuracy is verified using the Cal Compare program implemented as part of this work which is described in Chapter 4. The method compares the error co-efficients after two similar calibrations and thus plots the maximum upper bound error graph. The comparison helps establish the maximum error between two 70

PAGE 90

calibrations. The error is compared with the repeatability plot of two same successive calibrations to justify for the minimum error in the measurement system. Figure 5.1 Screen Shot of cSOLT Calibration Algorithm Implemented With LabVIEW. 5.3 ITT GaAs Microstrip Substrate The GaAs microstrip from ITT GaAsTEK (now part of M/A-Com) designed by Mike Imparato in 1999 [5], available as a whole wafer with multiple dies of the same standards was used for verification of accuracy with calibrations. When the S-parameter characteristics of the device under test are of prime importance, the calibration reference plane is then generally set at the center of the thru plane. This case corresponds to the zero length thru line case for which the complex thru model presented in Chapter 3 is not used. 71

PAGE 91

5.3.1 TRL Calibration Data Verification ITT GaAs Microstrip Substrate A TRL calibration is dependent on a few parameters that are essential to perform an accurate calibration. Factors like total number of lines with varied lengths used, characteristic impedance of the lines and estimate of the effective dielectric constant influence the accuracy of the calibration. Hence it is necessary that these factors are verified after a TRL calibration. The availability of a long enough delay line (8390um total length) made it possible to obtain low frequency data that follows the DC resistance of the load. The frequency bandwidth over which a multi-line TRL calibration can be performed is described by the effective phase delay. It is desired the phase delay is close to 90 or ideally at least between 20 and 160 [2] so that the difference phase between two lines never becomes zero. This would result in a singular point in the solution to TRL algorithm. This can be avoided by using no more than 8:1 bandwidth for each line. The effective phase delay of the delay lines on the ITT GaAs (Figure 5.2) clearly shows good phase data (greater than 30deg) from about 1.5GHz. The effective dielectric constant ( eff ) is one of the other parameter that is verified with a multiline TRL calibration. It is defined as the ratio of the actual capacitance of the dielectric to the capacitance when the dielectric is placed in air. The effective dielectric constant is used to treat propagation in a quasi-TEM transmission line. The effective dielectric constant is used to calculate propagation constant of the lines and hence is an important output of the calibration. Figure 5.3 shows the eff in real and imaginary and is about 8.35 over the frequency range for the ITT GaAs microstrip substrate. 72

PAGE 92

0 10 20 30 40 50 60Frequency [GHz] 0 10 20 30 40 50 60 70 80 90Effective Phase Delay [Deg] Figure 5.2 Effective Phase Delay of Delay Lines on the ITT GaAs Microstrip Substrate after TRL Calibration. 0 10 20 30 40 50 60Frequency [GHz] -15 -10 -5 0 5 10Effective Dielectric Constant-Eeff (Real Imaginary) Real EeffImagnary Eeff Figure 5.3 Effective Dielectric Constant ( eff ) of ITT GaAs Microstrip Substrate in Real Imaginary after Center of Thru TRL Calibration (Z 0 =50.9 @ 10GHz). 73

PAGE 93

The reference impedance of TRL calibration is ideally set to the characteristic impedance of the line. The reference impedance can be corrected to 50 by calculating for the capacitance of the line. The capacitance of the line can be calculated with the NIST CAP TM program [32]. It basically uses the load and effective dielectric constant measured at lower frequencies where the load is ideally a DC resistance and calculates the capacitance. The capacitance correction is included in the normal TRL calibration and thus the calibration is referenced to 50. The characteristic impedance of ITT GaAs is plotted in Figure 5.4. 0 10 20 30 40 50 60Frequency [GHz] -40 -30 -20 -10 0 10 20 30 40 50 60 70Characterisitic Impedance Z0 (Real, Imaginary) Real Z0Imaginary Z0 Figure 5.4 Characteristic Impedance of ITT GaAs Microstrip Substrate in Real Imaginary, after Center of Thru TRL Calibration. 5.3.2 cSOLT TRL Calibration Data Comparison The SOLT calibration standards were measured after the center of thru TRL calibration and modeled as discussed in Chapter 3. A cSOLT was performed with the standard definitions generated with the models fit to TRL data along with the DC 74

PAGE 94

resistance measurements. The calibration standards were measured with respect to the TRL and cSOLT calibrations as a part of calibration check between the two methods. Figure 5.5 shows load measured after the two calibrations and the data shows a good agreement between the two calibration sets. The zero length thru line is then compared with respect to the calibrations. The after calibration reflection co-efficient of the thru line is similar and is well within 30dB through 65GHz for the two methods. The transmission co-efficient of the thru line in magnitude and phase also compare well with both the calibrations as seen in Figures 5.6, 5.7 and 5.8. 0 10 20 30 40 50 60Frequency [GHz] -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5Reflection Co-efficient (S11) [dB] TRL cSOLT Figure 5.5 Reflection Co-Efficient (S11 in dB) of Load Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 75

PAGE 95

0 10 20 30 40 50 60Frequency [GHz] -90 -80 -70 -60 -50 -40 -30Reflection Co-efficient (S11) [dB] TRLcSOLT Figure 5.6 Reflection Co-efficient of Thru Line Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 0 10 20 30 40 50 60Frequency [GHz] -0.02 -0.015 -0.01 -0.005 0 0.005 0.01Transmission Co-efficient (S21) [dB] TRLcSOLT Figure 5.7 Transmission Co-efficient of Thru Line Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 76

PAGE 96

0 10 20 30 40 50 60Frequency [GHz] -0.15 -0.1 -0.05 0 0.05 0.1 0.15Transmission Co-efficient (S21) [Deg] TRLcSOLT Figure 5.8 S21 Phase of Thru Line Measured after TRL and cSOLT Calibrations on ITT GaAs Microstrip Substrate at Center of Thru Reference. 5.3.3 Upper Bound Error Comparison ITT GaAs Microstrip Substrate The cSOLT calibration is compared with TRL, mSOLT and SOLT calibrations. The comparison is made with respect to TRL and cSOLT calibrations as the reference calibration in Figures 5.7 and 5.8. The fact the cSOLT method is good at lower frequencies and behaves close to TRL at higher frequencies is highlighted with error bound graph where all the calibrations are compared with respect to cSOLT as the reference calibration (Figure 5.8). Note in Figure 5.8 that the cSOLT compares with SOLT at low frequencies, as desired and retains a low error at low frequency compared to TRL. In contrast the low-frequency errors in the TRL reference cause all the calibrations to depict a high error at low frequencies in Figure 5.7. The absolute value of this rise in 77

PAGE 97

error at low frequencies will vary depending on various factors impacting the quality of the TRL calibration standards (skin depth of metals used, length of longest line, etc.). 0 10 20 30 40 50 60Frequency [GHz] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Maximum Upper Bound Error [Sij-S'ij] TRL vs cSOLTTRL vs mSOLTTRL vs SOLTTRL 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 Figure 5.9 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL as Reference on ITT GaAs Microstrip Substrate with Center of Thru Reference. The smaller graph plotted within the Figure 5.9 shows zooms into the low frequency range of the error bounds data. The TRL repeatability data and TRL versus mSOLT calibrations error bounds are high at these frequencies. The mSOLT technique depends on the TRL calibration measured data files for its definitions of standards. Thus the accuracy of the calibration follows with the accuracy of TRL which fails at the lower end. Note the raise in error at low frequency due to low frequency inaccuracies of the reference TRL calibration at lower frequencies. The cSOLT calibrations have minimum error at the lower frequencies when compared to the TRL and mSOLT calibrations. 78

PAGE 98

Figure 5.10 clearly shows that the error bound for the ideal SOLT and cSOLT calibrations is negligible at the lower end of frequencies due to the reason that SOLT calibrations are accurate at lower frequencies. With increased frequency, SOLT method often loses accuracy, since the standards may not be defined accurately enough. However, with the cSOLT method where the standards are accurately defined, the error when compared is reduced to a great extent. Note cSOLT matches SOLT at low frequency and TRL at high frequency, as desired for a broad-band calibration. The zoomed in graph for the lower frequencies in Figure 5.10 highlights the aforementioned. 0 10 20 30 40 50 60Frequency [GHz] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Maximum Upper Bound Error [Sij S'ij] cSOLT vs TRLcSOLT vs SOLTcSOLT vs mSOLTcSOLT Repeat 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 Figure 5.10 Upper Bound Error Difference between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL on ITT GaAs Microstrip Substrate with Center of Thru Reference. 79

PAGE 99

5.3.4 Device Measurements w.r.t TRL and cSOLT Calibrations The accuracy of the cSOLT calibration is verified with S-parameter measurements of devices available on the ITT GaAs microstrip substrate. Two capacitors of values 0.03pF and 0.3pF were measured. Figure 5.11 shows the reflection co-efficient of a 0.03pF capacitor measured with respect to 50 Z 0 corrected TRL and cSOLT calibrations. The vector difference (Magnitude(S11 TRL S11 cSOLT )) between the two calibrations is also plotted to the right of the S11 graph in Figure 5.11. The measurements show good agreement between the two calibrations over the frequency range. Figure 5.12 compares the transmission co-efficient of the capacitor measured with both the calibrations with the vector error difference in S21. It is clear from the plots that the difference between the two calibrations is less than 0.05dB in both the cases. 0 10 20 30 40 50 60Frequency [GHz] -5 -4.5 -4 -3.5 -3 -2.5 -2 -1.5 -1 -0.5 0 0.5Reflection Co-efficient (S11) [dB] cSOLT DataTRL Data 0 10 20 30 40 50 60Frequency [GHz] 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045Vector Difference in S11 [STRL11 ScSOLT11] mag(TRL S11-cSOLT S11) Figure 5.11 S11 of 0.03pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S11 from TRL and cSOLT (Right). 80

PAGE 100

0 10 20 30 40 50 60Frequency [GHz] -70 -60 -50 -40 -30 -20 -10 0Transmission Co-efficient (S21) [dB] cSOLT DataTRL Data 0 10 20 30 40 50 60Frequency [GHz] 0 0.01 0.02 0.03 0.04 0.05 0.06Vector Difference in S21 [STRL21 ScSOLT21] mag(TRL S21 cSOLT S21) Figure 5.12 S21 of 0.03pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S21 from TRL and cSOLT (Right). Figures Figure 5.13 and Figure 5.14 show the S-parameter comparison of another capacitor (0.3pF) with their respective vector error difference graphs. It is verified that the vector difference between the two calibrations is less than 0.04dB. It is clear from the graphs that illustrate the difference between S-parameters that it less than the upper bound graph plotted in the previous section as expected. 0 10 20 30 40 50 60Frequency [GHz] -20 -18 -16 -14 -12 -10 -8 -6 -4 -2 0 2Reflection Co-efficient (S11) [dB] TRL DatacSOLT Data 0 10 20 30 40 50 60Frequency [GHz] 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035Vector Difference in S11 [STRL11 ScSOLT11] mag(TRL S11-cSOLT S11) Figure 5.13 S11 of 0.3pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S11 from TRL and cSOLT (Right). 81

PAGE 101

0 10 20 30 40 50 60Frequency [GHz] -45 -40 -35 -30 -25 -20 -15 -10 -5 0 5Reflection Co-efficient (S21) [dB] TRL DatacSOLT Data 0 10 20 30 40 50 60Frequency [GHz] 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045Vector Difference in S21 [STRL21 ScSOLT21] mag(TRL S21cSOLT S21) Figure 5.14 S21 of 0.3pF Capacitor w.r.t TRL and cSOLT Calibrations (Left). Vector Error Difference between S21 from TRL and cSOLT (Right). 5.3.5 Accuracy Verification with Multiple Copies of Calibration Sets R DC Variability The relation between DC resistance of load and RF performance has been discussed in Chapter 3. Since the RF performance (load impedance) is directly dependent on the R DC of the load, a best practice strategy for calibrating over multiple dies on a whole wafer is suggested. 82 The short, open and complex load with thru equation models are established on one of the dies based on measured data after Z 0 corrected TRL calibration. It has been verified that the load is the one calibration standard in SOLT that varies from port to port and wafer to wafer. Chapter 3 illustrates good agreement between the measured and model when the DC resistance of the different loads in the models was adjusted. Thus the calibration process can be simplified by adjusting for the value of R DC in the load model and perform SOLT calibrations on the multiple dies available. This eliminates the need to model standards after Z 0 corrected TRL calibrations for each new die in the substrate;

PAGE 102

still not compensating on the accuracy of the calibrations. A cSOLT calibration is performed on another substrate whose DC resistance of the load is 50.8 on port 1 and 50.35 on port 2(R DC on the reference substrate is 49.97 on port 1 and 49.93 on port 2). The model parameters calculated from the reference substrate is retained for the die under test except for the DC resistance. The R DC in the load model is changed to 51.8 and 51.65 respectively. 0 10 20 30 40 50 60Frequency [GHz] 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14Maximum Upper Bound Error [Sij S'ij] cSOLT RepeatcSOLT vs TRL (cal die)cSOLT vs. TRL (diff die with DC correction)cSOLT vs. TRL (diff die with no DC correction) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 Figure 5.15 Upper Bound Error Difference for cSOLT Calibration vs. TRL on Multiple Die from ITT GaAs Microstrip Substrate using cSOLT as the Reference Calibration. The calibration is thus performed and is compared with that of a TRL calibration performed on the same substrate. It is also compared with the cSOLT vs. TRL comparison data from the reference die. From Figure 5.15, it is clear that the error bound shows very good agreement with the cSOLT vs. TRL data from the reference substrate 83

PAGE 103

up to about 45GHz. It is also observed that the difference between the two error bounds is just about 0.03 after 45GHz. 5.4 M/A-Com GaAs Microstrip Standards In order to verify accuracy of the improved SOLT calibration over the maximum frequency measurable at the lab, custom GaAs microstrip TRL and SOLT calibration standards were designed by the author for use over 0.04 110GHz. The design of the standards is discussed in Appendix B. The calibration die fabricated by M/A-Com have typical TRL standards and SOLT standards which are the half the length of thru. Apart from these standards, SOLT standards with the same foot print size as that of the thru have also been designed. This is included in the cal die to substantiate the best practice strategy proposed for calibration. The size of calibration substrates can be reduced to consume the least real estate on a production wafer along with minimizing the time involved for the calibrating multiple substrates. With the availability of a semi-automatic probe station, the standard measurements can be fully automated thereby reducing human errors involved during probe placement. It also makes it possible to achieve repeatable measurements. In this section the SOLT standards with half the thru lengths and same foot print size standards are both analyzed for maximum upper bound errors when compared to the TRL and other SOLT calibrations. However once the calibration standards were fabricated, a couple of problems were observed. There was parasitic coupling between lines and the reflects were resonating around 56GHz. The former problem was eliminated by scratching out the thru 84

PAGE 104

line which was placed between two long delay lines and caused some coupling between the lines. However the latter problem could not be resolved. This hindered to perform real broad-band calibrations between 50 and 70GHz. The results thus illustrated in the section are only plotted up to 50GHz. The graphs that show the effective dielectric constant, phase delay and characteristic impedance after the TRL calibration are plotted in Appendix E. 5.4.1 Half the Thru SOLT Standards M/A-Com Die The cSOLT calibration is carried out on the standards designed with half the length of the thru is measured at the center of thru reference plane. Z 0 corrected TRL calibration is used to model the standards as described in the previous sections. The measured data with the complex load and thru models are illustrated in Appendix C. The load has been well fabricated and hence shows little variation from its DC resistance with increase in frequency. The DC resistance of the measured loads is typically around 52. The standards are measured with respect to the cSOLT and TRL calibrations and plotted against each other as a part of calibration check. The Figure 5.16 Figure 5.19 shows the S-parameters of the calibration standards corresponding to both calibrations and the plots show good agreement between the two calibrations. 85

PAGE 105

0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -45 -40 -35 -30 -25 -20 -15S11 Magnitude [dB] TRL DatacSOLT Data Figure 5.16 Magnitude of S11 (dB) of Load Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05S11 Magnitude [dB] -14 -12 -10 -8 -6 -4 -2 0 2S11 Phase [Deg] TRL DatacSOLT Data Figure 5.17 Magnitude (dB) and Phase of S11 of Open Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 86

PAGE 106

0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25 0.3S11 Magnitude [dB] -200 -150 -100 -50 0 50 100 150 200S11 Phase [Deg] TRL DatacSOLT Data Figure 5.18 Magnitude (dB) and Phase of S11 of Short Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -90 -80 -70 -60 -50 -40 -30 -20 -10 0S11 Magnitude [dB] -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1S21 Magnitude [dB] TRL DatacSOLT Data Figure 5.19 Magnitude of S11 (dB) and S21 (dB) of Thru Standard Measured with Respect to TRL and cSOLT at Center of Thru Reference on M/A-Com GaAs Microstrip Substrate. 87

PAGE 107

5.4.1.1 Upper Bound Error between Calibrations Figure 5.20 shows the upper bound error between the improved SOLT with TRL and other SOLT calibrations. The results show a maximum difference of 0.01 between the repeatability TRL data and the plot for TRL vs. cSOLT data as the frequency increases. It is also clear from the inner graph of Figure 5.21 that the error bound at lower frequencies is the least for cSOLT when compared to the other calibrations. Thus the accuracy of the improved SOLT (cSOLT) calibration is demonstrated over a broad-band range of frequencies. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09Maximum Upper Bound Error [Sij S'ij] cSOLT vs. TRLmSOLT vs. TRLSOLT vs. TRLTRL Repeat 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 Figure 5.20 Upper Bound Error Difference between cSOLT, mSOLT, SOLT with Respect to TRL Calibration on M/A-Com GaAs Microstrip Substrate. 88

PAGE 108

0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] 0 0.01 0.02 0.03 0.04 0.05 0.06Maximum Upper Bound Error [Sij-S'ij] cSOLT vs. TRLcSOLT vs. mSOLTcSOLT vs. SOLTcSOLT Repeat 0 0.1 0.2 0.3 0.4 0.5 0.6 0 0.01 0.02 0.03 0.04 0.05 0.06 Figure 5.21 Upper Bound Error Difference between cSOLT, mSOLT, SOLT with Respect to cSOLT Calibration on M/A-Com GaAs Microstrip Substrate. 5.4.2 Equal Foot Print SOLT Standards The importance of the equal length (same foot prints) SOLT standards is highlighted in cases where space is an issue in the fabrication of bulk wafers with active and or passive devices. In device wafers, the area allocated for calibration standards might be of concern if it is a significant number. Both TRL and SOLT standards were included on the custom calibration die to enable modeling of the standards. These custom SOLT standards are also pivotal to support the proposed best practice calibration strategy for calibrating multiple dies. From the design, it was noted that the TRL standards occupied about 4.2 by 9cm while the SOLT standards with the same foot print size occupied just about 1.7 by 1.4cm. Since the cSOLT calibration requires a set of TRL 89

PAGE 109

standards to model the short, open, load and thru standards, one reference substrate with the required TRL can be fabricated. The other die on the wafer can just have the SOLT standards. Chapter 3 illustrates the performance variation of load from die to die and the relation between the RF performance of the load and DC resistance. It has been illustrated that the loads measured on the other die can be modeled accurately by adjusting the DC resistance of the respective loads. It was observed that the dc load resistance variation was less significant for the MA/Com standards fabricated for the present study as compared to the previously. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -45 -40 -35 -30 -25 -20 -15S11 Magnitude [dB] TRL DatacSOLT Data Figure 5.22 Magnitude of S11 (dB) of Load Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. In this section, the SOLT standards with the same (probe contact) foot print size are measured with respect to a probe tip TRL calibration. The model parameters that are estimated are thus used for the probe tip SOLT calibration. The standards are measured 90

PAGE 110

after calibration and it is verified that the S-parameters show good agreement with each other from Figure 5.22 Figure 5.25. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -0.35 -0.3 -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1S11 Magnitude [dB] -30 -25 -20 -15 -10 -5 0 5S11 Phase [Deg] TRL DatacSOLT Data Figure 5.23 S11 Magnitude and Phase of Open Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -0.2 -0.15 -0.1 -0.05 0 0.05 0.1S11 Magnitude [dB] 145 150 155 160 165 170 175 180S11 Phase [Deg] TRL DatacSOLT Data Figure 5.24 S11 Magnitude and Phase of Short Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. 91

PAGE 111

0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -0.1 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0S21 Magnitude [dB] -90 -80 -70 -60 -50 -40 -30 -20 -10 0S21 Phase [Deg] TRL DatacSOLT Data Figure 5.25 S21 Magnitude and Phase of Thru Standard Measured with Respect to TRL and cSOLT on M/A-Com GaAs Microstrip Substrate at Probe Tip Reference Plane. 5.4.2.1 Upper Bound Error between Calibrations It is very important that a calibration comparison is performed with these standards as this is instrumental in proving that the equal foot prints SOLT standards can be substituted for TRL calibration when modeled accurately. The Figure 5.26 shows the maximum upper bound when TRL and cSOLT calibrations referenced at the probe tip plane are compared with each other. The results as seen are very close to the TRL repeatability data up to about 45GHz. The error rises to 0.055 at 50GHz and this is because the open and short are resonating at around 47GHz (Figure 5.23 and Figure 5.24). The resonance could be because of coupling from the standards adjacent to the standards. Nevertheless, the equal foot prints SOLT standards are validated to predict a very low upper bound error when compared to the TRL repeatability data. 92

PAGE 112

0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] 0 0.01 0.02 0.03 0.04 0.05 0.06Maximum Upper Bound Error [Sij S'ij] cSOLT (equal foot prints) vs. TRLTRL Repeat Figure 5.26 Upper Bound Error between cSOLT (Equal Length SOLT Standards) and TRL Calibration Referenced at Probe Tips on M/A-Com GaAs Microstrip Substrate. 5.5 Chapter Summary The accuracy of the suggested complex model SOLT calibration is verified using calibration comparison method. The comparison is based on the error co-efficients calculated by a calibration algorithm. Improvement in accuracy is verified on two GaAs microstrip substrates custom designed at USF during 1999 and 2003. The upper bound graphs have been plotted with respect to both TRL and cSOLT calibrations. The error bounds w.r.t TRL defines the closeness of the calibration with TRL repeatability data and shows how well it can predict the error co-efficients at higher frequencies. The error bounds w.r.t cSOLT clearly shows that the algorithm is accurate at the lower end of frequencies. Example passive devices (capacitors) have been measured with respect to 93

PAGE 113

TRL and cSOLT calibrations on the ITT GaAs microstrip substrate. It has been illustrated that the S-parameters from the two calibrations compare well with each other. It is also verified that the vector difference between the S-parameters with respect to both the calibrations is less than the upper bound results plotted in the chapter. The variation of DC resistance from load to load is compensated in the load model and SOLT calibrations with adjusted R DC are performed on multiple dies. The accuracy of the calibrations is still observed to be comparable to TRL. Finally, equal length SOLT standards have been suggested as the best practice method for space conservative accurate calibrations. These standards are calibrated over a broad-band and tested with a typical TRL calibration. It is verified that maximum error between the equal foot print SOLT and TRL calibrations is very small in magnitude. Thus the accuracy of the cSOLT calibration has been well illustrated in the chapter. 94

PAGE 114

CHAPTER 6 COMPLEX SOLT (cSOLT) CALIBRATION VERIFICATION ON COMMERCIAL AND HYBRID (FR4) SUBSTRATES 6.1 Introduction In this chapter, the accuracy of cSOLT calibration is verified for commercial substrates from GGB and Jmicro and custom hybrid FR4 substrates. The CS5 substrate from GGB has CPW transmission lines and the Jmicro and custom FR4 substrates have microstrip line structures. The reference plane on the CS5 substrate is at the probe tips while that in the other two substrates is at the center of thru plane. 6.2 Hybrid FR-4 14mil Microstrip Substrate The FR-4 copper clad substrate is particularly chosen to illustrate the compatibility of the load model with surface mount chip resistors. The accuracy of cSOLT calibration is explored with a good load model fit with measured data. The cSOLT calibration result is also compared with mSOLT, SOLT and TRL calibrations. The effective dielectric constant of FR-4 with respect to the thickness (14mil) and width of the line is determined to be 3.3. This is a smaller value of effective dielectric constant when compared to that of GaAs (8.5) and Alumina (6.45) discussed in the presented work 95

PAGE 115

and thus explores the validity of a wide range of substrates for the complex load and thru models. The calibrations are referenced to the center of thru plane on the substrate. The calibration standards were measured after a Z 0 corrected center of thru TRL calibration and fit to the complex models as discussed in Chapter 3. There were a few anomalies observed after the TRL calibration. It is attributed to the inconsistent placements of the vias in the probe pads of the calibration standards and/or the variation of line width which is significant in microstrip calibrations. The etch away method used to fabricate the hybrid FR4 boards may some times result in wider tolerances on the line widths. The TRL measured data thus showed some discrepancies after 15GHz. The calibrations were still performed up to 18GHz. 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04Reflection Co-efficient (S11) [dB] -14 -12 -10 -8 -6 -4 -2 0Reflection Co-efficient Phase (S11) [Deg] cSOLT DataTRL Data Figure 6.1 S11 Magnitude and Phase of Open Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 96

PAGE 116

A cSOLT calibration was then performed with the model parameters established with the TRL calibration. As a part of calibration verification, the standards are measured and plotted with respect to TRL and cSOLT calibrations (Figure 6.1 6.4). It is interesting to note that for most of these graphs the cSOLT calibrations remain better behaved at high frequencies and does not show the problems apparent in the TRL data above 14GHz. Another interesting observation from Figures 6.1 and 6.2 is that the measurements after cSOLT calibration also do not show the anomalies evident in TRL at low frequencies. 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -0.1 -0.05 0 0.05 0.1 0.15 0.2Reflection Co-efficient (S11) [dB] -200 -150 -100 -50 0 50 100 150 200Reflection Co-efficient Phase (S11) [Deg] cSOLT DataTRL Data Figure 6.2 S11 Magnitude and Phase of Short Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 97

PAGE 117

0 2 4 6 8 10 12 14 16 18Frequency [GHz] -60 -50 -40 -30 -20 -10 0Reflection Co-efficient (S11) [dB] cSOLT DataTRL Data Figure 6.3 Magnitude of S11 for Load Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -80 -60 -40 -20 0 20Reflection Co-efficient (S11) [dB] -0.008 -0.006 -0.004 -0.002 0 0.002 0.004Transmission Co-efficient (S21) [dB] cSOLT DataTRL Data Figure 6.4 Magnitude of S11 and S21 of Thru Measured after cSOLT and TRL Calibration at Center of Thru Reference on 14mil FR4 Microstrip Substrate. 98

PAGE 118

6.2.1 Upper Bound Error between Calibrations The cSOLT calibration is compared with TRL, mSOLT and convetional SOLT calibrations to demonstrate the improvement in accuracy. As illustrated for the GaAs substrates in the previous chapter, the comparison graphs are referenced to both cSOLT and TRL calibrations. The upper bound error graph that is referenced to cSOLT calibration data highlights the low frequency accuracy that is retained to achieve broad-band accuracy with SOLT calibrations. This is the case with mSOLT calibrations as the definitions of the standards depend on the TRL measured files which has discrepancies at lower frequencies. Figure 6.5 shows the maximum error between the calibrations referenced to TRL calibration. 0 2 4 6 8 10 12 14 16 18 20Frequency [GHz] 0 0.2 0.4 0.6 0.8 1 1.2Maximum Upper Bound Error [Sij S'ij] cSOLT vs. TRLmSOLT vs. TRLSOLT vs. TRLTRL Repeat 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.02 0.04 0.06 0.08 0.1 0.12 Figure 6.5 Upper Bound Error between cSOLT, mSOLT, SOLT with Respect to TRL Calibration on 14mil FR4 Microstrip Substrate. 99

PAGE 119

0 2 4 6 8 10 12 14 16 18 20Frequency [GHz] 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1Maximum Upper Bound Error [Sij S'ij] TRL vs. cSOLTmSOLT vs. cSOLTSOLT vs. cSOLTcSOLT Repeat 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 0.1 Figure 6.6 Upper Bound Error between cSOLT, mSOLT, SOLT with cSOLT Calibration on 14mil FR4 Microstrip Substrate. It is clear from the zoomed in graph of Figure 6.6, cSOLT calibration and SOLT calibrations have minimum error at the lower frequencies. The TRL and mSOLT calibrations have some measurement discrepancies at those frequencies that reflect in the comparison graphs. It also seen that the error bound for TRL versus cSOLT does not start from zero value but at 0.02. This is due to the aforementioned problems with low frequency TRL calibration. 100

PAGE 120

6.2.2 Device Measurements w.r.t TRL and cSOLT Calibrations The accuracy of the calibrations is verified by measuring a few 2-port capacitors. Figures 5.19 and 5.20 show the S-parameters of 0.2pF capacitor measured with respect to cSOLT and TRL calibrations. The data on the effective dielectric constant, phase delay and characteristic impedance after calibration are illustrated in Appendix E. The Figures 6.7, 6.8 and 6.9 show S-parameters of a 0.2pF capacitor measured and the vector error difference between the cSOLT and TRL calibrations. It is clear from the vector error graphs that the difference in S-parameters between the TRL and cSOLT is less than TRL. Figure 6.10 shows the S-parameters of a 0.4pF capacitor measured with respect to the aforementioned three calibrations. 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -14 -12 -10 -8 -6 -4 -2 0 2S11 of 0.2pF capacitor [dB] -45 -40 -35 -30 -25 -20 -15 -10 -5 0S21 of 0.2pF capacitor [dB] cSOLT DataTRL Data Figure 6.7 S11 and S21 of 0.2pF Capacitor w.r.t cSOLT and TRL Calibrations Referenced at the Center of Thru on 14mil FR4 Microstrip Substrate. 101

PAGE 121

0 2 4 6 8 10 12 14 16 18Frequency [GHz] 0 0.002 0.004 0.006 0.008 0.01 0.012 0.014 0.016Vector Difference in S11 [STRL11 ScSOLT11] mag(TRL S11 cSOLT S11) 0 2 4 6 8 10 12 14Frequency [GHz] 0 0.005 0.01 0.015 0.02 0.025Vector Difference in S21 [STRL21 ScSOLT21] mag(TRL S21 cSOLT S21) Figure 6.8 Vector Difference between the S-parameters of 0.2pF Capacitor Measured on 14mil FR4 Microstrip Substrate with Respect to cSOLT and TRL Calibrations. 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -1.2 -1 -0.8 -0.6 -0.4 -0.2 0 0.2S11 of 0.2pF capacitor [dB] cSOLT DataTRL Data Figure 6.9 S11 of 0.2pF Capacitor When Port 2 is Shorted during Simulation w.r.t cSOLT and TRL Calibrations Referenced at the Center of Thru. 102

PAGE 122

0 2 4 6 8 10 12 14 16 18Frequency [GHz] -14 -12 -10 -8 -6 -4 -2 0 2S11 of 0.2pF capacitor [dB] -45 -40 -35 -30 -25 -20 -15 -10 -5 0S21 of 0.2pF capacitor [dB] cSOLT DataTRL Data Figure 6.10 S11 and S21 of 0.4pF Capacitor Measured with respect to TRL and cSOLT Calibrations. 6.3 GGB CS5 Calibration Substrate The GGB CS5 calibration substrate used for accuracy verification of the cSOLT calibration is 635um thick substrate with CPW transmission lines. This commercial substrate is generally used in cases where calibration standards are not available for DUT characterization. The reference plane in these cases is at the probe tip (at the point the probes contact the substrate). This makes it essential that the standards are modeled accurately between the probe contact and DUT. It is also noteworthy that the importance of the thru line model comes into effect with such type of calibrations as the thru line is non-zero length line that has attenuation losses and phase for transmission. The measured data with the respective model fits after a probe tip TRL calibration on the GGB CS5 substrate have been discussed in Chapter 3. The effective dielectric 103

PAGE 123

constant, phase delay and characteristic impedance obtained with the multi-line TRL calibration are presented in Appendix E. It was observed that since the load is well fabricated and laser trimmed, the measured data after a probe tip TRL calibration showed little variation from its DC resistance for the entire frequency band of operation (DC 65GHz). The importance of the thru line equation comes into the picture when a non-zero length of thru is under consideration, which is the case of the probe tip calibrations. Since the standards are designed in such a way that there can be a true probe tip calibration, the comparison involved calibrations referenced at the probe tips. The open and short standards are modeled with ideal capacitance and inductance with a short piece of transmission line when the reference plane is at the probe tips (in this case length of line is negligible). The load standard is modeled with the complex model illustrated in Chapter 3. The thru line equations include the losses in a transmission line and thus predict the propagation constant of the thru line. The complex models are used to generate the standard definitions file for calibration. Once the definitions file is generated, the SOLT standards are measured for error calculation. The measurements on the CS5 are performed with Wiltron 360B. The standards were re-measured after TRL and cSOLT calibrations as a part of calibration verification. The comparison between the calibrations in terms of measured standards after calibration is illustrated in Appendix E. 104

PAGE 124

0 10 20 30 40 50 60Frequency [GHz] 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2Error Bounds [S'ij Sij] mSOLT vs. TRLcSOLT vs. TRLSOLT vs. TRLTRL Repeat 0 0.1 0.2 0.3 0.4 0.5 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Figure 6.11 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL on GGB CS5 Substrate. For calibration comparison purposes, an mSOLT and SOLT calibrations were performed. Figures 6.11 and 6.12 show the maximum error bound when cSOLT, mSOLT and ideal SOLT calibrations are compared with TRL and cSOLT algorithm. It is clear from the figures that the error bound for the between TRL and cSOLT is very close to the TRL repeatability data. Due to the fact the TRL fails at lower frequencies (in this case around 4GHz), the error at those frequencies seems to higher. Note that mSOLT calibration method faces the same problems of TRL at lower frequencies. The graph also shows the front panel SOLT calibrated error bound that has the maximum bound, since the models do not represent the actual measured data. From Figure 6.11, it can be verified 105

PAGE 125

that the complex models for load and thru that track well with the high frequency data, accurate calibrations can be obtained. 0 10 20 30 40 50 60Frequency [GHz] 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09Error Bounds [S'ij Sij] TRL vs. cSOLTmSOLT vs. cSOLTSOLT vs.cSOLTcSOLT Repeat 0 0.2 0.4 0.6 0.8 1 0 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 Figure 6.12 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT Calibrations with Respect to TRL on GGB CS5 CPW Substrate. 6.4 Jmicro 5mil Microstrip Substrate The accuracy of the cSOLT calibration was finally verified on another commercially available Jmicro 5mil thick microstrip calibration set. The dielectric of the Alumina substrate is 6.41. The standards measured as a part of calibration check are illustrated in Appendix E. The maximum error bounds between the calibrations of concern are compared as in the other substrates. Figures 6.13 and 6.14 show the comparison graphs with both TRL and cSOLT as reference data respectively. The error 106

PAGE 126

bound between the cSOLT and TRL is very close to negligible in this case. It is clear from the graphs that the error bound of cSOLT versus TRL is minimum and comparable to the calibration repeatability data. 0 5 10 15 20 25 30 35 40Frequency [GHz] 0 0.05 0.1 0.15 0.2 0.25 0.3Upper Bound Error [Sij S'ij] cSOLT vs. TRLmSOLT vs. TRLSOLT vs. TRLTRL Repeat 0 0.1 0.2 0.3 0.4 0.5 0 0.05 0.1 0.15 0.2 0.25 0.3 Figure 6.13 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT with Respect to TRL at the Center of Thru Reference on Jmicro 5mil Microstrip Substrate. 107

PAGE 127

0 5 10 15 20 25 30 35 40Frequency [GHz] 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2Upper Bound Error [Sij S'ij] cSOLT RepeatSOLT vs. cSOLTTRL vs. cSOLTmSOLT vs. cSOLT 0 0.1 0.2 0.3 0.4 0.5 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 Figure 6.14 Upper Bound Error between TRL, cSOLT, mSOLT and SOLT with Respect to cSOLT at the Center of Thru Reference. 6.5 Chapter Summary In this chapter, the accuracy of cSOLT has been verified with a hybrid FR4 substrate and two commercial substrates, GGB CS5 and Jmicro 5mil calibration substrates. Comparison of cSOLT calibration with TRL, mSOLT and SOLT methods clearly indicate that error bound for cSOLT is close to TRL at higher frequencies and is also accurate at lower frequencies for all the cases. The Z 0 correction in the 14mil FR4 substrate is verified to be inaccurate which could be attributed to fabrication of vias or calibration line width variation. Herein, the cSOLT measured results of the devices (capacitors) are compared with both Z 0 corrected and non-Z 0 corrected TRL calibrations. 108

PAGE 128

It has been illustrated that the capacitor measurements with respect to cSOLT and TRL (no Z 0 correction) compare well with each other. It has also been illustrated that since the on-chip resistor which is not well behaved in terms of load impedance over the frequency interest, the conventional SOLT had maximum error bound when compared to other calibrations. This highlights the fact that with accurate modeling of the load standard, a conventional SOLT calibration can be closely made as accurate as TRL calibrations. On the contrary, the GGB CS5 substrate has very well defined loads and hence there is minimum difference between SOLT and cSOLT. The difference observed is mainly attributed to the complex thru equation that models the losses in the transmission lines when the calibration involves a non-zero length thru. Thus the complex load and thru models proposed for the calibration standards in SOLT calibration increase the accuracy of the calibration over a broad-band range of frequencies. 109

PAGE 129

CHAPTER 7 CONCLUSIONS AND RECOMMENDATIONS 7.1 Conclusions The focus of the thesis is on broad-band accurate calibrations with a compact set of standards. The accuracy of conventional short-open-load-thru (SOLT) calibration is increased with the use of more complex load and thru models in place of the series RL model for the load and ideal lossless line for the thru. The significance of the utilized technique is highlighted by illustrating the advantages and disadvantages of the available methods. Calibration algorithms like TRL, ideal SOLT, LRM/ LRRM and mSOLT are explained briefly. The complex models for load and thru standards suggested are verified with illustrations that compare measured data and the model over a broad-band frequency range 0.04-65GHz for planar microstrip and CPW calibration standards realized on multiple substrates. The variation of the DC resistance of the load, between substrates and even ports is illustrated and the capability of the complex load model to account for the variation in the RF performance is also presented. This is utilized to demonstrate the fact that SOLT calibrations can be performed on multiple die without having to model the load variation on each individual die or pair of load standards. 110

PAGE 130

A LabVIEW program begun by a prior USF student has been improved by the author to integrate the complex models for calibration standards in the SOLT algorithm, and to incorporate a flexible calibration comparison program. The program (called BullCal V2.0) is compatible with two VNAs Wiltron 360B and Anritsu Lightning. The comparison algorithm compares two similar calibrations for the difference in error co-efficients. The error co-efficients are compared and the upper error bound data is generated. The program is very useful for comparing TRL with cSOLT for verifying accuracy of the cSOLT calibration and is also useful for comparing upper bounds between any two VNA calibrations in general. The improved SOLT calibration is performed on five different substrates and it has been illustrated that the results are very close to TRL calibration at higher frequencies. The advantage of the cSOLT method is that the calibration is accurate at lower frequencies where TRL and mSOLT fail and at the same time is able to provide a close match when compared to TRL at higher frequencies. Example passive devices have been measured to demonstrate the match between the two calibrations. The cSOLT calibration is performed at both the center of thru and probe tip reference planes over a broad-band frequency range from 0.04 65GHz. Finally, a custom set of calibration standards have been designed on 100um thick GaAs with microstrip transmission lines. The custom standards included TRL, half the thru SOLT and equal foot print SOLT standards. Equal foot print SOLT standards have been designed to validate the fact that with accurate complex models of the load and thru standards, SOLT calibrations can be performed on multiple wafers without having to 111

PAGE 131

model for the load variations that exist between substrates. The upper bound graphs plotted with this set of standards are indicative of broad-band accuracy. It has been shown that the accuracy of the cSOLT calibrations improve with the load and thru modeling of the standards. The main advantages to this method are that with the compact set of space conservative standards, probing is very easy and less time consuming and still highly accurate. Availability of a semi automatic probing system ensures more repeatable measurements with the equal foot print standards. The calibration algorithm can also be used for one port calibrations, which is not possible with TRL or LRM calibration techniques. Finally, broad-band accuracy can be achieved when compared to other methods where the compromise is either at the lower or higher frequency ranges. 7.2 Recommendations for Future Work The improved cSOLT calibration has been verified for it accuracy on CPW and microstrip substrates that are typical transmission line designs. A recommendation for future work is to test the complex load and thru models on non-typical transmission lines which include CPW lines with narrow slot widths and signal line, other transmission line topologies or substrates with high/low resistivities. The test may reveal the necessity to adopt for more complex equations for the thru standard. The cSOLT calibration algorithm can thus be performed on any type of on-wafer designs. The thesis herein focuses on 2-port on-wafer calibrations. Another recommendation is to implement the algorithm for 3 or more N-port network analyzer 112

PAGE 132

calibrations. Multiport/ Differential measurements are of growing interest with the growth of RFIC designs. TRL and LRM calibrations are the most used calibrations currently for multiport measurements and the design of multiport TRL standards makes it more difficult for calibration apart from its low frequency problem discussed in the thesis. Thus a four port SOLT calibration algorithm can make the calibration process much more simplified. The cSOLT calibration can be performed on the Wiltron 360B and Anritsu Lightning VNAs currently. The addition of the other popular VNAs like the HP8510 and HP8753 can help to obtain broad-band accurate calibrations with any network analyzer. Finally, the complex models can be extended into other calibration routines like the LRM and SOLR [33]. The models can help reduce the error factors in the calibrations and thus help to perform more accurate broad-band calibrations. 113

PAGE 133

REFERENCES [1] Glenn F. Engen, Cletus A. Hoer, Thru-Reflect-Line: An Improved Technique for Calibrating the Dual Six-port Automatic Network Analyzer, IEEE Transactions on Microwave Theory and Techniques, Vol. 27, October 1979. [2] Roger B. Marks, A Multiline Method of Network Analyzer Calibration, IEEE Transactions on Microwave Theory and Techniques, Vol. 39, No 7, July 1991. [3] Donald C. DeGroot, Kristopher L. Reed, Jeffrey A. Jargon, Equivalent Circuit Models for Coaxial SOLT Standards, 54 th ARFTG Conference Digest pp103 -115, December 1999. [4] H. J. Eul, B. Schiek, Thru-Reflect-Match: One Result of a Rigorous Theory for De-embedding and Network Analyzer Calibrations, Proc. 18 th European Microwave Conference, pp 909-914, September 1988. [5] M. Imparato, T. Weller, and L. Dunleavy, On-wafer calibration using space-conservative (SOLT) standards, 1999 IEEE MTT-S Intl Microwave Symposium, June 1999. [6] P. Kirby, Improved Vector Network Analyzer Calibrations utilizing Lumped Element Standards, Masters Thesis, University of South Florida. [7] On-wafer Vector Network Analyzer Calibration and Measurements, Application Note, Cascade Microtech. [8] David M. Pozar, Microwave Engineering, 2 nd edition, John Wiley & Sons, Inc. [9] Doug Rytting, Network Analyzer Error Models and Calibration Methods, 54 th ARFTG Conference short notes, December 2000. [10] Applying Error Correction to Network Analyzer Measurements, Agilent AN1287-3, Application note. [11] Anthony Lord, Advanced RF Calibration Techniques, Cascade Microtech. 114

PAGE 134

[12] C. A. Hoer, Calibrating Two Six-port Reflectometers with an Unknown Length of Precision Transmission Line, 1978 IEEE Transactions on Microwave Theory and Techniques, pp 176-178. [13] R.A. Speciale, N.R. Franzen, Super TSD, A Generalization of the TSD Network Analyzer Procedure, Covering n-port Measurements with Leakage, Microwave Symposium Digest, MTT-S International, Volume 77 Issue: 1, Jun 1977, Page: 114 117. [14] Glenn F. Engen, Calibration of arbitrary six-port junction for measurement of active and passive circuit parameters, IEEE Transactions Instrumentation Measurement, Vol. 22, pp 295-299, December 1973. [15] R.B. Marks, D.F. Williams, Characteristic Impedance Determination Using Propagation Constant Measurement, IEEE Microwave and Guided Wave Letters, Vol 1, No 6, June 1991. [16] Roger B. Marks, A Multiline Method of Network Analyzer Calibration, IEEE Transactions on Microwave Theory and Techniques, Vol. 39, No 7, July 1991. [17] Donald C. DeGroot, Jeffrey A. Jargon, Roger B. Marks, Multiline TRL Revealed, 60 th ARFTG Conference Digest, pp 131-155, December 2002. [18] Applying the 8510 TRL Calibration for Non-Coaxial Measurements, Agilent Product Note 8510-8A. [19] Andrew Davidson, Eric Strid, Keith Jones, Achieving Greater On-wafer S-parameters Accuracy with the LRM Calibration Techniques, Cascade Microtech. [20] Dylan F. Williams, Roger B.Marks, LRM Probe tip Calibrations using Non-Ideal Standards, IEEE Transactions on Microwave Theory and Techniques, Vol. 43, No 2, February 1995. [21] Andrew Davidson, Eric Strid, Keith Jones, LRM and LRRM Calibrations with Automatic Determination of Load Inductance, 36 th ARFTG Conference Digest, November 1990. [22] National Instruments Corporation, LabVIEW TM 11500 N Mopac Expwy, Austin, TX 78759. [23] Agilent Advanced Design System (ADS) Software, 395 Page Mill Rd., P.O. Box #10395, Palo Alto, CA 94303 [24] D.K. Walker, D.F. Williams, J.M. Morgan, Planar Resistors for Probe Station Calibration, 40 th ARFTG Conference Digest, pp 1-9, Dec 1992. 115

PAGE 135

[25] S. Padmanabhan, P. Kirby, J. Daniel, L. Dunleavy, Accurate Broadband on-wafer SOLT calibrations with Complex Load and Thru Models, 61 st ARFTG Conference Digest, June 2003. [26] P. Kirby, L. Dunleavy, T. Weller, The Effect of Load Variations on On-wafer Lumped Element Based Calibrations, 54 th ARFTG Conference, Dec 1999. [27] GGB Industries, P.O.Box 10958, Naples FL 34101. [28] Brian C. Wadell, Transmission Line Design Handbook, Artech House, Inc. [29] D. F. Williams, R. B. Marks, A. Davidson, Comparison of On-wafer Calibrations, 38 th ARFTG Conf. Digest, pp 68-71, Dec 1991. [30] R. B. Marks, D. F. Williams, A Universal Waveguide Circuit Theory, submitted to J. Res. National Inst. Stand. Technology. [31] R. B. Marks, J. A. Jargon, John R. Juroshek, Calibration Comparison Method for Vector Network Analyzers, 48 th ARFTG Conf. Digest, pp 38-45, Dec 5-6 1996. [32] D.F. Williams, R.B. Marks, Transmission Line Capacitance Measurement, IEEE Microwave and Guided Wave Letters, Vol 1, No 9, Sept 1991. [33] Ferrero, U. Pisani, Two-port Network Analyzer Calibration Using Unknown Thru, IEEE Microwave and Guided Wave Letters, Vol.2, No 12, December 1992. [34] Jmicro Technology Inc., 3744 NW Bluegrass Pl., Portland OR 97229. [35] Modelithics Inc., 13101 Telecom Drive, Suite 105, Tampa, FL 33637. 116

PAGE 136

APPENDICES 117

PAGE 137

Appendix A: Verification Substrates for Accuracy of CSOLT Calibration In this appendix the different substrates that have been used in the work to verify and validate the accuracy of the improved SOLT calibration are illustrated. The custom calibration standards designed on GaAs and fabricated by M/A-Com in 2003 is discussed in Appendix B. A.1 ITT GaAs Microstrip Substrate The ITT GaAs microstrip substrate was designed by Mike Imparato [1] in 1999. The substrate is 100um thick with an effective dielectric constant in this case is 8.125 (Dielectric Constant 12.9). The line width of the calibration and other structures on the wafer is 70um. The calibration and device structures that have been used for the work is listed below the figure A.1. Table A.1 List of Calibration Structures used for ITT GaAs Calibrations. #No Calibration Structure #No Calibration Structure 1 1764 um Delay 2 1239 um Delay 3 955.2 um Delay 4 50 ohm 500 um Thru 5 Short Reflect 6 Open Reflect 24 0.03 pF capacitor 25 0.3 pF capacitor 118

PAGE 138

Appendix A (Continued) Figure A.1 Layout of the ITT GaAs Microstrip Substrate [5]. 119

PAGE 139

Appendix A (Continued) A.2 Jmicro 5mil Calibration Substrate The Jmicro 5mil thick microstrip calibration substrate on Alumina has an effective dielectric constant of 6.4. There are three sets of calibration structures that can be used for the 20GHz, 40GHz or 80GHz bandwidths. The 80GHz frequency band structures have been used for the work. Figure A.2 Layout of Jmicro 5mil Calibration Substrate with Calibration Structures for up to 20GHz, 40GHz and 80GHz [34]. 120

PAGE 140

Appendix A (Continued) Table A.2 List of Calibration Structures used for Jmicro Calibrations. #No. Calibration Structures #No. Calibration Structures 7A Load 8A Short 9A Open25 10D Line0 6A Line5 10C Line10 6B Line15 11C/D Line37 A.3 GGB CS5 Substrate The GGB CS5 calibration substrate on Alumina is popularly used for calibrating devices which do not have calibration structures in its design. The 635um thick CPW substrate has an effective dielectric constant of 5.1 with line width of 50um and slot width of 25um. Table A.3 List of Calibration Structures used for GGB CS5 Calibrations. #No. Calibration Structures #No. Calibration Structures 51 Open 61 Short 71 Load 81 Thru 100 Line 500um 101 Line 1000um 102 Line1500um 10 Line 6600um 121

PAGE 141

Appendix A (Continued) Figure A.3 Layout of GGB CS5 Calibration Substrate [27]. A.4 FR4 14mil Microstrip Substrate The FR4 14mil thick hybrid board has microstrip lines with an effective dielectric constant of 3.3. 122

PAGE 142

Appendix A (Continued) Figure A.4 Layout of the hybrid FR4 14mil microstrip substrate [35]. Table A.4 List of Calibration Structures used for 14mil FR4 Calibrations. #No. Calibration Structures #No. Calibration Structures 1 Open 2 Thru 3 Line (3.7GHz) 4 Line (6 GHz) 5 Line (8 GHz) 6 Line (10 GHz) 7 Short 8 Load 123

PAGE 143

Appendix B: Design of Broad-band GaAs Calibration Standards In order to facilitate calibrations over a broad-band frequency range (0.04-110GHz), a set of custom calibration standards with microstrip type transmission method have been designed. The design incorporated TRL, half the thru SOLT and equal foot print SOLT standards. The significance of the equal foot print SOLT standards has been well elaborated in the chapters. The design has been fabricated by M/A-Com on a 100um thick GaAs substrate with effective dielectric constant of 8.5. The TRL standards have five delay lines that are quarter wavelength at frequencies that enable measurements covering the entire bandwidth. The length of the delay lines were calculated using, efffc* where f is the frequency at which the line is quarter wave length c is the speed of light (m/sec) and eff is the effective dielectric constant. The length of the thru line was set to be 500um. Thus the total line lengths of the delay lines is L = L thru + L /4 Table B.1 lists the different line lengths chosen with the frequencies at which the respective lengths are quarter wavelength. Since TRL requires longer lines to envelop lower frequency bandwidths, an 8174um line has been added to the design. 124

PAGE 144

Appendix B (Continued) Table B.1Line Lengths and Quarter Wavelengths. Line Lengths [um] Quarter Wavelength Frequencies [GHz] 8174 3.3 4170 7.2 2150 15.6 1355 30 867 70 The SOLT calibration standards were designed with both half the thru length and equal foot print lengths. The standards were placed on the design keeping in mind any cross talk or coupling that can occur if standards are in close proximity. Figure B.1 shows the layout of the calibration standards that has been fabricated. Though the design of calibration standards was laid out with great care to prevent any coupling, the fabricated calibration wafer showed more than one case of coupling between lines. The delay lines were not far enough from each other when placed side by side resulting in coupling. This reduced the maximum the frequency of operation down to 50GHz. A resonance at around 57GHz and 63GHz is found and it is because of the thru placed between the two long lines. 125

PAGE 145

Appendix B (Continued) Compact cSOLT Calibration Set Figure B.1 Layout of TRL and SOLT Calibration Standards on 100um Thick GaAs Substrate. 126

PAGE 146

Appendix C: Complex Load and Thru Model Data Jmicro 5mil & M/A-Com GaAs Substrates The appendix presents the load and thru standards measured on the Jmicro 5mil and M/A-Com with their respective complex model data. The complex load and thru models have been explained in detail in Chapter 3. The models are verified on five different substrates. The ITT GaAs microstrip, GGB CS5 and 14mil FR4 substrates are illustrated in the chapter and the results for the other are presented in this appendix. A good agreement between the measured data and model is found in all the figures listed. C.1 Complex Load Model Verification 0 5 10 15 20 25 30 35 40Frequency [GHz] 49 49.5 50 50.5 51 51.5 52 52.5Real Impedance [] Measured DataLoad Model Figure C.1 Real Impedance of Measured Load Vs. Complex Load Model on Jmicro 5mil Microstrip Substrate at Center of Thru Reference. 127

PAGE 147

Appendix C (Continued) 0 5 10 15 20 25 30 35 40Frequency [GHz] -2 0 2 4 6 8 10 12Imaginary Impedance [] Measured DataLoad Model Figure C.2 Imaginary Impedance of Measured Load vs. Complex Load Model on Jmicro 5mil Microstrip Substrate at Center of Thru Reference. Table C.1 Tabulation of Load Model Parameters and their Values from Simulation for Load Measured on Jmicro 5mil Substrate. Parameters Significance Values Rdc DC Resistance of load 49.6 L Series Inductance 49.35pH C Capacitance from signal to ground 6.4fF Cg Gap capacitance 1fF Lvia Via Inductance 11.4pH Table C.2Tabulation of Load Model Parameters and their Values from Simulation for Load Measured on M/A-Com GaAs Microstrip Substrate. Parameters Significance Values Rdc DC Resistance of load 52.62 L Series Inductance 57.14pH C Capacitance from signal to ground 15.813fF Cg Gap capacitance 47.7fF Lvia Via Inductance 153.04pH 128

PAGE 148

Appendix C (Continued) 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] 52.5 53 53.5 54 54.5 55 55.5Real Impedance [] Measured DataLoad Model Figure C.3 Real Impedance of Measured Load vs. Complex Load Model on M/A-Com 4mil Microstrip Substrate at Center of Thru Reference. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -2 0 2 4 6 8 10 12 14Imaginary Impedance [] Measured DataLoad Model Figure C.4 Imaginary Impedance of Measured Load vs. Complex Load Model on M/A-Com 4mil Microstrip Substrate at Center of Thru Reference. 129

PAGE 149

Appendix C (Continued) 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] 52 52.5 53 53.5 54 54.5 55Real Impedance [] Measured DataLoad Model Figure C.5 Real Impedance of Measured Load vs. Complex Load Model for Equal Foot Print Load Standard on M/A-Com 4mil Microstrip Substrate at Center of Thru Reference. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -2 0 2 4 6 8 10 12Imaginary Impedance [] Measured DataLoad Model Figure C.6 Imaginary Impedance of Measured Load vs. Complex Load Model for Equal Foot Print Load Standard on M/A-Com 4mil Substrate at Center of Thru Reference. 130

PAGE 150

Appendix C (Continued) C.2 Complex Thru Model Verification 0 5 10 15 20 25 30 35 40Frequency [GHz] -90 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35Reflection Co-efficient (S11) [dB] Measured DataThru Model Figure C.7 S11 in dB for Measured Data vs. Thru Model for 1168um Delay Line on Jmicro 5mil Substrate at Center of Thru Reference. 0 5 10 15 20 25 30 35 40Frequency [GHz] -0.18 -0.16 -0.14 -0.12 -0.1 -0.08 -0.06 -0.04 -0.02 0Transmission Co-efficient (S21) [dB] Measured DataThru Model Figure C.8 S21 in dB for Measured Data vs. Thru Model for 1168um Delay Line on Jmicro 5mil Substrate at Center of Thru Reference. 131

PAGE 151

Appendix C (Continued) 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -100 -90 -80 -70 -60 -50 -40 -30 -20S11 Magnitude [dB] TRL Measured DataThru Model Figure C.9 S11 Magnitude of Measured Data vs. Thru Model for 500um Line on M/A-Com GaAs Substrate at Probe Tip Reference. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -0.1 -0.09 -0.08 -0.07 -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0S21 Magnitude [dB] -90 -80 -70 -60 -50 -40 -30 -20 -10 0S21 Phase [Deg] TRL Measured DataThru Model Figure C.10 S21 Magnitude and Phase of Measured Data vs. Model for 500um Thru on M/A-Com GaAs Substrate at Probe Tip Reference. 132

PAGE 152

Appendix D: BullCal V2.0 Implementation of cSOLT and Cal Compare with LabVIEW This appendix gives a step by step procedure to perform a cSOLT calibration and to generate an upper bound error graph with CalCompare. D.1 cSOLT Calibration Program Measure and Model Standards The SOLT standards are measured after a Z 0 corrected TRL calibration. The measured standards are fit to complex models illustrated in Chapter 3. The optimization of the model with measured data is done using Agilent ADS TM [1]. These model parameters are used to define the standards in a cSOLT calibration. The following Figure D.1 shows BullCals main window of operation. Figure D.1 Screen Capture of the Main Screen in cSOLT Program to Perform Complex-SOLT Calibrations. 133

PAGE 153

Appendix D (Continued) Edit/ View Calibration Definitions The model parameters are input as definitions to the SOLT standards in this section. Buttons for short, open, load and thru standards are provided. The green lights below the buttons indicate if the standards are defined with a model or data file. TRL beased measured data files are used when mSOLT calibrations are performed with the program. Figure D.2 Screen Capture of Edit/View Calibration Standard Definitions Section. Open and Short Definitions The open and short definitions are simple capacitance and inductance models and the definitions are entered in the respective dialog boxes (Figures D.2 and D.3). There is also an option to enter a length of transmission line with impedance Z 0 when the reference of the calibration is not at the center of thru. This feature is available for all the four standard models. 134

PAGE 154

Appendix D (Continued) Figure D.3 Dialog Box for Short Standard Definitions at Port 1 and Port 2. Figure D.4 Dialog Box for Open Standard Definitions at Port 1 and Port 2. Load and Thru Standards Figures D.5 and D.6 are the editing windows for the load and thru standards where the model parameters provided by the ADS optimizations are entered. It is noted that the standards are defined separately for port 1 and 2 allowing any variation between the ports that can occur due to fabrication imperfections. 135

PAGE 155

Appendix D (Continued) Figure D.5 Dialog Box for Load Standard Definitions at Port 1 and Port 2. Figure D.6 Dialog Box for Thru Line Definitions. 136

PAGE 156

Appendix D (Continued) Calibration Standard Definitions A standard definition file is generated once the model parameters are defined by clicking on the Calc button (Figure D.7). The file stores the required S-parameters of the SOLT standards which are later used for error computation. Figure D.7 Calibration Standard Definitions Section. The data is generated in the following manner using real, imaginary format Freq[GHz] Short(S11)[Re,Im] Short(S22)[Re,Im] Open(S11)[Re,Im] Open(S22)[Re,Im] Load(S11)[Re,Im] Load(S22)[Re,Im] Thru(S11)[Re,Im] Thru(S12)[Re,Im] Thru(S21)[Re,Im] Thru(S22)[Re,Im] The data is stored in text format and has 21 columns of data. The number of rows depends on the number of points set for calibration on the VNA. The frequency points for the calculation of standard definitions are either obtained directly from the VNA or offline with respect to a measured data file. Isolation Correction Isolation correction can be included or excluded for the calibration. When isolation is included, the S21 data from the measured load is taken as the isolation error parameters. 137

PAGE 157

Appendix D (Continued) Measure SOLT Standards for Calibration The standards are measured in real and imaginary format and saved offline as text files (Figure D.8). The real imaginary format is selected for error correction as it gives a more accurate representation of the measured standards when compared to magnitude and phase. Figure D.8 Measurements Section where Raw Data of Calibration Standards are Measured. Reference Plane Shifting The reference plane of the calibration can be shifted (Figure D.9) to probe tip or center of thru before calculating the error terms in this section. Figure D.9 Embedding or De-embedding Reference Plane Shifting Section. 138

PAGE 158

Appendix D (Continued) Error Terms Calculation The error terms can be calculated (Figure D.10) once all the standards are measured on-wafer. The error terms are calculated in real, imaginary format and saved to the disk as a text file. Figure D.10 Calculation of Error Co-efficients Before Sending to Network Analyzer. The error co-efficients are calculated in real and imaginary and stored in the following format on to a text file. The file stores the 12 error co-efficients data in 24 columns. FREQ[GHz] EDF[Re,Im] ESF[Re,Im] ERF[Re,Im] EXF[Re,Im] ELF[Re,Im] ETF[Re,Im] EDR[Re,Im] ESR[Re,Im] ERR[Re,Im] EXR[Re,Im] ELR[Re,Im] ETR[Re,Im] Send Error Terms to Network Analyzer (CAL ON) The error co-efficients are sent to the network analyzer to turn on the calibration using the Send Error Terms to Analyzer button. 139

PAGE 159

Appendix D (Continued) D.2 Cal Compare Program The Cal Compare program is used to generate the upper bound error between two similar calibrations. The error co-efficients from the two calibrations are read and the error bound is calculated in terms [S ij S ij ] and plotted. The figure D.6 shows a screen capture of the Cal Compare program. Figure D.11 Screen Shot of the Cal Compare Program that Generates the Upper Bound Error between Two Calibrations. 140

PAGE 160

Appendix E: Calibration Verification Data and Comparison of Measured Standards The appendix presents the graphs that compare calibration standards measured with respect to TRL and cSOLT calibrations. It also presents the effective dielectric constant, phase delay and characteristic impedance of the line determined with TRL calibration (using MultiCAL) for GGB CS5, Jmicro 5mil, M/A-Com GaAs and FR4 susbtrates. The calibration standards on the GGB CS5 and Jmicro 5mil substrates measured after TRL and cSOLT calibrations are illustrated here. The results show good agreement between the measured data from both TRL and cSOLT calibrations. The reference plane on GGB CS5 is at the probe tips while on the Jmicro 5mil is at the center of thru plane. E.1 GGB CS5 Calibration Substrate 0 10 20 30 40 50 60Frequency [GHz] -12 -10 -8 -6 -4 -2 0 2 4 6Effective Dielectric Constant-Eeff (Real Imaginary) Real EeffImagnary Eeff Figure E.1 Effective Dielectric Constant of GGB CS5 Calibration Substrate after TRL Calibration at Probe Tip Reference Plane. 141

PAGE 161

Appendix E (Continued) 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -60 -40 -20 0 20 40 60Characteristic Impedance () Real ImpedanceImaginary Impedance Figure E.2 Characteristic Impedance of Standards on GGB CS5 Calibration Substrate after TRL Calibration at Probe Tip Reference Plane (Z 0 =49.82 @ 10GHz). 0 10 20 30 40 50 60Frequency [GHz] 0 10 20 30 40 50 60 70 80 90Effective Phase Delay (Deg) Figure E.3 Effective Phase Delay of Delay Lines on GGB CS5 Calibration Substrate after TRL Calibration at Probe Tip Reference Plane. 142

PAGE 162

Appendix E (Continued) 0 10 20 30 40 50 60Frequency [GHz] -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8S11 Magnitude [dB] 150 155 160 165 170 175 180S11 Phase [Deg] TRL DatacSOLT Data Figure E.4 S11 Magnitude and Phase of Short Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 0 10 20 30 40 50 60Frequency [GHz] -0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2S11 Magnitude [dB] -20 -10 0 10 20 30 40 50S11 Phase [Deg] TRL DatacSOLT Data Figure E.5 S11 Magnitude and Phase of Open Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 143

PAGE 163

Appendix E (Continued) 0 10 20 30 40 50 60Frequency [GHz] -60 -55 -50 -45 -40 -35 -30 -25S11 Magnitude [dB] TRL DatacSOLT Data Figure E.6 S11 Magnitude and Phase of Load Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 0 10 20 30 40 50 60Frequency [GHz] -70 -65 -60 -55 -50 -45 -40 -35 -30 -25S11 Magnitude [dB] TRL DatacSOLT Data Figure E.7 S11 Magnitude of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. 144

PAGE 164

Appendix E (Continued) 0 10 20 30 40 50 60Frequency [GHz] -0.06 -0.05 -0.04 -0.03 -0.02 -0.01 0 0.01 0.02S21 Magnitude [dB] -30 -25 -20 -15 -10 -5 0S21 Phase [Deg] TRL DatacSOLT Data Figure E.8 S21 Magnitude and Phase of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Probe Tip Reference on GGB CS5 Substrate. E.2 Jmicro 5mil Calibration Substrate 0 5 10 15 20 25 30 35 40Frequency [GHz] -6 -4 -2 0 2 4 6 8 10Effective Dielectric Constant-Eeff (Real Imaginary) Real EeffImagnary Eeff 145 Figure E.9 Effective Dielectric Constant of Jmicro 5mil Calibration Substrate after TRL Calibration at Center of Thru Reference Plane.

PAGE 165

Appendix E (Continued) 0 5 10 15 20 25 30 35 40Frequency [GHz] 0 10 20 30 40 50 60 70 80 90Effective Phase Delay (Deg) Figure E.10 Effective Phase Delay of Delay Lines on Jmicro 5mil Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 0 5 10 15 20 25 30 35 40Frequency [GHz] -20 -10 0 10 20 30 40 50 60Characteristic Impedance () Real ImpedanceImaginary Impedance Figure E.11 Characteristic Impedance of Standards on Jmicro 5mil Calibration Substrate after TRL Calibration at Center of Thru Reference Plane (Z 0 =50.2 @ 10GHz). 146

PAGE 166

Appendix E (Continued) 0 5 10 15 20 25 30 35 40Frequency [GHz] -0.25 -0.15 -0.05 0.05 0.15 0.25Reflection Co-efficient (S11) [dB] -200 -150 -100 -50 0 50 100 150 200S11 Phase [Deg] TRL DatacSOLT Data Figure E.12 S11 Magnitude and Phase of Short Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 0 5 10 15 20 25 30 35 40Frequency [GHz] -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04Reflection Co-efficient (S11) [dB] -12 -10 -8 -6 -4 -2 0S11 Phase [Deg] TRL DatacSOLT Data Figure E.13 S11 Magnitude and Phase of Open Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 147

PAGE 167

Appendix E (Continued) 0 5 10 15 20 25 30 35 40Frequency [GHz] -50 -45 -40 -35 -30 -25 -20 -15Reflection Co-efficient (S11) [dB] TRL DatacSOLT Data Figure E.14 S11 Magnitude and Phase of Load Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 0 5 10 15 20 25 30 35 40Frequency [GHz] -65 -60 -55 -50 -45 -40 -35Reflection Co-efficient (S11) [dB] TRL DatacSOLT Data Figure E.15 S11 Magnitude of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. 148

PAGE 168

Appendix E (Continued) 0 5 10 15 20 25 30 35 40Frequency [GHz] -0.1 -0.08 -0.06 -0.04 -0.02 0 0.02 0.04 0.06Reflection Co-efficient (S21) [dB] TRL DatacSOLT Data Figure E.16 S21 Magnitude of Thru Standard Measured w.r.t TRL and cSOLT Calibrations at Center of Thru Reference on Jmicro 5mil Substrate. E.3 Custom M/A-Com GaAs Substrate 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -10 -8 -6 -4 -2 0 2 4 6 8 10Effective Dielectric Constant-Eeff (Real Imaginary) Real EeffImagnary Eeff Figure E.17 Effective Dielectric Constant of Custom M/A-Com GaAs Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 149

PAGE 169

Appendix E (Continued) 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] 0 10 20 30 40 50 60 70 80 90Effective Phase Delay (Deg) Figure E.18 Effective Phase Delay of Delay Lines on Custom M/A-Com GaAs Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 0 5 10 15 20 25 30 35 40 45 50Frequency [GHz] -30 -20 -10 0 10 20 30 40 50 60Characteristic Impedance () Real ImpedanceImaginary Impedance Figure E.19 Characteristic Impedance of Standards of Custom M/A-Com GaAs Calibration Substrate after TRL Calibration at Center of Thru Reference Plane (Z 0 =49.9 @ 10GHz). 150

PAGE 170

Appendix E (Continued) E.4 FR4 14mil Substrate 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -0.5 0 0.5 1 1.5 2 2.5 3 3.5Effective Dielectric Constant-Eeff (Real Imaginary) Real EeffImagnary Eeff Figure E.20 Effective Dielectric Constant of Custom 14mil FR4 Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 0 2 4 6 8 10 12 14 16 18Frequency [GHz] 0 10 20 30 40 50 60 70 80 90Effective Phase Delay (Deg) Figure E.21 Effective Phase Delay of Delay Lines on Custom 14mil FR4 Calibration Substrate after TRL Calibration at Center of Thru Reference Plane. 151

PAGE 171

Appendix E (Continued) 0 2 4 6 8 10 12 14 16 18Frequency [GHz] -10 0 10 20 30 40 50 60Characteristic Impedance () Real ImpedanceImaginary Impedance Figure E.22 Characteristic Impedance of Standards of Custom 14mil FR4 Calibration Substrate after TRL Calibration at Center of Thru Reference Plane (Z0 = 49.3 @ 10GHz). 152


xml version 1.0 encoding UTF-8 standalone no
record xmlns http:www.loc.govMARC21slim xmlns:xsi http:www.w3.org2001XMLSchema-instance xsi:schemaLocation http:www.loc.govstandardsmarcxmlschemaMARC21slim.xsd
leader nam Ka
controlfield tag 001 001469416
003 fts
006 m||||e|||d||||||||
007 cr mnu|||uuuuu
008 040524s2004 flua sbm s000|0 eng d
datafield ind1 8 ind2 024
subfield code a E14-SFE0000318
035
(OCoLC)55731375
9
AJR1170
b SE
SFE0000318
040
FHM
c FHM
090
TK145
1 100
Padmanabhan, Sathya.
0 245
Broad-band space conservative on wafer network analyzer calibrations with more complex SOLT definitions
h [electronic resource] /
by Sathya Padmanabhan.
260
[Tampa, Fla.] :
University of South Florida,
2004.
502
Thesis (M.S.E.E.)--University of South Florida, 2004.
504
Includes bibliographical references.
516
Text (Electronic thesis) in PDF format.
538
System requirements: World Wide Web browser and PDF reader.
Mode of access: World Wide Web.
500
Title from PDF of title page.
Document formatted into pages; contains 171 pages.
520
ABSTRACT: An improved Short-Open-Load-Thru (SOLT) on-wafer vector network calibration method for broad-band accuracy is proposed. Accurate measurement of on-wafer devices over a wide range of frequency, from DC to high frequencies with a minimum number of space conservative standards has always been desirable. Therefore, the work is aimed at improving the existing calibration methods and suggesting a best "practice" strategy that could be adopted to obtain greater accuracy with a simplified procedure and calibration set. Quantitative and qualitative comparisons are made to the existing calibration techniques. The advantages and drawbacks of each calibration are analyzed. Prior work done at the University of South Florida by an improved SOLT calibration is briefed. The presented work is a culmination and refinement of the prior USF work that suggested that SOLT calibration improves with more complex definitions for the calibration standards. Modeling of the load and thru standards is shown to improve accuracy as the frequency variation of the two standards can be significant. The load is modeled with modified equivalent circuit to include the high frequency parasitics. The model is physically verified on different substrates. The relation of load impedance with DC resistance is verified and its significance in SOLT calibrations is illustrated. The thru equation accounts for the losses in a transmission line reflections and phase shift including dielectric and conductor losses. The equations used are important for cases where a non-zero length of thru is assumed for the calibration. The complex definitions of the calibration standards are included in the calibration algorithm with LabView and tested on two different VNA's -- Wiltron 360B and Anritsu Lightning. The importance of including the forward and reverse switch terms error correction in the algorithm is analyzed and measurements that verify the improvement are shown. The concept using same foot size calibration standards to simplify the calibration process is highlighted with results to verify the same. The proposed technique thus provides for calibration strategy that can overcome the low frequency problems of TRL, retain TRL accuracy at high frequencies while enabling the use of a compact common footprint calibration set.
590
Adviser: Lawrence P. Dunleavy
653
error correction.
cal comparison.
complex models.
TRL.
cSOLT.
690
Dissertations, Academic
z USF
x Electrical Engineering
Masters.
773
t USF Electronic Theses and Dissertations.
4 856
u http://digital.lib.usf.edu/?e14.318