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Fabrication And Testing Of A Cy lindrical Ion Trap Microarray For Tunable Mass Spectrometers by Mangesh Telrandhe A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Shekhar Bhansali, Ph.D. Timothy Short, Ph.D. Scott Samson, Ph.D. Date of Approval: April 3, 2004 Keywords: mems, drie, cytop, voltage breakdo wn test, mass instabil ity scan, electroless plating, ultrasonic drilling Copyright 2004 Mangesh Telrandhe
ACKNOWLEDGEMENTS First of all I would like to thank Dr. Bhansali and Dr. Timothy Short, my major professors, for their valuable guidance and support throughout this project. I would also like to thank, Dr. Scott Samson, my comm ittee member whose timely suggestions and criticism has proved to be of immense help. I am also very thankful to Dr. Friso Van Amerom, George Steimle, and Heather Broadbe nd for their guidance and help during the experimentation. I am grateful to my parents and my el der brother who has always been a source of continuous encouragement throughout my life. A special thanks to them. Last but not the least, I would like to thank my friends Amol, Anant, Navin, Santosh and Himanshu for their support and encouragemen t throughout my Masters program.
i TABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES iv ACKNOWLEDGEMENTS v ABSTRACT x Chapter 1 INTRODUCTION 1 1.1 Overview 1 1.2 Objective of the Research 3 1.3 Cylindrical Ion Trap (CIT ) and Microarray Concept 4 1.4 Parallel Researches on Cylindr ical Ion Trap (CIT) 8 1.5 Thesis Organization 10 Chapter 2 FABRICATION OF CYLINDRICAL ION TRAP (CIT) MICROARRAY COMPONENTS 12 2.1 Mask Design for CIT Microarray Components 13 2.1.1 Ring Electrode Mask 13 2.1.2 Endplate Mask 14 2.2 Fabrication of Endplate Electrode 15 2.2.1 Process Flow 16 18.104.22.168 PECVD of SiO2 Mask for DRIE 16 22.214.171.124 Photolithography Using Ri ng Electrode Mask on Side A 17 126.96.36.199 RIE on Side A 17 188.8.131.52 DRIE on Side A 18 184.108.40.206 DRIE on Side B (Back Side Thinning) 18 220.127.116.11 PECVD of SiO2 on Side B 19 18.104.22.168 Photolithography on Side B 19 22.214.171.124 Ashing 20 126.96.36.199 DRIE on Side B Using Endplate Mask 20 188.8.131.52 Removal of Bosch Polymer 20 2.3 Fabrication of Ring Electrode 21 2.3.1 Process Flow 21 184.108.40.206 Photolithography 22 220.127.116.11 Ultrasonic Drilling 22 18.104.22.168 Dicing 23
ii 2.4 Metallization of Electrodes 23 2.4.1 Electroless Plating 24 2.4.2 Metallizat ion of Endplate Electrode 25 2.4.3 Metallization of Ring Electrode 25 Chapter 3 CYLINDRICAL ION TRAP (CIT) MICROARRAY ASSEMBLY 27 3.1 Selection of an Insulating Material 27 3.2 Properties of CYTOP 28 3.3 CYTOP Release 29 3.3.1 Thermal Oxidation 30 3.3.2 CYTOP Spinning 30 3.3.3 Buffer Oxide Etch (BOE) 31 3.4 Bonding And Assembly of CIT Microarray 31 3.4.1 Step 1 31 3.4.2 Step 2 32 3.4.3 Step 3 33 Chapter 4 CYLINDRICAL ION TRAP (CIT) MICROARRAY TESTING AND EXPERIMENTATION 34 4.1 Miniature CIT Test Setup 35 4.1.1 Ionization Source 35 4.1.2 Residual Gas Analyzer (RGA) 36 4.1.3 Channeltron Detector 36 4.1.4 Miniature CIT Mounting 37 4.1.5 Timing Diagram 38 4.2 Voltage Breakdown Test for CYTOP 39 4.2.1 Voltage Breakdown Test Setup 40 4.2.2 Voltage Breakdown Test Procedure 41 Chapter 5 RESULTS AND DISCUSSION 42 5.1 Endplate Electrode Fabrication (Experimental) 42 5.1.1 PECVD of SiO2 43 5.1.2 RIE of SiO2 Hard Mask 43 5.1.3 DRIE 44 5.1.4 Ashing 45 5.1.5 Removal Of Bosch Polymer 46 5.2 Ring Electrode Fabri cation (Experimental) 47 5.3 Metallization of Electrodes 48 5.4 CIT Microarray Assembly 50 5.5 Voltage Breakdown Test for CYTOP 51 5.6 Miniature CIT Testing 52 5.6.1 Testing of a 4.00 mm CIT 52 5.6.2 CIT Microarray Testing 55 5.7 Discussion 55 5.7.1 Endplate Electrode Design 55 5.7.2 Electroless Nickel Plating of Endplate Grid 57
iii 5.7.3 CYTOP (Organic Insulator) 58 5.8 Future Work 59 REFERENCES 61 APPENDICES 63 Appendix A Equipments and Process Recipes 64 A.1 Deep Reactive Ion Etching (DRIE) 64 A.2 Photolithography 67 A.3 Nickel Electroless Plating 68 A.3.1 Solution Preparation 68 A.3.2 Conditioning 68 A.3.3 Catalyzation 69 A.3.4 Accelerator Bath 70 A.3.5 Plating Bath 70 A.4 Plasma Enhanced Chemical Vapor Deposition (PECVD) 70 A.5 Reactive Ion Etching (RIE) 71 Appendix B Vendors and Contacts 73
iv LIST OF TABLES Table 1.1 State-of-the-a rt Technology 9 Table 3.1 Properties of CYTOP 28 Table 3.2 Parameters for PE of CYTOP 32 Table 5.1 Observed Etch Rates for DRIE 44 Table 5.2 Effect of Operating Frequency on Voltage Breakdown of CYTOP 52 Table A.1 Process Parameters for Bosch Process for DRIE 66 Table A.2 Photoresists and Process Paramters fo r Spinning 67 Table A.3 Process Parameters for PECVD using GSI 71 Table A.4 Process Parameters for RIE Using PT-72 72
v LIST OF FIGURES Figure 1.1 Schematic of a Cylindrical Ion Trap (CIT) 5 Figure 1.2 Simulation Result for Potential Well in a Quadrupole Ion Trap 5 Figure 1.3 Simulation Result for Potentia l Well in a Cylindrical Ion Trap (CIT) 6 Figure 1.4 Schematic of an Array of Cylindrical Ion Trap (CIT) 7 Figure 2.1 Optical Microscope Photograph of 4x4 Array in Ring Electrode Mask 13 Figure 2.2 Optical Microscope Photograph of Arrays of 5 m Diameter Holes with 10 m Pitch in an Endplate Electrode Mask 14 Figure 2.3 Optical Micros cope Photograph of Enlarged View of an Endplate Electrode Mask 14 Figure 2.4 Deposition of Hard Mask (SiO2) for DRIE 17 Figure 2.5 Patterning of Side A Usi ng Photoresist 17 Figure 2.6 Patterning of Hard Mask (SiO2) using RIE 18 Figure 2.7 DRIE on Side A 18 Figure 2.8 Backside Thinning of Side B 19 Figure 2.9 PECVD of Oxide on Side A 19 Figure 2.10 Patterning of Side B 20 Figure 2.11 Through Holes After DRIE 20 Figure 2.12 HF Dip for Oxide Removal 21 Figure 2.13 Schematic of Ring Electrode With 4x4 A rray 23 Figure 2.14 Schematic of Ring Electrode After Dicing 23 Figure 3.1 Schematic of Thermal Deposition of SiO2 30
viFigure 3.2 Schematic of Spin Coating of CYTOP 30 Figure 3.3 Schematic of Re leased CYTOP Film 31 Figure 3.4 Schematic of First Endplate Electrode Bonding 32 Figure 3.5 Schematic After First Plasma Etching 33 Figure 3.6 Schematic After Second E nd Plate Bonding and Plasma Etch 33 Figure 4.1 Schematic of the 4mm Diameter Mi niature CIT 34 Figure 4.2 Schematic of Mini ature CIT Test Setup 35 Figure 4.3 Photograph of th e Miniature CIT Test Setup 37 Figure 4.4 Miniature CIT on a Mounting Flange 38 Figure 4.5 Schematic of Timing Sequence for Mass Instability Scan 39 Figure 4.6 Schematic of Voltage Breakdown Test Setup 41 Figure 5.1 Optical Micros cope Photograph of Top View and SEM of Side View of Endplate Electrode 45 Figure 5.2 SEM Photograph of Cross Sec tion (3D View) of Endpl ate Electrode 46 Figure 5.3 SEM Photograph of Cross S ection of Endplate Electrode 46 Figure 5.4 Optical Micr oscope Photograph of 4x4 Array Fabricated Using Ultrasonic Drilling 47 Figure 5.5 Optical Micros cope Photograph of Enlarged View of a Single Hole fabricated using Ultrasonic Drilling 48 Figure 5.6 Optical Microsc ope Photograph of Endplate El ectrode After Electroless Nickel Plating 48 Figure 5.7 Optical Mi croscope Photograph Showing Improper Adhesion of Gold to the Substrate 49
viiFigure 5.8 Optical Mi croscope Photograph of Ring Electrode After Gold Electroless plating 50 Figure 5.9 CIT Microarray 51 Figure 5.10 Mass Spectrum Showing Isotopes for Chloroform 53 Figure 5.11 Mass Spectrum for Chlorofo rm Obtained During Mass Selective Instability Scan with a 4.0 mm CIT 54 Figure 5.12 Schematic and SEM Photograph of Endplat e Grid 56 Figure 5.13 Schematic of CIT Micr oarray with Broken Pieces of Endplate Grid 57 Figure 5.14 Optical Micr oscope Photograph of Melted Endplate Grid Due to Excessive Heating due to RF Voltages 58 Figure 5.15 Schematic of New Endplate Electr ode Grid Design 60 Figure A.1 Schematic of Cylindrical ICP Source for Unaxis 770 64
viii FABRICATION AND TESTING OF A CYLINDRICAL ION TRAP (CIT) MICROARRAY FOR TUNABLE MASS SPECTROMETER Mangesh Telrandhe ABSTRACT This research presents a novel micr ofabrication approach and testing methodology for cylindrical ion trap (CIT) mi croarray tunable for massspectrometers. The growing interest in cylindrical ion trap (CIT) mass-spectrometers is primarily due to ease with which cylindrical geometry can be re alized as compared to hyperbolic surfaces found in conventional quadrupole ion traps. Also due to the fact that the potential at the center of hyperbolic electrode in quadrupole ion trap a nd cylindrical electrode in cylindrical ion trap (CIT) does not differ significantly. Since the RF voltage required to eject a given mass-to-charge ion scales as the square of the ion trap radius, a decrease in ion trap dimensions provides a significant reduction in electronics requirements, there by providing a pathway for overall system miniaturization. The reduction in sensitivity due to reduced ion storage capacity as a result of miniaturization can be improved by employing an array of identically sized ion traps. Microfabrication approach promises excellent uniformity in the fabrication of identically sized holes which in turn leads to low-cost high performance CIT microarray for mass spectrometers[1,2]. The criterion used for the dete rmination of trap diameter was to ensure that the hole to be 1.09 times the wafer thickness to provide optimal potential to trap ions. The end-
ixplates were designed to optimi ze the electron and ion transmi ssion into and out of the ion trap and provide a high quality electric fiel d definition within each cylindrical ion trap (CIT). Two different approaches, namely deep reactive ion etching (DRIE) and mechanical drilling using u ltrasonic disc cutter were proposed and used for the fabrication of ring-electrode which forms the main body of the ion trap. Excellent uniformity in hole diameter was observed in both the approaches. The end-plates were fabricated using deep reactive ion etching (D RIE) which provided hi gh transmission rigid grid structure for ions and el ectrons. Standard Bosch proces s was used for deep reactive ion etching (DRIE). The two electrodes were metallized using electroless plating which provides excellent uniformity of coating even on end-plate structur es with 5m through holes. CYTOP, a cyclized perfluoro polymer was used as an insulation layer and intermediate bonding layer between the ring electrode and end-plates. The breakdown voltage for a released 16 m thick CY TOP layer was found to be 1.47KV. An assembly for testing miniature cylindrical ion trap (CIT) was designed and built. An electron impact ionization source was used for generation of ions. Mass selective instability scan was used to selectively eject ions with different mass-to-charge ratio. A cylindrical ion trap (CIT) with 4mm diameter was fabricated and tested for analyte gases such as krypton and xenon.
1 CHAPTER 1 INTRODUCTION 1.1 Overview A Mass spectrometer is a device which separates ions according to its mass-tocharge ratios. Due to its ability to effectiv ely analyze large as well as small molecules, mass spectrometry has emerged as a prominen t analytical technique for the chemical analysis of known and unknown compounds . Biotechnology, environmental monitoring, protein synthesis and DNA sequenc ing are some of the potential areas where the capabilities of mass spectrometr y are currently being explored. A typical mass spectrometer main ly consists of an ion source, an analyzer and a detector. The ion source constitutes a co mponent of a mass spectrometer where the analyte is converted into gaseous phase and ionized. Electron impact ionization, chemical ionization, electrospray ionization and fast at om bombardment, etc. are some of the commonly used ionization tec hniques. The need for analyzing very high mass compounds has resulted in development of ionization techniques such as plasma desorption, matrix-assisted laser desorption a nd electrospray. The analyzer performs the function of separating ions according to their mass-to-charge ratios. Depending on the application, various types of analyzers are employed, such as time-of-flight, magnetic sectors, quadrupole mass filters and ion traps.
2The history of quadrupole ion tr aps takes us to the work of Wolfgang Paul and Hans Steinwedel, who were conferre d with a noble prize in physics in 1989 for the invention of quadrupole ion traps. Initially, the quadrupole ion trap was used as a tool for studying basic gas-phase physical processes. One importa nt event in the development of ion traps was the discovery of mass-selective instability scan by George C. Stafford, Jr. This discovery led the way for the creation of versatile mass-spectrometers for commercial use. The quadrupole ion trap mass spectromete r was first introduced as a simple gas chromatography (GC) detector. But the underl ying advantages of a quadrupole ion trap, such as compact size and high sensitivity, resulted into developm ent of the quadrupole ion trap into a high performance mass-spect rometer. With advanced techniques for ionization at hand, mass spectrometry is gain ing prominence as a tool to analyze high mass compounds like biomolecules, peptide and protein etc. The continual quest for improving the pe rformance of a quadrupole ion trap mass spectrometer has resulted in techniques for improving the mass range. These techniques include : reduction in size of the ion tra p, reduction in main rf drive frequency and, utilizing an alternating current (AC) of appropriate frequency for the resonant ejection of ions from the ion trap, a technique which is called as axial modul ation. The experiments for improving the mass resolution resulted in the finding that the resolution can be improved by slowing the rate of the mass-sel ective instability scan while applying axial modulation. Very high resolution can be achieved by very slow scans. The reduction in size of the ion trap for improving the performance of the device has propelled the development of a cylindric al ion trap (CIT). The simulation results indicate that, if the proper di mensions are used, the potential at the centre of hyperbolic
3electrode in quadrupole ion trap and the cylindrical electrode in cylindrical ion trap does not differ significantly. Hence, an effectiv e trapping potential can be obtained using cylindrical geometry. The inherent advantage of a cylindrical ion tr ap is the ease with which cylindrical geometry can be realized and miniaturized as compared to the hyperbolic surfaces found in the conventional quadrupole ion traps. This fact makes a cylindrical ion trap an enticing candidate fo r miniaturization for enhancing performance of a mass spectrometer system as a whole. 1.2 Objective of the Research The primary objective of this research wa s to fabricate and test a cylindrical ion trap microarray for use as a tunable ma ss spectrometer. Various microfabrication techniques were used, such as reactive i on etching (RIE), deep reactive ion etching (DRIE), plasma etch (PE), contact lit hography, plasma enhanced chemical vapor deposition (PECVD), electroless plating, descumming and low temperature bonding, to fabricate the CIT microarray. Since the RF voltage required to eject a given mass-tocharge ion scales as the square of the ion trap radius, a decr ease in ion trap dimensions provides a significant reduction in electronic s requirements, thereby providing a pathway for overall system miniaturization. The reduction in sensitivity due to reduced ion storage capacity as a result of miniaturizat ion can be improved by employing an array of identically sized ion traps Microfabrication approaches promise excellent uniformity in the realization of identically sized hol es, which in turn leads to low-cost high performance CIT-array devices.
4 For the proof of concept and evaluation of a CIT test setup, in itial efforts have been concentrated on the testing of a 4 mm diameter miniature cylindrical ion trap machined using stainless steel as a basi c structural material. An electron impact ionization source has been employed to an alyze xenon gas to obtain a mass spectrum showing isotopes for the particular gas. Expe riments were also conducted to verify the effect of buffer gas and axial modulation on the efficiency of the cylindrical ion trap. After successfully testing a miniature cylin drical ion trap, the efforts were focused on the fabrication and assembly of various co mponents of a microfabricated cylindrical ion trap microarray, which include end pl ate electrode, ring electrode and CYTOP (cyclized perfluoro-polymer) which was used as an insulator and as a bonding material. Tests were also conducted to verify the br eakdown voltage of va rious thicknesses of CYTOP at different frequencies. 1.3 Cylindrical Ion Trap (CIT) and Microarray Concept An ion trap mass spectrometer is a devi ce in which ions are stored by creating a potential well, and ejected sequentially accord ing to their mass-to-charge ratios during a mass instability scan. A typical quadrupol e ion trap consists of a hyperbolic ring electrode and two hyperbolic e nd cap electrodes on each side of the ring electrode. These electrodes are separated by an el ectrical insulation layer that prevents arcing between the two electrodes at high voltage and frequency. The spacing of the end cap electrodes and thickness of this insulation layer can be adju sted to optimize the performance of an ion trap mass spectrometer. An rf trapping volta ge is applied at the ring electrode and the two end cap electrodes are grounde d. An alternating current (AC) can also be applied at
5the two end plate electrodes to improve the performance of an i on trap by resonantly ejecting ions. In a cylindrical ion trap, the hyperbolic ring electr ode is replaced by a simple cylinder and the two hyperbolic end cap electrodes are repl aced by two planar endplate electrodes (see figure 1.1). Figure 1.1 Schematic of a Cylindrical Ion Trap (CIT) Although there are differences in the type of potential well formed in a cylindrical ion trap as compared to qua drupole ion trap, it does not di ffer significantly if the proper geometry is chosen. This can be dem onstrated by simulating the potential pattern inside the cylindrical and qua drupole ion trap geometry us ing Simion 3D software, as shown in figure 1.2 and 1.3. Figure 1.2 Simulation Result for Potential Well in a Quadrupole Ion Trap End-plate electrode End plate electrode Ring electrode Insulation layer Ions from ion source To detector
6 Fig 1.3 Simulation Result for Potential We ll in a Cylindrical Ion Trap (CIT) Existing mass spectrometers are larger in size as compared to the other hand held monitoring devices. The need for smaller porta ble instruments for in-situ field chemical analysis requires miniaturization of ma ss spectrometer technology. The inherent advantages of miniaturiza tion of an ion trap are re duced power and voltages and increased mass range as compared to the la rger system. This reduction in power and voltage level further provides an incentive, in that the size of the electronics system can also be reduced significantly, leading to miniaturization of a mass spectrometer as a whole. The decrease in RF voltage required to eject ions (and therefore the increase in mass range) can be very well understood by low-mass-cutoff equation. According to low-mass-cutoff equation, (m/e) = 8Vrf/ qz2 (r0 2 + 2z0 2) (1.1)
7where (m/e) is the mass-to-c harge ratio of the ion, Vrf is the amplitude of the applied rf voltage, qz is the value of the Mathieu parameter, is the angular frequency of the applied rf, r0 is the internal radius of the ring-electrode and z0 is the center-to-end-plate distance. The Mathieu parameter is a dimensionl ess factor that determ ines the stability of the ion trajectories within the ion trap (i.e., whether they are trappe d or not) and depends upon their mass-to-charge ratio, th e size of the ion trap, the fundamental rf voltage and frequency. Although the miniaturization of a cylindrical ion trap promises above mentioned advantages, this approach suffers a drawback due to reduced ion storage capacity. This reduced ion storage capacity adversely affect s the performance of a device. The reduction in sensitivity due to reduced ion storage cap acity as a result of miniaturization can be taken care by employing an array of identic ally sized cylindrical ion traps. The advantages due to miniaturization are a ugmented by microfabrication approach which promises excellent uniformity in the realiz ation of identically sized holes (employing standard microfabrication techniques) which in turn leads to low-co st high performance CIT-array devices. Figure 1.4 Schematic of an Array of Cylindrical Ion Trap (CIT) Array of ion traps
81.4 Parallel Research on Cylindrical Ion Trap (CIT) Predominantly, two more groups are curre ntly concentrating on the development of cylindrical ion traps (CIT). The first group is from Department of Chemistry at Purdue University. Their main attention is on optimiz ing the geometry of cylindrical ion traps by maximizing the quadrupole field component as compared to the higher-order field contents. This group successfully optimized the geometry to obtain mass spectra with better than unit mass resolution and the perf ormance of this device was found to be comparable with that of a conventional quadr upole ion trap. The material used for fabricating the electrodes was stainless steel and machinable ceramic glass was used for electrical isolation. The ion trap s used for the study had a ring electrode radius of 1.0 cm. And the end-plates had a hole of 2 mm diameter at the center. The rf trapping voltage of peak-to-peak amplitude of 7.5 KV with a frequency of 1.1 Mz was used for massselective instability scan. Th e typical ramping rate for RF voltage was chosen at 5555 Da/s. The closest distance between the center of the ring electrode and the end-plate was varied and the relative field contributions due to quadrupole and higher order fields were simulated using Poissions / Superfish code. Th e calculations showed that the potential well was optimized at Z0 value of 0.9 cm that minimized the higher order field components to minimum. One of the important conclusions of these calculations was regarding the spacing between ring electrode and the end-plate. It was inferred that as the distance between the ring electrode and the e nd-plate is decreased th e higher order field components are lowered giving a more quadrupolar field. The tests were also conducted on array of four CITs, each having an inner radius of 2.5 mm. The array was operated using a single electronics system under common
9conditions of trapping and mass analysis. The resolution for m-dichlorobenzene was observed to be ~180 (full width at half-maxim um). The initial test results for a 10-CIT array with individual element of inner radi us 1.5 mm was also repor ted. The experiments were also conducted to validate the increase in ion storage capacity due to increase in number of CITs in an array. Table 1.1 State-of-the-art Technology Research Group Type of Device Minimum Feature Size Highlights Purdue University CIT Radius : 2.5 mm 4x4 Array, m/z range 50-500 Oak Ridge National Laboratory CIT Radius : 0.5 mm Resolution : 0.2 Da University of Liverpool, England QMS Diameter:0.5 mm Length:10-30mm Sensitivity : 10-100 ppm Jet Propulsion Laboratory, NASA QMS Diameter:2 mm Length:25 mm Resolution : 0.5 Da University of South Florida CIT Radius : 0.8 mm Mi crofabricated CIT Array
10The second group is from Oak Ridge Nati onal Laboratory, TN. This group carried out experiments on submillimeter size ion trap s and achieved spectral line width of 0.2 Da for the single mass scans of the trapped i ons. The electrodes for these ion traps were made up of stainless steel. The typical diamet er of the ring electrode for their experiments was 1.0 mm and the thickness of the ring electrode was 0.9 mm. The endplates were carrying 0.4 mm central hole in a stainless steel plate which we re thinned at the center. The mica spacers and Teflon spacers have been reported as an electrical insulation between adjacent electrodes. One of the important findings for thes e experiments was that, there was no noticeable improvement in the performance after applying axial modulation. The reason proposed being the fact that the number of ions that can be trapped with this size of ion traps was well below the space charge limit. Th e fabrication and testing of an array of 1mm diameter ion traps machined out of st ainless steel was reported. The mass spectrum obtained from this array of ion trap show s clearly resolved isotopic peaks for Xenon gas. 1.5 Thesis Organization Chapter 2 discusses the detail fabrica tion processes for various CIT microarray components such as ring electrode and the end cap electrodes. It also illuminates various microfabrication techniques and tools used for CIT microarray fabrication. The Chapter 3 includes the CIT microarra y assembly. This chapter highlights various properties of CYTOP and low temperature bonding technique employed for CIT microarray device assembly.
11Chapter 4 discusses various experiments performed during testing of a miniature ion trap. This chapter also discusses expe riments performed to measure the breakdown voltages for different thicknesses of CYTOP layer. Chapter 5 is the compilation of results and discussions.
12 CHAPTER 2 FABIRCATION OF CYLINDRICAL ION TRAP (CIT) MICROARRAY COMPONENTS The novel aspect of this part icular cylindrical ion trap (CIT) microarray is that it is fabricated using silicon using various mi crofabrication technique s. The motivation for choosing silicon as a structural material for the fabrication of a CI T microarray is that it has been extensively studied and is a well characterized material. Various microfabrication techniques, such as lit hography, deep reactive ion etching (DRIE), reactive ion etching (RIE), low pressure ch emical vapor deposition (LPCVD) and plasma enhanced chemical vapor deposition (PECVD), etc., are very well es tablished for silicon. These techniques can be characterized and em ployed for fabricating structures with precise dimension control and excellent uniformity. The process flow designed for the fabrica tion of CIT microarray components was based on bulk micromachining approach. The bulk micromachining approach utilizes bulk of the substrate to fabricate structures with high aspect ratios. Wet chemical etching and dry etching are commonly used techni ques for bulk micromachining depending upon the application. Dry etching techniques we re used for the fabrication of endplate electrode in a CIT microarray.
132.1 Mask Design for CIT Microarray Components A standard technique called photolithography was used for patterning. Photolithography utilizes a photosensitive mate rial for patterning of a mask for bulk micromachining. The masks required fo r photolithography were designed using Coventorware software package. 2.1.1 Ring Electrode Mask The criterion used for the determination of trap diameter was to ensure the hole diameter to be 1.09 times the wafer thickness to provide the optimal trapping potential. The particular value for above ratio was obtained from Ethan R. Badman, Indiana University. A standard 1600 m thick double side polished wafer was used for the fabrication of ring electrode. Th is requires the effective diamet er of individual cylindrical ion trap to be 1744 m. Hence a dark field mask was made with 24x24 array of 1744 m diameter holes on a standard 4x4 mask plate. Figure 2.1 Optical Microscope Photograph of 4x4 Array in a Ring Electrode Mask
142.1.2 Endplate Mask The endplates were designed to optimize the electron and ion transmission into and out of the CIT. The grid provides high quality electric poten tial within each CIT. Hence a dark field mask was designed to ensu re that the ring elec trode was capped with endplates that had an array of 5 m diameter holes at a 10 m pitch. Figure 2.2 Optical Microscope Photogra ph of Arrays of 5 m Diameter Holes with 10 m Pitch in an Endplate Electrode Mask Figure 2.3 Optical Microscope Photograph of Enlarged View of an Array in an Endplate Electrode Mask
15The entire process for the fabricatio n of a CIT microarray based on bulk micromachining using various microfabricati on techniques can be divided into following steps: 2.2 Fabrication of Endplate Electrode As shown in figure 1.1, the two endplate el ectrodes are identi cal and attached on either side of ring electrode. In stead of a single hole at the ce ntre, a circular array of 5 m diameter through holes with 10 m pitch wa s used to improve the transmission of electrons and ions in and out of the ion trap, while maintaining a more uniform potential to ensure a high quality potential well inside each CIT. The major challenge in the fabrication of endplate electrode is to fabricate through holes with straight vertical walls in a s ilicon wafer. Wet chemical etching and dry chemical etching approaches were evaluate d for fabricating through holes in a silicon substrate. With recent developments su ch as Inductively Coupled Plasma (ICP) Source, Capacitively Coupled Plasma (CCP) source and back side Helium cooling etc., DRIE offered an effective method for fabricati ng through holes with vertical side walls at relatively higher etch rate as compared to Wet Chemical Etching. The entire microfabrication of End Plate electrodes was carried out at Cornell Nanofabrication Facility (CNF). Unaxis 770 ICP Etcher w ith high conductance pumping system and ICP source was used for DRIE. The detail informa tion about the construc tion and operation of Unaxis 770 ICP Etcher can be obtained in appendix A ( Section A.1).
162.2.1 Process Flow Although a standard Bosch process for fabr icating trenches w ith vertical side walls was available, fabrication of through hol es in a standard double side polished 250 m thick silicon wafer was limited by the aspe ct ratio for DRIE. Aspect ratio provides the relation between diameter and the maxi mum depth for the trenches. The specified aspect ratio for DRIE was 20:1. Hence with a circular pattern having 5 m diameter, maximum possible depth was 100 m. A 100 m thick lapped wafer could have been used for fabricating through holes, but the us e of wafers thinner than 250 was not allowed in Unaxis 770 ICP etcher due to pressure i ssues related to back side Helium cooling. Hence a novel process flow was designed for fabricating through holes with 5m diameter in a standard double side polishe d 250 m thick silicon wafer using Unaxis 770 ICP etcher. In this approach, the wafer was processed on both sides to fabricate endplate electrode discussed as under. 22.214.171.124 PECVD of SiO2 Mask for DRIE A standard 250 m thick double side polis hed (DSP) silicon wafer was used for fabricating endplate electrode. Init ially a 3.5 m thick layer of SiO2 was deposited on side A using Plasma Enhanced Chemical Vapor Deposition (PEC VD) technique. SiO2 layer was used as a hard mask for DRIE A standard program for the deposition of undoped SiO2 that is suitable for DRIE was used. Various parameters for PECVD of SiO2 are listed in appendix A ( Section A.4).
17 Figure 2.4 Deposition of Hard Mask (SiO2) for DRIE 126.96.36.199 Photolithography Using Ring Electrode Mask on Side A The wafer was patterned on side A using ring electrode mask. STR 1045 photoresist was used as a photoresist for photolithography. Various parameters used during photolithography are explained in appendix A (section A.2). Figure 2.5 Patterning of Si de A Using Photoresist 188.8.131.52 RIE on Side A Reactive ion etching (RIE) wa s used for patterning SiO2 hard mask for DRIE. Plasma Therm 72 was used for RIE. A st andard recipe for etching thermal SiO2 was used for RIE of SiO2 hard mask. Parameters used during RI E are listed in appendix A (section A.5). SiO2 Hard Mask using PECVD 250m DSP Silcon Wafer Side A Side B Side B Patterned Photoresist SiO2 Hard Mask Deposited using PECVD Side A
18 Figure 2.6 Patterning of Hard Mask (SiO2) Using RIE 184.108.40.206 DRIE on Side A DRIE was done on side A with patterned SiO2 hard mask to obtain 150-160 m deep vertical trenches. A standard Bosc h process program was used for DRIE. The parameters used during DRIE are lis ted in appendix A (section A.1) Figure 2.7 DRIE on Side A 220.127.116.11 DRIE on Side B (Back Side Thinning) The wafer was thinned down from back side i.e. side B. The standard Bosch process program used in step 4, was used for back side thinning. In this step, DRIE was done on side B without any mask. Due to ab sence of any mask, the wafer was etched uniformly over the surface. Back side th inning was done for 35-40 min. The parameters used during DRIE are listed in appendix A (section A.1). Side A Side B 150-160m Deep Trenches Obtained using DRIE Side A Side B Patterned SiO2 Hard Mask using RIE
19 Figure 2.8 Back side Thinning of Side B 18.104.22.168 PECVD of SiO2 on Side B SiO2 was deposited on side A for preventi ng Helium leak due to through holes. GSI tool was used for deposition of SiO2 using PECVD technique. The thickness of deposited SiO2 was 1.5m. The parameters us ed during this PECVD of SiO2 are listed in appendix A (section A.4). Figure 2.9 PECVD of Oxide on Side A 22.214.171.124 Photolithography on Side B In this step, the wafer was patterned on side B using endpl ate mask. Karl Suss MA6 Contact Aligner was used to align each circular array of 5 m holes on the End plate mask with individual holes with 1.6 mm diameter on side A. Shipley 1045 photoresist was used as a mask for DRIE on side B. The parameters used during photolithography are listed in appendix A (section A.2). Side A Side B Side B after 4045m thinning Side B Side A PECVD oxide for Helium leak Check on side A
20 Figure 2.10 Patterning of Side B 126.96.36.199 Ashing In this step, the patterned photoresist on side B was subjected to ashing using oxygen plasma. RIE chamber of PT72 was used for ashing. The ashing was done for 2.0 min. The value of pressure during photor esist ashing was 60 mTorr and applied RF power was 150 W. 188.8.131.52 DRIE on Side B Using Endplate Mask The wafer was subjected to DRIE on side B. The parameters used during DRIE are listed in appendix A (section A.1). The wafer was continuously monitored for through holes by intermediately discontinuing DRIE and holding the wafer against the light source. Figure 2.11 Through Holes After DRIE 184.108.40.206 Removal of Bosch Polymer Finally HF dip was done to remove SiO2 on side A. The wafer was also subjected to nanostrip dip for removing Bosch polymer. Side B Side A Through Holes After DRIE on Side B Side B Pattern on Side B Using End Plate Mask
21 Figure 2.12 HF Dip for Oxide Removal 2.3 Fabrication of Ring Electrode The ring electrode constitutes the centra l cylinder where ions are stored during ionization period. The geometry of this cylinde r plays an important role in developing a potential well for trapping ions. Ultrasonic drilling was used for fabri cating an array of 1.6 mm diameter through holes in a silicon wafer. This approach utilizes abrasive machining for drilling holes in a variety of substrates. In th is particular technique, ultr asonic vibrations agitate and bombard abrasive particles against the substr ate. Commonly used abrasive particles are boron carbide, caborundum, diamond powder etc. that are mixed with water to form a slurry. A Piezoelectric transdu cer is responsible for ultrason ic vibrations which are then transferred to a tool of any shap e. It is equally effective in dr illing holes in soft as well as hard materials such as glass, ceramic, semiconductors, etc. 2.3.1 Process Flow A 2 double side polished (DSP) 1600m thick silicon wafer was used for the fabrication of ring electrode. The steps involved in the fabrication of ring electrode are as follows: Side A Side B
220.127.116.11 Photolithography The wafer was patterned using ring electro de mask. Photoresist Shipley 1813 was used for this contact photo lithography. Various parameters used are explained in appendix A (section A.2). 18.104.22.168 Ultrasonic Drilling A Disc Cutter by Gatan Inc. ( Model 601) was used to drill a 4x4 array of 1.6 mm diameter through holes in the patterned sili con wafer. The sample wafer was bonded to a carrier wafer using a low melting wax. This stack was bonded to the specimen holding block using a low melting wax. The carrier wafer ensured that there was no direct contact of cutting tool with the specimen holding block once the cutting tool went through the sample wafer. A stereo microsc ope with X-Y positioning table was used to align disc cutter tool with the features on th e patterned wafer. After aligning, the sample was loaded on the Disc Cutter, where it is magnetically held in position to avoid any lateral movement of wafer rela tive to the tool. The cutting site was continuously flooded with slurry containing cutting grit mixed with water. The tool was gradually moved down which applied pressure on wafer mounted on a sp ring loaded table. The pressure and feed rate was adjusted to reduce chipping at e dges. After drilling 4x4 a rray of 1.6mm diameter through holes, the wafer was detached from the specimen holding block by heating it to melting point of wax. The wafer was cleaned us ing acetone in ultrasonic bath to remove slurry particles.
23 Figure 2.13 Schematic of Ring Electrode With 4x4 Array 22.214.171.124 Dicing Finally the ring electrode wafer was diced into a square piece (1x1) with a 4x4 array of 1.6mm diameter through holes. This makes it easier to mount CIT microarray into the testing assembly. Figure 2.14 Schematic of Ri ng Electrode After Dicing 2.4 Metallization of Electrodes The wafers used for the microfabrica tion of CIT microarray components were silicon wafers with resistivity of 1-5 cm. The mass selective instability mode of operation requires high voltages to be applie d to the ring electrode. Hence the surface resistivity of the electrodes should be as low as possible to reduce the heating of electrodes. This necessitates metallization of electrodes. 1600m thick silicon wafer 4 x 4 Array of 1.6mm diameter through holes
24Microfabrication offers various coati ng techniques such as evaporation, sputtering, chemical vapor deposition (CVD), electroplating and elec troless plating are predominantly used for metallization. CIT microarray components have three dimensional topographies which mainly in clude thorough-holes, the coating technique used needs to ensure uniform coating on a ll exposed surface. Evaporation and sputtering tend to be directional, offer different coati ng rate on the side walls of through holes and could not be used. Hence electroless plating was used for the metallization of electrodes that offers conformal seed layer on thr ee dimensional topographies. 2.4.1 Electroless Plating Electroless plating is a t echnique of depositing metals various substrates through auto-catalytic process. A commercial electr oless plating process, ENPLATE NI -425 was used for metallization. ENPLATE NI -425 wh ich is an advanced electroless nickel process was used for the metallization of elect rodes. It has superior plating capabilities for plating structures having critical topographies. This proc ess typically deposits nickel phosphorous alloy and is capable of plating on various types s ubstrates such as aluminum alloys, stainless steel, carbon and alloy stee ls, copper alloys, and certain non-conductors such as silicon. Because of its excellent corrosion resistan t properties ENPLATE NI-425 is recommended in various applications that require stringent corrosi on resistance. It is particularly useful in food processing a pplications and for manufacturing medical and surgical parts due to its resistance to staining. A plating station dedicated to electrole ss plating at Center for Ocean Technology, University of South Florida, St. Petersbur g, FL, was used for plating experiments.
252.4.2 Metallization of Endplate Electrode Endplate electrode consists of microfab ricated 4x4 array of holes with 5 m diameter and 10 m pitch. Since initial electro less plating experiments showed improper adhesion of nickel to the substr ate, the endplate wafers were partially etched to make the surface slightly rough. A Fluoride-Bifluoride-Hydr ofluoric acid buffer w ith stabilized HF activity was used for partially etching wafe rs. The partial etching was done for 4 min. The wafers were properly rinsed with DI wa ter and then passed al ong the plating line as explained in appendix A (section A.3). The pl ating time was 35 sec for endplate electrode wafers. 2.4.3 Metallization of Ring Electrode Ring electrode consists of a 1x1 wa fer with 4x4 array of holes with 1.6 mm diameter. Since higher voltages have to be applied to the ring electrode during mass selective instability scan a relatively thicker coating of highly conductive metal was required to minimize the heating of the ring electrode. As the initial electroless nickel platin g experiments showed improper adhesion to the substrate, but excellent adhesion to the inside walls of the holes, a 12 m alumina type lapping compound was used to make the surface rough which makes it conducive for nickel electroless plating. The ring el ectrode wafer was lapped for 90 sec using a lapping compound. After rinsing properly with DI water, the wafer was passed along the electroless nickel plating line as e xplained in appendix A (section A.3).
26Bright electroless gold by Tr ansene Company inc., was used for gold plating of ring electrode. Bright electr oless gold plates gold on me tal parts by an electroless immersion process. Electroless nickel acted as a seed layer for bright electroless gold plating of the ring electrode. The pH value of the solution was maintained at 7. The plating temperature was 90C. The solution was continuously stirre d using a horizontal bar. The plating was done for 15 min.
27 CHAPTER 3 CYLINDRICAL ION TRAP (CIT) MICROARRAY ASSEMBLY 3.1 Selection of an Insulating Material After fabrication of CIT microarray components i.e., ring electrode and the endplate electrodes, a CIT microarray device ha s to be assembled The ring electrode and two endplate electrodes on either sides of ring electrode have to be bonded in such as way that these electrodes are electr ically insulated from each ot her. The insulating material should with-stand the high voltages required to create a potential well inside each cylindrical ion trap (CIT). The primary require ments for this particular insulating material used to bond adjacent electrodes are as follows: (a) It should be able to withstand high voltages applied duri ng mass instability scan. (b) It has to be compatible with low operating pressures in a mass spectrometer i.e., it should be free fro m degassing issues at low operating pressures. (c) It should also act as a bonding materi al between ring electrode and the two endplate electrodes. (d) It should be compatible with various microfabrication techniques such as spin coating, reactive ion etching (RIE) etc.
28Apart from these specific requirement s the insulating material should possess excellent chemical and temperature resistance. In this particular application, chemical resistance of the insulating material is of paramount importance as the integrated miniature sensors are exposed to harsh e nvironments while detecting a variety of unknown compounds. Various insulating materials such as SiO2, Si3N4, Teflon etc., have been considered for this particular applicati on that provide excellent electrical insulation and are compatible with microfabrication techniques. After reviewing various process integr ation issues for CIT microarray, CTL800M series of CYTOP was chosen as an insulating and bonding layer. 3.2 Properties of CYTOP CYTOP, a cyclized perfluoro polymer, was chosen as an insulating material for this application. CYTOP has various chem ical and electrical properties that are comparable to the fluorocarbon polymers. It is a new class of perfluoro-polymer that can be obtained by cyclopolymerizati on of perfluoro. The fact th at it is soluble in some fluorine containing solvents, allows CYTOP to be used as a protective coating from various chemicals. CYTOP can be used as a bonding material which enables a low temperature bonding technique for CIT microarray assembly. Table 3.1 Properties of CYTOP  Glass Transition Temperature (C) 108 Yield Strength (MPa) 40 Dielectric Constant 2.1~2.2 Dielectric Breakdown Voltage (kV/0.1mm) 11
29CYTOP is available in various grad es. A particular grade of CYTOP is selected for an application depending upon various factors involved. CTL-800M series was chosen for this particul ar application. CTL-800M is a solution of CYTOP whose polymer end groups are modified to have a exce llent adhesion to vari ous substrates such as silicon, SiO2, Al, Cu, Au and glass. The voltage breakdown tests were conducte d on CYTOP layers with different thicknesses. The voltage breakdown test result s indicated that, a 16 m thick layer of CYTOP was sufficient to provide adequate electrical insulation to with-stand high voltages up to 1.0 KV at 2.7 MHz (section 4.2). Th is necessitates use of 4 layers of 4 m thick CYTOP films to provide re quired thickness of insulation. Various coating methods such as spin coating, dip coating, potting and spray coating are available depending upon the t ype of substrate an d target thickness. CYTOP has also been well char acterized in terms of target thickness and spin speeds. 3.3 CYTOP Release CYTOP can be spin coated on variety of substrates withou t any pretreatment. The thickness of the film can be controlled by changing spin speed and spin time. The ability to release and etch a free standing la yer of CYTOP of ta rget thickness makes it conducive for this par ticular application. A standard recipe for releasing a 4 m thick film of CYTOP CTL-809M was used. The CYTOP was spin coated twice w ith intermediate baki ng. The steps involved in CYTOP release were as follows
303.3.1 Thermal Oxidation Standard single side polished, 550 m thick, dummy wafer was used for this application. Thermally grown SiO2 was used as a sacrificial layer which can be easily etched using 10:1 buffered oxide etch (BOE). A 1.4 m thick layer of SiO2 was grown using thermal oxidation. Figure 3.1 Schematic of Thermal Deposition of SiO2 3.3.2 CYTOP Spinning The first layer of CYTOP CTL-809M was spun at 500 rpm for 10 sec and then at 1000 rpm for 20 sec. The first layer was bake d at 100C for 30 min to remove solvents after first spinning. Film of CYTOP with thickness gr eater than 2 m requires multiple spinning depending upon the target thickness of CYTOP film. Hence for the formation of 4 m thick film, CYTOP wa s spun for second time at 500 rpm for 10 sec and at 1000 rpm for 20 sec. The second layer wa s baked at 100C for 30 min. It was fully cured at 200C for 60 min. Figure 3.2 Schematic of Spin Coating of CYTOP 4m Thick Spin Coated CYTOP Layer 1.4m Thick Thermal SiO2 Layer
313.3.3 Buffer Oxide Etch (BOE) A free standing CYTOP layer with 4 m thickness was obtained by removing sacrificial SiO2 film. BOE (10:1) was used for this release process. The wafer was completely immersed in BOE (10:1) solution. An ultrasonic bath was used to expedite the release process. The total time required fo r this release process was found to be approximately 10 Hr with intermittent ultrasonic energy. Figure 3.3 Schematic of Released CYTOP Film 3.4 Bonding And Assembly of CIT Microarray The ring electrode and the e ndplate electrodes on either sides of ring electrode have to be aligned and bonded with a require d thickness of CYTOP film in between to form a CIT microarray. The steps involved in the assembly of CIT microarray were as follows 3.4.1 Step 1 Ring electrode and the endplate electr odes were cleaned with acetone in the ultrasonic bath before bonding. The ring electro de was heated to 120C using a hot plate. The four CYTOP layers were properly placed on the ring electrode. A tweezer was used to remove air pockets. The ring elec trode wafer was cooled down. The array of 1.6 mm diameter holes in ring el ectrode was aligned with corr esponding features on one of 4 m Thick Free Standing Layer of CYTOP
32the endplate electrodes with CYTOP as an insulation. A microscope with back side illumination facility was used for this alignment purpose. The two electrodes were bonded at 180C in a vacuum oven by appl ying a constant weight of 0.5 Kg. Figure 3.4 Schematic of First Endplate Electrode Bonding 3.4.2 Step 2 The portion of CYTOP visibl e from side B in figure 3.4 from side B has to be completely removed to avoid charging probl em during the operati on of CIT microarray and to clear the way for ions and electrons in and out of the CIT. Plasma etching (PE) was used for removing the CYTOP film. PT 72 was used for plasma etching. Plasma etching was done from both sides to en sure complete removal of CYTOP. The parameters used during PE of CYTOP are listed in table 3.2 Table 3.2 Parameters for PE of CYTOP O2 (Gas Flow)100 sccm Pressure 40 mTorr RF (Power) 100W Time 90 min Side A Side B Ring electrode 16m thick CYTOP layer Endplate electrode
333.4.3 Step3 The second endplate electrode was aligne d and bonded to the ring electrode as explained in step1 with a re quired thickness of CYTOP film in between two electrodes. Plasma etching was done on both sides to en sure complete rem oval of CYTOP. The parameters used for plasma et ching are listed in table 3.2. Figure 3.5 Schematic After First Plasma Etching Figure 3.6 Schematic After Second Endplate Bonding and Plasma Etch The device was tested for proper insu lation between the electrodes before mounting into the testing assembly. Side A Side B Ring electrode 16 m thick CYTOP layer Endplate electrode Side A Side B Ring Electrode 16 m Thick CYTOP Layer Endplate Electrode
34 CHAPTER 4 CYLINDRICAL ION TRAP (CIT) MICROARRAY TESTING AND EXPERIMENTATION The experimental setup to test miniatur e CIT structures was assembled at the Center for Ocean Technology (COT), Universi ty of South Florida, St. Petersburg. The test setup was designed for test ing miniature CIT stru ctures in the standard mass-selective instability mode. Experiments were carried out on a 4 mm diameter miniature CIT fabricated from stainless steel. The dimensi ons for the miniature CIT are shown in figure 4.1. Krypton, xenon, chloroform and PFTBA were us ed as analyte gases since the stable isotopes for these gases are well known. Figure 4.1 Schematic of the 4m m Diameter Miniature CIT 4.0mm 1.58mm 3.32mm Ring Electrode Endplate Electrode 1 End p late Electrode 2 High Voltage Insulation
354.1 Miniature CIT Test Setup The test assembly comprised of a vacuum housing with inlets for analytes and Helium buffer gas, a turbo pump capable of reaching pressures as low as 10-8 Torr, an electron gun for ionization with a raster power supply, a re sidual gas analyzer (RGA), a flange with electric feedthroughs with a mount for a miniature CIT in the vacuum chamber, and control electronics. Copper gask ets were used in between the flanges and vacuum housing to prevent leakag e of gases into the vacuum Figure 4.2 Schematic of a Miniature CIT Test Setup 4.1.1 Ionization Source Ion impact ionization was chosen as a method to ionize analytes. An EGA-1108, Kimball Physics Inc. electron gun was used for ionization. The electron gun uses a space Pulse Delay Generator Detector Power Supply Electron Gun Power Supply Oscillosco p e Residual Gas Analyzer (RGA) Broadband Power Amplifier Hi g h Volta g e Vacuum Waveform Generator Detector Current Preamplifier End p late Electrode 1 Endplate Electrode 2 Ring electrode Detecto r Axial Modulatio n Si g nal Com p ute r Electron Gun Filament Air Coil Grid Power supply
36charge limited refractory metal cathode to generate an uniform focusable beam. The cathode of the electron gun is heated by an is olated voltage source and the electrons are emitted by thermionic emission. The emitted elec trons are accelerated to full kinetic energy using a series of grids. One of the grid s, the electron gate gri d, is used to suppress the emission of electrons from the cathode pe rimeter to gain contro l over the ionization time in the CIT. The anode grid controls the energy and focus of the emitted electron beam. The raster power supply module RGDU3C, Kimball Physics Inc., gives precise control over the trajectory of the emitted beam of electrons to enable positioning of the electron beam at a particular CIT in an array at which ioni zation of analyte takes place. 4.1.2 Residual Gas Analyzer (RGA) A residual gas analyzer (MicropoleTM, Ferran Scientific) was incorporated into the system. The RGA monitors the partial pressures of indi vidual gases in the vacuum housing. The MicropoleTM is an array of quadrupole mass spectrometers. It consists of 16 quadrupole rods which provide 9 de tection areas. The MicropoleTM uses an electron impact ionization technique for ionization of the analytes. A mass range of 2-100 AMU can be obtained with a resolution of 1 AMU. The fastest achievable scan rate for this RGA is 0.6 sec/AMU. 4.1.3 Channeltron Detector A DeTech channeltron electron multiplier (Model: XP-2074) was used to collect the ions emerging out of mi niature CIT during the mass instability scan. The maximum
37voltage rating for this channeltron elect ron multiplier detector was 2000 V with a specified gain of 14x107. The optimum value of the distan ce between the detector and the endplate electrode for maximum de tection efficiency was 3.0 mm. Figure 4.3 Photograph of the Miniature CIT Test Setup 4.1.4 Miniature CIT Mounting The miniature CIT was positioned in the center of the vacuum housing. eV parts vacuum components by Kimball Physics Inc. we re used to mount the miniature CIT. The eV parts allow precise centeri ng of the miniature CIT into the vacuum housing which was important for correct ionization. Since high voltages have to be applied to the ring electrode and detector, the eV parts were carefully assembled and checked for any possible short circuit. Alumina spacers were used as an insulator for this particular application. The feedthroughs on the mounting fl ange include electric connections for the RF voltage, axial modulation signal to the cl osest endplate, detect or high voltage, and
38detector signal. Various gase s were introduced into the va cuum housing using a capillary with an inner diameter of 50 m. The test setup was equipped with needle valves for controlling the flow rates of ga ses entering the vacuum housing. Figure 4.4 Miniature CIT on a Mounting Flange 4.1.5 Timing Diagram Figure 4.5 shows the schematic of the timing sequence used for the mass instability scan. During ionization electron gate grid is turned on and a trapping voltage is applied to the ring electrode which creates a potential well that constraints ions with different masses to the center of the ion tr ap. Period A-B (38 ms) depicts the ionization period. The electron gate grid is turned off at B. The detector is turned on af ter a delay of 2.5 ms. Period B-C depicts the delay of 2.5 ms. This delay prevents saturation of the detector during ionization.
39 Figure 4.5 Schematic of Timing Sequence for Mass Instability Scan The amplitude of the rf voltage, with a frequency of 1.5 MHz-2.0MHz, at the ring electrode starts ramping when the detector is turned on at point C. During ramping, increasingly higher mass ions are ejected from the trap, which gives a mass separation in time. Period C-D (50 ms) depicts the ramping pe riod. The detector is turned off at point E after a delay of 2 ms and the total time sequence is repeated. 4.2 Voltage Breakdown Test for CYTOP The primary purpose of breakdown tests for CYTOP was to characterize the breakdown voltage with respect to CYTOP thickness. The effect of the operating frequency was also investigated on the br eakdown voltage of CYTOP. The test setup -130 V A B CD 38 ms 50 ms 40.5 ms 52 ms Filament ON Detector ON 330 V 130 V -330 V A B CD 38 ms 50 ms 40.5 ms 52 ms Filament ON Detector ON 330 V 130 V -330 V E
40for characterization of breakdown voltage as a function of CYTOP thickness was designed and assembled at Center for Ocean Technology, University of South Florida, St. Petersburg, FL. 4.2.1 Voltage Breakdown Test Setup The voltage breakdown test setup consiste d of a waveform generator, a broadband power amplifier, a DC power supply for broadband amplifier, an air coil (series resonating circuit) and an os cilloscope for monitoring sign als at various points in the circuit. Figure 4.2 shows the schematic of se tup for voltage breakdown test of CYTOP. The waveform generator, Wavetek-Da tron, Model 195, provided a sinusoidal waveform which was amplified to delive r a high sinusoidal current, at a frequency ranging from 1.5 MHz-4.0 MHz, to the series re sonating circuit. The waveform generator provides precise control over the magnitude and frequency of the sinusoidal waveform for series resonating circuit. The series resona ting circuit consists of an air coil and the capacitance of the CIT. The output of the br oadband power amplifier was applied across two dummy electrodes. A standard procedure for CYTOP releas e as explained in Section 3.3 was used for releasing multiple CYTOP layers of 4 m thickness. 1cmx1cm pieces of Silicon with nickel electroless plati ng were used as dummy electrodes. During these experiments, the thickness of CYTOP between adjacent electrodes was varied. A low temperature bonding technique as explained in section 3.4 was used to bond two electrodes with CYTOP as an insulation. The electrical conn ections to the electrodes were made using common soldering technique.
41 Figure 4.6 Schematic of Voltage Breakdown Test Setup 4.2.2 Voltage Breakdown Test Procedure The breakdown voltage tests were conduc ted for different CYTOP thicknesses e.g., 8 m, 16 m, and 32 m etc. The re sonance frequencies for the circuit were observed by changing the frequency of the sinus oidal wave from the waveform generator. At the resonance frequency, the magnitude of the voltage across the two adjacent electrodes was increased and monitored for CYTOP breakdown. The procedure was repeated at higher frequencies using an ai r coil with lower inductance to observe the effect on the breakdown voltage at higher frequencies. WAVEFORM GENERATOR BROADBAND POWER AMPLIFIER POWER SUPPLY OSCILLOSCOPE END CAP ELECTRODES RING ELECTRODE AIR COIL HIGH VOLTAGE
42 CHAPTER 5 RESULTS AND DISCUSSION A variety of experiments were perf ormed during the fabrication of CIT microarray for tunable mass spectrometer. These experiments mainly include characterization of various processes, that gives an idea about the effect of various parameters involved in a process. The initial st ep in any processing fi eld application is to design a process flow that includes designing of masks required at various stages in the entire process flow. For this particular application, lit hography, electr oless plating, bonding and DRIE etc. were characterized at va rious stages during the entire fabrication. A theoretical understanding of various techni ques and equipments was essential for the precise dimension control of components to be fabricated (Chapt er 2 and Chapter 3). 5.1 Endplate Electrode Fabrication (Experimental) Microfabrication of endplate electrodes were fabricated with 5m diameter through holes with 10 m pitch in a silic on wafer. The aspect ratio for DRIE and incompatibility of the equipments for wafers thinner than 250 m, were the two important issues responsible for modified process flow, (section 2.1.2) that required processing on both sides of silicon wafer. A standard 4 n-type<100> double side polished (DSP) silicon wafer was used for th e fabrication of endplate electrodes. The
43approach of bulk micromachining was used for the fabrication of structures with high aspect ratios. Various technique s used during the entire fabr ication and observed values for parameters are as follows, 5.1.1 PECVD of SiO2 SiO2 deposited using PECVD technique was us ed as a hard mask for DRIE during fabrication of endplate electrodes (see secti on 2.1.2, step 1). It was also used to check Helium leak due to through holes (see secti on 2.1.2, step 8). A load locked single wafer deposition tool by GSI was used for depositing amorphous SiO2 film. A standard recipe for the deposition of undoped SiO2 suitable for DRIE was used. Various parameters for this recipe are listed in appendix A (section 6.1.4). The specified deposition rate for undoped SiO2 was 2600 A/min. The deposition time for 3.6 m thick SiO2 that was used as a hard mask for DRIE was 15 min. Hence the observed deposition rate for PECVD was 2400 A/min. The time required for depositing a layer of 1.5 m that was used to check Helium leak was 8 min. Hence the observed deposition rate during this step was 2100 A/min. The index for SiO2 deposited using PECVD was found to be 1.4. The specified compressive stress for PECVD SiO2 was 291 MPa. 5.1.2 RIE of SiO2 Hard Mask Plasma Them 72 was used for RIE of SiO2 hard mask. The specified value for etch rate of thermal oxide was approx imately 300-400 A/min. A standard recipe
44available for RIE of SiO2 was used. Various parameters em ployed for RIE are listed in appendix A (section 6.1.4). The RIE was done for 90 min, which ensured complete patterning of 3.6 m thermal SiO2. 5.1.3 DRIE The modified process flow based on bulk micromachining used DRIE as a tool for fabricating structures w ith high aspect ratios. Unaxis 770 ICP Etcher was used for DRIE during the fabrication of endplate elect rode. Important features of Unaxis 770 ICP Etcher are listed in appendix A (section 6.1.1). SiO2 was used as a hard mask for DRIE. The parameters used during DRIE ar e listed in appendix A (section 6.1.1). DRIE was done multiple number of times during the entire fabrication of endplate electrode. The results obtained during DRIE can be summarized as listed in table 5.1 Table 5.1 Observed Etch Rates for DRIE Feature SizeEtch Depth Etch Time Etch Rate 1600 m 150-160 m100-105 min1.5 m/min No mask 40-45 m 35-40 min 1.14 m/min 5 m 60-50 m 35 min 1.42 m/min The etch rate was found to be dependent on feature size. The etch rate reduced with the increased feature size for same ope rating parameters. The etch rate was also
45found to be dependent on the position of th e feature in the chamber. The non uniform etch rate throughout the wafer surface indicated non uniformity of plasma in the chamber. It was observed that the etch rate during backside thinning was less because entire wafer was exposed to the high density plasma as co mpared to a patterned wafer with partial masking. 5.1.4 Ashing After developing photoresist with endplate mask in step 7 (see section 126.96.36.199), a short ashing run was done using PT72 in the RIE chamber. The parameters used for photoresist ashing are listed in table 3.4. The specified etch rate for photoresist ashing was 100 nm/min. The ashing was done for 2 min. The short spell of photoresist ashing run using oxygen plasma minimizes imperfections in the patterned photoresist due to various patterning issues such as overexposure and underdevelopment. This short sp ell of RIE ensures vertically straight walls for the patterned photoresist which in turn minimizes scalloping effect on the side walls of the through holes during DRIE. Figure 5.1 Optical Microscope Photograph of Top View and SEM Photograph of Side View of Endplate Electrode
465.1.5 Removal of Bosch Polymer No standard procedure is available to remove this black polymer which gets deposited on the side walls of the through holes during DRIE. The recommended techniques for removal of Bosch polymer are HF dip, MOS cleans, ashing using oxygen plasma and nanostrip dip which is also know n as piranha dip were used to partially remove Bosch polymer deposited during DRIE. Figure 5.2 SEM Photograph of Cross Sec tion (3D View) of Endplate Electrode Figure 5.3 SEM Photograph of Cross S ection of Endplate Electrode
475.2 Ring Electrode Fabrication (Experimental) An n type <100> double side polished (DSP), 2, 1600 m thick silicon wafer with a resistivity 1-5 -cm was used for the fabrication of ring electrode. A disc cutter by Gatan Inc. (Model 601) was used to drill 4x4 array of 1.6 mm diameter through holes in a patterned 1600 m thick silicon wafer. Ultrasonic drilling was found to be a fast er technique for dril ling holes in silicon substrate that required relatively low axial load and power. The topography of the drilled holes showed an effect of tool feed rate and axial load on the amount of chipping at the edges. The chipping at the edges due to ultr asonic drilling can be minimized by using low tool feed rate. The wafer was lapped with 12 m alumina type lapping compound after drilling holes to reduce the eff ect of chipping on the edges. Figure 5.4 Optical Microscope Photograph of 4x4 Array Fabricated using Ultrasonic Drilling
48 Figure 5.5 Optical Microscope Photograph of Enlarged View of a Single Hole Fabricat ed using Ultrasonic Drilling 5.3 Metallization of Electrodes ENPLATE NI -425 electroless nickel process was used for the metallization of electrodes that further acted as a seed layer for electroless gold process. The specified deposition rate for ENPLATE NI -425 electr oless nickel process was 0.2 m/min at 88C. The plating was done for 30 sec at 90 C at a pH value of 4.9. The wafers were subjected to post baking at 300C for 30 mi n. The observed value of surface resistivity using four point probe was 29.6 m -cm. Figure 5.6 Optical Microscope Photograph of Endplate Electrode After Electroless Nickel Plating
49The initial plating experiments of en dplate electrodes with ENPLATE NI -425 Electroless Nickel process showed improper ad hesion to the substrate. Hence the wafers were partially etched by using Fluoride-Bi fluoride-Hydrofluoric acid buffer with stabilized HF activity for 4 min prior to electroless plating. This made the surface conducive for improved adhesion of nickel to the substrate. Figure 5.7 Optical Microscope Phot ograph Showing Improper Adhesion Of Gold to the Substrate The ring electrode was lapped with a 12 m alumina type lapping compound before ENPLATE NI -425 electroless nickel process. The lapping made the surface rough and conducive for improved adhesion of ni ckel to the substrate. The parameter used during ENPLATE NI -425 electroless nickel are listed in appendix A (section A.3). The plating time was 1 min. Bright Electroless Gold by Transene Company Inc. was used for the gold plating of ring electrode. The plating was done at 90C with a pH value of 8. The plating
50time was 15 min. The sample was baked at 300C for 30 min. Figure 5.7 shows the improper adhesion of electroless gold to the substrate due to impurities. The sample was carried from electroless nickel bath to bri ght electroless gold bath in a DI water rinse which minimized the chances of oxidation of nickel. Figure 5.8 Optical Microscope Photograph of Ring Electrode After Gold Electroless plating 5.4 CIT Microarray Assembly CYTOP CTL-809M, a class of perfluoropolymer was used as an insulation and a bonding material between two adjacen t electrodes. A free standing layer of CYTOP was obtained by using a release pr ocess as explained in section 3.3. The bonding was done in vacuum oven at 180C for 30 min with a constant load of 0.5 Kg. Plasma etching was used to remove CYTOP present between the ring electrode and the endplate electrodes in each CIT. The paramete rs used for plasma etching are listed in table 3.2. The etch time for 16 m thick CYTOP layer was 90 min. The measured value of capacitance of the device with two endplate electrodes shorted was 180 pF.
51 Figure 5.9 CIT Microarray 5.5 Voltage Breakdown Tests for CYTOP The voltage breakdown tests were perf ormed to characterize the breakdown voltage with respect to CYTOP thickness. The effect of operating frequency on the breakdown voltage was also investigated. 1cmx1cm pieces of silicon with nickel electroless plating were used as dummy el ectrodes. The voltage breakdown tests were conducted on 8 m, 16 m, and 32 m etc. thick CYTOP layers between the electrodes. A low temperature bonding technique as explained in section 3.4 was used for bonding two dummy electrodes. Table 5.2 shows the observed values for breakdown voltages at various frequencies for different CYTOP thickne sses. It was observed that the value breakdown voltage increases with the thic kness of the CYTOP. It can also be concluded from the experimental results that for a CYTOP layer of same thickness the breakdown voltage increases significantly with increasing values of operating frequency.
52Table 5.2 Effect of Operating Frequenc y on Voltage Breakdown of CYTOP CYTOP Thickness (m) Frequency (MHz) Breakdown Voltage (KV) 8 4.2 0.04 2.68 0.4 2.70 0.9 16 3.48 1.47 1.5 1.38 3.0 1.4 32 3.5 1.7 A 16 m thick layer of CYTOP was chosen for the fabrication of CIT microarray since the expected value for operating voltage and frequency during mass selective instability mode we re 1.0 KV and 2.0 MHz respectively. 5.6 Miniature CIT Testing The testing experiments were performe d on a 4.0 mm diameter CIT and a CIT microarray. The devices were operated in st andard mass-selective instability mode. 5.6.1 Testing of a 4.0 mm CIT The timing pulse, described in sectio n 4.1.5, was applied to the ring electrode during mass selective instability scan. The operating frequency of the voltage was 1.76
53MHz. An axial modulation of amplitude 7.5 V(0-peak) was applied to one of the endplate electrodes at a frequency 0.56 MHz. The magnitude of voltage applied du ring ion storage period (A-B) was 130 V(0peak) A delay of 2 ms was introduced between the electron gate grid turn off and the detector turn on. During the ramp period (C-D ), the magnitude of voltage was gradually increased to a value of 330 V(0-peak ). The magnitude of detector voltage during ramping time was 1.75 KV. The optimum value of ramping time was found to be 50 ms. Chloroform was used as an analyte. He lium was used as a buffer gas. The total pressure of the gases in vacuum housing was 5x10-4 Torr. The total pressure inside vacuum housing with no helium was 1.2x10-5 Torr. The total pressure for back ground gases in the vacuum housing (withou t helium and chloroform) was 2x10-6 Torr. Figure 5.10, shows a mass spectrum for chloroform (Courtesy NIST chemistry webbook). Figure 5.10 Mass Spectrum Showing Isotopes for Chloroform
54 Figure 5.11, shows the mass spectrum obtai ned during mass selective instability scan for chloroform using 4.0 mm CIT. Three major peaks are visible for the Chloroform isotopes with m/z of 83, 85, and 87. Chloroform 2.5 10-5 Torr Helium buffer gas 5.7 10-4 Torr0.663 0.665 0.667 0.669 0.671 0.673 0.675 0.677 0.679 0.681 60708090100110120130140 m/z (Th)Signal intensity Figure 5.11 Mass Spectrum for Chlo roform Obtained During Mass Selective Instability Scan with a 4.0 mm CIT
555.6.2 CIT Microarray Testing The experiments were performed to op erate CIT microarray in a standard mass instability mode. Chloroform was used as an analyte gas. Helium was used as a buffer gas. The timing pulse, described in section 4.1.5, was applied to the ring electrode during mass selective instability scan. The observed resonance frequencies for the device were 4.02 MHz at 14.5 V and 3.25 MHz at 75 V. An axial modulation of amplitude 7.5 V(0-peak) was applied to one of the endplate electrodes at a frequency 0.56 MH z. The testing was stopped due to failure of insulation between the endplate and the ring electrode. Further testing of the CIT microarray was not possible because all the endp late electrode grid samples fabricated at CNF were exhausted. The results obtained du ring testing of CIT microarray were not consistent to be reported. 5.7 Discussion The CIT microarray device failed during th e final stages of te sting. There can be variety of reasons for the failure of the devi ce. Various factors responsible for the failure of the device can be summarized as follows: 5.7.1 Endplate Electrode Design The primary function of endplate electrode gr ids, in a CIT microarray, is to allow path for entry and egress of ions. The endplate mask was designed with arrays of circular
56patterns with 5 m diameter holes and 10 m pitch. The modified process flow (see section 2.2) was used for fabri cating endplate electrode grid. During the modified process flow, the wafe rs were processed from both sides to fabricate 5 m diameter through holes with 10 m pitch. The endplate electrode grid fabricated using modified process flow had a thickness of 40-45 m at the grid portion. Due to this fact the endplate grid wafers we re very fragile and created handling problems during electroless plating, bonding and device handling. Figure 5.12 Schematic and SEM P hotograph of Endplate Grid The endplate electrode wafers were frag ile and could not be diced using a dicing saw. Hence the wafers were manually scribe d and cleaved using a diamond tip cutter to prepare endplate electrode grids. Manual cut ting left sharp edges at the corners of the endplate electrode grid used for assembli ng CIT microarray. The application of RF voltages of high magnitude can cause high poten tial points at the shar p edges. These high Side A Side B
57potential points at the sharp edges could cause electrical s hort circuit between the ring electrode and the endplate electrode. The broken pieces of endplate grid tr apped into the CIT could cause the breakdown of an insulation between the ring electrode and the endpl ate electrode (see figure 11.6). These broken pieces of endplate grid can cause electr ical short circuit between the ring electrode and the endplate when high voltages are applied to the ring electrode. Figure 5.13 Schematic of CIT Micr oarray with Broken Pieces of Endplate Grid 5.7.2 Electroless Nickel Plat ing of Endplate Grid The endplate grid was metallized using electroless nickel plating. The initial plating experiments showed improper adhesion of nickel to the subs trate (see figure 5.7). A Fluoride-Bifluoride-Hydrofl uoric acid buffer with stabi lized HF activity was used which showed improved adhesion of nickel to the substrate. Furt her gold electroless plating on endplate electrode grid showed clogging of 5m diameter through holes. Hence the endplate grid with only nickel electroless plating was used in a CIT microarray. Broken pieces of endplate grid
58 The RF voltages of magnitude 1.0 KV and frequency 1.76 MHz were applied to the ring electrode during mass-instability s can. The application of RF voltages of magnitude 1.47 KV and frequency of 3.48 MHz resulted into excessive heating of electroless nickel plated substrates during voltage breakdown tests for CYTOP. The melting of nickel plated endplate electrode grid was observed during voltage breakdown tests for CYTOP as shown in figure 11.7. Figure 5.14 Optical Micros cope Photograph of Melted Endplate Grid Due to Excessive Heating due to RF Voltages The excessive heat produced due to a pplication of RF voltages can degenerate CYTOP that could cause breakdown of in sulation between the ring electrode and the endplate electrode. 5.7.3 CYTOP (Organic Insulator) CYTOP is an organic material obtai ned by cyclopolymerization of perfluoro. CYTOP is known to degenerate hydrofl uoric acid, perfluoro product isobuthylene and other harmful substances by thermal decomposition under high temperature and low
59operating pressures. The heating of electro de due to application of RF voltages of high magnitude could cause degeneration of CYTOP resulting into degassing. The degassing due to excessive heat may form ai r-pockets in the CYTOP layer that could cause electrical short circuit between the ring electrode a nd the endplate electrodes. 5.8 Future Work The analysis of failure of the CIT microa rray during the final stages of testing proved that there is a need to modify th e design of an endplate electrode grid. The circular features of size 5 m diameter posed problems during fabrication and electroless plating of an endplate electrode grid. The modi fied process flow used for the fabrication of an endplate electrode grid with 5 m diameter through holes resulted into very fragile structures. Hence handling of the CIT microa rray became tedious. The electroless plating experiments on an endplate electrode grid st ructure showed that the chances of clogging of more through holes increase with the electroless gold pl ating. Hence only electroless nickel plating was used for an endplate electr ode. This resulted into excessive heating of the substrate which in turn caused breakdown of an insulation betw een the ring electrode and the endplate electrodes. The new design of an endplate electrode would carry circular holes with 20 m diameter and 40 m pitch. This new design w ould not require processing on both sides of the wafer, since the through holes of 20 m di ameter can be etched in a standard 250 m thick wafer using DRIE. The endplate electrode grid would be having more strength as compared to the previous design. The pr oblem of clogging of through holes due to
60electroless gold over seed layer of elect roless nickel would be minimized due to increased feature size in an endplate electrode grid. The 1600 m diameter circular patterns of the ring electrode were of the same size as that of the diameter of array with 5 m diameter ci rcular patterns in an endplate electrode grid. Hence the alignment of the ri ng electrode and the e ndplate electrode grid during bonding of the device was critical. In the new design th e size of the arrays with 20 m diameter circular patterns in an endplat e electrode grid would be greater than the individual ring electrode diamet er as shown in figure 11.8. Figure 5.15 Schematic of New Endpl ate Electrode Grid Design The failure of an insulation between th e ring electrode and th e endplate electrodes due to various issues discussed above necess itates search for a ne w inorganic insulating material which is free from degassing problems. Endplate Electrode Grid Ring Electrode 1600 m 1800 m
61 REFERENCES  Raymond E. March, John F. J. Todd, Practical Aspects of Ion Trap Mass Spectrometry, Vol. 2(1995).  J. Mitchell Wells, Ethan R. Badma n, and R. Graham Cooks, A quadrupole Ion Trap with Cylindrical Geometry Operated in the Mass-Selective Instability Mode, Analytical Chemistry, Vol. 70(1998), 438-444.  Oleg Kornienko, Peter T. A. Reilly, W illiam B. Whitten, and J. Michael Ramsey, Electron Impact ionization in a micr oion Trap Mass Spectrometer, Rev. of Scientific Instruments, Vol. 70(1999), 3907-3909.  Ethan R. Badman, Rudolph c. Johnson, Wolfgang r. Plass, and R. Graham Cooks , A miniature Cylindrical Quadrupole I on Trap: Simulation and Experiment, Analytical Chemistry, Vol. 70(1998), 4896-4901.  Ethan R. Badman and R. Graham Cooks, A Parallel Miniature Cylindrical Ion Trap Array, Analytical Ch emistry, Vol.72 (2000), 3291-3297.  Himani Peddanenikalva, Kiran Potlu ri, Shekhar Bhansali, R. Timothy Short and David Fries, A Microfabrication St rategy for Cylindrical ion trap Mass Spectrometer Arrays, Sensors, Vol.1(2002), 651-655.  A.A. Ayon, C.C. Lin, R. A. Braff, R. Bayt, H. H. Sawin and M. A. Schimidt, Etching Characteristics ad Pr ofile Control in a Time Multiplexed Inductively Coupled Plasma Etcher, Solid State Sensor and Actuator Workshop, Hilton Head, SC, 1998, pp. 41-44.  Raymond E. March, Richard J. Hughes, Quadrupole Storage Mass Spectrometry, (1989).  Oleg Kornienko, Peter T. A. Reill y, William B. Whitten, and J. Michael Ramsey, Microscale Ion Traps: 2-Dimensional Arrays.  A. A. Ayon, X. Zhang, and R. Khanna Ultra Deep Anisotropic Silicon Trenches Using Deep Reactive Ion Etching (DRIE) , Solid-State Sensor and Actuator Workshop, Hilton Head, South Carolina, 2000, pp. 339-342.
62 S. A. McAuley, H. Ashraf, L. Chambers S. Hall, J. Hopkins, and G. Nicholls, Silicon Micromachining Using a High-Density Plasma Source, Journal of Physics D: Applied Physics, 34 (2001), 2769-2774.  Stefan Vogel, Ulrich Kuhl, Rainer Sc hafflik, H. Pradel, F. Kozlowski, and B. Hillerich, Novel Microstr ucturing Technologies in Si licon, MicrosystemtechnikSymposium Zur Productronica, 1997.  J. Bharadwaj, H. Ashraf, and A. Mc Quarrie, Dry Silicon Etching for MEMS, The Symposium on Microstructures and Micr ofabricated Systems, Electrochemical Society, Montreal, Quebec, Canada, 1997, 1-13.  A. A. Ayon, R. Bra ff, C. C. Lin, H. H. Sawin, and M. A. Schmidt, Characterization of a Time Multiplexed Inductively Coupled Plasma Etcher, Journal of The Electrochemi cal Society, Vol.146(1999), 339-349.  CYTOP Technical Informa tion Manual, Asahi Glass Company.  Technical Data Sheet, ENPLATE NI-425.  Technical Data Sheet, CUPOSIT Accelerator 19, Shipley.  Technical Data Sheet, CATAPOSIT Catalyst, Shipley.  Technical Data Sheet, CIRCUPOSIT Conditioner 3320, Shipley.  M. Madou, Fundamentals of Microfab rication, CRC Press, Boca Raton, Florida, 1997.  Nadim Maluf, An Introduction to Microelectromechanical Systems Engineering, Artech House, January 2000.  Operation Manual, Unaxis 770 ICP, CNF.  Operation Manual, Plasma Therm 72, CNF.  Operation Manual, GS I PECVD Tool, CNF.  Ethan R. Badman and R. Graham Co oks, A Parallel Miniature Cylindrical Ion Trap Array", Analytical Ch emistry, Vol. 72 (2000), pp 3291-3297.
64Appendix A Equipments and Process Recipes A.1 Deep Reactive Ion Etching (DRIE) Unaxis 770 ICP Etcher was used for DRIE during the fabrication of CIT microarray. The fact that a high density pl asma can be achieved by transferring power into bulk plasma via the magnetic field resu ltant from inductive coupling is employed in this ICP etcher. In this case, a conventi onal SLR system was modified to accommodate an ICP source. In an ICP system, a high density plasma discharge is generated by applying RF power into an inductive coil capable of transforming power into a low pressure gas. Hence the coupling mechanism is different than standard diode type reactive ion etching machine in a way that power is applie d magnetically rather than directly through electric field. This machin e is also equipped with a high conductance pumping system which allows for relativel y low operating pressures of high density plasma system. Figure A.1 Schematic of Cylindrical ICP Source for Unaxis 770 The ICP source for this particular machin e is based on cylindrical configuration. In this configuration, a dielectric vessel is surrounded by an inductive Substrate RF Coil Substrate Bias Voltage Source
65Appendix A (Continued) coil to which rf energy is applied. The rf coil is designed in such a way to maximize source current thereby maximizing the efficien cy in plasma generation. This kind of coil configuration is very effec tive in coupling rf power into the low pressure gaseous medium. The rf energy in the coil induces a strong magnetic field at the center of the chamber that is responsible for producing a high density plasma in this chamber. The ion current density and the plasma density can be controlled by adjusting the power level applied to the high density sour ce. The frequency of the rf pow er in the coil is adjustable between 1.7MHz and 2.1MHz. This frequency is kept low to reduce the rf impedance of the coil which allows large currents through the coil. This frequency of rf power should be greater than the average ion transit freque ncies to avoid direct acceleration of ions by rf energy. The low operating pressures also en sures that the excited plasma species are less susceptible to collisional recombination which assures high density plasma at reasonable power levels. In addition to this, lo w operating pressure also enables the ions to traverse the sheath above substrate without multiple body collisions. This collision free sheath ensures that the ions are driven norma l to the substrate which is of paramount importance when perfectly straight sidewa lls are required. The lower electrode is powered with 13.56 MHz and allows the bias volta ge to be controlled independent of the total input power. A separate voltage source is used to control the bias voltage to the substrate. A standard Bosch process used for DRIE c onsists of a cycle which is repeated for specific number of times as per the etch de pth requirement. Each cycle is a combination of two steps namely a deposition st ep and an etch step. During
66Appendix A (Continued) deposition, a passivation layer is depo sited all over the substrate. C4 F8 is the only necessary gas during depositi on step. At this time, SF6 is kept low to keep the flow controller in on state as the de position and etch steps are short and this avoids the time required to switch on the flow controller. Vari ous parameters such as time, pressure, and gas flows can be adjusted to achieve a specifi c etch rate. The bias voltage is not required during this step, still this power is kept low so as to keep the power supply in on state. During etch step, the passivation on the substr ate is removed and the silicon underneath is etched. SF6 is the only necessary gas during etch step and the at this time C4 F8 is kept low to keep the flow controller in on state. Bias voltage is applied to the substrate by switching on the substrate power supply. Vari ous parameters used during standard Bosch process for DRIE are listed in table A1. Table A.1 Process Parameters During Bosch Process for DRIE  Cycle Deposition Step Etch Step Pressure (mTorr)23 23 C4F8 (sccm) 70 0.3 SF6 (sccm) 0.3 100 Ar (sccm) 50 50 RF1 (W) 0.1 8 RF2 (W) 850 850
67Appendix A (Continued) A.2 Photolithography The fabrication of high aspect ratio stru ctures using bulk micromachining requires patterning of the masking material at va rious stages. Photolithography is a commonly used technique for patterning of a mask ing material. Photolithography utilizes a photosensitive material that changes its chemical properties upon illumination with a radiation. UV light sources are commonly used during photolithography. Various exposure wavelength technologies such as Iline (365 nm), G-line (436 nm), and broad band (380-450 nm) etc., are availa ble for specific applications. Photosensitive material used dur ing photolithography is commonly known as photoresist. Photoresist can also be used as a masking material for bulk micromachining. Various techniques such as spin coating, spra ying, lamination, and el ectroplating etc. are available for applying photoresist to the substr ate. The substrates are cleaned and exposed to a reagent, hexamethyldisilizane (HMDS) which improves adhesion of photoresist to the substrate. Spin coating technique was used fo r the applying photoresist. Various photoresists and parameters used during CIT microfabrication are listed in table A2. Table A.2 Photoresists and Pr ocess Parameters for Spinning Photoresist STR 1045Shipley 1813 Spin Speed (rpm) 5000 4000 Spin Time (sec) 30 30 Soft Bake Temperature (C)90 115
68Appendix A (Continued) Table A.1 continued Soft Bake Time (sec) 90 60 Exposure Time (sec) 4.5 3.5 Developer MIF 300MIF 321 Developing Time (min)5 1 Thickness (m) 3.6 1.8 A.3 Nickel Electroless Plating The plating experiments were perfor med at Center for Ocean Technology, University of South Florida, St. Peters burg. ENPLATE NI-425 was used for nickel electroless plating. A specified procedure for sample cleaning and preparation was followed. Various steps involved during nickel electroless plating are as follows: A.3.1 Solution Preparation The solution was heated to 85C. The pH value of the solution was monitored and adjusted to 4.9 by adding dilute ammonium hydroxide. The solution was heated at 90C and continuously stirre d using a horizontal rod. A.3.2 Conditioning Conditioning constitutes the initial step for sample preparation. This process was patented by Shipley and it uses CI RCUPOSIT CONDITIONER 3320 which is
69Appendix A (Continued) mildly acidic for conditioning of the samples. The normality and PH value of the baths was maintained at 0.49 and 2.0 respectivel y. The bath was maintained at a Appendix A (Continued) constant temperature of 125F. The samples were immersed into the solution and continuously agitated. The main objectives of conditioning step are as follows 1. It promotes the absorption of conformal thin layer of catalyst. 2. It eliminates the chances of over-cat alyzation thereby producing conformal coating of electroless nickel. A.3.3 Catalyzation CATAPOSIT 44, CATALYST is a patente d, tin palladium colloidal catalyst specially formulated to seed the nonconduc tive surfaces for complete and uniform deposition of electroless nickel. It is mildly acidic, chloride containing catalyst that is nonvolatile and nonfuming. The sample was dipp ed into catalyst pre-dip before going into catalyst bath which protects catalyst from harmful drag-in and thus maintain its superior performance and extend its life. Th e bath was maintained at a constant temperature of 125F and the sample was dipped and agitated mechanically for 5 min. The main objectives of catalyzation step are as follows 1. It promotes complete and uniform electroless metallization.
70Appendix A (Continued) 2. It also promotes excellent adhesion of electroless metal to conductive as well as nonconductive surfaces A.3.4 Accelerator Bath CUDEPOSIT ACCELERATOR 19 c onstitutes an important step in the electroless plating as it modifies the absorbed catalyst to allow quick and uniform metal deposition. Accelerato r solution was prepared by adding one part of ACCELERTOR 19 solution to 5 parts of di stilled water. The sample was dipped vertically and agitated into the solution for 5-8min at room temperature. The main objectives of accelerator step are as follows 1. It assures rapid and uniform electroless nickel coverage. 2. Prevents voids that can be cau sed by over-aggress ive acceleration. A.3.5 Plating Bath Finally the sample was rinsed properly for 30 sec in deionized water and then immersed into electroless nickel plat ing solution. The plating rate depends on temperature of the solution, PH value and the plating time etc. The sample was rinsed after plating and annealed at 300 degree Celsius for 30min. A.4 Plasma Enhanced Chemical Vapor Deposition (PECVD) GSI tool, at Cornell Nanof abrication Facility (CNF), was used for deposition of undoped SiO2 GSI is a load locked si ngle wafer deposition tool for
71Appendix A (Continued) deposition of oxides, nitrides, and amorphous silicon films. GSI employs plasma enhanced chemical deposition (PECVD) technique for deposition. Films with thicknesses ranging from 1000A to several micr ons can be deposited using GSI. Undoped SiO2 suitable for DRIE was used as masking layer. The parameters used during PECVD are listed in table A3. Table A.3 Process Parameters for PECVD using GSI N2 (Gas Flow) 1800sccm SiH4 (Gas Flow)18sccm N2O (Gas Flow)1800sccm RF1 (Power) 300W Temperature 400C A.5 Reactive Ion Etching (RIE) Plasma Therm 72, at Cornell Nanofabrication Facility (CNF) was used for reactive ion etching (RIE), dur ing the fabrication of CIT microarray. RIE was used for etching SiO2, which was used as a hard mask for DRIE. Plasma Therm 72 was also used for descumming, where oxygen plasma was used for etching photoresist. RIE offers anisotropic profiles which in turn mi nimize scalloping effect during DRIE. A standard recipe for SiO2 / Si 3N4 was used for RIE during the fabrication of CIT microarray. The parameters used during RIE are listed in table A4. The etch rate
72Appendix A (Continued) for SiO2 / Si 3N4 depends on power. The etch rate in creases with the increasing power. The limit being set by stability of photoresis t. The stability of photoresist can be increased by increasing the post bake temper ature. Pressure and gas flows have very small effect on the etch rate. Oxygen (appr ox. 5%) is used during RIE that prevents excessive polymer formation. The speci fied etch rate for thermal SiO2 was 300400A/min. The approximate value of selectivity of SiO2/photoresist was 3:1. Table A.4 Process Parameters for RIE using PT-72 CHF3 (Gas Flow)45 sccm O2 (Gas Flow) 10 sccm Temperature 35C Pressure 40 mTorr RF (Power) 150 W DC (Power) 450 V
73Appendix B Vendors and Contacts Photoresist Vendor : Shipley Company Address: EFI Headquarters, 272 Buffa lo Avenue, Freeport, NY, USA 11520 Phone : 800-645-2996 Fax : 516-868-8074 Website : www.shipley.com CYTOP (CTL-809M) Vendor : Bellex International Corporation Address : 501 Carr Road, Suite 100, Wilmington, DE 19809 Phone: 302-761-9886 Miscellaneous 1. Chemical Supplies (Acetone, Me thanol, HF (49%), BOE (10:1)) Vendor: Doe & Ingalls of Florida Inc. Address : 9940 Currie Davis Driv e, Suite 0-16, Tampa, FL 33619 Phone : 813-622-8824 2. Dicing Blade Vendor : Thermocarbon Inc. Address : PO Box 181220, Casselberry, FL 32718 3. Electroless Plating Solutions Vendor : Surface Finishing Technologies
74Appendix B (Continued) Address : 12200, 34th Street North, Clearwater, FL 33762 Phone : 727-578-7664 Website : www.technic.com
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Fabrication and testing of a cylindrical ion trap microarray for tunable mass spectrometers
h [electronic resource] /
by Mangesh Telrandhe.
[Tampa, Fla.] :
University of South Florida,
Thesis (M.S.E.E.)--University of South Florida, 2004.
Includes bibliographical references.
Text (Electronic thesis) in PDF format.
System requirements: World Wide Web browser and PDF reader.
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ABSTRACT: This research presents a novel microfabrication approach and testing methodology for cylindrical ion trap (CIT) microarray tunable for mass- spectrometers. The growing interest in cylindrical ion trap (CIT) mass-spectrometers is primarily due to ease with which cylindrical geometry can be realized as compared to hyperbolic surfaces found in conventional quadrupole ion traps. Also due to the fact that the potential at the center of hyperbolic electrode in quadrupole ion trap and cylindrical electrode in cylindrical ion trap (CIT) does not differ significantly. Since the RF voltage required to eject a given mass-to-charge ion scales as the square of the ion trap radius, a decrease in ion trap dimensions provides a significant reduction in electronics requirements, thereby providing a pathway for overall system miniaturization. The reduction in sensitivity due to reduced ion storage capacity as a result of miniaturization can be improved by employing an array of identically sized ion traps. Microfabrication approach promises excellent uniformity in the fabrication of identically sized holes which in turn leads to low-cost high performance CIT microarray for mass spectrometers[1,2]. The criterion used for the determination of trap diameter was to ensure that the hole to be 1.09 times the wafer thickness to provide optimal potential to trap ions. The end- plates were designed to optimize the electron and ion transmission into and out of the ion trap and provide a high quality electric field definition within each cylindrical ion trap (CIT). Two different approaches, namely deep reactive ion etching (DRIE) and mechanical drilling using ultrasonic disc cutter were proposed and used for the fabrication of ring-electrode which forms the main body of the ion trap. Excellent uniformity in hole diameter was observed in both the approaches. The end-plates were fabricated using deep reactive ion etching (DRIE) which provided high transmission rigid grid structure for ions and electrons. Standard Bosch process was used for deep reactive ion etching (DRIE). The two electrodes were metallized using electroless plating which provides excellent uniformity of coating even on end-plate structures with 5micro m through holes. CYTOP[trademark], a cyclized perfluoro polymer, was used as an insulation layer and intermediate bonding layer between the ring electrode and end-plates. The breakdown voltage for a released 16 micro m thick CYTOP[trademark] layer was found to be 1.47KV. An assembly for testing miniature cylindrical ion trap (CIT) was designed and built. An electron impact ionization source was used for generation of ions. Mass selective instability scan was used to selectively eject ions with different mass-to-charge ratio. A cylindrical ion trap (CIT) with 4mm diameter was fabricated and tested for analyte gases such as krypton and xenon.
Adviser: Bhansali, Shekhar
mass instability scan.
voltage breakdown test.
x Electrical Engineering
t USF Electronic Theses and Dissertations.