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Characterization of HfO2 Films for Flash Memory Applications by Surendra Gaddipati A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Y. L. Chiou, Ph.D. Andrew M. Hoff, Ph.D. Don Morel, Ph.D. Date of Approval: June 28, 2004 Keywords: control oxide, high-k, hafnium oxide, poole-frenkel, conduction mechanism Copyright 2004, Gaddipati Surendra
Acknowledgements I take this opportunity to thank each and everyone who is directly or indirectly involved in the completion of my thesis: First of all I like to thank my uncle Mr. G. S. Rao who has given me an opportunity to come here and pursue my Masters degree through his financial support. I would also like to extend my gratitude to my major professor Dr. Y. L. Chiou who has given me constant support throughout the completion of my thesis. I would like to extend my gratitude to Mr. Mehdi Mansouri, who has done the processing and testing pertaining to this thesis and similarly I like to extend my gratitude to the Sharp Laboratories of America, Inc. where the work was done. I would like to extend my special thanks to Dr. Andrew M. Hoff for his critical comments about the subject and the actual write up of this document. I also like to thank my other committee member Dr. Don Morel for spending his valuable time in the completion of my thesis. Finally I would like to extend my thankfulness to my parents and friends for their unwavering support in the completion of my thesis.
i Table of Contents List of Tables iii List of Figures iv Abstract vi Chapter One Introduction 1 1.1 Introduction 2 1.2 Alternative Dielectrics 4 Chapter Two MOS Capacitor 8 2.1 The MOS Structure 8 2.2 Ideal MOS Structure 9 2.2.1 CV Curve for Ideal MOS Structure 13 2.3 Non-Ideal MOS Structure 18 2.3.1 Charges in the Non-Ideal MOS Structure 19 2.4 Conduction Mechanism in Dielectric Films 21 2.5 Non-Volatile Memory Devices 23 Chapter Three Fabrication of HighDielectric Films 27 3.1 HighMaterial Properties 27 3.2 Deposition Methods 29 3.2.1 Sputtering 30 18.104.22.168 Theory of Sputtering 30 22.214.171.124 Sputtering System 31 3.3 Fabrication of Test Structures 32 3.3.1 Test Structures 34 3.4 Testing 36 Chapter Four Electrical Properties of HighFilms 37 4.1 Material Properties of Reactive Sputtered HfO2 Films 37 4.1.1 Determination of Dielectric Constant 37 126.96.36.199 MIM Films 38 188.8.131.52 MIS Films 42 4.1.2 Determination of Interfacial Layer Thickness 45 4.1.3 Determination of Flat Band Voltage 47 4.1.4 Determination of Doping Concentration 48
ii 4.1.5 CV Characteristics 49 4.2 Conduction Mechanism in HfO2 Films 52 4.2.1 Effect of Interfacial Layer 58 4.3 Electrical Properties of HighStack 62 4.3.1 Based on Continuity of Electrical Displacement 63 4.3.2 Based on Single Layer Films 65 Chapter Five Conclusions and Future Work 69 References 72 Appendices 74 Appendix A: MATLAB Program 75
iii List of Tables Table 1.1 MOS Challenges for the 21st Century 2 Table 2.1 Conduction Mechanism in Thin Insulating Films 22 Table 2.2 Bias Voltages for FGMOSFET Cell 25 Table 4.1 Data for Obtaining the HfO2 Dielectric Constant in MIM Films 38 Table 4.2 Data for Obtaining the HfO2 Dielectric Constant in MIS Films 42 Table 4.3 Poole-Frenkel Slopes for Single Layer HfO2 Films 56 Table 4.4 Poole-Frenkel Slopes for Single Layer HfO2 Films Considering the Interfacial Layer 61
iv List of Figures Figure 2.1 MOS Structure 9 Figure 2.2 Energy Band Diagram of an Ideal MOS Structure 10 Figure 2.3 Energy Band Diagram of an Ideal MOS Structure in Accumulation 11 Figure 2.4 Energy Band Diagram of an Ideal MOS Structure in Depletion 12 Figure 2.5 Energy Band Diagram of an Ideal MOS Structure in Inversion 12 Figure 2.6 Energy Band Diagram at the Surface of a p-type Semiconductor 13 Figure 2.7 CV Curve for an Ideal p-type MOS Capacitor 17 Figure 2.8 Charges in the MOS Interface 19 Figure 2.9 Floating Gate Device 24 Figure 2.10 Charge Trapping Device 24 Figure 3.1 Schematic of a Sputtering System 32 Figure 3.2 Single Film MIM Test Structure 35 Figure 3.3 Single Film MIS Test Structure 35 Figure 3.4 Multi Layer (or) Stack Test Structure 36 Figure 4.1 Growth Curve for Single Layer HfO2 Films 39 Figure 4.2 1/Capacitance Density vs Sputtering Time for Single Layer HfO2 MIM Films 40 Figur e 4.3 1/Capacitance Density vs Sputtering Time for Single Layer HfO2 MIS Films 43 Figure 4.4 Ideal and Measured CV Curves for a 294 HfO2 Film 50
v Figure 4.5 CV for a 294 HfO2 Film Before and After Annealing 51 Figure 4.6 IV for a 294 HfO2 Film 52 Figure 4.7 Current vs Electric Field for HfO2 Films of Varying Thickness 53 Figure 4.8 Fowler-Nordheim Plot for a 294 HfO2 Film 54 Figure 4.9 Poole-Frenkel Plot for a 294 Film 56 Figure 4.10 Poole-Frenkel Plot for a 480 Film 57 Figure 4.11 Voltage Distribution in a Single Layer Film Considering the Interfacial Layer 58 Figure 4.12 Poole-Frenkel Plot for a 294 Film Considering the Interfacial Layer 60 Figure 4.13 IV Characteristics for SiO2/HfO2/SiO2 Stack 62 Figure 4.14 Voltage Across Stack vs Voltage Across Highand Oxide Layers 64 Figure 4.15 Voltage Across Stack vs Electric Field Across Highand Oxide Layers 64 Figure 4.16 IV for Single Layer and Stack Film 65 Figure 4.17 Voltage Across Stack vs Voltage Across Highand Oxide Layers 66 Figure 4.18 Poole-Frenkel Plot for HfO2 Layer in the Stack Structure 68 Figure 5.1 Temperature Dependent IV Plot for SiO2/HfO2/SiO2 Stack 70 Figure 5.2 Arrhenius Plot @ 8V 71 Figure 5.3 Arrhenius Plot @ 20V 71
vi Characterization of HfO2 Films for Flash Memory Applications Surendra Gaddipati ABSTRACT The scaling of integrated circuits requires the use of alternative dielectric materials as the replacement for silicon dioxide in the submicron devices. The scaling limit for silicon dioxide used in MOSFETs is 1.2nm and the Oxide Nitride Oxide (ONO) stack used in flash memory applications is 13.0nm. The use of alternative dielectrics with highvalue will alleviate the problem of charge retention and also would help to decrease the programming voltage in case of flash memory cells. Many alternative highdielectric materials such as TaO2, TiO2, Al2O3 etc., have been examined for this purpose previously. Recently the metal oxides such as ZrO2 and HfO2 have been found to be viable replacements for the existing oxide. The highvalue along with high bandgap motivates this replacement. A complete modeling of the reactively sputtered HfO2 films in the thickness range of 294 to 480 is attempted using the data obtained by one of the group members at the Sharp Laboratories of America, Inc. The IV and CV data is used to characterize the material properties and conduction mechanism in HfO2 films used as a control dielectric. The slope of the Poole-Frenkel plot is close to the theoretical value in the intermediate region however it starts to deviate at high field regions. Temperature dependent data also suggests that there are two types of
vii traps active in the intermediate and high field regions. However the origin of these traps is not known. Temperature dependent data indicates that there is a rapid increase in the leakage current at elevated temperatures in the high field region further suggesting that the charge retention capability of the device would be adversely affected under such conditions.
1 Chapter One Introduction The semiconductor industry has achieved gains in productivity and performance by aggressive device scaling over the years. The aggressive scaling lead to a two-fold increase in die/wafer and two-fold increase in speed every two years leading to an improved performance and decline in manufacturing costs. Initially scaling has been fueled by improved lithography tools, masks, photoresists and etch processes. Scaling of the devices was done by following Moores law that states, The transistor density on integrated circuits doubles every couple of years. The Moores law started as an observation by Dr. Gordon E. Moore, about which he mentioned in his paper of 1965 . Dr. Gordon E. Moore was projecting the decline in manufacturing cost of the components on a chip as more components are integrated on to the chip. This law applied to any other industry is impractical. The exponential growth and ever-shrinking transistor size result in increased performance and decreased cost. The traditional materials used for the basic devices, MOSFET and capacitor are silicon, oxide of silicon and polycrystalline silicon. This aggressive scaling has pushed these materials to their fundamental material limits and hence continued scaling now requires new materials to replace the existing materials. As MOSFETs are scaled beyond the submicron (i.e. 100nm or 0.1 m) technology node ultra thin SiO2 gate dielectrics with a thickness of 11-14 are required. This means
2 further scaling would lead to gate dielectrics with few molecules of SiO2 to form the films thickness. According to the 2001 International Technology Roadmap for Semiconductors (ITRS) the 22nm technology node predicted to be in production in 2016 would have a gate oxide thickness of 4-5 . 1.1 Introduction The MOSFET operation is possible because of the MOS structure. The MOS structure has the simple characteristics of a capacitor. The top plate of the capacitor is the poly-silicon gate or a metal electrode (M in MOS), the bottom plate is the semiconductor (S in MOS) and presently insulator is the oxide of silicon (O in MOS). The electric field can penetrate a small distance into the semiconductor and hence helps in altering the charge distribution at the surface eventually leading to a control over the current flow from drain to source. The oxide capacitance ( Cox) is given by 2/ cm F t Cox ox o ox (1.1) Table1.1: MOS Challenges for the 21st Century YEAR 2001 2003 2005 2007 2010 2016 Technology generation m 0.13 .10 .08 .065 .045 .022 Gate oxide thickness nm 1.3-1.61.1-1.40.8-1.00.6-1.1 0.5-0.8 0.4-0.5 Gate Dielectric Leakage @ 100oC nA/m 10 70 300 1000 3000 10000
3 In Eq. (1.1), o is the permittivity of free space, ox is the relative permittivity of the dielectric and tox is the thickness of the dielectric. From Eq. (1.1), it could be said that thin oxides are desirable as they result in increased capacitance, which in turn enhances the current through the MOSFET. The increase in saturation drain current would lead to increased switching speeds. Hence a thin oxide which enhances the transistor performance also leads to higher leakage currents due to direct tunneling beyond a thickness of 40. An equivalent capacity can be reached by having thicker dielectric with a higher dielectric constant. At the same time a thicker dielectric can reduce the direct tunneling component of the leakage current. The scaling techniques have enabled the feature size to be reduced to about 0.1m in 2003 from about 10m in 1970. The technology roadmap for the next decade is shown in Table 1.1 . The MOS structure is found in majority of the commercial integrated circuits or the principal of MOS is used in the device operation. The basic structure is obviously the MOSFET transistor, but the actual revolution came with the invention of the MOS memory. The first of this kind was the Dynamic Random Access Memory (DRAM) which needs to be refreshed continuously and later came in the Static Random Access Memory (SRAM). In SRAM the data is lost after the power supply is removed. Hence the alternative to DRAM and SRAM being widely used today is the Floating Gate MOSFET (FGMOSFET) or the flash memory. More about memory is discussed in a separate section in chapter 2. As the technology advanced more memory is being crammed into the same size die by device scaling. However scaling down the devices is not permanent and it is found that the ONO stack used in FGMOSFET has a limit of
4 13.0nm . ONO is used as the dielectric in between the control and floating gates in a flash memory cell. As the limit approaches it is essential to replace it with alternative dielectric stacks. In this research the data obtained for HfO2 and O/HfO2/O stack fabricated and tested by one of the group members is examined as a replacement for the ONO stack. 1.2 Alternative Dielectrics For many years thermally grown silicon dioxide has been the primary dielectric in integrated circuits. For ultra-thin dielectrics oxynitrides are used because of their immunity to electrical stress and suppression of boron penetration. The main reasons for limitation to the gate oxide scaling are transistor performance degradation due to loss of inversion layer charge through gate leakage and the degradation of carrier mobility in the channel from increased scattering. Further the intrinsic reliability prohibits further scaling. The process of intrinsic degradation in gate dielectric begins with trap creation and formation of interface states as the device gate dielectric is stressed at elevated voltages and temperatures. The creation of these defects continues with the injected current until the defect density reaches a critical value, after which dielectric breakdown occurs . It was also reported that a gate leakage of 1A/cm2 would be the scaling limit of Tox by measuring either gate injected or substrate injected gate current . However in submicron transistors gate direct tunneling is more important in determining the Tox scaling limit. The gate oxide thickness and tunneling current variation for different
5 technology nodes are shown in Table1.1. Considering the direct gate leakage current the limit for gate oxide scaling would be 12 for MOSFETs . Metal-Oxides have been found to be viable as alternative dielectrics and research has been going on to evaluate various materials such as Al2O3, ZrO2, HfO2, Ta2O5 and TiO2 etc. Any alternative material should have high dielectric constant, large band gap, good interface state stability and high thermal stability. Materials with very high dielectric constant may lead to increase in fringing fields . Materials like Ta2O5 and TiO2 are thermally unstable when in contact with Silicon  and hence need an additional barrier layer. The additional barrier layer would effect r and also adds to process complexity. Among the medium high-k materials that are viable with silicon are Hf and Zr. Among these Hf forms most stable oxide with highest heat of formation . Hf can reduce native SiO2 layer to form HfO2 and the silicide of Hf can be oxidized to form HfO2 which is very resistive to impurity diffusion and intermixing at the interface. Moreover HfO2 has medium dielectric constant of ~30 and a reasonable bandgap of 5.68ev . In addition HfO2 is compatible with polysilicon gate without use of any barrier material. All these properties make HfO2 the most promising material to replace the SiO2 as an alternative dielectric. The incorporation of any dielectric other than the traditionally grown SiO2 in MOSFETs requires fundamental paradigm changes in process flow. This is necessary because the dielectric material in this case needs to be deposited. Whereas in the case of thermally grown SiO2 the Si-SiO2 interface is continuously regenerated as the dielectric film grows. For other dielectrics this is not the case and the interface must be formed
6 either prior to film deposition or formed during initial stages of deposition by interface reactions with process gases. Previous research experience and results show that there must be separate and independent process steps for interface formation and film deposition . Deposition in an oxidizing or other chemically active environment would result in subcutaneous chemical reactions which generally lead to interfacial defects that degrade the device performance. Traditional method of deposition of (HfO2) is done by first depositing a thin Hafnium layer and then following with RTA reoxidation. Hafnium can be deposited by various techniques like sputtering, evaporation, CVD etc. HfO2 films were also deposited using Jet vapor deposition system . The grown highdielectric should be controlled on a mono layer scale, also the films should be smooth and the deposition temperature should be low to suppress the growth of SiO2. Controlling the formation of interfacial layer and controlling the deposited films on a mono-layer scale is not possible with traditional processing techniques. To overcome the problems involved with traditional growth methods, these methods are replaced by new deposition methods such as Atomic Layer Deposition. However the samples used in here have HfO2 deposited by reactive sputtering as ALD was not available. This work emphasizes on studying the electrical characteristics of highdielectric materials especially HfO2 deposited by reactive sputtering. Data for single layer MIS and stack structures with varying thickness is used for this purpose. The interpoly dielectric/control oxide in flash memory cells would be 11.0-13.0nm for the flash technology node of 100nm. However the scaling limit for this is 13.0nm for an ONO stack. Control oxide less than 13.0nm thickness would have charge retention and
7 threshold voltage instability problems as discussed in . To further increase the density of the NVM devices beyond the present scaling limits it is essential to replace the dielectric material with a highlayer. This would permit a thicker control oxide and hence avoid the problems encountered with a thinner dielectric. This thesis contains five chapters including the Introduction. The second chapter deals with the MOS structure and its operation comprehensively. Also the different kinds of memory and their evolution are presented in chapter 2. The third chapter deals with the fabrication of the test structures used in this research along with the various factors that influenced the choice of HfO2 as the replacement dielectric material. In chapter 4 a complete modeling of these structures is attempted. It deals with finding the dielectric constant, flat band voltages, interfacial layer thickness and the leakage mechanism in HfO2. Conclusions and the scope for future work are included in chapter 5.
8 Chapter Two MOS Capacitor The MOS capacitor is the basic structure of the integrated circuit family. It is imperative to study the MOS structure as it would help in understanding the integrated circuit fabrication and studying the electrical properties involving the MOS structure such as MOSFET, Charge Coupled Device (CCD) and Non Volatile Memory (NVM). The MOS structure is simple to fabricate and hence is used in this study. In this study the SiO2 layer is used as the insulator layer in the MOS structure later the theory is extended to analyze the structure with HfO2 as the dielectric. Based upon the results obtained it would be incorporated into the integrated circuit fabrication. The basic MOS capacitor and its electrical properties have been reviewed in this chapter. Basing on the theory presented here the measured properties of the MOS capacitor are evaluated in chapter 4. 2.1 The MOS Structure The basic MOS structure is shown in Fig. 2.1. The MOS capacitor is a parallel plate capacitor with silicon (S) as one electrode and the metal (M) as the other electrode. The insulator is generally an oxide (O) layer of silicon. The metal electrode is also known as the gate of the system. The silicon has an ohmic contact to provide an external electrical contact. The thickness of the insulator layer is denoted by d and it determines the capacitance of the MOS system. VG is the voltage applied to the gate of the MOS
9 system to drive the MOS into its different operating regions according to the desired functionality. VG is positive when the gate is positively biased with respect to the ohmic contact. Figure 2.1: MOS Structure 2.2 Ideal MOS Structure In an ideal MOS system when there is no voltage applied i.e., when VG is 0 the bands are flat denoting flat-band condition. There is no band bending under flat-band conditions. The energy band diagram of an ideal MOS system under zero biasing conditions for a p-type semiconductor is shown in Fig. 2.2. In an ideal MOS system The energy difference ( ms) between the metal work function ( m) and the semiconductor work function ( s) is zero (Eq.2.1). ms = m s (2.1) V G Insulator Ohmic Contact Metal Semiconductor d
10 The only charges that can exist in the system under any biasing conditions are those in the semiconductor and those with an equal but opposite sign on the metal surface adjacent to the insulator. The resistivity of the insulator is infinity i.e., there is no carrier transport through the insulator under DC biasing conditions. Figure 2.2: Energy Band Diagram of an Ideal MOS Structure In Eq. (2.1) the metal work function is a numerical value where as the semiconductor work function can be calculated from the expression shown in Eq. (2.2). B g sq E 2 (2.2) Where, is the semiconductor electron affinity, Eg the bandgap in the semiconductor and B the potential difference between the Fermi level EF and the intrinsic level Ei. E C E i E F q i q B EF M O S q m q q B E V E g /2 Vacuum Level
11 In an ideal MOS structure when VG 0 three cases may exist at the semiconductor surface. Basing upon the electron density on the semiconductor surface the three cases are named as Accumulation, Depletion and Inversion . The different regions of operation are briefly explained for a p-type device. Accumulation: When a negative voltage is applied to the metal plate with respect to the semiconductor the valence band bends upwards. For an ideal MOS structure no current flows in this condition and the Fermi level remains constant in the semiconductor. The band bending causes an accumulation of majority carriers at the semiconductor surface as the carrier density depends exponentially on the energy difference EF-EV. The energy band diagram in such a state is given in Fig. 2.3. Figure 2.3: Energy Band Diagram of an Ideal MOS Structure in Accumulation Depletion: When a small positive voltage is applied the majority carriers are depleted from the semiconductor surface. This is the depletion case and the corresponding energy diagram is shown in Fig. 2.4. EF VG<0 E V E i E F E C M O + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + S
12 Figure 2.4: Energy Band Diagram of an Ideal MOS Structure in Depletion Inversion: When a larger positive voltage is applied the bands bend downward further. If the voltage is sufficiently large the intrinsic level Ei at the surface crosses over the Fermi level EF. Under these circumstances the number of minority carriers at the surface is larger than the majority carriers and the surface is said to be in inversion. The energy band diagram of the p-type semiconductor in inversion region is shown in Fig. 2.5. Figure 2.5: Energy Band Diagram of an Ideal MOS Structure in Inversion _ _ _ _ EF EV E C VG>>0 M O S Ei S Ei _ + + + + + O VG>0 E C EF EV M
13 2.2.1 CV Curve for Ideal MOS Structure To determine the capacitance-voltage (CV) characteristics of a MOS structure it is important to find the relation between surface potential ( s), space charge (Qs) and electric field (E). To start consider the band diagram at the surface of the semiconductor in the MOS structure shown in Fig. 2.6. In the figure (Fig 2.6) is the potential in the semiconductor, and it is zero in the bulk of the system. As the band bending starts will have a non zero value and at the surface of the semiconductor this potential is denoted by s and is called the surface potential. Figure 2.6: Energy Band Diagram at the Surface of a p-type Semiconductor The electron and hole concentrations in the bulk of the semiconductor are given by Eqs. (2.3a) and (2.3b) . kT q po pe n n (2.3a) kT q po pe p p (2.3b) q Eg Semiconductor EC Semiconductor Surface Ei EF EV x q B Insulator q s s>0
14 is positive when the bands are bent downward, npo and ppo are the equilibrium densities of electrons and holes. In Eq. (2.3b), q is the charge of the electron, k is the Boltzmann constant, and T is the temperature in Kelvin. All these three are constants and the expression k T q is denoted by the symbol Substituting the value of = s in Eqs. (2.3a) and (2.3b), the following regions of surface potential can be distinguished. s < 0 accumulation of holes s = 0 flat-band condition B > s > 0 depletion of holes B = s midgap region 2 B > s > B weak inversion 2 B < s strong inversion The value for potential ( ) as a function of the distance can be obtained from the Poisson equation for the one-dimensional models, which is shown in Eq. (2.4). sx dx d ) (2 2 (2.4) Where, s is the relative permittivity of the semiconductor and (x) is the total space charge density given by Eq. (2.5). ) ( ) (p p A Dn p N N q x (2.5) Where, DN and AN are the densities of the ionized donors and acceptors, but in the bulk of the semiconductor (x) = 0 owing to the charge neutrality condition. Also in the bulk of the semiconductor = 0. Applying the two conditions to the Eq. (2.5), an expression shown in Eq. (2.6) is obtained.
15 po po A Dp n N N (2.6) From, Eqs. (2.3a) and (2.3b), e n e p n ppo po p p (2.7) Using Eqs. (2.6) and (2.7) in the Poissons expression shown in Eq. (2.4). 1 12 2 e n e p q dx dpo po s (2.8) Integrating Eq. (2.8) from bulk to surface d e n e p q x d xo po po s x1 10 (2.9) But Electric Field E is given by dx d E (2.10) From, Eqs. (2.9) and (2.10) 1 1 2 22 2 e p n e qp q kT Epo po s po (2.11) To find the electric field at the surface let = s po po Dp n F qL kT E 2 (2.12) Where, po pop n F is given by 2 / 11 1 e p n epo poand LD is the extrinsic Debye length given as po sqp Es is positive when s > 0 and Es is negative when s < 0
16 From Gausss law the charge required to produce this field is po po s D s s s sp n F qL kT E Q 2 (2.13) The differential capacitance of the semiconductor depletion layer is given by po po s po po D s s s Dp n F e p n e L Q Cs s, ) 1 )( / ( ) 1 ( 2 (2.14) Assuming that there are no work function differences and zero oxide charge, when a voltage VG is applied across the MOS structure it appears partly across the insulator Vi, and partly across the semiconductor s (Eq 2.15). VG = Vi + s (2.15) i s i id Q d E V (2.16) Where, Ei is the oxide electric field. The total capacitance of the system is the series capacitance of the semiconductor depletion layer capacitance and insulator capacitance. D i D iC C C C C F/Cm2 (2.17) The oxide capacitance is constant for a given MOS structure. This corresponds to the maximum capacitance of the system. The semiconductor depletion layer capacitance is given by Eq. (2.14). This capacitance depends on the applied voltage. Using these along with the equation for capacitance shown in Eq. (2.17), gives the ideal CV curve for the MOS structure shown in Fig. 2.7.
17 Figure 2.7: CV Curve for an Ideal p-type MOS Capacitor When the voltage, VG is negative i.e., in accumulation the majority carriers are accumulated and therefore there is a high differential capacitance of the semiconductor. Hence the effective series capacitance is closer to the capacitance that is lower in magnitude. In this case it would be the oxide capacitance. As the voltage is reduced depletion region forms that acts as a dielectric in series with the insulator and the total capacitance decreases. The depletion ends when the surface potential equals the barrier potential. As the voltage is further reduced and as the polarity reverses the capacitance reaches its minimum. When the voltage, VG is increased and exceeds the threshold
18 voltage, VT, strong inversion occurs and the capacitance starts to increase and reaches the maximum again. The increase of capacitance depends on the ability of the electron concentration to follow the applied ac signal. It is possible at lower frequencies when the recombination-generation rates of the minority carriers (electrons in p-type and holes in n-type) can keep up with the small signal variation and lead to charge exchange with the inversion layer in step with the measurement signal. In the case of an applied high frequency signal the minority carrier generation-recombination cannot keep up with the signal change and the capacitance is dominated by the differential capacitance. In Fig. 2.7 the low frequency and high frequency curves are shown separately. There are three regions as described. The three operating regions are distinguished by VFB and VT. The region in between VFB and VT is the depletion region. The region before VFB is the accumulation region and the region beyond VT is the inversion region. These three regions are shown in Fig. 2.7. The capacitance at s = 0 is called the flatband capacitance expressed as CFB and has the expression shown in Eq. (2.18). 2/ / q p kT d Cpo s s i i FB (2.18) 2.3 Non-Ideal MOS Structure The first assumption in obtaining the ideal CV characteristics is that the work function difference given by Eq. (2.1) and the oxide charge are zero. For a non ideal MOS this value is not zero. This leads to the experimental CV curve to be shifted by a
19 voltage equal to VFB, where VFB is known as the flat band voltage shift. Assuming a negligible interface trapped charges VFB is given by Eq. (2.19) . i o ms FBC Q V (2.19) Where, Qo is the oxide charge. The silicon dielectric interface is not completely devoid of surface states as there is a lattice mismatch between silicon and the dielectric. For practical MOS structure interface traps and oxide charges exist that will affect the ideal behavior of the MOS system. The various types of charges are shown in Fig. 2.8 and explained in the following section . 2.3.1 Charges in the Non-Ideal MOS Structure Figure 2.8: Charges in the MOS Interface Interface Trapped Charge (Qit): This is also known as the surface state, fast state or interface state. This charge exists within the forbidden gap due to the interruption in + + + Na+ K+Metal Dielectric Interface Silicon + + + + + Mobile Ionic Charge (Qm) Interface Trapped Charge (Qit) Fixed Oxide Charge (Qf) Oxide Trapped Charge (Qot)
20 the periodic lattice structure at the surface of a crystal. This charge changes occupancy with gate bias and have energy levels distributed throughout the band-gap . When interface traps are present more charge is required on the metal to produce a given surface potential. Because of this stretch out occurs along the voltage axis for the CV curve. The interface trap charge could be measured by comparing the low frequency and high frequency curves. At high frequencies interface traps cannot follow the ac voltage swing so they do not contribute to the total capacitance and hence the CV curve is similar to a curve without any interface trapped charge. However at low frequencies the capacitance due to the interface traps also contributes to the effective capacitance and hence stretch-out of CV curve occurs. For thermally grown oxides the interface trapped charge can be reduced by low temperature annealing in the presence of Hydrogen. Oxide Charge (Qo): It comprises of the oxide fixed charge (Qf) oxide mobile charge (Qm) and oxide/dielectric trapped charge (Qot) The distinction between interface trap charge and oxide charge is that interface trap charge varies with gate bias whereas the oxide charge is independent of the gate bias . The first kind of charge namely the fixed oxide charge (Qf) is present at the interface. This charge is fixed and cannot be charged or discharged over a wide range of surface potential. Its density is not affected by oxide thickness or type of impurities in the silicon. The fixed oxide charge originates because of the excess silicon i.e., trivalent silicon or the loss of an electron from excess oxygen centers. The mobile ionic charge (Qm) is most commonly caused by the presence of ionized alkali metal atoms such as sodium and potassium. This charge leads to
21 reliability problems in devices as they move back and forth through the oxide layer depending on the bias and thus give rise to voltage shifts. The oxide trapped charge (Qot) is located in the oxide layer. These charges are generally electrically neutral and are charged by introduction of holes and electrons into the oxide. The oxide charge could be measured from the shift of the high frequency CV curve with respect to the ideal CV curve. This shift is given by Eq. (2.19), and if the work function difference is known the oxide charge density could be calculated. For both ntype and p-type devices a negative charge produces a positive shift in the CV curve along the voltage axis and a positive charge does the opposite. The shift is because the charge neutrality has to be maintained in the system. This requires every charge on the gate to be compensated by an equal and opposite charge in the oxide and silicon. In case of an ideal system the entire charge compensation is done by the ionized donors. However for a practical MOS structure a part of the compensating charge is provided by the oxide charge rather than the ionized donors. As a fewer ionized donors are required in this case the silicon depletion layer width would be smaller than when the oxide charge is zero at any given bias. 2.4 Conduction Mechanism in Dielectric Films Dielectrics are materials that do not allow any carrier flow through their bulk when a voltage is applied across them. In other words their resistivity is infinite and the conductivity is nil. This condition holds good for ideal insulators. However under elevated fields these materials show elevated conductivity. A list of different possible
22 conduction mechanisms in insulators is shown in Table 2.1. Depending on various factors like temperature and electric field the conduction could be due to different mechanisms. Table 2.1: Conduction Mechanisms in Thin Insulating Films  Schottky Emission t i i BqEe T A J 4 / 2* Fowler-Nordheim Tunneling i BE B i Be E A J3 2 22 / 34 Poole-Frenkel Emission t i i BqE ie E J / h q A 22, h q m B 2 4 Schottky Emission: The emission in this case occurs because of the lowering of the potential barrier due to image-force. The lowering of the barrier increases with the increase of the electric field increasing the conduction. The Schottky emission is electrode limited. Fowler-Nordheim Tunneling: At higher electric fields electrons can be injected into the conduction band of the dielectric. For a finite barrier height, quantum mechanics eq B eq B e
23 predicts that few of the electrons can penetrate through the energy barrier from the electrode to the conduction band of dielectric and to the opposite electrode. This mechanism that results in the tunneling current through the dielectric with the assistance of a high electric field is known as Fowler-Nordheim tunneling. Tunneling in this case occurs through a triangular barrier. The tunneling starts at a relatively higher electric field and if the field is further increased the conduction increases rapidly and the dielectric breakdown occurs. The expression for the current density is given by the expression in the Table 2.1. It indicates that a plot of 2 E J against E 1 gives a straight line. The slope of this line gives the potential barrier ( B) Poole-Frenkel Emission: Poole-Frenkel effect is the lowering of the Coulombic potential barrier when a trap interacts with an electric field. The conduction in this case is because of the field-enhanced thermal excitation of the trapped electrons into the conduction band. This is an analog of the Schottky effect at an interfacial barrier. The barrier height is the depth of the trap potential well. The current equation for this type of conduction is given in Table 2.1. The conduction is bulk limited in this case unlike Schottky emission. 2.5 Non Volatile Memory Devices From the day the MOS memory was invented their main drawback was its intrinsic volatility i.e., the content is lost once the external power is removed. Non Volatile Memory or NVM is the memory that has the capability to retain the contents
24 even after the external power is removed. The first solution to this problem was the floating gate concept introduced in the 1970s. There are different types of reprogrammable nonvolatile memories that came later. These included the UV-erasable and Electrically Programmable Read Only Memory (EPROM), Electrically Erasable and Programmable Read Only Memory (EEPROM), Nonvolatile Random Access Memory (Nonvolatile RAM). The basic operating principle behind the nonvolatile memory devices is the ability to charge/un-charge the gate insulator of the MOSFET. The charge in the insulator of the MOSFET alters its threshold voltage. The information content of the device is detected by applying a gate voltage with a value in between the two possible threshold voltages. In one state the transistor would be turned on and is conducting current while in the other the transistor is cut off . However, when the power supply is interrupted the device would continue to retain the content. Figure2.9: Floating Gate Device Figure2.10: Charge Trapping Device VB VS VD VG Floating Gate Dielectrics Semiconductor VB VD VG VS Semiconductor
25 The storage of charges in the gate insulator of a MOSFET can be realized in two ways. The first one is based on the storage of charge on a conducting or semi conducting layer that is completely surrounded by a dielectric (Fig 2.9). In the second case the charge is stored in discrete trapping centers of an appropriate dielectric layer (Fig 2.10). The structures in this study are the FGMOSFET structures and hence the operation of FGMOSFET is considered here also this is the basic building block of the flash memory. The FGMOSFET stores charge on a conducting or semiconductor layer that is completely surrounded by a dielectric. This layer acts as a completely isolated gate and hence this type of device is known as a floating gate device. Any standard memory cell has three basic operating conditions distinguished according to the bias conditions as shown in Table 2.2 . Table 2.2: Bias Voltages for FGMOSFET Cell  Vs VD VG Program GND Vdd Vpp Erase Vcc FLOAT GND Read GND Vread Vcc Vpp=12V, Vdd=5-7V, Vcc=5-7, Vread=1-2V Hot-Electron Injection Program: The memory cell is programmed by hot electron injection. During programming a high voltage is applied across the control gate and the
26 drain. This condition drives the MOSFET into saturation. The gate voltage inverts the channel while the drain bias drives the electrons towards it making them very energetic (hot). Because of their high energy they can easily cross from the conduction band of silicon into the conduction band of oxide. This oxide being very thin the electrons can easily tunnel into the floating gate. Because of the high potential well on either side, the floating gate retains the charge thereby enabling the programming of the cell. Fowler-Nordheim Tunneling Erase: For the erase operation the control gate is grounded and the source is slightly positive biased. This will create a triangular barrier for the electrons at the floating gate oxide interface thereby allowing the electrons to tunnel through the oxide and into the silicon. This type of tunneling over a triangular barrier due to the barrier lowering is known as Fowler Nordheim tunneling. Read: This is done by first selecting a word line by applying voltage to the control gate. Then a moderate voltage is applied to the drain of the selected cell via a current sense amplifier. If the cell is programmed to a high threshold voltage and the voltage applied to the drain is below this voltage the cell will not conduct. This is sensed by the current amplifier and the cell content is decoded accordingly. If the cell has lower threshold voltage then the applied voltage the cell conducts current and this state is accordingly decoded.
27 Chapter 3 Fabrication of HighDielectric Films It is imperative to discuss the fabrication of MIS structures incorporated with highdielectrics as this brings about a fundamental change in the process flow that has been used traditionally over decades. The process parameters highly influence the actual device parameters. Hence the process flow is studied and also first the factors that influenced in choosing the highmaterial are looked at. 3.1 HighMaterial Properties Many materials have been considered as replacement for SiO2 as the dielectric material for sub micron regime. The key guidelines for selecting an alternative dielectric are , permittivity and band gap thermodynamic stability film morphology interface quality process compatibility Permittivity and Band Gap: Obviously it is essential to choose a material with a higher dielectric constant than that of SiO2. To reduce the leakage current the conduction
28 band offset should be preferably more than 1.0ev. Initially various materials like Si3N4 and Al2O3 have been considered but they will also have to be replaced in the near long term because of their moderate dielectric constant. Few others like Ta2O5 and SrTiO3 have been tried but they were found to have a band gap offset less than 0.5ev and hence this could increase tunneling through the oxide. Metal oxides like HfO2 and ZrO2 were found to have high dielectric constant as well as high band gap. Thermodynamic Stability: The highmaterial should be stable when in contact with silicon. Most of them were found to react with silicon and form an undesirable interfacial layer. This would reduce the effective dielectric permittivity of the system. Hence it is essential to a choose a material that is more stable when in contact with the silicon or the other choice is to deposit a barrier layer on silicon and then deposit actual dielectric on top of it. Film Morphology: It is desirable to select a material that has an amorphous structure. However most of the metal oxides of choice are highly crystalline in nature. It is possible to limit the crystallization by choosing appropriate composition and thermal processing. A low temperature processing would prevent crystallization for very thin films. The crystalline dielectrics are problematic as the grain boundaries serve as high leakage paths. Also the varying grain sizes and orientations alter the value of k within the gate area leading to irreproducible properties.
29 Interface Quality: A high quality interface would preserve the capacitance gain obtained by using a highmaterial. Interface state density of metal oxides is more than that of SiO2 and hence considerable flatband voltage shifts are caused. Process Compatibility: It is necessary that any new materials should be able to be incorporated into the existing process flow. High temperature steps like annealing would lead to undesirable properties at the interface. Also the deposition process like PVD would lead to surface damage and create more interface states. The reaction kinetics associated with CVD film deposition process requires careful attention to control the interfacial layer formation. CVD process requires a precursor and it should be chosen to minimize the impurities in the film. However a more recent technique like ALD is better suited when uniformity and better interfacial layer control are essential. Taking the above factors into consideration HfO2 is used as the highmaterial in this research. Various test structures explained in the later sections were fabricated using HfO2 as the dielectric layer. 3.2 Deposition Methods Traditionally the dielectric used in integrated circuit processing has been SiO2 and it was grown on top of the silicon substrate by means of oxidation. For other materials this is not possible and the dielectric layer has to be deposited. There are different methods of depositing thin films such as evaporation, PVD, CVD, Sputtering etc.
30 3.2.1 Sputtering In this the atoms are ejected from the surface of a material when the surface is struck by energetic particles. In this method uniformity over large wafers can be achieved by sputtering from large targets. Also desired film thickness can be achieved by controlling the process parameters. The sputtering step is performed in vacuum to achieve the purity required in integrated circuit processing. There are many kinds of sputtering. For example for depositing electrically conductive materials such as Al, W and Ti sputtering is performed using a dc power source and sputtering of dielectrics is achieved by RF sputtering . In this study the highmaterial is deposited by reactive sputtering. In this the reactive gases are introduced into the chamber and they react with the ejected particles on the surface of the substrate to form the desired compound in the form of a film on the substrate. 184.108.40.206Theory of Sputtering The sputtering process starts with the creation of glow-discharge and sustaining this discharge. The energetic particles used to strike the target and release the particles are generated by glow-discharges. A glow-discharge is a partially ionized gas containing positive and negative ions. When a free electron enters the chamber it is excited by the potential difference between the two electrodes in the chamber. If this energy is larger than the ionization potential a second free electron will be created. Subsequently these free electrons create more electrons and at a potential called the breakdown potential the
31 discharge occurs in the chamber. Hence a current path is created in the system through the discharge . When a solid surface is bombarded by atoms, ions or molecules the kinetic energy of these particles determine the events that follow the collision. At very low energies (<5ev) such events are limited to reflection or physisorption of the bombarding material. At very high energies (>10ev) the impinging particles travel into the bulk of the target material before depositing their energy. At moderate energies (5-10ev) that exceed the binding energy of the target material surface damage takes place. The other possibility at such energy levels is that a fraction of the energy causes atoms from the surface to be dislodged and ejected into the gas phase. These particles later travel to the surface of the substrate and get deposited. 220.127.116.11 Sputtering System A typical sputtering system is shown in Fig. 3.1. It consists of a) the sputter chamber b)Vacuum pumps c) power supplies d) sputtering gas supply and flow controllers e) monitoring equipment f) wafer handling system and g) controller. The system consists of a vacuum chamber in which the sputtering is performed. The target and the substrate are placed in the vacuum chamber. The vacuum system consists of the cryo pump and a roughing pump. The roughing pump is first used to bring the chamber to a moderate vacuum level of approximately 1Torr from the atmospheric pressure. Then the cryopump takes over which pumps the chamber to ultra high vacuum
32 levels. A liquid nitrogen trap is used to reduce the pressure in the vacuum to approximately 10-4 Torr. The power (DC/RF) source is selected according to the sputtering mechanism. Ion and thermocouple gauges are used at a number of points to monitor the pressure continuously. The valves are controlled by a control system. Figure 3.1: Schematic of a Sputtering System 3.3 Fabrication of Test Structures The fabrication is performed on bare P-type prime grade silicon wafers. To obtain high performance and high reliable devices it is essential to remove the contaminants present on the surface of silicon. To achieve this RCA cleaning is performed on these wafers. RCA cleaning involves the standard cleaning steps SC-1, SC-2 and a diluted HF dip. In SC-1 insoluble organic contaminants are removed. After SC-1, SC-2 clean is Vacuum Chamber Power Supply Anode Cathode Sputtering Gases Cryo Pump Roughing Pum p
33 performed. This step removes any heavy metals or ionic contaminants. The wafers are then dried and readied for the next step. The RCA clean is followed by the deposition of highmaterial. This is done by the sputtering process. HfO2 films are obtained by sputtering hafnium targets in a mixture of argon and oxygen with Ar/O2 flow ratio set at 5/2, where, argon is the sputtering gas and the oxygen is the reactive gas. These gases were introduced into the chamber separately and controlled by standard mass flow controllers. Pre-conditioning consisted of sputtering for two minutes in a pure Argon atmosphere with the shutter closed and the DC power at 300 W. Typical deposition conditions were 5E-7 Torr; Base Vacuum Pressure 7E-3 Torr; Ar + O2 Pressure Ar Flow Rate for 2 Minutes; 5E-3Torr O2 Flow Rate of 10 Seconds; 2E-3Torr 300 Watts of Power for Hf at Room Temperature The shutter was opened for the wafers to be coated with the highmaterial. To achieve the desired coating thickness all of the process parameters such as power, Ar/O2 flow ratio and pressure were kept constant except for the sputtering time, which was determined by the desired film thickness. The next step is Rapid Thermal Annealing (RTA) in the presence of oxygen. High temperature annealing above 500oC is not advisable as it leads to the crystallization of the HfO2 film.
34 The next step involves the deposition of the gate material. This is deposited by sputtering in RF plasma discharge in the presence of an inert gas. The gate material used in this case is TiN. First the TiN was deposited and then photoresist is coated and developed. After developing, TiN is etched to obtain various devices. Finally after the gate formation forming gas annealing is performed. Forming gas is a nitrogen dominant mixture of hydrogen and nitrogen generally 95% N2 and 5%H2. This is done to improve the quality of the film. This helps in tying up the dangling bonds and there by reducing the leakage current. 3.3.1 Test Structures Different test structures are fabricated according to the applications. The single film test structures consisted of the MIM and MIS structures. MIM capacitors are used for constant capacitance applications. They are widely used in Radio Frequency (RF) circuits. MIS structures form the basis of all the modern day integrated circuits. The multilayer structures are fabricated to evaluate the use of HfO2 as a dielectric in FGMOSFET applications. The process flow for various test structures is explained in the following paragraph. Single Film: The MIM and MIS films are deposited on the same substrate. The fabrication is performed on 6 p-type silicon wafers with <100> orientation and a resistivity of 4-10 Cm. First the standard cleaning procedures are performed and then a bottom metal stack is deposited by physical sputtering. The bottom metal stack consisted
35 of Ti/TiN/AlCu/Ti/TiN. Then patterning is performed and the metal layer is etched where MIS films are to be deposited. Then HfO2 is deposited and RTA annealing is performed. After this a TiN metal gate is deposited and later this is etched to identify various test structures. At the end forming gas annealing is performed. The structures are shown in Figs. 3.2 and 3.3. Figure 3.2: Single Film MIM Test Structure Figure 3.3: Single Film MIS Test Structure Stack Film: These structures are deposited on 6 n-type wafers with a <100> orientation. The test structure is shown in Fig. 3.4. The structure consisted of 3-layer stack with silicon dioxide as the top and bottom layer and hafnium oxide in the middle. The standard processing steps are listed in the previous section. The wafers were first cleaned and then a 35 bottom oxide layer is grown by the thermal process at 950oC. P-type Substrate Highfilm Metal P-type Substrate Highfilm Metal Metal
36 Then the highlayer is deposited by the sputtering process. The top layer is a 50 silane oxide. After this the gate metal is deposited and forming gas annealing is performed. Figure 3.4: Multi Layer (or) Stack Test Structure 3.4 Testing The IV and CV characteristics have been obtained on the smallest die available with an area of 100 m X 100 m. The IV characteristics were obtained in the accumulation region. This would give a better perspective of the dielectric as the entire voltage appears across the dielectric layer under accumulation. The CV characteristics were obtained by driving the device into accumulation and then into depletion and finally into accumulation and in the reverse direction. Generally the sweep voltage was -3V to +3V and then from +3V to -3V. N-type Substrate Hi g hfilm Oxide Oxide Metal
37 Chapter Four Electrical Properties of HighFilms Modeling of single layer and stack highHfO2 films is attempted in this research. The data was collected from MIM and MIS structures having varying dielectric thickness. An attempt has been made to calculate the dielectric constant from the growth curves and the CV data. The CV data was used for determining the flat-band voltage and thus the nature of charge present in the films. It is necessary to understand that all the data presented in this research is a representative data. The data obtained from smallest available (100 m X 100 m) die is used in this study. 4.1 Material Properties of Reactive Sputtered HfO2 Films 4.1.1 Determination of Dielectric Constant An attempt has been made to arrive at a value for the dielectric constant of single layer HfO2 films deposited by the reactive sputtering process. In this study five different samples consisting of MIM and MIS test structures were considered. In all these samples the HfO2 was deposited by the reactive sputtering process as explained in Chapter 3. The determination of dielectric constant for MIM and MIS structures is discussed in two separate sections. An explanation is given for the contrasting capacitance values for MIM and MIS structures having same thickness. The data shown in Tables 4.1 and 4.2 is used for this purpose.
38 18.104.22.168 MIM Films The equation for a MIM capacitor is similar to that of a parallel plate capacitor. The only composition of the total capacitance is the oxide capacitance as there is no semiconductor layer and hence the semiconductor depletion layer capacitance as in the case of a MIS doesnt come into existence. The equation is shown in Eq. (4.1), where o is the permittivity of free space given as 8.854*10-3 fF/ m, r is the relative permittivity of the dielectric in consideration, A is the area of the device, and d is the dielectric thickness. d A Cr o (4.1) Table 4.1: Data for Obtaining the HfO2 Dielectric Constant in MIM Films Wafer Sputtering Time (Sec) Thickness ( ) Capacitance (pF) Capacitance Density (fF/ m2) 1/CD ( m2/fF) SL-1 50 159 124 12.4 .0806 SL-2 80 285 84 8.4 .119 SL-3 90 294 75 7.5 .133 SL-4 120 370 58 5.8 .172 SL-5 150 480 47 4.7 .213 First a plot of thickness against the sputtering time from the data shown in Table 4.1 is obtained. This plot is shown in Fig. 4.1. The plot is expected to be a straight line as the deposition rate is constant. The plot is almost a straight line but a regression technique is used to fit a straight line for the actual plot (Fig 4.1). From this an equation for the
39 thickness of the dielectric deposited is obtained. The equation would have the form shown in Eq. (4.2), where k1 is the slope, k2 is the intercept, t is the sputtering time, and d is the thickness of the layer. The thickness measurements in this case were made using the ellipsometer. 2 1* k t k d (4.2) 1 2k k d t (4.2a) Figure 4.1: Growth Curve for Single Layer HfO2 Films From the curve shown in Fig. 4.1 the growth equation is d ( ) = 3.06 t+ 17.83 (4.3)
40 Hence, the constants k1 and k2 are k1=3.06 /Sec k2= 17.83 (4.4) Next a plot of the sputtering time against reciprocal of capacitance density is obtained as shown in Fig. 4.2. Again this plot is expected to be a straight line as the capacitance is inversely proportional to the thickness. The thickness is directly dependent on the sputtering time and hence the reciprocal of capacitance density should be directly proportional to the sputtering time. This straight line could be expressed in the form of a linear equation with a slope of a1, and an intercept of a2 as shown in Eq. 4.5. 2 1*a t a C A (4.5) Figure 4.2: 1/Capacitance Density vs Sputtering Time for Single Layer HfO2 MIM Films
41 from Fig. 4.2 ) / ( 0138 0 00132 0 ) / (2 2fF m t fF m C A (4.6) Hence, the constants a1 and a2 are a1=0.00132*107 c m2/FSec a2= 0.0138*107 c m2/F (4.7) But from Eq. (4.1), the reciprocal of capacitance density can be expressed as shown in Eq. (4.8). r od C A (4.8) From, Eqs. (4.5) and (4.8) 2 1*a t a dr o (4.9) Substituting expression fort of Eq (4.2a) in Eq. (4.9), 2 1 1 2* a a k k d dr o (4.10) Rearranging the terms would give an expression for the relative dielectric constant ( r) as shown in Eq. (4.11). 1 1 2 2 1 1* k a a k d d a ko r (4.11) Substituting the constants obtained in Eqs. (4.4) and (4.7) in Eq. (4.11) would give an equation for the relative dielectric constant in terms of the actual dielectric thickness (Eq 4.12).
42 d dr16 14 18 26 (4.12) Hence it could be said that the dielectric constant for these films is not constant but slightly dependent on the thickness of the dielectric. The dielectric constant for films of varying thickness could be obtained by substituting the value of thickness in Eq. (4.12). The dielectric constant approaches a maximum value of 26.18 as the thickness increases. 22.214.171.124 MIS Films The relative dielectric constant for MIS films also could be found by the same method described in section 126.96.36.199 from the growth curve and the CV data. The data used for this purpose is shown Table 4.2. Only three samples are considered in this case as the first two samples shown in Table 4.1 do not have MIS structures on them. The results obtained for MIM films along with the results obtained here can be used to study the effect of interfacial layer in MIS films. Table 4.2: Data for Obtaining the HfO2 Dielectric Constant in MIS Films Wafer Sputtering Time (Sec) Thickness ( ) Capacitance (pF) Capacitance Density (fF/ m2) 1/CD ( m2/fF) SL-3 90 294 47.8 4.78 .209 SL-4 120 370 41.1 4.11 .243 SL-5 150 480 34.5 3.45 .290
43 The growth curve for MIS and MIM films is same as the HfO2 layer is deposited simultaneously for both the structures on the same substrate. Therefore the constants k1 and k2 for MIS films would be same as the constants obtained for MIM films in section 4.1.1. The MIS and MIM data do not have the same CV characteristics and hence it is essential to obtain the new constants a1 and a2 for MIS films. To obtain these new constants a curve for reciprocal of accumulation capacitance density and sputtering time is plotted as shown in Fig. 4.3. Again the plot is expected to be a straight line as explained in previous section. Figure 4.3: 1/Capacitance Density vs Sputtering Time for Single Layer HfO2 MIS Films
44 From Fig. 4.3 ) / ( 085 0 00135 0 ) / (2 2fF m t fF m C A (4.13) From this the new constants a1 and a2 for MIS films are a1 = 0.00135*107 cm2/FSec a2 = 0.085*107 cm2/F (4.14) Substituting these constants of Eq. (4.14), along with the constants k1 and k2 of Eq. (4.4), in Eq. (4.11) an expression for the relative dielectric constant for MIS films is obtained as shown in Eq. (4.15). d dr175 6 25 (4.15) From Eq. (4.15) it is observed that the dielectric constant of the HfO2 films in MIS structures is also slightly dependent on the thickness of the dielectric. The dielectric constant varies from 16.05~18.76 for films with a thickness range of 294~480. The dielectric constant of the HfO2 film in MIM structures varies from 24.04 for a thickness of 159 film to 25.43 for a film thickness of 480 Where as the dielectric constant of the HfO2 in MIS films varies from 16.05 for a thickness of 294 to 18.76 for a dielectric thickness of 480. It has been observed that there is a huge difference in the relative dielectric permittivity of MIS and MIM films. This may be because of the presence of an interfacial layer between the dielectric and silicon bulk in MIS structures. Also the increased capacitance in case of MIM films may be due to the surface roughness involved with the top metal layer. Next section would concentrate on finding the thickness of this interfacial layer.
45 4.1.2 Determination of Interfacial Layer Thickness The capacitance of the MIM and MIS structures fabricated on the same wafer with the same thickness was found to be not equal. To explain this discrepancy the deposition of these films has been analyzed. The HfO2 films were deposited by reactive sputtering process from the hafnium target in the presence of Ar and O2. Argon is the sputtering gas and oxygen is the reactive gas. Due to the presence of the oxygen and its direct contact with silicon in the case of MIS structures would have deposited an oxide layer on top of the silicon. This is known as the interfacial layer. The interfacial layer might have formed at various stages of fabrication. There might have been a native oxide before the actual deposition, also some interfacial layer might have been formed during deposition and some of it might have been formed during RTA in the presence of Oxygen. In MIS structures the total capacitance is because of the capacitance of the highlayer and because of the interfacial layer. The MIS capacitance is given as CMIS, the MIM capacitance is given as CMIM and the interfacial capacitance is given as 2SiOC. The series capacitance of high(CMIM) and interfacial layer,2SiOC,is the total capacitance given by Eq. (4.16). 21 1 1SiO MIM MISC C C (4.16) Equation (4.16) indicates that the overall capacitance is going to be less than either of the two capacitances. Also the dielectric constant of the SiO2 is very small. Hence the capacitance due to interfacial layer would be very small when compared to the capacitance of the same layer having a higher dielectric constant. Hence it could be said
46 that MIS structures in this study have been found to have a lesser oxide capacitance than their MIM counterparts due to the presence of an interfacial oxide layer. To find the thickness of this interfacial layer some of the equations obtained previously are used. Consider the equation shown in Eq. (4.8). Along with this consider the Eqs. (4.6) and (4.13). Eq. (4.6) is the equation for reciprocal of capacitance density for MIM films, and Eq. (4.13) is the equation for reciprocal of the capacitance density for MIS films. The difference of Eqs. (4.6) and (4.13) would give an equation for the reciprocal of the capacitance density for the interfacial layer (Eq. 4.17). ) / ( 10 0712 0 10 00003 0 ) / (2 7 7 22F cm t F cm C ASiO (4.17) But from Eq. (4.8), ) / ( 10 0712 0 10 00003 02 7 7F cm t dr o (4.18a) 14 510 854 8 9 3 10 12 7 300 t d (4.18b) t d 58 24 01036 0 ) ( (4.18c) In Eq. (4.18c) the sputtering time dependent term is very small when compared to the constant term. Hence the thickness of the interfacial layer is around 24.58. This value is considered exorbitant by industry standards. This might be because while considering the MIM capacitance surface roughness was not considered. The superior capacitance in case of MIM might be partially because of the increased area due to surface roughness. Data was not available to calculate this increase and hence the inferior capacitance in case of MIS was considered to be entirely due to the presence of an interfacial layer.
47 4.1.3 Determination of Flat Band Voltage Flat Band voltage is defined as the voltage at which there is no band bending and all the bands are flat. The charge in the semiconductor layer is zero under these conditions. For an ideal device this voltage would be zero. It is imperative to find the flat band voltage while analyzing the conduction mechanism in thin films since this voltage would change the magnitude of the actual voltage across the dielectric film. Also flat band voltage of the system would help to analyze the various types of charges present in the system. The flat band voltage is obtained by comparing the CV curve for an ideal MOS capacitor to a measured CV curve from a real MOS capacitor. The ideal curve is calculated for a device without oxide charges and work function difference between gate electrode and semiconductor, but with the same oxide thickness and doping profile as the experimental device . By definition VFB is given by (Eq. 4.19), ox m ox it ox f ms FBC Q C Q C Q V ) 0 ( ) 0 ( (4.19) The ideal and measured CV curves for sample SL-3 is shown in Fig. 4.4. The thickness of the film under consideration is 294 For calculating the ideal CV curve it is important to know the doping of the substrate. Two methods of finding the doping concentration are explained in section 4.1.4. In this study the second method is used as it is more accurate.
48 4.1.4 Determination of Doping Concentration (NA) In the first method the doping concentration is obtained from the CV curve. The minimum capacitance is obtained under strong inversion when a high frequency signal is applied and the expression for the same is shown in Eq. (4.20). D iC C C1 1 1min (4.20) The depletion layer capacitance under strong inversion is given ass m DW C/ Assuming that there is no deep depletion Wm is the maximum width of the depletion layer. Hence Eq. (4.20) can be written as shown in Eqs. (4.21) and (4.21a). s m iW C C 1 1min (4.21) i s mC C W 1 1min (4.21a) Also, the maximum width of the depletion layer is given by Eq. (4.22) . 2 12 2 A B s mN q W (4.22) and B is the Fermi potential and could be evaluated from the relation given by i An N q KT ln, from this the equation for Wm is given by Eq. (4.23a).
49 2 1 2 1) / ln( 2 A i A s mN n N q KT q W (4.23a) 2 1 2 12 ) / ln( q KT q W N n Ns m A i A (4.23b) A numerical value can be obtained for the right hand term of Eq. (4.23b) as Wm can be calculated from Eq. (4.21a) and the rest of the terms are constants. The equation is non linear hence a solution for NA can be obtained by trial and error method considering the intrinsic concentration ( ni) of 1.45 X 1010/cm3. The doping concentration for a 294 film was obtained from Eq. (4.23b) and was found to be 2.8 X 1015/cm3. The second method is from the literature i.e. from the doping vs resistivity curves shown in . The resistivity of the bare wafers was given to be 4-10 Cm. Based on this value, from the resissitvity curve the doping is found to be in between 3.5 X 1015 to 1.5 X 1015. This is close to the value obtained from the experimental data. The value obtained from experimental data is used in obtaining the CV curve for an ideal device. 4.1.5 CV Characteristics The capacitance of the device is given by Eq. (2.17). The dielectric capacitance ( Ci) is constant and is the maximum capacitance of the system. The dielectric capacitance is realized from the measured CV curves. The semiconductor depletion layer capacitance
50 ( CD) is given by Eq. (2.14). The complete explanation of the ideal CV curve and corresponding equations is given in chapter 2. Using Eqs. (2.14), (2.15), (2.16) and (2.17) ideal CV curve is calculated for a 294 film and is plotted as shown in Fig. 4.4. First the semiconductor depletion layer capacitance is calculated from Eq. (2.14) assuming a value for the surface potential (s). Later the charge (Qs) is calculated from Eq. (2.13) and subsequently the actual gate voltage is obtained from Eqs. (2.15) and (2.16). A plot of the measured CV data is also shown in the figure (Fig 4.4). The flat band voltage and flat band capacitance are clearly marked. Figure 4.4: Ideal and Measured CV Curves for a 294 HfO2 Film
51 Similarly the flat band voltage for wafers with a thickness of 370 and 480 is measured. The average flat band voltage was found to be about 1.21V for a film of 294 film and it was about 1.32V and 1.58V for samples of 370 and 480 respectively. Figure 4.5: CV for a 294 HfO2 Film Before and After Annealing The CV curves before and after forming gas annealing are shown in Fig. 4.5. It is observed that hysteresis has significantly decreased after annealing. This indicates that the oxide trapped charge has reduced after annealing. There was also a substantial positive shift in the CV curve after annealing indicating an increase in the flat band
52 voltage. This might be because of an increase in oxide fixed charge. From Fig. 4.4 it was found that the charge present is negative. The slope of the CV curve also increased after annealing further indicating that there is a reduction in the interface trapped charges. 4.2 Conduction Mechanism in HfO2 Films IV data is used for determining the conduction mechanism. IV plots indicating inter wafer and intra wafer uniformity are shown in Figs. 4.6 and 4.7. In Fig. 4.6 an IV plot for a 294 film is shown for different die on the same wafer. Similarly in Fig. 4.7 a plot of current against electric field is obtained for different wafers. Figure 4.6: IV for a 294 HfO2 Film
53 Figure 4.7: Current vs Electric Field for HfO2 Films of Varying Thickness The various types of conduction mechanisms in thin films have been explained in chapter 2. It is expected that none of the methods like the Fowler-Nordheim or the Schottky emission are the conduction mechanisms involved with Highfilms. First of all Schottky emission is electrode limited which means that the current should be independent of the dielectric thickness. The general property of Fowler-Nordheim tunneling is the rapid increase of current over a narrow range of electric field which was not observed in this case. Although Fowler-Nordheim tunneling was ruled out still an attempt has been made to obtain more data from the FN Plot. The plot is shown in Fig. 4.8
54 Figure 4.8: Fowler-Nordheim Plot for a 294 HfO2 Film Fowler-Nordheim plot is obtained by plotting log (J/E2) against 1/E Observations indicate that the linearity is better in the case of Poole-Frenkel plot. The main feature of Fowler-Nordheim tunneling is the rapid increase of current over several decades in a narrow field range which is not observed in the plot shown (Fig. 4.8). Hence this mechanism may not be the cause of the leakage current in the highfilms in this study. The electric field is the oxide electric field. To obtain this the flat band voltage obtained in the previous section is taken into consideration. The electric field is given by Eq. (4.24a).
55 cm V d V V EFB G/ (4.24a) The leakage current density (J) could be calculated as the area and leakage current in the wafer are known (Eq. 4.24b). 2/cm A A I J (4.24b) A complete study of the Poole-Frenkel mechanism in HfO2 films is attempted here. As explained in chapter 2 the conduction mechanism is E dependent in the case of the Poole-Frenkel mechanism. The expression for current density by Poole-Frenkel mechanism is given in Table 2.1. To validate that the conduction mechanism is PooleFrenkel a plot of log (J/E) against E is obtained. Theoretical expression for slope could be obtained from the current equation shown in Eq. (4.25a). The slope of this plot is given by Eq. (4.25b). The Poole-Frenkel plots for the highfilms with various thicknesses are shown in Figs. 4.9 and 4.10 kT qE q E Ji B / exp ~ (4.25a) The current density equation shown in Eq. (4.25a) can be written in the form shown in Eq. (4.25b). r o Bq KT q kT q E J ~ log (4.25b) From this the slope of the Poole-Frenkel plot is given by Eq. (4.25c). 2 / 1 0 rq kT q Slope (4.25c)
56 Figure 4.9: Poole-Frenkel Plot for a 294 Film Table 4.3: Poole-Frenkel Slopes for Single Layer HfO2 Films Wafer Thickness ( ) Dielectric Constant Theoretical Slope Measured Slope SL-1 294 24.42 5.97*10-3 6.60*10-3 SL-2 370 24.66 5.94*10-3 7.14*10-3 SL-3 480 24.87 5.91*10-3 6.23*10-3 The theoretical slope calculated from Eq. (4.25c) is compared with the slope obtained from the measured data. The theoretical slope in this study is calculated based
57 on the dielectric constant calculated from capacitance value at 1MHz. Table 4.3 shows various Poole-Frenkel slopes for the single layer highfilm of varying thickness. Figure4.10: Poole-Frenkel Plot for a 480 Film In the plots shown in Figs. 4.9 and 4.10 the actual curve and the fitted curve are shown separately. The Poole-Frenkel curve plotted for actual data is almost a straight line but a simple function in MTALAB is used to fit a straight line and the slope is obtained for this curve. Again for calculating the slope a MA TLAB function is used. The entire program is given in Appendix A.
58 4.2.1 Effect of Interfacial Layer As discussed in section 4.1.2 there is an interfacial layer present between the highfilm and the silicon substrate. The thickness of such a layer has been estimated in the same section before. The Poole-Frenkel plot in the previous section is obtained without considering the presence of such a layer. It implies that all the applied voltage is assumed to have been present across the highlayer. Hence Eq. (4.24) is not appropriate for calculating the electric field across the highlayer and a new expression has to be obtained. For this consider the two layer structure shown in Fig. 4.11. Figure 4.11: Voltage Distribution in a Single Layer Film Considering the Interfacial Layer In Fig. 4.11 the voltage across interfacial layer and the voltage across highlayer are defined as Vi and Vh respectively and similarly the thickness of the two layers is identified as di and dh respectively. The total voltage across the two layers is defined as Vt (Eq. 4.26a). FB G tV V V (4.26a) i h tV V V (4.26b) SiO2 HfO2 dh di Vi Vh Vt
59 Where, VG is the actual gate voltage applied. Let the electric field across the highlayer be given by E (Eq.4.27a) h hd V E (4.27a) From, Eq. (4.27a) h i td V V E (4.27b) The voltage across interfacial layer Vi can also be written as i i id E V (4.27c) But based on the continuity equation of electrical displacement at the boundary i i hE E (4.27d) Where, h, i are the dielectric constants of the highand oxide layer respectively. Also, Ei is the electric field of the oxide layer. Using Eq. (4.27d) in Eq. (4.27c) an expression for voltage across dielectric is obtained as shown in Eq. (4.27e). i i h id E V (4.27e) Again substituting the value of Vi from Eq. (4.27e) in Eq. (4.27c) an expression shown in Eq (4.27f) is obtained. h i i h h td d E d V E (4.27f) EOT d E d V Ei h t (4.27g)
60 Where EOT is given as h h id and rearranging the terms in the Eq. (4.27g) the formula for electric field is obtained as shown in Eq. (4.27h), CF d V V Eh FB G* (4.27h) Where CF is the correction factor given by EOT di1 1 Considering Eq. (4.27g) for calculating the electric field across the highlayer the plot shown in Fig. 4.12 is obtained and the corresponding slopes for three different samples are shown in Table 4.4. Figure 4.12: Poole-Frenkel Plot for a 294 Film Considering the Interfacial Layer
61 Table 4.4: Poole-Frenkel Slopes for Single Layer Films Considering the Interfacial Layer It is observed that the Poole-Frenkel slope has increased after considering the interfacial layer. This could be explained if Figs. 4.9 and 4.12 are considered. They show the Poole-Frenkel plots for a 294 film before and after correction. The field across the highlayer is less than the value obtained without considering the interfacial layer. Here for a reduced field there is a same amount of leakage current and hence the slope has increased. The reason for the deviation of the measured slope from the theoretical slope could be because of the dielectric constant used in calculating the theoretical slope. The theoretical slope was calculated with the dielectric constant obtained at 1MHz. Literature suggests that dielectric constant obtained at higher frequency be used . From the literature it is expected that the dielectric constant decreases with the increasing frequency. Also the interfacial layer considered was not very accurate for the reasons mentioned in section 4.1.2. Hence a lower value of dielectric constant and an appropriate value for interfacial layer thickness would give an appropriate theoretical slope in agreement with the measured slope. Wafer Thickness Dielectric Constant Theoretical Slope Measured Slope SL-1 294 24.42 5.97*10-3 8.23*10-3 SL-2 370 24.66 5.94*10-3 8.17*10-3 SL-3 480 24.87 5.91*10-3 7.24*10-3
62 4.3 Electrical Properties of HighStack In the previous section an attempt has been made to analyze the conduction mechanism in single layer HfO2 films. In single layer films the entire applied voltage appears across the single layer HfO2 film. However in the stack structure the voltage distribution across the three different layers is not exactly known. In this section first an effort has been made to find the correct voltage distribution pattern across the three layers of the stack and then this voltage is used to analyze the conduction mechanism in the high-k structure of the stack. A typical IV curve for the stack structure is shown in Fig. 4.13. Figure 4.13: IV Characteristics for SiO2/HfO2/SiO2 Stack
63 The fabrication of the three layer stack structures has been explained in the previous chapter. The stack structure has a 35 thermal oxide at the bottom and a 50 silane oxide on the top. The HfO2 layer is a 135second sputtered film whose thickness is calculated from the growth curve of Fig. 4.1 and Eq. (4.3). The thickness is found to be approximately 431. 4.3.1 Based on Continuity of Electrical Displacement The major assumption in this case is that there are no charges present in the oxide. Therefore the electric field is constant thus voltage is directly proportional to the EOT. The EOT for the top and bottom oxides would be same as the physical thickness. The EOT for the HfO2 film can be calculated from Eq. (4.28). Where, h is the relative dielectric constant of the HfO2, o is the relative dielectric constant of oxide, and dh is the thickness of HfO2 layer. EOT do h h (4.28) The dielectric constant h for the HfO2 film from Eq. (4.10) is 25.35. The thickness of high-k film is 431 and the o is 3.9. Hence the EOT for the HfO2 film is 66.3 from Eq. (4.25). From this the total EOT of the stack is the sum of the thicknesses of the two oxide layers and EOT. From this the voltage ( Vh) across the HfO2 layer is calculated by Eq (4.29). Here VTot is the actual voltage applied, and EOTTot is the total EOT of the stack. EOT EOT V VTot Tot h* (4.29)
64 The difference between the actual voltage ( VTot) and the voltage ( Vh) across the high-k layer is the voltage across the SiO2 layers. A plot of total voltage against the voltage across individual layers is shown in Fig. 4.14. A plot of voltage against the electric field across these two layers is also shown in Fig. 4.15. Figure 4.14: Voltage Across Stack vs Voltage Across Highand Oxide Layers Figure 4.15: Voltage Across Stack vs Electric Field Across Highand Oxide Layers From Figs. 4.14 and 4.15 it is observed that the voltage across the stack while breakdown is about 28V. The voltage across the two oxide layers at this point is about 15Volts which corresponds to a field of 18Mv/Cm. The voltage across the 431 HfO2 layer is around 12Volts and the corresponding field is about 3Mv/Cm. The breakdown field in the case of single layer HfO2 films was found to be in the range of 5.2Mv/Cm to 5.9Mv/Cm. Based on these observations it could be said that in case of stack the oxide layers take most of the stress. However it is not known exactly when the breakdown starts to occur. It is possible that the breakdown occurs in the oxide layers first. Further studies would give an idea of the approximate breakdown phenomenon in the stack films.
65 4.3.2 Based on Single Layer Films In this case first a plot of voltage ( Vs) against the current ( Is) is obtained for stack films. On the same plot voltage ( Vh) against current ( Ih) for the HfO2 layer in single layer films is plotted. For calculating Vh the theory explained in section 4.2.1 is used. The plot is shown in Fig. 4.16. Figure 4.16: IV for Single Layer and Stack Films Now from the graph for a given current value the corresponding voltage in stack ( Vs) and single layer ( Vh) films is obtained. In Fig. 4.16 consider a current of 1*10-9A. The voltage corresponding to this current for the single layer films is noted. Now this is the voltage across the highfilm in the stack. Let this voltage be denoted by Vhs.
66 Similarly obtain the voltage from the curve for stack and this voltage is the total voltage across stack denoted by Vs. Similarly for different values of current Vhs and Vs are obtained. Now as the voltage across the highlayer in the stack structure is known the voltage across the two oxide layers is obtained using Eq. (4.30). hs s oV V V (4.30) A plot of voltage across the highlayer ( Vhs) and voltage across oxide ( Vo) against stack (Vs) is shown in Fig. 4.17. Figure 4.17: Voltage Across Stack vs Voltage Across Highand Oxide Layers
67 The figure (Fig. 4.17) indicates that the voltage across oxide increases rapidly in the beginning and the voltage across highincreases steadily. It is found that the voltage across oxide is negative until the voltage across the stack reaches about 5V. The leakage current in the stack at 5V is less than 10pA. Hence it could be said that this model may not give exact distribution of voltages across the different layers of stack for low leakage currents. The voltage across highrises steadily and the voltage across the oxide rises sharply until a voltage of about 10V is reached. During this period the leakage current increases by a decade from 20pA-200pA over a window of about 13V. The PooleFrenkel plot is obtained in this region (medium field region) as shown in Fig. 4.18. When the voltage across the stack is increased from 17V-24V, the voltage across the oxide layers increases from 7V-10.5V and the voltage across the oxide rises from 10V-13.5V. During this the IV characteristics indicate that the current increases by more than a decade. The IV and Poole-Frenkel plots indicate that there is a small protuberance in the curve during this period. Also there is some instability is observed from the curve. The reasons for this could not be explained. When the voltage applied is about 24V the voltage across the oxide starts to decrease and the voltage across the highincreases much rapidly. This situation indicates that breakdown might have occurred on the oxide layer. During this short window of about 2V the voltage across the highincreases and the voltage across the two oxide layers decreases. In this range the current increase from about 3nA-10nA. After this the current increases almost by a decade over a voltage range of 2V and the device breakdown occurs at a current of about 0.8 A.
68 Figure 4.18: Poole-Frenkel Plot for HfO2 Layer in the Stack Structure The Poole-Frenkel plot for the highlayer in the stack structure is shown in Fig. 4.18. The Poole-Frenkel plot in stack films is also obtained in the medium field range. The IV and Poole-Frenkel curves show some instability in the film. To obtain the PooleFrenkel plot, IV for a voltage of 4.8V-9.3V is considered. The theoretical slope calculated is 5.86*10-3 whereas the measured slope is 8.72*10-3. The slope is close to the slope obtained in the case of single layer films.
69 Chapter Five Conclusions and Future Work The main aim of this study was to characterize the highHfO2 films used as control oxide for flash memory applications. The growth curves were studied for these films. The dielectric constant of these films with an EOT of 5.0-7.0nm was found to be around 25 slightly dependent on thickness. This is considered to be a good value and this would highly increase the performance of the transistor as desired. The CV curves prior to and after forming gas annealing indicate that the hysteresis has reduced which indicates that there is a reduction in the oxide trapped charge, also, the shift indicates that there is an increase in oxide fixed charge. Further there is an improvement in slope of the CV curve which indicates that the interface trapped charge has decreased after annealing. An attempt has been made to study the conduction mechanism in single layer and stack films. In case of single layer films the process of finding the electric field is simple as there is a single layer and all the applied voltage appears across this layer. PooleFrenkel plot indicates that it has a better linearity over the Fowler-Nordheim plot. The measured slope is close to the theoretical slope in the medium field range and there is a deviation in the high field region. After this an attempt has been made to find the voltage distribution in stack films. Two different techniques were used to find the voltage distribution. Both the methods indicate that the voltage drop across the oxide layers is dominant in the medium to high field region. Poole-Frenkel plot for the HfO2 layer in the
70 stack indicates that the slope is close to the slope obtained in case of single layer films. The temperature dependent data for the stack is shown in Fig. 5.1. Figure 5.1: Temperature Dependent IV Plot for SiO2/HfO2/SiO2 Stack Assuming that the conduction process has an Arrhenius type of behavior the depth of the trap level (or) the energy barrier could be calculated . Under such conditions the equation for conduction is given as in Eq. (5.1). kT q EBe KT I2 (5.1) Where, K is the constant and this could be written as shown in Eq. (5.2).
71 kT q E K T IB ) log( log2 (5.2) Figure 5.2: Arrhenius Plot @ 8V Figure 5.3: Arrhenius Plot @ 20V Basing on Eq. (5.2) log 2 T I against T 1 at different gate voltages (VG=8V & 20V) are obtained as shown in Figs. 5.2 and 5.3. The barrier energy obtained from these plots is 0.125ev and 0.55ev respectively for 8V and 20V. This indicates that there are two types of traps active at intermediate and high field regions, however the origin of the traps is not known. To understand this further studies are suggested. Temperature dependent data shows that there is a rapid increase of the leakage current at high fields suggesting that the charge retention capability of the device would be adversely affected at elevated temperatures.
72 References  G. E. Moore, Cramming More Components onto Integrated Circuits ftp://download.intel.com/research/silicon/moorespaper.pdf.  International Technology Roadmap for Semiconductors, the ITRS 2002 Update (http://public.itrs.net/).  S. Mori, Y. Y. Araki, M. Sato, H. Meguro, H. Tsunoda, E. Kamiya, K. Yoshikawa, N. Arai, E. Sakagami, Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices, IEEE Transactions on Electron Devices, vol 43, pp. 47, 1996.  Bin Yu, Haihong Wang, C. Riccobene, Qi Xiang, Ming-Ren Lin, Limits of gateoxide scaling in nano-transistors, VLSI Technology, 2000. Digest of Technical Papers. 2000 Symposium on 2000 Page(s): 90 91.  B. Cheng, M. Cao, R. Rao, A. Inani, P. Vande Voorde, W.M. Greene, J.M.C. Stork, Yu Zhiping, P.M. Zeitzoff, J.C.S. Woo, The impact of high-k gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs, IEEE Transactions on Electron Devices, vol 46, pp. 1537, 1999.  C. T. Liu, Circuit requirement and integration challenges of thin gate dielectrics for ultra small MOSFETs, IEDM Technical Digest, pp. 747, 1998.  Byoung Hun Lee, Laegu Kang, Wen-Jie Qi, Renee Nieh, Yongjoo Jeon, Kastunori Onishi, Jack.C Lee, Ultrathin hafnium oxide with low leakage and excellent reliability for alternative gate dielectric application, IEDM Technical Digest, pp.133, 1999.  M. Balog, M. Schieber, M. Michman, S. Patai, Chemical vapor deposition and characterization of HfO2 films from organo-hafnium compounds, Thin Solid Films, vol 41, pp 247, 1977.  T. Yasuda, Y. Ma, S. Habermehl, G. Lucovsky, Low-temperature preparation of SiO2/Si(100) interfaces using a two-step remote plasma-assisted oxidationdeposition process, Applied Physics Letters, vol 60, pp434.
73  W. J. Zhu, Tso-Ping Ma, Takashi Tamagawa, J. Kim, Y.Di, Current Transport in Metal/Hafnium Oxide/Silicon Structure, IEEE Electron Device Letters, vol. 23, no2.  S. Mori, Y. Y. Araki, M. Sato, H. Meguro, H. Tsunoda, E. Kamiya, K. Yoshikawa, N. Arai, E. Sakagami, Thickness scaling limitation factors of ONO interpoly dielectric for nonvolatile memory devices, IEEE Transactions on Electron Devices, vol 43, pp. 47, 1996.  S. M. Sze, Physics of Semiconductor Devices, 2nd ed., John Wiley & Sons Inc., New York, 1981.  E.H. Nicollian, J.R. Brews, MOS Physics and Technology, Wiley, New York 1982.  B. E. Deal, Standardized Terminology for Oxide Charges Associated with Thermally Oxidized Silicon, IEEE Trans. Electron Devices, vol 27, pp 606, 1980.  M. Mansouri, Floating Gate Flash Memory Devices Using High-k Materials as Inter-Poly Oxide Thesis (Ph.D.), University of South Florida, 2002.  M. I. Leon, G. Reinhard, Handbook of thin film technology, McGraw-Hill, New York, 1970.  W. D. Brown, J. E. Brewer, Nonvolatile Semiconductor Memory Technology, IEEE, New York, 1998.  G. D. Wilk, R. M. Wallace, J. M. Anthony, HighGate Dielectrics: Current Status and Material properties Considerations, Applied Physics Review, Journal of Applied Physics, vol 89, 2001.  R. C. Jaeger, Introduction to Microelectronics Fabrication, Modular Series on Solid State Devices-V, Addison-Wesley, New York, 1988.  S. Wolf, R. N. Tauber, Silicon Processing for the VLSI era, 2nd ed, vol1,Processing Technology, Lattice Press, California, 2000.  S. M. Sze, Physics of Semiconductor Devices, 2nd ed., Fig 21, John Wiley & Sons Inc., New York, 1981.  S. O. Kasap, Principles of Electronic Materials and Devices, 2nd ed., McGrawHill Higher Education, Boston, 2002.
75 Appendix A: MATLAB Program A program is written in MATLAB to find the Poole-Frenkel slope. The data available in Microsoft Excel files is first imported to the MATLAB workspace. Later the imported variables are used to obtain the plots and fit a straight line. The program is self explanatory with the inserted comments. %all the comments are preceded by a % sign %Program to fit a straight line for a given curve with given variables clear all; %Loads the data from matlab data file SL1_5.mat into the current workspace load SL1_5 % m is the number of elements in the variable m = length(I) ; %Physical thickness of the high-k layer d = 294e-8; % k is dielectric constant k=25.6*(d/(d+14.16e-8)) %Slope is the theoretical slope Theoretical_Slope=(1.6E-19/(1.3807E-23*298))*sqrt(1.6e-19/(pi*k*8.854e-14)) %Electric field calculation-'A' is the x-variable for Poole-Frenkel plot
76 Appendix A (Continued) E_F = V/d; A=sqrt(E_F); J=I/0.0001; %B is the y-variable for the Poole-Frenkel plot for j=1:m B(j)=J(j)/E_F(j); B1(j)=log(B(j)); end; % p is the matrix that contains the coefficients for the 1st order % polynomial equation with variables 'A' and 'B1' p=polyfit(A,B1,1) % new value for the y-variable is calculated that satisfies a straight line f=polyval(p,A); for i=1:m B2(i)=exp(f(i)); end semilogy(A,B,'-+'); hold on; semilogy(A,B2,'-*'); Measured_Slope=p
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Characterization of HfO films for flash memory applications
h [electronic resource] /
by Surendra Gaddipati.
[Tampa, Fla.] :
University of South Florida,
Thesis (M.S.E.E.)--University of South Florida, 2004.
Includes bibliographical references.
Text (Electronic thesis) in PDF format.
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ABSTRACT: The scaling of integrated circuits requires the use of alternative dielectric materials as the replacement for silicon dioxide in the submicron devices. The scaling limit for silicon dioxide used in MOSFETs is 1.2nm and the Oxide Nitride Oxide (ONO) stack used in flash memory applications is 13.0nm. The use of alternative dielectrics with high-
Adviser: Chiou, Y. L.
x Electrical Engineering
t USF Electronic Theses and Dissertations.