USF Libraries
USF Digital Collections

Stimulus-free RT level power model using belief propagation

MISSING IMAGE

Material Information

Title:
Stimulus-free RT level power model using belief propagation
Physical Description:
Book
Language:
English
Creator:
Ponraj, Sathishkumar
Publisher:
University of South Florida
Place of Publication:
Tampa, Fla.
Publication Date:

Subjects

Subjects / Keywords:
inference
sampling
clique
simulation
Behavioral Level
Register Transfer Level
bottom-up
top-down
Dissertations, Academic -- Electrical Engineering -- Masters -- USF
Genre:
government publication (state, provincial, terriorial, dependent)   ( marcgt )
bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

Notes

Summary:
ABSTRACT: Power consumption is one of the major bottlenecks in current and future VLSI design. Early microprocessors, which consumed a few tens of watts, are now replaced by millions of transistors and with the introduction of easy-to-design tools to explore at unbelievable minimum dimensions, increase in chip density is increasing at a alarming rate and necessitates faster power estimation methods. Gate level power estimation techniques are highly accurate methods but when time is the main constraint, power has to be estimated a lot higher in the abstraction level. Estimating power at higher levels also saves valuable time and cost involved in redesigning when design specifications are not met. We estimate power at every levels of abstraction for a breadth first design-space exploration.This work targets a stimulus-free pattern-insensitive RT level hierarchical probabilistic model, called Behavioral Induced Directed Acyclic Graph (BIDAG), that can freely traverse between the RT and logic level and we prove that such a model corresponds to a Bayesian Network to map all the dependencies and can be used to model the joint probability distribution of a set of variables. Each node or variable in this structure represents a gate level Directed Acyclic Graph structure, called the Logic Induced Directed Acyclic Graph (LIDAG). We employ Bayesian networks for the exact representation of underlying probabilistic framework at RT level, capturing the dependence exactly and again use the same probabilistic model for the logic level. Bayesian networks are graphical representations used to concisely represent the uncertain knowledge of the system.In order to get an posterior belief of a query node or variable, with or without preset nodes or variables called the evidence nodes, we use stochastic inference algorithm, based on importance sampling method, called the Evidence Pre-propagation Importance Sampling (EPIS) which is anytime and scales really well for RT and logic networks. Experimental results indicate that this method of estimation yields high accuracy and is qualitatively superior to macro-models under a wider range of input patterns. The main highlights of this work is that as it is a probabilistic model, it is input pattern independent and nonsimulative property implies less time for power modelling.
Thesis:
Thesis (M.S.E.E.)--University of South Florida, 2004.
Bibliography:
Includes bibliographical references.
System Details:
System requirements: World Wide Web browser and PDF reader.
System Details:
Mode of access: World Wide Web.
Statement of Responsibility:
by Sathishkumar Ponraj.
General Note:
Title from PDF of title page.
General Note:
Document formatted into pages; contains 57 pages.

Record Information

Source Institution:
University of South Florida Library
Holding Location:
University of South Florida
Rights Management:
All applicable rights reserved by the source institution and holding location.
Resource Identifier:
aleph - 001498130
oclc - 57716635
notis - AJU6725
usfldc doi - E14-SFE0000531
usfldc handle - e14.531
System ID:
SFS0025222:00001


This item is only available as the following downloads:


Full Text

PAGE 1

Stimulus-FreeRTLevelPowerModelusingBeliefPropagationbySathishkumarPonrajAthesissubmittedinpartialfulllmentoftherequirementsforthedegreeofMasterofScienceinElectricalEngineeringDepartmentofElectricalEngineeringCollegeofEngineeringUniversityofSouthFloridaMajorProfessor:SanjuktaBhanja,Ph.D.WilfridoA.Moreno,Ph.D.KennethA.Buckle,Ph.D.DateofApproval:October25,2004Keywords:Top-down,Bottom-up,RegisterTransferLevel,BehavioralLevel,Simulation,Clique,Inference,SamplingcCopyright2004,SathishkumarPonraj

PAGE 2

DEDICATIONTomyparents,Ponraj&Hemalatha,fortheirunconditionallove,guidance,supportandenthusiasm.

PAGE 3

ACKNOWLEDGEMENTSIwouldliketotakethisopportunitytoexpressmysinceregratitudetomyadvisorDr.San-juktaBhanjaforherconstantencouragement,supportandguidancethroughtoutthecourseoftheresearch.IwouldalsoliketothankDr.WildoA.MorenoandDr.KennethA.Buckleforac-ceptingmyrequestandservingmycommittee.IwouldalsoliketothankmyfriendKarthikeyanBalakrishnanforencouragingmeathardtimesandgivingmeinnovativeideas.

PAGE 4

TABLEOFCONTENTSLISTOFTABLESiiiLISTOFFIGURESivABSTRACTvCHAPTER1INTRODUCTION11.1VLSIPowerConsumption11.1.1StaticPowerConsumption11.1.2Short-CircuitPowerConsumption21.1.3DynamicPowerConsumption21.2DomainsofDescription31.3LevelsofAbstraction51.3.1ArchitecturalLevel51.3.2AlgorithmicLevel51.3.3FunctionalBlockLevel51.3.4LogicLevel61.3.5CircuitLevel61.4ComponentsofRegisterTransferLevel61.5ContributionsofthisThesis61.5.1BehaviorInducedDAG71.5.2LogicInducedDAG71.6FlowofthisThesis8CHAPTER2RELATEDWORK92.1Top-DownPowerEstimationTechniques102.2Bottom-UpPowerEstimationTechniques12CHAPTER3BAYESIANNETWORKSFORREGISTERTRANSFERLEVELPOWERMODELING163.1BayesianNetworks193.2BehaviorInducedDirectedAcyclicGraph253.3LogicInducedDirectedAcyclicGraph28CHAPTER4BAYESIANNETWORKINFERENCE314.1ExactInferenceAlgorithms314.2ApproximateInference324.2.1ProbabilisticLogicSampling33i

PAGE 5

4.2.2LikelihoodWeighting334.2.3AdaptiveImportanceSampling344.2.4EvidencePrePropagatedImportanceSampling35CHAPTER5EXPERIMENTALRESULTS38CHAPTER6CONCLUSION43REFERENCES44ii

PAGE 6

LISTOFTABLESTable3.1.ConditinalProbabilityTablefortheSumBitofanAdder29Table3.2.ConditionalProbabilitySpecicationsforOutputandInputLineTransitionsforTwoInputANDGate30Table5.1.ResultsonTotalDynamicPowerDissipationforBenchmarkCircuits38Table5.2.TotalDynamicPowerDissipationforBenchmarkCircuits39Table5.3.TotalDynamicPowerDissipationforBenchmarkCircuits39Table5.4.ResultsonTotalDynamicPowerDissipationforBenchmarkCircuitsforDif-ferentImplementaitonofAdder40Table5.5.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforFIRFilter40Table5.6.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforFIRFilter40Table5.7.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforFIRFilter40Table5.8.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforIIRFilter40Table5.9.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforIIRFilter41Table5.10.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforIIRFilter41Table5.11.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforEL-LIPTICFilter41Table5.12.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforEL-LIPTICFilter41Table5.13.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforEL-LIPTICFilter42iii

PAGE 7

LISTOFFIGURESFigure1.1.DesignRepresentation4Figure2.1.Top-DownandBottom-UpMethods11Figure2.2.RegisterTransferLevelPowerEstimationTechniques15Figure3.1.FullAdderLogicCircuit17Figure3.2.BayesianNetworkfortheFullAdder18Figure3.3.GraphicalModelsusedtoRepresentaDigitalCircuit19Figure3.4.ParentsforEachoftheOutputBitsofan4-BitAdder23Figure3.5.ParentsforEachoftheOutputBitsofan4-BitAdderafterIntroductionofDummyNodes24Figure3.6.DataFlowGraphforanIIRFilter26Figure3.7.DirectedAcyclicGraphforanIIRFilter27Figure3.8.TerminalNodeSwitchingPropagatedtotheLIDAG28Figure4.1.PowerEstimationSteps37iv

PAGE 8

STIMULUS-FREERTLEVELPOWERMODELUSINGBELIEFPROPAGATIONSathishkumarPonrajABSTRACTPowerconsumptionisoneofthemajorbottleneckincurrentandfutureVLSIdesign.Earlymicroprocessorswhichconsumedafewtensofwattsarenowreplacedbymillionsoftransistorsandwiththeintroductionofeasy-to-designtoolstoexploreatunbelievableminimumdimensions,increaseinchipdensityisincreasingataalarmingratenecessitatesfasterpowerestimationmethods.Gatelevelpowerestimationtechniquesarehighlyaccuratemethodsbutwhentimeisthemainconstraintpowerhastobeestimatedalothigherintheabstractionlevel.Estimatingpowerathigherlevelsalsosavesvaluabletimeandcostinvolvedinredesigningwhendesignspecicationsnotmet.Weestimatepowerateverylevelsofabstractionforabreadthrstdesign-spaceexploration.Thisworktargetsastimulus-freepattern-insensitiveRTlevelhierarchicalprobabilisticmodel,calledBehavioralInducedDirectedAcyclicGraph(BIDAG),thatcanfreelytraversebetweentheRTandlogiclevelandweprovethatsuchamodelcorrespondstoaBayesianNetworktomapallthedependenciesandcanbeusedtomodelthejointprobabilitydistributionofasetofvariables.EachnodeorvariableinthisstructurerepresentsagatelevelDirectedAcyclicGraphstructure,calledtheLogicInducedDirectedAcyclicGraph(LIDAG).WeemploybayesiannetworksfortheexactrepresentationofunderlyingprobabilisticframeworkatRTlevelcapturingthedependenceexactlyandagainusethesameprobabilisticmodelforthelogiclevel.Bayesiannetworksaregraphicalrepresentationsusedtoconciselyrepresenttheuncertainknowledgeofthesystem.Inordertogetanposteriorbeliefofaquerynodeorvariable,withorwithoutpresetnodesorvariablescalledtheevidencenodes,weusestochasticinferencealgorithm,basedonimportancesamplingmethod,calledtheEvidencePre-propagationImportanceSampling(EPIS)whichisanytimeandscalesreallywellforRTandlogicnetworks.Experimenatalresultsindicatethatthismethodofestimationyieldsv

PAGE 9

highaccuracyandisqualitativelysuperiortomacro-modelsunderawiderrangeofinputpatterns.Themainhighlightsofthisworkisthatasitisprobabilisticmodel,itisinputpatternindependentandnonsimulativepropertyimplieslesstimeforpowermodelling.vi

PAGE 10

CHAPTER1INTRODUCTIONUntilrecentlythemajorconcernsoftheVLSIdesignresearchwerearea,performance,costandreliability;thedesignpowerwasofsecondaryconcern.Withthedevicesizesgraduallyshrinkingtohavebetterperformanceandpackagingofmillionsoftransistorsinasinglechipthepowerdissipation,whichincreasesasaresult,hasbecomeamorecriticaldesignconcernthanspeedandarea.Theincreaseinpowerdissipationincreasesthecostforcoolingthechipandtherebyincreasesthebatteryweight.Toovercometheseproblemsdesignershadtomakedevicesthatoperateatlowpower.Estimationofpowerconsumptionofthedesignistherststeptowardsintegratingpowerminimizationtechniques.1.1VLSIPowerConsumptionTheaveragepowerdissipatedinadigitalCMOScircuitisgivenbytheformula,PavgPdynamicPshortcircuitPleakagePstatic(1.1)where,Pavgistheaveragepowerdissipation,Pdynamicisthedynamicpowerdissipationduetoswitchingoftransistors,Pshortcircuitistheshort-circuitcurrentpowerdissipationwhenthereisadirectpathfrompowersupplytoground,PleakageisthepowerdissipationduetoleakagecurrentsandPstaticisthestaticpowerdissipation.1.1.1StaticPowerConsumptionTheCMOScircuitsaredesignedinsuchawaythatatanytimeforainputstateonlyoneofthetwonetworks,eitherthepull-uporthepull-downnetworkis”ON”andtheothernetworkis”OFF”.1

PAGE 11

Butinreality,thereissomesmallstaticdissipationduetothereversebiasleakagebetweendiffusionregionsandthesubstrate.Thissubthresholdconductioncontributestothestaticdissipation.1.1.2Short-CircuitPowerConsumptionThecurrentthatowsthroughboththepull-upandpull-downnetworksduringthetransitionpe-riod,icc,iscalledtheshort-circuitcurrentandhencetheshortcircuitpowerdissipation,Pshortcircuit.1.1.3DynamicPowerConsumptionThecharginganddischargingoftheparasiticcapacitancecontributestothedynamicpowerdissipation,Pdynamic.Thedynamicpowerhasbeenthedominantcomponentinpowerdissipationandcontributestoabout80%ofthetotalpower.ThedynamicpowerisgivenbytheequationPdynamic05fclkV2ddClSx(1.2)wherePdynamicisthedynamicpowerdissipation,fclkistheclockfrequency,Vddisthesupplyvoltage,ClistheloadcapacitanceandSxistheaverageswitchingactivityofanoutputnodex.Itisevidentfromequation1.2thatexceptfortheloadcapacitanceandtheswitchingactivityofanode,alltheothervariablesareconstants.Hencethedynamicpowerestimationcanbeeasilycalculatediftheloadcapacitanceandswitchingactivityareknown.Powerestimationhasbeenperformedatdifferntlevelsofofabstraction,namelyarchitecturallevel,algorithmiclevel,functionalblocklevel,logiclevel,circuitlevel.ReadercanrefertotheChapter2forclearunderstandingofvariouspowerestimationtechniquesateachoftheseabstrac-tionlevels.Powercanbeaccuratelyestimatedatlowlevelapproaches,suchasthelogiclevelandthecircuitlevelbuttheonlyproblemwiththepowerestimationatthelatterlevelsisthatbythetimethecircuithasbeenspeciedingatesandtransistors,ifthedesignspecicationsarenotmet,thewholecircuithastobedesignedagainwithdifferentimplementation.Hencethetimeinvolvedandtheheavycostforredesignstepactasdrivingforcestowardsthehighlevelpowerestimation.Thoughpowerisalittleinaccurateinthislevel,thedesignerisallowedtoperformarchitecturalexplorationandtrydifferentimplementationslotearlyinthedesigncycle.Inthisthesiswebringin2

PAGE 12

tofocustheimportanceofRTlevelpowerestimationandproposeatechniqueofpowerestimationatRTlevelusingaProbabilisticGraphicalmodelcalledtheBayesiannetworks.BayesiannetworksarediscussedindetailinChapter3.AttheRTlevelifthegatelevelimplementationofthecircuitisknownthedynamicpower,whichisthedominatingpowercomponentiscompletelydependentontheswitchingactivityofthenode.Switchinactivityofanodedenotestotheactualactivityofthenode,whenthenodemakesatransitionfrom01or10.Higherswitchingactivitymeansmorenumberofnodetransitionsandmoredynamicpowerdissipation.Toeffectivelymodeltheswitch-ingactivityofanodethefollowingfactorsshouldbetakenintoconcernarenodecorrelation,inputstatistics,circuitconnectivity.Thenodecorrelationissplitintotwosubcomponents,namelyspa-tialcorrelationsandtemporalcorrelations.TheTemporalcorrelationsreferstothedependenceofnodesswitchingactivityonthesamenodespreviousvalue.TheSpatialcorrelationreferstothede-pendenceofonenodesvalueonthatofothernodesinthecircuitandnally,whenthenodesvaluedependsontheothernodespreviousvaluesthenitsSpatio-temporalcorrelation.Manyworkshavebeendoneonpowerestimationwithonlyinputactivityintoconcern,butthisassumptionresultsinenormouserrorsinnalpower.Ourmodeltakesintoconcerntheinputactivity,spatialcorrelationandtemporalcorrelation.1.2DomainsofDescriptionAsstatedinearlierpowerestimationdoneathigherlevelofdesignspecicationareadvanta-geousthancomparedtothatdoneinthelowerlevels.Toperformsuchashiftbetweendifferentlevelsadetailedunderstandingofthedifferentmethodsofdesignrepresentationisvital.In[1]au-thorspresentthreedomainsforcircuitrepresentation.Thethreedomainsofcircuitrepresentationareasfollows:BehavioralDomain.StructuralDomain.PhysicalDomain.3

PAGE 13

STRUCTURAL DOMAINDOMAINPERFORMANCE SPECIFICATIONSALGORITHMSREGISTER TRANSFERSBOOLEAN EQUATIONSDIFFERENTIAL EQUATIONSPHYSICAL PARTITIONSCLUSTERS FLOORPLANSTRANSISTORSGATESALU, MUX, REGISTERSHARDWARE MODULESCPU, MEMORIESFUNCTIONAL BLOCKALGORITHMICARCHITECTURALCIRCUITLOGICCELL ESTIMATESCELL DETAILSPHYSICAL DOMAIN BEHAVIORAL Figure1.1.DesignRepresentationThebehavioraldomainspeciesthebehaviorofthefunctionalityofthedesign.Atthisstageonlythestaticanddynamiccomponentsofthecircuitareknown.Thestaticcomponentreferstothetimeinvariantportionofdescriptionnamelyparticularoperation-multiplication,subtractionandthedynamiccomponentreferstotheorderingofoperations-sequencing,pipeliningandtiming.Atthisaxesofdomainspecication,interconnectionbetweenthedifferentcomponentsarenotknown.Thelogicalstructureofthedesign,theinterconnectionbetweendifferentcomponentsarespeciedinthisdomain.Thestructuraldomainistheintermediatestagebetweenthebehavioralandphysicaldomains.Thephysicaldomainofacircuitdeneshoweachofthecomponentsdescribedintheirstructuraldomainbeactuallyimplementedwithrealphysicalcomponents.Speed,powerandareaconstraintsarepartofthephysicaldomain.Duringthedesignspecication,eachofthethreedomainsmayalsocontaintwonewcompo-nentsnamely,descriptioncomponentandtheconstraintcomponent.Theinitialspecicationsofdesignwhichmaybeeitherspeciedbytheuserormaybetheoutputfromacontrolsystemforms4

PAGE 14

thedescriptioncomponent,usuallythedescriptioncomponentreferstotheinputspecication.Thesecondcomponent,constraintcomponentreferstothevarioustargetrequirementsofthedesign,namelyconstraintsonarea,timingandpower.1.3LevelsofAbstractionDomainsofdescriptionspeciedintheprevioussectioncanbehierarchicallydecomposedintodifferentlevelsofabstraction.Figure1.1.showsthethedifferentdomainsalongthreeaxesanddifferentlevelsofabstractionalongtheconcentriccircles.Eachofthesecomponenetsaredescribedindetailinthefollowingsection.1.3.1ArchitecturalLevelArchitecturallevelisthetopmostabstractionleveloftencalledasthesystemlevel.Thebehav-ioraldomainatthearchitecturallevelspeciesthebehaviorofthesystem,withoutconsideringthedetailsonhowtheoperationoccurs.Thecomponentssuchasthecontrolunits,processorswhichperformsuchoperationsspeciedbythebehavioraldomainconstititethestructuraldomain.Asitthetopmostlevelofabstraction,moredetailedlogicalstructureisunavailable,andhencephysicalpartitioningofthedesigndetailsarespeciedbythephysicaldomain.1.3.2AlgorithmicLevelAlgorithmiclevelalsoknownasBehaviorallevel,describesthebehavioralofthedomainintermsofalgorithms,owcharts,processesandstructures.ThehardwaremodulesthatareusedtorepresenttheBehavioraldomain,suchasthecontrolpathanddatapath,isspeciedintheStructuraldomain.ClusteringorpartiotioningofsimilaroperationsthatmightbedescribedinthestructuraldomainaredescribedinthePhysicaldomain.1.3.3FunctionalBlockLevelAlsocalledasRegisterTransferLevel(RTL),thislevelformstheboundarybetweenthelogicgatesandhigherlevelrepresentation.Thearithmeticandlogicoperationsofthedatastoredinregis-5

PAGE 15

tersconstitutethebehavioraldomainatRTLevel.Manymethodsareusedtorepresentthebehavior,namelythefunctionalordataowmethodorthroughstatemachineorientedmethods.Componentssuchasmultiplexors,arithmeticlogicunits,comparatorsconstitutethestructuraldomain.Theyphysicaldomainatthisleveldealswiththeoorplanningthelayoutofthedesign.1.3.4LogicLevelInLogicLevel,alsocalledastheGateLevelthebehaviorisspeciedbybooleanequations.Inthestructuraldomaingatesareusedtoimplementthespeciedbehavior.Atthisincreasinglydetailedspecicationlevel,thetimingconstraintsmaydetailedwithinformationonpropagationdelay,setupandholdtimes.1.3.5CircuitLevelThisisthebottommostabstractionlevelwiththebehaviordescribedintermsofdifferentialequationsrepresentingthecurrentandvoltageterms,structuraldomainintermsoftransistors,ca-pacitors,diodes,resistorsandthephysicaldomaincontributestogeometricspecicationsandtheirplacement.1.4ComponentsofRegisterTransferLevelRegisterTransferLeveldesignsarecomposedoftwocomponentsthatinteractwitheachother,namelythedatapathandthecontrollerpath.Thedatapathconsistsoftheexecutionunitssuchastheadders,multipliers,multipliexors,buffersandregisters.Athigherlevelofdesignspecicationaccuratepowerestimationisdifcultduetothelackofsufcientimplementationdetail.Thecon-trollerconsistsofasetofstatemachinesandgeneratescontrollinesforthedatapathcomponents.1.5ContributionsofthisThesisInthisthesiswepresentanewmethodofpowerestimationthatutilizesthebehavioraldescrip-tionofthecircuitandgatelevelimplementationdetailstoeffectivelymodelthepower.Whenthebehavioralspecicationisgivenandthegateleveldetailsareknown,thentheloadcapacitancecan6

PAGE 16

beeasilycalculated.TheswitchingactivityateachnodeisthencalculatedusingtheBayesianNet-works.Modelsbuiltbasedonindependentinputs,randominputsarehighlyinefcientaswhentheinputforthecircuitisanoutputfromanothercircuittheinputsarehighlycorrelated.Ourmodelworksforbothindependentinputsandhighlycorrelatedinputs.Oncethepowerisestimatedusingonetypeofimplementation,anotherimplementationofthesamecircuitcanbeestimatedinnotimeandthebestofthetwocircuitscanbeselectedbasedonthedesignspecications.Inthisthesiswork,twotypesofadderimplemenationsaretestedfordifferenceinpowerofthewholecircuit.Thoughourmodeliszerodelaymodelresultinginsomereductioninestimation,ourmodelishighlytimeefcient.1.5.1BehaviorInducedDAGThebehavioraldescriptionisanDataFlowGraph(DFG)isusedtoconstructaBayesianNet-work(BIDAG),withnodesrepresentingthevariablesandthearcsrepresentatingthedependenciesbetweenthevariable.Oncethebayesiannetworkisconstructedweuseoneofthestochasticsam-plingalgorithmcalledtheEvidencePre-propagationalgorithmtomodelthenodedependencies.Sicethebehavioraldescriptionincludescomponentssuchasadders,multipliers,registers,subtrac-tors,weidentifyeachofthecomponentsinputsandfeedittoanotherbayesiannetwork(LIDAG)constructedusingthecomponentsimplementationdetails.1.5.2LogicInducedDAGTheterminalprobabilitiesfromtheBehavioralBayesianNetworkarefedtoabayesiancon-structedatthegatelevel.TheBayesiannetworkconstructedataLogicleveliscalledtheLogicInducedDirectedAcyclicGraph(LIDAG).OncetheoutputprobabilitiesareavailablefromtheBIDAGcalculatingpowerforanytypeofcircuitimplementationisveryfast.WeusedHSPICEtomodeltheloadcapacitancesandtoverifytheoutputsweusedourowngatelevelsimulatorandtheresultsarepresentedintheresultsection.ThisworkfocusesonmappingaBehavioralDataFlowGraphs(DFG's)intoGraphicalProbabilisticnetworkscalledtheBayesiannetworks.WenamedourstructureBIDAGasitisacombinationoftopdownandbottomupmethodologies.We7

PAGE 17

provethatBIDAGisabayesiannetworkandthenestimatepowerinRTLbenchmarkcircuitstoillustrateourcase.Oncethenodalswitchings,whichareinturninputstotheinternalcomponentsofthetop-levelcircuit,areknown,theseprobabilitiesarefedtoanLIDAG,whichisLogicInducedDirectedAcyclicGraphthatareusedtorepresenttheprobabilisticknowledgeofthegatelevelim-plementation.Withthisstepalltheinternalnodeswitchingofthedifferentcomponentsofthemaincircuitareextracted.ThenextstepinvolvescalculationofPowerwithcapacitanceextractedfromgatelevelimplementation.Sinceourmethodisacombinationaltop-down,bottom-upmethod,thecapacitancevaluesarealreadyextracted.AverageswitchingactivityisestimatedfortheRTLcom-ponentsandusedtocalculatepower.Thispowervalueiscomparedwithgatelevelpowerestimateandresultstabulated.1.6FlowofthisThesisTheoutlineofthisthesisisasfollows.DifferentpowerestimationtechniquesatRegisterTrans-ferlevelarediscussedintheChapter2.InChapter3wediscussthebasictheoryofBayesianNet-worksandmodellingaRTLcircuitusingbayesiannetwork.AftertheconstructionoftheBayesianNetworktheinferencing,whichisprobabilisticupdating,isexplainedintheChapter4andnallywepresentourresultinChapter5.8

PAGE 18

CHAPTER2RELATEDWORKLowpowerdesignhasbeentheprimaryconcernforcurrentVLSIresearchers.Shrinkingthedevicesizesandpackingmillionsoftransistorsinasinglechipincreasesthepowerdissipationperunitareaandthispowerhastobeestimatedinordertoimplementanylowpowertechnique.Powerestimationhasbeenperformedatdifferentlevelsofabstraction,suchasthelogiclevel,functionalblocklevel,algorithmiclevelandarchitecturallevel.Powerestimationatlogiclevelgiveshigheraccuracybutishighlyinefcientwithtimeandcostasexplainedearlier.ThepowerestimationatRegisterTransferLevelisfasterthanthegatelevelpowerestimation.SurveyofdifferenttechniquesofpowerestimationinRegisterTransferLevelhasbeenbestdiscussedin[2,3].TheRTLpowerestimationcanmethodscanbebroadlycategorizedintotwomethods,namelytop-downmethods.bottom-upmethods.Top-downmethodsareusedwhennoinformationisavailableontheblockwhosepoweristobeestiamted.Theblockactsasablackboxandthepowerismodelledwithknowledgeoftheinputstatistics.Theseblackboxmodelsarecalledasthesoftmacros.Top-downmothodsaredependentontheinitialconditions,suchastheactivityandthecapacitance.Iftheinternaldetailsofthefunctionalblockisknownthenthesemethodarehighlyinaccurate.Bottom-upmethodsareusedwhentheinternalimplementationdetailsofthefunctinalblocksareknown.Thesefunctionalblockswithsynthesizablegatelevelspecicationofthehardwareblocksarecalledthehardmacros.Figure2.1.showswhenbottom-upandtop-downmethodsbeapplied.IntherstcasefortheAdder,A1noinformationisavailableonthetypeimplimentationofadder.Itmightbearipplecarryadder,9

PAGE 19

carrypropagateadder.Butwhenimplementationdetailsareknownitfallsundertobottom-upmethods.2.1Top-DownPowerEstimationTechniquesSurveyofvarioustopdowntechniquesthatoperateatarchitectural,behavior,instructionandsystemdomainshasbeendonebyLandmanetal.[10].In[5]Mullerproposedamethodtocalculatepowerdissipation,areaandspeedbasedontheinformationfromaknowledgebase.Theuserhastodecideonthedesigndescriptionliketheestimatedgateequivalents,cells,switchingactivityandcapacitancesandaccuracydependsontheusersjudgement.Thesetechniqueshavesomeaccuracyinareaswherecomplexityparametersareeasilytoestimate.Inasimilartechniquebasedonthecomplexity[4],Liuetal.proposeddifferntcomplexityparametersfordifferentfunctionalblocksandtheswitchingactivityfactorwasstillassumedtobeauser-speciedconstant.EntropyandInformationtheoreticmesaureswereusedtoesitmatepowerin[6,7]and[8,9].In[7]activitydensityofthefunctionalblock,Disestimatedbasedontheentropy.Giventheprobabilityofthesignalispthen,theentropyofthenodeisgivenby,Hxplog21 p1plog21 1p(2.1)Ifthesignalcantakenvariablesthentheentropyisgivenby,Hxnin1pilog21 pi(2.2)UsingEquation2.2inputandoutputentropies,Hinp,Hout,areestimatedandtheaverageentropy,Havg,ofthefunctionalblockiscalculatedusingtheequation2.3.Havg23 nmHinp2Hinp(2.3)Entropyisgoodrepresentationofthesignalactivitywhenthesignalisconsideredindependentp05.Hencethesemethodsarebestsuitedwhentherandominputsareconsideredattheinputs.In[14]powerestimationforsoftmacros,functionalblockforwhichsynthesizableHDLisavailable10

PAGE 20

EACH COMPONENTSTRUCTURE OF ON THE TYPE OF NO INFORMATIONTOP DOWN INTERNAL NODE DETAILS KNOWNDETAILED KNOWLEDGEOF THE COMPONENTSKNOWNPRIMARY INPUTSCOMPONENT LIBRARYCOMPONENT LIBRARYBOTTOM UP METHODFINAL OUTPUTSAVAILABLE REGISTERREGISTERREGISTERREGISTER ADDERADDERADDERFINAL OUTPUTSPRIMARY INPUTSINFORMATION ON PRIMARY INPUTS AND OUTPUTS Figure2.1.Top-DownandBottom-UpMethods11

PAGE 21

butthegatelevelimplementations,dependingontheinputandoutputactivityisproposed.Charac-terizationisbasedonatechniqueofadaptivesignalprocessingknownasleastmeansquares.2.2Bottom-UpPowerEstimationTechniquesSeveralbottom-uppowerestimationtechniqueshavebeenproposedrecently.Whentheimple-mentationdetailsareknown,bottom-uptechniqueshavemoreaccuracythanthetop-downmethods.Thoughextensiveresearchhasbeenintheestimationofaveragepower,worksoncycle-by-cyclepowerhasalsobeenpresented.Mostbottom-upmethodsarebasedonmacromodeling.Apowermacromodelisconstructedforafunctionalblockandisthenusedforhighlevelpowerestimation.Macromodelsareclassiedintotwotypes:equation-basedmacromodels.look-uptablebasedmacromodel.Thesimplestpowermacromodelingtechniqueproposedin[15]calledthepowerfactorap-proximationmodelstheaveragepowerwiththeassumptionthattheinputsarehighlyindependent.Thisassumptionresultsinlossofaccuracyasthepowerisdependentoninputcorrelations.In[16]slightlyimprovedapproachwasproposedbyLandmanetal..Theinputsarenotcompletelyindependent,butthetemporalcorrelationsareconsideredintheMSBsandtheLSBsareconsid-eredrandom.Thisassumptioncanbemoreaccurateifmorestatisticslikethespatialcorrelationsandspatio-temporalcorrelationswereconsidered.Moreworksonregressionbasedmodelsinclude[17,18,21].Sinceregressionisdependentonthetrainingpattern,accuracyisdecreasedwhenoperatedunderdifferentinputpatternsthentheonesusedtocharacterizethemacromodel.In[18]twomacromodelingtechniqueswereproposedfortimeeffectiveandmoreaccuratemacromodel-ing,namelytheSamplermacromodelingandAdaptivemacromodeling.InSamplermacromodelingtechniqueinputsaresampledbasedonarandomsamplingmethodtherebyreducingthenumberofcyclesinwhichtheinputstatisticsarestudiedtherebyreducingthetimeforsimulation.Adap-tivemacromodelingisbasedonregressionanalysisutilizinggatelevelpowersimulationandhencerecordbetteraccuracy.12

PAGE 22

OneofthepioneeringworkbyNajmetal.[21]usedLook-Up-Tablebasedcharacterizationapproachtotobuildthepowermacromodelandhasbeenshowntohaveimporvedaccuracyandrobustness.ThisworkbyNajmetal.isanextensionoftheworkbythesameauthorin[36].In[36]athreedimensionaltableisconstructedwhoseaxesareaverageinputprobabilityPinp,averageinputtransitiondensityDinpandaverageoutputzerodelaytransitiondensityDout.Foranyselectionofthethreevaluesresultsinapowervalueforthemodule.ButthishasmoreerrorsincetwovaluesofPinp,Dinp,Doutdoesnotalwaysresultinsamepower.HenceNajmetal.introducedafourthdimensionintothetable,InputSpatialCorrelationsSCinp.Intheprevioussentencesinputprobability,istheprobabilitythatthesignalis'1',transitiondensity,isthenumbertransitionsperunittime,spatialCorrelationreferstothedependenceoftheparticularnodeonanynode.Theaveragepowerbasedonthefourdimensionallookuptableisgivenby,PavgfPinprDinprSCinprDout(2.4)Eachofthevariablesthatconstitutetheaxesofthemacromodelsatisfytheconditiongivenbelow,Dinp 2Pinp1Dinp 2(2.5)nD2inpPinp n1SCinpPinp(2.6)SimilarLook-up-tablesareutilizedinpowermacromodelingasin[20,34,22,23].Inputde-pendentandinputindependentmodelsdependoncharacterization.Characterizationistheprocessthatimprovesaccuracyofpowermodelsbyexploitingaccuratesimulationsofthegatelevelimple-mentationoftheunittobemodeled,repeatedforsignicantinputtransitions.Applicationssuchasnoiseanalysis,heatdissipationanalysisneedpowertobecalculatedateverycycle.Cluteringap-proachproposed[34]tocalculatethecycle-by-cyclepowerisbasedontheassumptionthatcloselyrelatedinputtransitionshavesimilarpowerdissipation.Thisassumptionisnotalwaystrueandwhenthenumberofclustersbecomeslargeitresultsininaccurateresults.Anautomaticprocedure13

PAGE 23

forcycle-accuratemacromodelgenerationwasproposedbyWuetal.[19].Improvedcharacteri-zationofmacromodelsareaddressedin[11,20,29,28,27,30,31].[20]isaLook-up-tablebasedapproach,whereinputsareclusteredforhigheraccuracy.Theaveragepoweristhenangivenby,PavgfPLinprPHinprDLinprDHinprDout(2.7)PLinpistheprobabilityofthelowswitchinginput,PHinpistheprobabilityofhighswitchinginput,DLinpdensityofthelowswitchinginput,DHinpisthedensityofthehighswitching,Doutisthedensityoftheoutput.ClusteringtheinputsbasedontheswitchingintohighandlowswitchingincreasesthedimensionoftheLookupTableandtherebyincreasesthecharacterizationtime.Powermodelusingnodesamplingwasproposedin[29].Theassumptionthatpowercanbemodeledwithpartialknowledgeoffewnodesishighlypronetoerrors.Anothernodesamplingtechniquewasproposedin[27]whereinsteadofinternalnodesaresampledinsteadoftheinputnodes.AnothercyclepowerestimationtechniqueproposedbyPotlapallyetal.in[11]isbasedonseperatingtheinputspaceintoregionswithsimilarpowerbehaviorandseperatemacromodelsareconstructedforeachoftheseinputspaces.TheselectionoftheappropriatepowermodelforagivenspaceisdeterminedbyafunctioncalledPowermodeIdenticationFunction(PIF).Powermacromodelingbasedonpowersensitivitywasproposedin[33].PowerisrepresentedasafunctionofpowersensitivitytoprimaryinputactivityzaxigivenbyEquation2.8andpowersensitivitytoprimaryinputprobabilityzPxigivenbyEquation2.9.ThenalpoweriscumofpowerduetonormalaveragepowerdissipationPnormandsensitivityandisgivenbytheEquation2.10.SpuriousactivityinRegisterTransferLevelisaddressedin[24,25].zaxidPoweravg daxiiprimaryinputsfanoutjdaj daxi(2.8)zaxidPoweravg dPxiiprimaryinputsfanoutjdaj dPxi(2.9)PowerPowernomiprimaryinputszaxiaxizPxiPxi(2.10)14

PAGE 24

TOP-DOWN METHODSPROBABILISTIC MACROMODEL BASEDTABLE BASED EQUATION BASEDRTL POWER ESTIMATION TECHNIQUESCosta et al., '99 [38]Ferreira et al., '00 [39]This thesis workTopology of RTL PowerEstimation Techniques BOTTOM-UP METHODS Crenshaw et al., 97, [12]Nemani et al., 96, [8]Nemani et al., '99, [6]Muller et. al., '91, [5]Potlapally et al., '01, [11]Liu et al., '94, [4] Landman, '96 [10]Marculescu et al., '96 [8], [9]Bogliolo et al., 97, [14] Gupta et al., '00 [21]Wu et al., '98 [19]Hsieh et al., '96 [18] Mehta et al., '96 [34]Anton et al., '01 [23]Bernacchia et al., '99 [22]Corganti et al., '99 [20]Bogliolo et al., '00 [17] Figure2.2.RegisterTransferLevelPowerEstimationTechniques15

PAGE 25

CHAPTER3BAYESIANNETWORKSFORREGISTERTRANSFERLEVELPOWERMODELINGTosolveacomplexproblemoneneedstohaveaclearknowledgeofthenatureoftheproblemandthereasonwhyithadhappened.Inmostofthereallifesituationstheknowledgeoftheproblemisobscureandcomingtoconculsionsbasedontheseuncertainknowledgeishighlyerraneous,thusrequiringadifferentmethodofrepresentation.Bayesiannetworks,alsocalledasBayesianbeliefnetworks,casualnetworksorprobabilisticnetworks,aregraphicalmodels,thatutilizetheprobabilisticandstatisticaltechniques,toconciselyrepresenttheknowledgeoftheuncertainity.ToillustratebetterabouttheneedforBayesiannetworks,considercircuitofafulladdershowninFigure3.1..Theprobabilitydistribution,thatgivesthecurrentknowledgeorbelief,ofthecurcuitoralsocalledasthebelieffortheadder,isafunctionwitheveryinput,outputandpresentstateofthegateandisrepresentedas,PArBrCrI1rI2rI3rI4rI5rI6rSumrCarry(3.1)Therealtimeintelligentsystemdomainsarehugewithmorenumberofvariablesintheprob-abilisticdistribution.Increaseinnumberofvariableseventuallymakesthebeliefupdatingun-tractable.Thegraphicalprobabilisticmodelsontheotherhandutilizethedependencybetweenthenodesandtheresultingprobabilitydistributionissimpler.BayesiannetworkforthefulladderisshownintheFigure3.2.,whereeachofthenodesrepresenttherandomvariablesandthelinksbetweenthenodesdeterminetheinuenceofonenodeoverother.HerenodesA,B,Careinputnodes,I1,I2,I3,I4areinternalnodesandSum,Carryareoutputnodes.WhenthebeliefofthenodesI1andI4areknownthentheposteriorbeliefofSumcanbeupdatedwithknowledgeofitsparent,I1andI4.Thisindependencyofachildnodeoverallothernodes,giventheitsparentnodes16

PAGE 26

I6I5I2I3I4FULL ADDER LOGIC CIRCUITCBSUMCARRYI1A Figure3.1.FullAdderLogicCircuitbeliefiscalledastheconditionalindependence.ABayesiannetworkrepresentstheexponentiallysizedjointprobabilitydistributioninacompactmanner.Thejointprobabilitydistributionforanetwithnvariables,withbeliefofparentPaXk,isgivenby,PX1rrXNn'kn1PXkPaXk(3.2)Hencegraphicalmodelsthatutilizetheconditionalindependence,areusedtoconciselyrepre-senttheprobabilisticknowledgeofthecircuit.Thedomainreferstoacollectionofvariablesinaset.Eachofthesevariableshaveadiscretespace,fromwheretheygettheirvalues.ThetermBeliefupdatingreferstoupdatingtheknowledgeofthepriorbeliefwithposteriorbelief.Thegraphsthatareusedtorepresentthebayesiannetworkandupdatethecurrentbeliefofanetworkcanbeofthreetypes,namelydirected,undirectedandhybrid.Thenodesinthegraphrepresentthevariableandtheedgebetweenthenodesrepresentthedirectdependencebetweenthenodes.Asthenamesuggests,inundirectedgraphsasshowninFigure3.3.(b)thenodesareconnectedbyanundirectededgeandthepathrepresentedbyN1rN5rN7rN8.ThedirectedgraphisshownintheFigure3.3.(a)withtheedgebetweenthenodesreplacedwithdirectedarcs.Thegraphisdirectedacyclicgraphand17

PAGE 27

AI4 I0BCI2I3 I1 BAYESIAN NETWORK FOR AN FULL ADDER Figure3.2.BayesianNetworkfortheFullAdder18

PAGE 28

(b) HYBRID GRAPHN8N7N6N5N4N3N2N1N8N7N6N5N4N3N2N1 N8N7N6N5N4N3N2N1 (b) DIRECTED GRAPH (a) UNDIRECTED GRAPH Figure3.3.GraphicalModelsusedtoRepresentaDigitalCircuitthepathisrepresetedasN4rN6rN7rN8rN10andeverynodehasaincomingheadandhasanoutgoingheadofthearrow.Ahybridgraphiscombinationofcyclicandacyclicgraphs.3.1BayesianNetworksBayesiannetworkisagraphicalmodelthatefcientlyencodesthejointprobabilitydistributionforlargesetofvariables.EachvariablevigetsitsvaluefromanitespaceDvi.Inourcaseinordertomodeltheswitchingactivityatthenodesofthebayesiannetwork,thenitespaceforeachofthevariablesisfourinlength,eachcontainingknowledgeonswitchingnamely,00r01r119

PAGE 29

0r11.Thedesignspaceisthenthecartesianproductofthespacesforthevariables.EachoftheelementinDvi,iscalledaconguration.TheuncertainitiesinthedependencebetweenvariablesarerepresentedintermsofaprobabilityfunctionPdenedoverthevariables.PXxYyrepresentsthebeliefonthetruthofxgiventhetruthofyandistermedasconditionalprobabilityandunconditionaldistributionovertheentiredomainisreferredtoas/jointprobabilitydistribution.InthefollowingsectionwewilldiscussvariousnotationsanddenitionsfromPearl[44].Denition1:LetU=U1rU2rUnbeanitesetofvariablesthatcanassumediscreteval-ues.LetPbethejointprobabilityfunctionoverthevariablesinU,andletX,YandZbeanythreesubsetsofU.X,YandZmayormaynotbedisjoint.XandYaresaidtobeconditionallyindependentgivenZifPxyrzPxzwheneverPyrz0(3.3)IXrZrYrepresentstheconditionalindependenceofXandY,whichstatesthatXandYareindependentoneachotherwhentheknowledgeoftheothersubsetZisknown.IntheFigure3.3.havingaknowledgeofthenode,I1,makesthevariablesAandSumindependentofeachother.Adependencymodel,M,ofadomainshouldcaptureallthesetripletsnamelyArI1rSum.Thepropertiesinvolvingthenotionofindependenceareaxiomatizedbythefollowingtheorem.Theorem1:LetX,Y,andZbethreedistinctsubsetsofU.IfIXrZrYstandsfortherelation“XisindependentofYgivenZ”insomeprobabilisticmodelP,thenImustsatisfythefollowingfourindependentconditions:IXrZrYIYrZrX(symmetry)(3.4)IXrZrYWIXrZrY&XrZrW(decomposition)(3.5)IXrZrYWIXrZWrY(weakunion)(3.6)20

PAGE 30

IXrZrY&IXrZYrWIXrZrYW(contraction)(3.7)SymmetryaxiomstatesthatifanobservationofZisavailableandifXhasnoinuenceonY,thenYhasnoinformationonX.ThedecompositionaxiomstatesthatiftwosetsareirrelevanttoXhavingaknowledgeofZ,thentheyareindividuallyirrelevant.TheaxiomofweakunionsuggeststhatlearninganirrelevantinformationWcannotmakeYmorerelevantofX.IfWisfoundirrelevanttoXafterlearningsomeirrelevantinformationY,thenWwasirrelevanttoXevenbeforewelearnedY.Denition2:IfX,Y,andZarethreedistinctnodesubsetsinaDAGD,thenXissaidtobed-separatedfromYbyZ,XZY,ifthereisnopathbetweenanynodeinXandanynodeinYalongwhichthefollowingtwoconditionshold:(1)everynodeonthepathwithconvergingarrowsisinZorhasadescendentinZand(2)everyothernodeisoutsideZ.Ifthereexistsuchapathwheretheabovetwoconditionshold,thepathiscalledanactivepath.IntheFigure3.3.,considerthenodesSum,I4andI1.NodeSumisconnectedwithBviaI2andI4.Thereexiststwointermediatenodesinbetweentheprimarynodeandtheproductnode.ThenodeI2d-seperatesthenodesI4andB,whichinturnisdeseperatedfromnodeSumbytheI2.I4andI1actingasdirectparentstotheSumnodecannotbefurtherd-seperated.NextwediscussabouttheDAGwithwithsuchd-seperationswithconditionalindependence.Denition3:ADAGDissaidtobeanI-mapofadependencymodelMifeveryd-separationconditiondisplayedinDcorrespondstoavalidconditionalindependencerelationshipinM,i.e.,ifforeverythreedisjointsetsofverticesX,Y,andZ,wehave,XZY IXrZrY.IntheFigure3.3.nodesSum,I4,Isexhibitconditionalindependence,whennodeSumisun-changednomatterbythepresenceofabsenceoftheknowledgeofI2,whichisshownintheequa-tion3.8.Furtherseperationofthenodesresultsinlossofdependencyandinformationandthusthisminimizedd-seperatedgraphsformtheminimalI-mapandtheDAGwithminimumI-mapsiscalledasaBayesianNetwork.Thisisillustratedinthefollowingdenitions.pSumArBrCrI1rI2rI4pSumI1rI4(3.8)21

PAGE 31

Denition4:ADAGisaminimalI-mapofMifnoneofitsedgescanbedeletedwithoutdestroyingitsdependencymodelM.Denition5:GivenaprobabilityfunctionPonasetofvariablesU,aDAGDiscalledaBayesianNetworkofPifDisaminimumI-mapofP.Denition6:AMarkovblanketofelementXi!UisasubsetSofUforwhichIXirSrUSXiandXi"!S.AsetiscalledaMarkovboundary,BiofXiifitisaminimalMarkovblanketofXi,i.e.,noneofitspropersubsetssatisfythetripletindependencerelation.Denition7:LetMbeadependencymodeldenedonasetUX1rrXnofelements,andletdbeanorderingXd1rXd2roftheelementsofU.TheboundarystrataofMtermedasBMrelativetodisanorderedsetofsubsetsofU,Bd1rBd2r#suchthateachBdiisaMarkovboundary(denedabove)ofXdiwithrespecttothesetUdi%$UXd1rXd2r&rXd'i1(,i.e.BdiistheminimalsetsatisfyingBdi$UandIXdirBdirUdiBdi.TheDAGcreatedbydesignatingeachBdiastheparentsofthecorrespondingvertexXdiiscalledaboundaryDAGofMrelativetod.ItshouldbenotedherethattheonlyorderingrestrictionisthatthevariablesintheMarkovBoundaryset(ofaparticularvariable)havetobeorderedbeforetherandomvariable.Theorem2:LetMbeanydependencymodelsatisfyingtheaxiomsofindependencelistedinEqs.3.4-3.7.IfthegraphstructureDisaboundaryDAGofMrelativetoorderingd,thenDisaminimalI-mapofM.Thistheoremalongwithdenitions2,3,and4above,speciesthestructureoftheBayesiannetwork.WeusethesetoproveourtheoremregardingthestructureofBayesiannetworktocapturetheswitchingactivityofacombinationalcircuit.Denition8:AtaBehaviorallevel,theDirectedAcyclicGraph(DAG)representsthebehaviorofthesystem,whereeachnoderepresentsthevariables,includingprimary,intermediateandoutput,andedgesspecifythedirectdepedencyofthenodesbeingconnected.Theintermediatenodesaretheresultofoutputsfrommultipliers,addersorcomparators.Eachnodecarrytheswitchingprobabilityinformationwhichisthentraversedtothechildnodestowhichtheoutgoingdirectedgraphsfromprimarynodeareconnected.TheDAGforthebehavioralspeciation,calledthe22

PAGE 32

B1B2B3 S3 S0S1S2S3S4A0A1A2A3B0C04-BIT ADDER B1B2S1 C0A0B0S0 B0 C0A0A1 A2B0B1B2S2 C0A0A1A2A3B0B1B2B3 A1 C0A0Figure3.4.ParentsforEachoftheOutputBitsofan4-BitAdderBehaviorInducedDirectedAcyclicGraph(BIDAG)isshownforanIIRFilterFigure3.7..HerethenodesA0,A1,A2,A3,A4,B0,B1,B2,B3,B4,B5aretheprimarynodes,I1,I2,I3,I4,I5,I6,I7,I8,aretheintermediatenodesasaresultofadditionormultiplicationandYoutistheoutputnode.Thedependenciesoftheoutputbitsofan4-BitAdderisshowninFigure3.4..ItisevidentfromthegurethatasthesizeoftheAdderincreases,thenetnumberofparentsforeachoftheoutputbitalsoincreasesandtherebythejointprobabilitydistributionforanyhigherorderoutputbitisacomplexfunction.IntheexampleshowninFigure3.4.,numberofparentsfortheS3bitis9.Inordertoovercomethecomplexfunctionsthatresultfromthepreviousstructure,dummynodesareintroducedinthecircuittominimizethesizeoftheprobabilitydistribution.Thesedummynodeseffectivelycapturethedependencerelationbetweenanodetoitsparents.Introductionofdummynodesin4-BitAddercircuitisshowninFigure3.5.wherenodes,C1,C2,C3,C4arethedummynodesthatcontributetoacasewhereanyoutputnodeisdependentonlyonamaximumof3inputs.Theorem3:TheBIDAGstructureisaminimalI-mapoftheunderlyingswitchingdependencymodelandhenceisaBayesiannetwork.Proof:Tobetterunderstand,letustakethedataowgraph23

PAGE 33

A1A0 A2S2S2C2B2A2CinParents of Sum Node S2S4S3S1S0C3C2C1B3B2B1B0A3 Figure3.5.ParentsforEachoftheOutputBitsofan4-BitAdderafterIntroductionofDummyNodes24

PAGE 34

ofthefulladdershownin3.5.,wherenodes,ArBrepresentsetofallthebitinputstotheadderandthebitsCrSdenotethecarryordummynodesandthesumnodes.ItisclearfromthegurethatSumnodesaredependentonthepreviousbitadderoutputCarry,whichinturnisconditionallydependentontheprimaryinputsatthatpreviousstage.ThoughA0rB0rA1rB1rC1rC2constitutethedistantandimmediateparentofthenodeS2,knowledgeofswitchingattheintermediatenodewhichformitsimmediateparentorcalledastheMarkovboundary,C2issufcientenoughtomodeltheSumandCarry,thusprovingthatIS2C2A1andanyswitchingintheinputnodeswillhavecausaleffectontheoutputnodes,inourcase,Adders.ThusformedBIDAGisaDirectedAcyclicGraphstructurecorrespondsexactlytotheDAGstructureonewouldarrivebyconsideringprinciplesofcausalitywhichstatesthatonecanarriveataappropriateBayesianNetworkbydirectinglinksfromnodesthatarecausestonodesthatrepresentimmediateeffects,withthedirectedlinktheimmediatecausesofswitchingthatquality.3.2BehaviorInducedDirectedAcyclicGraphThepowermodelingpresentedinthisthesisworkutilizesinformationfromtwolevelsofdesignspecication,namelygatelevelandRegisterTransferLevel,thustwodifferenttypesofbayesiannetworksarerequiredtobeconstructed.Theconstructionofsuchbayesiannetworks,BIDAGsforBehaviorallevel,andGatelevelLIDAGsareexplainedinthefollowingsection.Atthebehaviorallevel,thecircuitisspeciedintermsofregisters,arithmeticunits,suchasadders,multipliersandatypicalDataFlowGraph(DFG)issuitableenoughtorepresentthecircuit,asshownforaIIRlterinFigure.3.6..Thisgraphcanbetransformedintoabayesiannetworkwithnodesactingasthevariablesandthearithmeticfunctions,addition,subtraction,multiplication,berepresentedbyadirectedarc.Thisdirectedarccapturesallthedependenciesofthechildnode,eg.I1multiplieroutput,ontheparentnodeA0.EachvariableornodeinthenetworkholdstheprobabilityofeachtypeoftransitionsA000rA001rA010rA011.FourbitinputsareconsideredandhenceeachA0issubdividedintoA00,A01,A02,A03andareindependentofeachotherunlesstheyareoutputsfromanothercomponentthatmightdecidetheinputofthecurrentcircuitinhand,the25

PAGE 35

*****KJHGFEDCBI1ADATA FLOW GRAPH OF IIR FILTERYout+I8+I7I6++I5I4I3I2 Figure3.6.DataFlowGraphforanIIRFilter26

PAGE 36

ABCDEFBAYESIAN NET FOR IIR FILTER YoutI8I7I6I5I4I3I2I1KJHG Figure3.7.DirectedAcyclicGraphforanIIRFilterIIRlter.Theowofmessages,forbeliefupdatingdiscussedinthenextchapter,dependsontheconditionalprobabilitytableconstructedfortheeachoftheunits,multipliers,adders.Inthecaseofanadder,whichdeterminesnodesI7,I8andYout,behavioralformatoftheadder'soutputsumandcarry,theequationformat,isutilizedtoconstructtheConditionalProbabilityTable.Tomakeitmoreclear,theadderSumandCarryequationsaregivenbyEquations.3.9and3.10.Sumi1Ai1Bi1Carryi1%2(3.9)CarryiAi1Bi1Carryi1)Sumi 2(3.10)SwitchingintheSumandCarryisstudiedbyobservingthepreviousvaluesoftheSumandCarry.TheConditionalProbabilitytablefortheSumoftheAdderstructureisshownintheTa-27

PAGE 37

DCB E++I6I7+I8+YoutDATA FLOW GRAPH OF IIR FILTERAI78,I76,I75,.....I70I58,I56,I55,.....I50GATE LEVEL ADDER I89,I88,I86,I85,.....I80I5FGHJK*****I1I2I3I4 Figure3.8.TerminalNodeSwitchingPropagatedtotheLIDAGbles.3.1..HereX00,X01,X10,X11representswitchingfrom01,01,10,11forinputsXinput1,Xinput2,Xinput3andoutputXoutput.ConditionalProbabiltytablesofsuchkindarebuiltforeachoftheintermediatenodesandafullBayesiannetworkisconstructedwithallthenodesofthecircuit.Thisbayesiannetworkwiththeinformationontheinputnodeprobabilitydeterminestheoutputprobabilitesofeachintermediatenodeseffectively.3.3LogicInducedDirectedAcyclicGraphSinceourmethodissandwitchmethodwithknowledgeofbothhigherlevelspecicationandlowerlevelimplementationdetails,inordertocomputepowerlogiclevelbayesiannetwork(LIDAG)isconstructedwiththeknowledgeofswitchingfromtheBehaviorallevelBayesianNetwork(BIDAG).ThisisbestillustratedintheFigure.3.8..Oncethebeliefupdatingisdoneforthebehavioralbayesiannetwork,terminalprobabilitiesofthedifferentcomponentsarefedtothegatelevelbayesiannetwork.Theterminalprobabilitiesoftheoutputofadderandmultiplier,I7andI5arefedtothegatelevelBayesianNetwork,LIDAG.Sincethisfreedomofdesignselectionisavailable,these28

PAGE 38

Table3.1.ConditinalProbabilityTablefortheSumBitofanAdder P*Xoutput+Xinput1,Xinput2forXoutput. Xinput1Xinput2Xinput3 /x00x01x10x110 === 1000 x0x0x0 0100 x0x0x1 0010 x0x0x2 0001 x0x0x3 0100 x0x1x0 1000 x0x1x1 0001 x0x1x2 0010 x0x1x3 0010 x0x2x0 0001 x0x2x1 1000 x0x2x2 0100 x0x2x3 0001 x0x3x0 0010 x0x3x1 0100 x0x3x2 1000 x0x3x3 0100 x1x0x0 1000 x1x0x1 0001 x1x0x2 0010 x1x0x3 1000 x1x1x0 0100 x1x1x1 0010 x1x1x2 0001 x1x1x3 0001 x1x2x0 0010 x1x2x1 0100 x1x2x2 1000 x1x2x3 0010 x1x3x0 0001 x1x3x1 1000 x1x3x2 0100 x1x3x3 P*Xoutput+Xinput1,Xinput2forXoutput. Xinput1Xinput2Xinput3 /x00x01x10x110 === 0010 x2x0x0 0001 x2x0x1 1000 x2x0x2 0100 x2x0x3 0001 x2x1x0 0010 x2x1x1 0100 x2x1x2 1000 x2x1x3 1000 x2x2x0 0100 x2x2x1 0010 x2x2x2 0001 x2x2x3 0100 x2x3x0 1000 x2x3x1 0001 x2x3x2 0010 x2x3x3 0001 x3x0x0 0010 x3x0x1 0100 x3x0x2 1000 x3x0x3 0010 x3x1x0 0001 x3x1x1 1000 x3x1x2 0100 x3x1x3 0100 x3x2x0 1000 x3x2x1 0001 x3x2x2 0010 x3x2x3 1000 x3x3x0 0100 x3x3x1 0010 x3x3x2 0001 x3x3x3 29

PAGE 39

Table3.2.ConditionalProbabilitySpecicationsforOutputandInputLineTransitionsforTwoInputANDGate TwoInputANDgate PXoutputXinput1rXinput2 forXoutput Xinput1 Xinput2 x00x01x10x11 = = 1000 x00 x00 1000 x00 x01 1000 x00 x10 1000 x00 x11 1000 x01 x00 0100 x01 x01 1000 x01 x10 0100 x01 x11 1000 x10 x00 1000 x10 x01 0010 x10 x10 0010 x10 x11 1000 x11 x00 0100 x11 x01 0010 x11 x10 0001 x11 x11 terminalbehaviorformtheBIDAGcanbefedtoanytypeofthegatelevelcircuitimplementation.GatelevelbayesiannetworkisaDirectedAcyclicGraphwithnodesrepresentingthevariablesandtheedgesgivingthedependenciesbetweentheconnectednodes.Atthegateleveltheedgesholdtheconditionalprobabilityinformationoftheparticulargatetype,eg.XORgate,NANDgate.TheconditionalprobabilitytableforanANDgatethatisusedinthefulladderisshownintheTa-ble.3.2..HereX00,X01,X10,X11representswitchingfrom01,01,10,11forinputsXinput1,Xinput2andoutputXoutput.Asthegatelevelspecicationsareknowninthismethod,switchingactivityateachnodeiscalculatedwiththeknowledgeofcapacitancefromthecompo-nentlibrary.Thusconstructingadifferentimplementationofthesamefunction,eg.addition,canbetestedforpowerandthebestofthetwoimplementationscanthatmeetsuserspecicationscanbeusedinthenalmodel.Weusedtwoimplementationsofadders,namelyripplecarryadderandcarrypropagateadder,toaddresstheshiftinimplementationsanddifferenceinpower.30

PAGE 40

CHAPTER4BAYESIANNETWORKINFERENCEInferenceinprobabilisticexpertsystemsreferstocalculatingprobabilitydistributionofaquerynodegivenanobservationorevidence.Thetwomaintasksofbayesiannetworkinferencearebeliefupdatingandbeliefrevision.Beliefupdatingistheprocessofcalculatingtheposteriorprobabilityofanquerynode,X,giventheobservedvalueoftheevidencenode,E,whichisgivenbytheequation.4.1PXEePXErEe PEe(4.1)Beliefrevisionreferstothemostprobableinstantiationofthevariables,giventheobservedevidence.Whenthevariablesthataretotbecomputedarenonevidencenodes,thenthemethodisalsocalledascomputingamostprobableexplanation,MPE.Mostprobableexplanationreferstocomputingmostprobableexplanation.BayesianInuencealgorithmsarebroadlyclassiedintotwotypes,namely,ExactInferenceandApproximateInference.ExactinferencealgorithmsarebestsuitedforsmallcircuitsandAp-proximateinferencealgorithmsareusedwhenbeliefupdatingistobedoneforlargecircuitswithhighernumberofnodes.4.1ExactInferenceAlgorithmsExactInferencealgorithmsarebestsuitedforsmallcircuitswithlessnumberofloops,alsocalledathecliques.Numberofexactinferencealgorithmswereproposed.Perlproposedexactin-ferencealgorithmsformessagepassingpolytrees,oneofwhichisloopcutsetconditioningwheretheconnectivityofanetworkischangedbyanalgorithmandasubsetofnodescalledloopcutset31

PAGE 41

areformed.Polytreealgorithmisusedtosolvethesesinglyconnectedloopcutsets.Asdifferentinstantiationshavetobeconsideredwhileformingtheloopcutsetsthesemethodsarehighlycom-plexandfailforhighernumberofnodes.Clique-treepropagationisanothercommonbayesiannetworkinferencealgorithm,whereamultiplyconnectednetworkisconvertedintotcliquetreebyclusteringthetriangulatedmoralgraphoftheundirectedgraph.Thecliquetreealgorithmalsofailsforcomplexnetworks.Othermethodsofexactinferencealgorithmsincludetheconditioning,arcreversal,Symbolicprobabilisticinfrence,eliminationanddifferentialmethods.IntheArcrever-sal/nodereductionmethod,linksbetweendifferentnodesareinversedusingBayesruletosuchastatethattheevidencenodesaredirectlyconnectedtothequerynodes.Inthedifferentialmethodpartialderevativesofmultivariatepolynomialofthebayesiannetworkisusedtocomputetheprob-abilisticqueriesofthehypothesisnodes.Bayesiannetworkinferencealgorithmsdiscussedsofarcanbeappliedtonetworkswithlessnumberofnodesandthataresimpler.Whenthecomplexityofthenetworkincreasesandwiththeincreaseinthenodesize,beliefupdatingbyexactinferenceisimpossibleandhencewegoforanothersetofinferencealgorithmscalledApproximateInferenceAlgorithms.4.2ApproximateInferenceTomeetwiththeNP-hardnatureofbeliefupdatingindensenetworkswithlargenodesizes,ap-proximatealgorithmsareusedtogettheprobabilityofanquerynodeforagivenevidence.Approx-imateinferencealgorithmsworkbygeneratingrandomsamplesforthevariablesusinganpseudorandomnumbergeneratorandapproximatingtheconditionalprobabilitiesofthequerynodes.Sincetheprobabilitiesofnodesconvergetoavalueonlywhenalmostallthepossiblecombinationsarecapturedbythegivensample,thesemethodsareeffectivewhengivenalongsamplesandwhentimeisnotaconstraint.Inputsamplesarerandomlygeneratedandhencetheyareindependentoneachother.ApproximateInferencealgorithmsalsocalledasStochasticSimulationAlgorithms,arebroadlyclassiedintotwotypes,namelyImportanceSamplingAlgorithmsandMarkovChainMonteCarlomethods.StochasticSimulationAlgorithmsarebroadlyclassedintothefollowingtwotypes:32

PAGE 42

ForwardSamplingBackwardSamplingIntheForwardsamplingstochasticsimulationalgorithmspseudorandomnumbersaregeneratedandpropagatedfromtheinputnodestraversedbythetopologicalorderwhereasBackwardsam-plingstochasticsimulationalgorithmsstartfromtheevidencenodesandndthebesttforrestofthenodeprobabilites.ForwardsamplingtechniquescanbeProbabilisticLogicSampling,Likeli-hoodweighingandBackwardsamplingtechniquesincludeImportancesamplingalgorithms,suchasAdaptiveImportanceSampling,EvidencePrePropagationImportanceSampling,togeneratesamplesbasedonanimportancefunction.BackwardSamplingalgorithmsaremainlyusefulwhenthereisunlikelyevidencenodeswhenforwardsamplingtechniquesarehighlyinaccurateincalcu-latingtheposteriorprobabilities.4.2.1ProbabilisticLogicSamplingTherstandthemostsimplemethodofstochasticinferencingistheprobabilisticlogicsam-pling[52].Givenevidenceforcertainnodes,arandomnumbergeneratorandtraversedtotroughthetopologyofthenetworktothechildnode.Duringeachrun,theprobabilitesateachnodeiscapturedandtheaverageofthenodeprobabilityiscalculatedattheendofthesampling.Whenev-idencenodesarepresent,thenthesamplesduringwhichtheinconsistentprobabilitiesofevidencenodevaluesarerejectedandsimulationisdoneformatchingevidencenodeprobabilites.Proba-bilisticLogicSamplingishighlyerraneouswhentheevidenceisveryunlikely,whenthenumberofsampleswhichsatisfythesetevidenceisveryfewthantheactualnumberofsamplesneedfortheprobabilitiestoconverge.ProbabilisticLogicSamplingtechniquesaresuitedforsmallcircuitswithveryfewornoevidencenodes.4.2.2LikelihoodWeightingProblemcausedduetotheProbabilisticLogicSamplingishandledinaddressedintheLikeli-hoodweightingalgorithm[54].Unlikethepreviousmethodwherethesamplesarerejectedforin-consistentevidencevalues,theobservedvalueoftheevidencevariableareusedtocalculateweight33

PAGE 43

ofthesamplecalledasthescorefortheprobabilityofanevent.Scoremodelsthefractionofprob-abilityofaneventinthesamplethatmatcheswiththeevidencetotheprobabilityofthesameeventconsideringeverysamplenomatteritmatchesevidenceornot.Importancesamplingalgorithmsexhibitimprovedsamplingapproachbyusinganimportancesamplingfunction,toapproximatetheposteriorprobabilitydistribution.TocomputeIntegralasshowninEquation.4.2,similartocomputingtheprobabilityofanode,importancesamplingap-proachisgiveninEquation.4.3.ThefunctionfXistheimportancefunctionI1QgXdX(4.2)ˆI1QgX fXfXdX(4.3)SamplesthatareusedtoapproximatetheconditionalprobabilityaredependentonthefunctionfX.Oncethesamplingisdonetheintegralfunctionisgivenby,ˆI1QgSi fSsifXdX(4.4)Thevarianceoftheprobabilitytableisinverselyproportionaltoincreaseinthenumberofnodes.Theimportancealgorithmscanbeclassiedbasedontwoclasses,namely,Selsamplingalgorithmandheuristicimportancesampling.Circuitimportancefunctionisupdated,usingthescoresgeneratedinthealgorithm,torevisetheconditionalprobabilitytablesinordertomakethesamplingalgorithmapproachtotheestimaton.Intheheuristicimportancesamplingmethodedgesareremovedinthenetworktomakeitsimilartopolytreesandthenapolytreealgorithmisusedtocomputethelikelihoodfunctions.Iftheheuristicimportancefunctionevaluavediscloseenoughtotheoptimalimportancethenitcanleadtoasignicantimprovementinperformance.4.2.3AdaptiveImportanceSamplingChengetal.in[50]proposedanimportancesamplingalgorithmcalledtheAdaptiveImportanceSampling,(AIS),thatminimizesthesamplingvariancebyvaryingtheimportancefunctionsothatit34

PAGE 44

iscloseenoughtotheoptimalimportancefunction.Theoptimalimportancesamplingfunction,thatisacomplexmathematicalexpression,forcalculatingtheposteriorprobabilitiesgiventheevidenceofquerynodesisidenticaltotheimportancesamplingfunctionwhensamenetworkstructureisusedduringtheevidence.ThenoptimalimportancewhichcaptureseffectofallevidenceoneverynodeinthenetworkisgivenbyEquation4.5rXEm'kn1PXkPaXkrE(4.5)ImportanceConditionalProbabilityTables(ICPT)areusedtoupdatetheposteriorprobabilitiesofeachnodeconditionalontheevidencenodes.Insteadofincrementingtheoccuranceasintheprevioussamplingtechniques,ICPTtablesverysimilartotheConditionalprobabilitlytablesareupdatedduringtheimportancefunctionlearningprocess.ThethirdmainreasonforimprovedresultsinAdaptiveImportanceSamplingaraisesfromtheinitializationoftheimportancefunction.Twoheuristicsarepresentedforbetterperformance.Whilelearningtheimportancefunction,iftheinitialvalueoftheimportancefunctionisclosetotheoptimalimportancefunction,convergenceisachievedatanearliertime.Theimmediateancestralnodestotheevidencenodesarethemostaffectednodesthanonesthatarefurtherdownthepath.Chengetal.hadproposedthatbyinitializingtheImportanceConditionalProbabilityTablesofimmediateancestralnodeshigherconvergenceratesareachieved.Addressinguncertainevidenceproblemintheprevioustechniques,hehadsuggestedthatifathresholdQcanbesetsuchthatwhenanynodeprobabilityisbelowthethresholdvalueitisreplacedwiththethresholdvalue.Inturnthisthresholdisdeductedfromthelargestprobabiliyinthesameconditionalprobabilitydistribution.4.2.4EvidencePrePropagatedImportanceSamplingProposedbyYuanetal.in[51],EvidencePre-propagatedImportancesamplinguseslocalmessagepassingandstochasticsamplingtechniquestoeffectivelycalculatetheprobabilitiesofquerynodesforgivenevidencenodes.EPISissimilartotheAdaptiveImportancesamplingmethodexceptthatthelearningtolearntheapproximationsoftheICPTsaredirect.IfXX1,X2rrXiisasetofvariablesinBayesiannetwork,letPaXibetheparentofXiandEbethesetofevidence.35

PAGE 45

TheoptimalimportancefunctionisthengivenbytheEquation4.6,wherePXiPaXirEisdenedastheimportanceconditionalprobabilitytable.PXEn'kn1PXiPaXirE(4.6)Denition:AnimportanceconditionalprobabililtytableonXiisatableofposteriorprobabili-tiesPXiPaXirEconditionalontheevidenceandindexedbyitimmediatepredecessors,PaXi.Everynodeinthepolytreed-seperatesintotwosubsetscalledtheEandE2.EdenotestheevidenceconnectedtothechildrenandE2denotestheevidenceconnectedtotheparentofanynodeXi.Thetwosubsetsareindependentoneachotherandtheevidencemessagethuspassedaretermedas,lxmessagesforthosesentbytheparentsandpxmessagesforthosesentfromthechildrentotheparents.lxPXiPaXE(4.7)pxPXiPaXE2(4.8)Afterthemessagesarepropagatedandconvergenceisachievedtheposteriorbeliefonanynodeisgivenby,Belxalxpx(4.9)Perlsbeliefpropagationalgorithmcanbeappliedtonetworkswithloopswherethebeliefofthenodeiscontinuouslyupdatedinalooptillbeliefconverges.SimilartotheAISmethod,inEPISmethodthethresholdforthelowprobabilityinthenetworkisidentiedandreplacedwithanqthresholdandatthesametimethelargestprobabilityofthenetworkissubtractedbythiscutoff.Stochasticsamplingtechniquesdiscussedaboveworkneforbayesiannetworksastheoptimalimportancefunctionistheproductoftheconditionalprobabilityfunctionofallnodes.WeusedEPISalgorithmstoestimatetheswitchingactivtyforourcircuits,andwefoundthatsamplesaslowas5000aresufcientenoughforallthecircuits.Inadditiontotheinput,theinputstatespacesare36

PAGE 46

for Load Capacitance Proposed Power Estimation Technique Gate Level Simulatoin (Groundtruth) Steps Involved in Our Power Estimation Technique (BIDAG) Component Library Generate a Gate Level Netlist Behavioral Data Flow Graph (DFG) Generate Individual Component Netlist(LIDAG) Calculate Component Power Approximate Inferencing methodGet probabilities of nodes by EPIS (BIDAG)Construct Bayesian Network for the complete circuit Calculate Component Power (EPIS)Switching from BIDAG InferenceGet Individual component Input Figure4.1.PowerEstimationStepssampledsimultaneouslyusingastrongcorrectivemodelascapturedbyBayesiannetwork.Anotherimportantadvantageofthismethodisthatitisinputpatterninsensitiveandtheconvergencerateisveryhigh.37

PAGE 47

CHAPTER5EXPERIMENTALRESULTSInthissectionwediscussthepowerestimatesatRTlevelbenchmarkcircuits.Foreverybench-mark,weconvertthemintoadata-owgraphwhosenodesaretheresourceslikeadder,multiplierandedgesareinputsandoutputsoftherespectiveresources.WethentranslatethisDFGtoaBehavioral-DAG(BIDAG)whichisproventoaBayesianNetworkswhichtheminimalI-mapfortheunderlyinglogicaldependenceyinherentinthealgorithm.TheestimationstepsarehighlightedinFigure4.1..OnceweobtaintheBIDAG,weinfertheprobabilitiesoftheinputs/outputsusingEvidencePre-propagatedImportanceSamplingwhichmodelstheuncertaintyinthesystemandtheprobabilitiesthatweobtainmatchthebeliefofthesystem.Next,weuselogiclevelimplementationofindividualresourcesandmodelthemasLiDAGs.WeusetheinferredprobabilitiesfromtheBIDAGtothecorrespondingLiDAGstructureandusethesamebeliefpropagationtoobtaintheswitchingproleoftheindividualinternalsignals,thepowerdissipationoftheentiresystemisthuscomputed.Thus,wepartitionourproblemintohandlinglogicleveldependencyusingtheBIDAGstructureandhandlethestructuraldependencyusingtheLIDAGstructure.WeuseWINDOWSXPcomputerwithPentiumIV,2.00GHzprocessortorunourInferencealgorithmsandSunSolarismachinesforourgatelevelsimulations.WetestedourmodelforthreeTable5.1.ResultsonTotalDynamicPowerDissipationforBenchmarkCircuits LowInputSwitching /x00.035x01.0315x10.0315x11.0320 Circuit No3ofNodes EPIS Simultion 4%error4 FIR 1573 0.00143 0.00143 0.00 IIR 1522 0.00141 0.001411 0.00 ELLIPTIC 9081 0.0069 0.0070 1.4 38

PAGE 48

Table5.2.TotalDynamicPowerDissipationforBenchmarkCircuits RandomInputSwitching /x00.0325x01.0325x10.0325x11.03250 Circuit No3ofNodes EPIS Simultion 4%error4 FIR 1573 0.002438 0.00244 0.08 IIR 1522 0.002430 0.002428 0.08 ELLIPTIC 9081 0.001 0.0103 2.90 Table5.3.TotalDynamicPowerDissipationforBenchmarkCircuits HighInputSwitching /x00.031x01.034x10.034x11.0310 Circuit No3ofNodes EPIS Simultion 4%error4 FIR 1573 0.002811 0.002811 0.00 IIR 1522 0.002798 0.002798 0.00 ELLIPTIC 9081 0.01154 0.01177 1.90 typesofinputbehaviorandforELLIPTIClterwhichhavereconvergencepathswehaveamaxi-mumerrorofonly3%.Therstsampleisanforlowinputswitchingbehavior,showninTable5.1.whereascircuitpowerforhighinputswitchingbehaviorisshowninTable5.3..ThecompletelyrandominputbehaviorwhichistheconditioninnonfeedbackcircuitsisdiscussedinTable5.2..Thusourmodelhaslessthen3%andisinputpatternindependent.InTable5.4.wehavepresentedthepowerfortheltersthatresultduetoadifferenttypeofadder,CarryPropagateAdderunderthreeinputswitchingbehavior.FinallywehavediscussedtheclosenessofourBiDAGswitchingestimateswiththegatelevelswitchingestimates.Table5.5.,5.6.,5.7.showstheaverageoutputnodeswitchingineachcomponentintheFIRlter,table.5.8.,5.9.,5.10.showstheaverageoutputnodeswitchingineachcomponentintheIIRlterandTable5.11.,5.12.,5.13.showstheaverageoutputnodeswitchingineachcomponentintheELLIPTIClter.Wecomparedthisswitchingwithgatelevelswitchingestimateandthemaximumerrorof2%wasrecordedforthe4bitmultiplier.39

PAGE 49

Table5.4.ResultsonTotalDynamicPowerDissipationforBenchmarkCircuitsforDifferentIm-plementaitonofAdder PowerforDifferentInputSwitching Circuit No.ofNodes SampleI Sample2 Sample3 FIR 4388 0.0027 0.0041 0.0046 IIR 3769 0.0025 0.0039 0.0042 ELLIPTIC 27939 0.0131 0.0184 0.0201 Table5.5.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforFIRFilter SampleI Modlue Simulation EPIS 4%error4 4MULT 0.254 0.25645 0.9 8ADD 0.334 0.3347 0.2 9ADD 0.3498 0.3510 0.3 10ADD 0.3767 0.3802 0.9 11ADD 0.3339 0.3291 1.4 Table5.6.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforFIRFilter SampleII Modlue Simulation EPIS 4%error4 4MULT 0.4206 0.4254 1.1 8ADD 0.4432 0.4407 0.05 9ADD 0.4280 0.4248 0.07 10ADD 0.4208 0.4178 0.07 11ADD 0.3808 0.3809 0.02 Table5.7.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforFIRFilter SampleIII Modlue Simulation EPIS 4%error4 4MULT 0.4532 0.4534 0.00 8ADD 0.4580 0.4583 0.06 9ADD 0.4340 0.4313 0.62 10ADD 0.4173 0.4142 0.74 11ADD 0.3884 0.3866 0.46 Table5.8.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforIIRFilter SampleI Module Simulation EPIS 4%error4 4MULT 0.2629 0.2575 2.0 8ADD 0.3344 0.3351 0.2 9ADD 0.3555 0.351 1.2 10ADD 0.3682 0.3641 1.1 40

PAGE 50

Table5.9.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforIIRFilter SampleII Module Simulation EPIS 4%error4 4MULT 0.4202 0.4206 0.09 8ADD 0.4436 0.4428 0.1 9ADD 0.4279 0.4255 0.5 10ADD 0.4155 0.4172 0.4 Table5.10.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforIIRFilter SampleIII Module Simulation EPIS 4%error4 4MULT 0.4532 0.4519 0.28 8ADD 0.4581 0.4579 0.04 9ADD 0.4340 0.4356 0.36 10ADD 0.4239 0.4256 0.39 Table5.11.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforELLIPTICFilter SampleI Module Simulation EPIS 4%error4 4SUB 0.4179 0.4245 1.5 4MULT 0.2635 0.2664 1.08 8ADD 0.3005 0.3019 0.46 4ADD 0.4091 0.4081 0.24 9SUB 0.3191 0.3211 0.62 8SUB 0.3212 0.3208 0.12 9MULT 0.1865 0.1843 1.19 8MULT 0.209 0.2093 0.14 18ADD 0.2200 0.219 0.45 19ADD 0.2204 0.2192 0.54 Table5.12.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforELLIPTICFilter SampleII Module Simulation EPIS 4%error4 4SUB 0.4716 0.4735 0.40 4MULT 0.4001 0.4137 3.2 8ADD 0.3807 0.3933 3.2 4ADD 0.4989 0.4997 0.16 9SUB 0.3949 0.3936 0.33 8SUB 0.3876 0.3886 0.27 9MULT 0.2629 0.2628 0.03 8MULT 0.2716 0.2721 0.18 18ADD 0.2756 0.2762 0.21 19ADD 0.2673 0.2669 0.14 41

PAGE 51

Table5.13.ResultsonBIDAGSwitchingvsActualSwitchingfromSimulationforELLIPTICFilter SampleIII Module Simulation EPIS 4%error4 4SUB 0.4434 0.4507 1.6 4MULT 0.4297 0.4443 3.3 8ADD 0.3929 0.4059 3.3 4ADD 0.5310 0.5318 0.15 9SUB 0.3873 0.3997 3.2 8SUB 0.3936 0.3955 0.4 9MULT 0.2781 0.2770 0.39 8MULT 0.2850 0.2855 0.17 18ADD 0.2848 0.2842 0.21 19ADD 0.2735 0.2719 0.58 42

PAGE 52

CHAPTER6CONCLUSIONPowerestimationhasbeenanactiveresearchtopicformorethanadecade.Thisthesisin-troducescombinationalTop-downBottom-upmethodtoaccruatelymodelthepoweratRegisterTransferLevel.WehaveshowntheresultsofPowerforvariousRTLbehchmarkcircuits.WeusedBayesiannetworkstogettheprobabilityofanyquerynodegiventheevidenceforanyothernode.WeusedanImportancesamplingcalledEvidencePre-propagationImportanceSamplingmethodtoupdatethebelief.Since5000samplesresultedingoodconvergenceintheprobabilities,itismuchfasterthanpowermacromodelingwherethetableconstructiontakemostofthetime.OurprobelmiszerodelaymodelandhencetheextensionofourworkwouldberealdealymodelforRTLpowerestimation.43

PAGE 53

REFERENCES[1]R.A.WalkerandD.E.Thomas,“AModelofDesignRepresentationandSynthesis,”IEEE/22ndDesignAutomationConference,pp.453–459,1985.[2]F.N.Najm,“ASurveyofPowerEstimationTechniquesinVLSIcircuits”,IEEETransactionsonVLSISystems,vol.2,No.4,pp.446-455,1994.[3]E.Macii,M.PedramandF.Somenzi,“High-LevelPowerModeling,EstimationandOpti-mization”,IEEETransactionsonComputer-AidedDesignofIntegratedCircuitsandSystems,pp.1061-1079,vol.17,no.11,Nov.1998.[4]D.LiuandC.Svensson,“PowerConsumptionEstimationinCMOSVLSIChips”,IEEEJournalofSolidStateCircuits,pp.663-670,1994.[5]K.Muller-Glaser,K.KirschandK.Neusinger,“EstimatingEssentialDesignCharacteristicstoSupportProjectPlanningforASICDesignManagement”,IEEEInternationalConferenceonComputerAidedDesign,pp.148-151,1991.[6]M.NemaniandF.N.Najm,“High-LevelAreaandPowerEstimationforVLSICircuits”,IEEETransactionsoncomputer-AidedDesignofIntegratedCircuitsandSystems,vol.18-6,pp.697-713,June1999.[7]M.NemaniandF.N.Najm,“TowardsaHigh-LevelPowerEstimationCapability[DigitalICs]”,IEEETransactionsonComputerAidedDesignofIntegratedCircuitsandSystems,vol.15-6,pp.588-598,June1996.[8]D.Marculescu,R.MarculescuandM.Pedram,“InformationTheoreticMeasuresforPowerAnalysis”,IEEETrans.onComputer-AidedDesignofIntegratedCircuitsandSystems(Spe-cialIssueonLowPowerDesign),vol.15-6,June1996.[9]D.Marculescu,R.MarculescuandM.Pedram,“TheoreticalBoundsforSwitchingActiv-ityAnalysisinFinite-StateMachines”,IEEETrans.onVLSISystems(SpecialIssueonLowPowerDesign),vol.8-3,June2000.[10]P.Landman,“High-levelpowerestimation”,ACM/IEEEInt.Symp.Low-PowerElectronicsandDesign,pp.29-35,1996.[11]N.R.Potlapally,A.Raghunathan,G.Lakshminarayana,M.S.Hsiao,S.T.Chakradhar,“Ac-curatePowerMacro-modelingTechniquesforComplexRTLCircuits”,IEEEVLSIDesignConference,pp.235-241,Jan.2001.[12]J.E.CrenshawandM.Sarrafzadeh,“AccurateHighLevelDatapathPowerEstimation”,1997.44

PAGE 54

[13]R.Zafalon,M.Rossello,E.MAcii,M.Poncino,“PowerMAcromodelingforaHighQual-ityRT-levelPowerEstimation”,IEEEFirstInternationalSymposiumonQualityElectronicDesign,pp.59-63,2000.[14]A.Bogliolo,L.BeniniandG.D.Micheli,“AdaptiveLeastMeanSquareBehavioralPowerModeling”,Eur.DesignandTestConference,pp.404-410,1997.[15]S.PowellandP.Chau,“EstimatingPowerDissipationofVLSISignalProcessingChips:ThePFATechnique”,VLSISignalProcessing,pp.250-259,1990.[16]P.E.LandmanandJ.M.Rabaey,“ArchitecturalPowerAnalysis:TheDualBitTypeMethod”,IEEETransactionsonVeryLargeScaleIntegration(VLSI)Systems,vol.3-2,pp.173-187,June1995.[17]A.Bogliolo,L.BeniniandG.D.Micheli,”Regression-BasedRTLPowerModeling”,ACMTransactionsonDesignAutomationofElectronicSystems,vol.5-3,pp.337-372,July2000.[18]C.Hsieh,QingWu,C.DingandM.Pedram,”StatisticalSamplingandRegressionAnalysisforRT-LevelPowerEvaluation”,ProceedingsoftheInternationalConferenceonComputerAidedDesign,pp.583-588,Nov.1996.[19]Q.Wu,Q.Qiu,M.PedramandC-H.Ding,”Cycle-AccurateMacro-ModelsforRT-LevelPowerAnalysis”,IEEETrans.onVLSI,vol.6-4,pp.520-528,December,1998.[20]R.Corgnati,E.MaciiandM.Poncino,“ClusteredTable-BasedMacromodelsforRTLPowerEstimation”,ProceedingsNinthGreatLakesSymposiumonVLSI,pp.354-357,March1999.[21]S.GuptaandFN.Najm,“AnalyticalModelsforRTLPowerEstimationofCombinationalandSequentialCircuits”,IEEETransactionsonComputer-AidedDesignofIntegratedCircuitsandSystems,vol.19-7,pp.808-814,Jul2000.[22]G.Bernacchia,M.C.Papaefthymiou,“AnalyticalMacromodelingforHigh-LevelPowerEsti-mation”,IEEE/ACMInternationalConferenceonComputer-AidedDesign,pp.280-283,Nov.1999.[23]M.Anton,I.Colonescu,E.MaciiandM.Poncino,“FastCharacterizationofRTLPowerMacromodels”,IEEEInternationalConferenceonElectronics,CircuitsandSystems,vol.3,pp.1591-1594,Sep.2001.[24]A.Raghunathan,S.DeyandN.K.Jha,“Register-TransferLevelEstimationTechniquesforSwitchingActivityandPowerConsumption”,IEEE/ACMInternationalConferenceonComputer-AidedDesign,ICCAD,pp.158-165,Nov.1996.[25]A.Raghunathan,S.DeyandN.K.Jha,“GlitchAnalysisandReductioninRegisterTransferLevelPowerOptimization”,33rdDesignAutomationConferenceProceedings,pp.331-336,june1996.[26]D.Bruni,G.Olivieri,A.BoglioloandL.Benini,“Delay-SensitivePowerEstimationattheRegister-TransferLevel”,IEEEInternationalConferenceonElectronics,CircuitsandSys-tems,vol.2,pp.1031-1034,Sep.2001.45

PAGE 55

[27]A.BoglioloandL.Benini,“RobustRTLPowerMacromodels”,IEEETransactionsonVeryLargeScaleIntegration(VLSI)Systems,vol.6,pp.578-581,no.4,Dec.1998.[28]A.Bogliolo,L.Benini,G.De.Macheli,“Characterization-freebehavioralpowermodeling”,ProceedingsofDesign,AutomationandTestinEurope,pp.767-773,Feb.1998.[29]A.BoglioloandL.Benini,“NodeSampling:ARobustRTLPowerModelingApproach”,IEEE/ACMInternationalConferenceonComputer-AidedDesign,ICCAD,pp.461-467,Nov.1998.[30]M.Eiermann,W.Stechele,“NovelModelingTechniqueforRTLPowerEstimation”,Proceed-ingsofthe2002InternationalSymposiumonLowPowerElectronicsandDesign,pp.323-328,Aug.2002.[31]M.Eiermann,W.Stechele,“RTLPowerModelingTechniquesforCombinationalandSequen-tialRTLmacroblocks”,InternationalConferenceonElectronics,CircuitsandSystems,vol.2,pp.705-508,Sept.2002.[32]Yi-MinJiang,Shi-YuHuang,Kwang-TingCheng,D.C.Wang,ChingandYenHo,“AHybridPowerModelforRTLPowerEstimation”,ProceedingsoftheASP-DAC,DesignAutomationConference,pp.551-556,Feb.1998.[33]Z.ChenandK.Roy,”APowerMacromodelingTechniqueBasedonPowerSensitivity”,ACM/IEEEDesignAutomationConference,pp.678-683,1998.[34]H.Mehta,R.M.OwensandM.J.Irwin,“EnergyCharacterizationBasedonClustering”,Pro-ceedingsofACM/IEEEDesignAutomationConference,pp.702-707,1996.[35]S.GuptaandF.N.Najm,“Energy-Per-CycleEstimationatRTL”,InternationalSymposiumonLowPowerElectronicsandDesign,pp.121-126,Aug.1999.[36]S.GuptaandF.N.Najm,“PowerMacromodelingforHighLevelPowerEstimatoin”,Pro-ceedingsof34thDesignandAutomationConference,pp.365-370,Anaheim,California,June9-13,1997.[37]T.Sato,Y.Ootaguro,M.NagamatsuandH.Tago,“EvaluationofArchitecture-LevelPowerEstimationforCMOSRISCProcessors”,SymposiumonLowPowerElectronics,pp.44-45,1995.[38]J.Costa,J.Monteiro,L.M.SilveiraandS.Devadas,“AProbabilisticApproachforRT-Levelpowremodeling”,The6thIEEEInternationalConferenceonElectronics,CircuitsandSys-tems,September1999.[39]R.Ferreira,A.M.Trullemans,J.CostaandJ.Monteiro,“ProbabilisticBottom-UpRTLPowerEstimation”,ProceedingsofIEEEFirstInternationalSymposiumonQualityElectronicDe-sign,pp.439-446,Mar.2000.[40]S.BhanjaandN.Ranganathan,“DependencypreservingprobabilisticmodelingofswitchingactivityusingBayesiannetworks,”IEEE/ACMDesignAutomationConference,pp.209–214,2001.46

PAGE 56

[41]S.BhanjaandN.Ranganathan,“SwitchingActivityEstimationofVLSICircuitsUsingBayesianNetworks,”IEEETransactionsonVLSISystems,vol.11,no.4,pp.558–567,Aug.2003.[42]S.BhanjaandN.Ranganathan,”SwitchingactivityestimationoflargecircuitsusingmultipleBayesiannetworks,”ProceedingsofASP-DACand15thInternationalConferenceonVLSIDesign,pp.187–192,2002.[43]R.G.Cowell,A.P.David,S.L.Lauritzen,D.J.Spiegelhalter,“ProbabilisticNetworksandExpertSystems,”Springer-VerlagNewYork,Inc.,1999.[44]J.Pearl,“ProbabilisticReasoninginIntelligentSystems:NetworkofPlausibleInference,”MorganKaufmannPublishers,Inc.,1988.[45]“GraphicalNetworkInterface”URLhttp://www.sis.pitt.edu/genie/genie2.[46]S.M.Kang,“AccurateSimulationofPowerDissipationinVLSICircuits,”IEEEJournalofSolid-stateCircuits,vol.21,no.5,pp.889–891,Oct.1986.[47]URLhttp://www.hugin.com/.[48]ShivaShankarRamani,andS.Bhanja,”Any-timeProbabilisticSwitchingModelusingBayesianNetworks”,InternationalSymposiumonLowPowerElectronicsandDesign,pp.86-89,NewportBeach,CA,2004.[49]Z.ChenandK.Roy,“AnEfcientStatisticalMethodtoEstimateAveragePowerinSequentialCircuitsConsideringInputSensitivities”,ASICConferenceandExhibit,pp.189–193,1997.[50]J.Cheng,“EfcientStochasticSamplingAlgorithmsforBayesianNetworks,”Ph.DDisserta-tion,UniversityofPittsburgh,2001.[51]C.YuanandM.J.Druzdzel,“AnImportanceSamplingAlgorithmBasedonEvidencePre-propagation,”Proceedingsofthe19thAnnualConferenceonUncertaintyonArticialIntelli-gence,pp.624–631,2003.[52]M.Henrion,”PropagatingUncertainityinBayesianNetworksbyProbabilisticLogicSam-pling”,InUncertainityinArticialIntelligence2,pp.149-163,NewYork,N.Y.,1988.Else-vierSciencePublishingCompany,Inc.[53]P.DagumandM.Luby,”ApproximatingprobabilisticinferenceinBayesianbeliefnetworksisNP-hard”,ArticialIntelligence,60(1):141-153,1993.[54]R.FungandK.-C.Chang,”WeightingandintegratingevidenceforstochasticsimulationinBayesiannetworks”,InM.Henrion,R.Shachter,L.Kanal,andJ.Lemmer,editors,Uncer-tainityinArticialIntelligence5,pages209-219,NewYork,N.Y.,1989.ElsevierSciencePublishingCompany,Inc.47

PAGE 57

[55]R.D.ShachterandM.A.Poet,”Simulationapproachestogeneralprobabilisticinferenceonbeliefnetworks”,InM.Henrion,R.Shachter,L.Kanal,andJ.Lemmer,editors,UncertainityinArticialIntelligence5,pages221-231,NewYork,N.Y.,1989.ElsevierSciencePublishingCompany,Inc.[56]R.FungandB.delFavero,”BackwardsimulationinBayesiannetworks”,InProceedingsoftheTenthAnnualConferenceonUncertainityinArticialIntelligence(UAI-94),pages227-234,SanMateo,CA,1994.MorganKaufmannPublishers,Inc.[57]K.Murphy,Y.Weiss,andM.Jordan,”LoopyBeliefPropagationforApproximateInference:AnEmpiricalstudy”,ProceedingsoftheConferenceonUncertainityinAI(UAI-99),pp.467-475,1999.48


xml version 1.0 encoding UTF-8 standalone no
record xmlns http:www.loc.govMARC21slim xmlns:xsi http:www.w3.org2001XMLSchema-instance xsi:schemaLocation http:www.loc.govstandardsmarcxmlschemaMARC21slim.xsd
leader nam Ka
controlfield tag 001 001498130
003 fts
006 m||||e|||d||||||||
007 cr mnu|||uuuuu
008 041209s2004 flua sbm s000|0 eng d
datafield ind1 8 ind2 024
subfield code a E14-SFE0000531
035
(OCoLC)57716635
9
AJU6725
b SE
SFE0000531
040
FHM
c FHM
090
TK145 (ONLINE)
1 100
Ponraj, Sathishkumar.
0 245
Stimulus-free RT level power model using belief propagation
h [electronic resource] /
by Sathishkumar Ponraj.
260
[Tampa, Fla.] :
University of South Florida,
2004.
502
Thesis (M.S.E.E.)--University of South Florida, 2004.
504
Includes bibliographical references.
516
Text (Electronic thesis) in PDF format.
538
System requirements: World Wide Web browser and PDF reader.
Mode of access: World Wide Web.
500
Title from PDF of title page.
Document formatted into pages; contains 57 pages.
520
ABSTRACT: Power consumption is one of the major bottlenecks in current and future VLSI design. Early microprocessors, which consumed a few tens of watts, are now replaced by millions of transistors and with the introduction of easy-to-design tools to explore at unbelievable minimum dimensions, increase in chip density is increasing at a alarming rate and necessitates faster power estimation methods. Gate level power estimation techniques are highly accurate methods but when time is the main constraint, power has to be estimated a lot higher in the abstraction level. Estimating power at higher levels also saves valuable time and cost involved in redesigning when design specifications are not met. We estimate power at every levels of abstraction for a breadth first design-space exploration.This work targets a stimulus-free pattern-insensitive RT level hierarchical probabilistic model, called Behavioral Induced Directed Acyclic Graph (BIDAG), that can freely traverse between the RT and logic level and we prove that such a model corresponds to a Bayesian Network to map all the dependencies and can be used to model the joint probability distribution of a set of variables. Each node or variable in this structure represents a gate level Directed Acyclic Graph structure, called the Logic Induced Directed Acyclic Graph (LIDAG). We employ Bayesian networks for the exact representation of underlying probabilistic framework at RT level, capturing the dependence exactly and again use the same probabilistic model for the logic level. Bayesian networks are graphical representations used to concisely represent the uncertain knowledge of the system.In order to get an posterior belief of a query node or variable, with or without preset nodes or variables called the evidence nodes, we use stochastic inference algorithm, based on importance sampling method, called the Evidence Pre-propagation Importance Sampling (EPIS) which is anytime and scales really well for RT and logic networks. Experimental results indicate that this method of estimation yields high accuracy and is qualitatively superior to macro-models under a wider range of input patterns. The main highlights of this work is that as it is a probabilistic model, it is input pattern independent and nonsimulative property implies less time for power modelling.
590
Adviser: Bhanja, Sanjukta.
653
inference.
sampling.
clique.
simulation.
Behavioral Level.
Register Transfer Level.
bottom-up.
top-down.
690
Dissertations, Academic
z USF
x Electrical Engineering
Masters.
773
t USF Electronic Theses and Dissertations.
4 856
u http://digital.lib.usf.edu/?e14.531