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Varanasi, Ravi Kumar.
Linearity optimization of power transistors utilizing harmonic terminations
h [electronic resource] /
by Ravi Kumar Varanasi.
[Tampa, Fla.] :
University of South Florida,
Thesis (M.S.E.E.)--University of South Florida, 2004.
Includes bibliographical references.
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ABSTRACT: This thesis focuses on the characterization and optimization of microwave power transistors using a commercial on-wafer harmonic load pull system. Specific attention is paid to the output tuning of the second harmonic impedance presented to the device. The ability to quantify the level of accuracy in a load pull system is explored by using various calibration validation methods, including a method called Delta-Gt. In this work experiments and simulation comparisons are described for three different device technologies, namely GaAs pHEMT, GaAs HJFET and InGaP HBT. Externally supplied non-linear models were used for the simulations and these were exercised and compared against 2.45 GHz fundamental frequency measurements made as part of this work to first validate the models against IV, S-Parameter and fundamental load-pull data and finally to explore performance variations under 2nd harmonic impedance tuning.The measured harmonic load-pull data pointed to different guidance on how one would match the 2nd harmonic for best performance. With regard to the model validation/assessment work it was found that only in the case of the pHEMT did the available non-linear model provide a good fit to all the different types of measurement data, including 2nd harmonic tuning data. This model was then used to show that even though the 2nd harmonic tuning measurement had a limited maximum reflection coefficient of about 0.8. Simulated results showed that the worst case linearity condition occurred for the same reflection angle as that measured, but that the variation between worst-case and best case linearity under 2nd harmonic tuning grows considerably larger as the magnitude of the 2nd harmonic reflection coefficient approaches 1.A key aspect of the methodology presented in this work is that once a non-linear model is proved to be valid for harmonic tuning conditions it can be used to explore harmonic tuning-related design trade-offs under a much wider range of frequency and tuning conditions than can be practically explored with measurements alone.
Adviser: Dunleavy, Lawrence P.
x Electrical Engineering
t USF Electronic Theses and Dissertations.
Linearity Optimization of Power Transistors Utilizing Harmonic Terminations by Ravi Kumar Varanasi A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Lawrence P. Dunleavy, Ph.D. Thomas Weller, Ph.D. Jim Paviol, MSEE Date of Approval: November 3, 2004 Keywords: amplifier, load pull, triplexer, model, correlation Copyright 2004, Ravi Kumar Varanasi
DEDICATION This thesis is dedicated to my father, Murali, my mother Padma and to my brother Venu and to the memory of my grandmother, Venkatalakshmi. Thanks for all the support and encouragement you have provided me throughout my academic career.
ACKNOWLEDGEMENT I would like to acknowledge Dr. Lawrence P. Dunleavy for providing the opportunity to get involved in harmonic load pull research. I would like to recognize Jiang Liu for his help in this project. Jiang helped me to sort out my ideas and made some suggestions that helped towards the writing of this manuscript. I would like to thank Mr. Jim Paviol from Conexant Systems, Inc., for his continued support and unlimited ideas that contributed to this thesis. Conexant Systems provided the financial support for this research. I would like to recognize Mr. Jim Schellenberg from Schellenberg Associates for his helpful input and for emphasizing the exploration of second harmonic tuning effects on linearity. For his help related to the software, I credit Eric Kueckels at Maury Microwave. For his input towards the selection of a device, I would like to thank Mr. Allen Podell. For their contribution of a device, device model, calibration boards and useful advice, I want to acknowledge Modelithics, Inc., and in particular William Clausen. And for being there for me during all the tough times, I thank my family and friends.
i TABLE OF CONTENTS LIST OF TABLES iv LIST OF FIGURES vi ABSTRACT x CHAPTER 1 INTRODUCTION 1 1.1 Overview 1 1.2 Technical Approach 2 1.3 Contributions of the Work 3 1.4 Organization of the Thesis 3 CHAPTER 2 REVIEW OF HARMONIC TUNING MEASUREMENTS AND DESIGN PRACTICE 5 2.1 Introduction 5 2.2 Methods to Test Nonlinearity 6 2.3 Classes of Operation 8 2.3.1 Overview of Amplifier Topologies 9 2.4 Design Aspects 13 2.4.1 Active vs. Passive Tuner System 14 2.4.2 Source Tuning vs. 50-ohm Source Impedance 16 2.4.3 One-tone vs. Two-tone Tuning 17 2.5 Design Examples from the Literature 18 2.6 Chapter Summary 23 CHAPTER 3 DEVICE TECHNOLOGY AND MODELS 24 3.1 Introduction 24 3.2 HJFET Device Technology 24 3.2.1 HJFET Device Structure 25 3.2.2 Principle of Operation for HJFET 26 3.2.3 Advantages and Disadvantages of the HJFET Technology 27 3.2.4 Specific HJFET Device Studied in this Work 28 3.3 pHEMT Device Technology 29 3.3.1 pHEMT Device Structure 29 3.3.2 Principle of Operation for pHEMT 32 3.3.3 Advantages and Disadvantages of the pHEMT Technology 35 3.3.4 Specific pHEMT Device Studied in this Work 36
ii 3.4 HBT Device Technology 37 3.4.1 HBT Device Structure 37 3.4.2 Principle of Operation for HBT 38 3.4.3 Advantages and Disadvantages of the HBT Technology 39 3.4.4 Specific HBT Device Studied in this Work 40 3.5 Summary of Non-linear Device Models 41 3.5.1 TOM Model 41 3.5.2 EEHEMT Model 42 3.5.3 Gummel-Poon Model 43 3.6 Chapter Summary 44 CHAPTER 4 EXPERIMENTAL METHODS AND VALIDATIONS 46 4.1 Introduction 46 4.2 Pulsed IV Theory 46 4.3 S-Parameter Measurements and Theory 47 4.4 Source and Load Pull Measurement Theory and Validations 53 4.5 Triplexer Characteristics 63 4.6 Chapter Summary 67 CHAPTER 5 MEASURED AND SIMULATED IV AND VNA RESULTS 68 5.1 Introduction 68 5.2 Setup and Basic Simulations: EEHEMT Model for pHEMT 69 5.2.1 IV and S-Parameter Simulations and Measurements 69 5.2.2 50-ohm Power Sweep Simulations and Measurements 72 5.3 Setup and Basic Simulations: Gummel-Poon Model for HBT 74 5.3.1 IV and S-Parameter Simulations and Measurements 74 5.3.2 50-ohm Power Sweep Simulations and Measurements 76 5.4 Setup and Basic Simulations: TOM Model for HJFET 78 5.4.1 IV and S-Parameter Simulations and Measurements 78 5.4.2 50-ohm Power Sweep Simulations and Measurements 80 5.5 Chapter Summary 81 CHAPTER 6 MEASURED AND SIMULATED LOAD PULL RESULTS 83 6.1 Introduction 83 6.2 pHEMT Measured/Simulated Comparison 83 6.2.1 Fundamental Load Pull 84 6.2.2 Second Harmonic Load Pull 86 6.3 HBT Measured/Simulated Comparison 91 6.3.1 Fundamental Load Pull 92 6.3.2 Second Harmonic Load Pull 93 6.4 HJFET Measured/Simulated Comparison 94 6.4.1 Fundamental Load Pull 94 6.4.2 Second Harmonic Load Pull 95 6.5 Chapter Summary 96
iii CHAPTER 7 CONCLUSIONS AND RECOMMENDATIONS 98 7.1 Conclusions 98 7.2 Recommendations 99 REFERENCES 102 APPENDICES 106 Appendix A: Additional Measurement Validation Results 107 A.1 Introduction 107 A.2 HBT Source and Load Conjugate Match 107 A.3 HBT 50-ohm Power Sweeps 109 A.4 HJFET Source and Load Conjugate Match 111 A.5 HJFET 50-ohm Power Sweeps 113 Appendix B: ADS Templates used for Non-linear Simulations 115 B.1 Introduction 115 B.2 Two-Tone Power Sweep Simulation Template 115 B.3 Fundamental Load Pull Simulation Template 117 B.4 Second Harmonic Load Pull Simulation Template 119
iv LIST OF TABLES Table 3.1: Summary of Commercial Devices used in this Thesis [44, 45] 45 Table 4.1: pHEMT Conjugate Source and Load Matching Comparison @ 2.45 GHz 62 Table 4.2: 2.45 GHz Triplexer Return Loss and Insertion Loss 64 Table 5.1: Summary of pHEMT Quiescent Bias Points 70 Table 5.2: Measured and Modeled pHEMT Class AB S-Parameters at 2.45 GHz 71 Table 5.3: pHEMT Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz 73 Table 5.4: Summary of HBT Quiescent Bias Points 75 Table 5.5: Measured and Modeled Class AB HBT S-Parameters at 2.45 GHz 76 Table 5.6: HBT Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz 77 Table 5.7: Summary of HJFET Quiescent Bias Points 79 Table 5.8: Measured and Modeled HJFET Class AB S-Parameters at 2.45 GHz 80 Table 5.9: HJFET Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz 81 Table 6.1: Summary of pHEMT Fundamental Load Pull Comparisons 85 Table 6.2: Comparison of pHEMT Class AB Second Harmonic Tuning at Pin=13 dBm 88 Table 6.3: Summary of HBT Fundamental Load Pull Comparisons 92 Table 6.4: Comparison of HBT Class AB Second Harmonic Tuning at Pin= -2 dBm 94 Table 6.5: Summary of HJFET Fundamental Load Pull Comparisons 95
v Table 6.6: Comparison of HJFET Class AB Second Harmonic Tuning at Pin= -1 dBm 96 Table A.1: S-Parameter Calibrations used in this Thesis 107 Table A.2: Summary of Conjugate Source/Load Match for InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA) 109 Table A.3: HBT Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz 110 Table A.4: Summary of Conjugate Source/Load Match for GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=-0.41 V, Ids=18 mA) 112 Table A.5: HJFET Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz 114
vi LIST OF FIGURES Figure 2.1: Output Spectrum for Typical ACPR Measurement  7 Figure 2.2: Output Spectrum for Typical NPR Measurement  7 Figure 2.3: Typical RF Power Amplifier Circuit with DC Load Line [13, 14] 10 Figure 2.4: PA Fundamental Load Pull System Utilizing Electro-mechanical Tuners  14 Figure 2.5: PAE/Pout vs. Pin with/without Harmonic Terminations @ 1.5 GHz  19 Figure 2.6: Measured PAE/Pout vs. Frequency with/without Harmonic Terminations  19 Figure 2.7: Effects of Harmonic Tuning vs. DC Drain Bias Current @ 1.5 GHz  20 Figure 2.8: Active Harmonic Load Pull System for Testing HBT and MESFET  21 Figure 2.9: Effects of 2nd Harmonic Tuning on an HBT (left) and MESFET (right)  22 Figure 3.1: HJFET Device Structure  25 Figure 3.2: MESFET Device Structure  29 Figure 3.3: HEMT Device Structure  30 Figure 3.4: pHEMT Device Structure  31 Figure 3.5: HBT Device Structure  37 Figure 3.6: ADS TOM Model for GaAs HJFET LNA 41 Figure 3.7: ADS EEHEMT Model for GaAs pHEMT 43
vii Figure 3.8: Standard SPICE Gummel Poon Model  44 Figure 4.1: 1.75 to 8.75 GHz pHEMT S-Parameters using Lightning VNA 48 Figure 4.2: pHEMT Source (left) and Load (right) Stability Circles at 2.45 GHz 52 Figure 4.3: Fundamental Load and Source Tuning Block Diagram 53 Figure 4.4: Typical Second Harmonic Load Pull Setup 54 Figure 4.5: Fundamental Source and Load Impedance Spreads with System Losses 55 Figure 4.6: Second Harmonic Load Tuner Impedance Spread with System Losses 55 Figure 4.7: Delta-Gt Measurement on Probe Point CM 10 Calibration Substrate 58 Figure 4.8: pHEMT Class AB 50-ohm Power Sweep Comparisons b/w Maury and VNA 59 Figure 4.9: Conjugate Source Matching Comparisons 61 Figure 4.10: Conjugate Load Matching Comparisons 61 Figure 4.11: Insertion Loss for each Path of 2.45 GHz Maury Microwave Triplexer 64 Figure 4.12: Tuning Independency Results  65 Figure 4.13: Deviation of Tuner States vs. Degradation in Isolation (MAX Deviation)  66 Figure 5.1: Simulated (dashed) vs. Measured (solid) IV Curves (Pulse Conditions: Vds=8 V, Vgs=-0.8 V, Ids=162 mA, NDU=0.081) 69 Figure 5.2: Comparison of pHEMT Class AB S-Parameters from 1.75 to 8.75 GHz 71 Figure 5.3: Comparison of Class AB 50-ohm pHEMT Power Sweeps at 2.45 GHz 72 Figure 5.4: Simulated (dashed) vs. Measured (solid) IV Curves (Pulse Conditions: Vce=3.3 V, Ibb=200 uA, Icc=20 mA, NDU=0.184) 74 Figure 5.5: Comparison of HBT Class AB S-Parameters from 1.75 to 15.75 GHz 75 Figure 5.6: Comparison of Class AB 50-ohm HBT Power Sweeps at 2.45 GHz 77
viii Figure 5.7: Simulated (dashed) vs. Measured (solid) IV Curves (Pulse Conditions: Vds=3 V, Vgs=-0.5 V, Ids=17 mA, NDU=0.1) 78 Figure 5.8: Comparison of HJFET Class AB S-Parameters from 1.75 to 5.25 GHz 79 Figure 5.9: Comparison of Class AB 50-ohm HJFET Power Sweeps at 2.45 GHz 81 Figure 6.1: pHEMT Fundamental TOI Load Tuning Comparison @ Pin=13 dBm 85 Figure 6.2: pHEMT Second Harmonic Load Tuning Comparison @ Pin=13 dBm 87 Figure 6.3: Comparison of C/I and IM3 vs. Second Harmonic Phase @ Pin=13 dBm 87 Figure 6.4: C/I (dBc) vs. Second Harmonic Tuning Simulations for pHEMT 89 Figure 6.5: IM3 (dBm) vs. Second Harmonic Tuning Simulations for pHEMT 90 Figure 6.6: Carrier vs. Second Harmonic Tuning Simulations for pHEMT 90 Figure 6.7: Drain Efficiency vs. Second Harmonic Simulations for pHEMT 91 Figure 6.8: HBT Fundamental TOI Load Tuning Comparison @ Pin= -2 dBm 92 Figure 6.9: HBT Second Harmonic Load Tuning Comparison @ Pin= -2 dBm 93 Figure 6.10: HJFET Fundamental TOI Load Tuning Comparison @ Pin= -1 dBm 94 Figure 6.11: HJFET Second Harmonic Load Tuning Comparison @ Pin= -1 dBm 96 Figure A.1: Conjugate Source Match of InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA) 108 Figure A.2: Conjugate Load Match of InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA) 108 Figure A.3: 50-ohm Power Sweep Comparisons for InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA) 110 Figure A.4: Conjugate Source Match of GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=-0.41 V, Ids=18 mA) 111 Figure A.5: Conjugate Load Match of GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=-0.41 V, Ids=18 mA) 112
ix Figure A.6: 50-ohm Power Sweep Comparisons for GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=-0.41 V, Ids=18 mA) 113 Figure B.1: 2-Tone 2.45 GHz 50-ohm Power Sweep Simulation Template 116 Figure B.2: ADS 2.45 GHz Fundamental Load Pull Simulation Template 117 Figure B.3: Indexing of Impedances for 2.45 GHz Fundamental Frequency Tuner 118 Figure B.4: ADS 4.9 GHz Second Harmonic Load Pull Simulation Template 119 Figure B.5: Simulated Impedance Spreads from Second Harmonic Template 120
x LINEARITY OPTIMIZATION OF POWER TRANSISTORS UTILIZING HARMONIC TERMINATIONS Ravi Kumar Varanasi ABSTRACT This thesis focuses on the characterization and optimization of microwave power transistors using a commercial on-wafer harmonic load pull system. Specific attention is paid to the output tuning of the second harmonic impedance presented to the device. The ability to quantify the level of accuracy in a load pull system is explored by using various calibration validation methods, including a method called Delta-Gt. In this work experiments and simulation comparisons are described for three different device technologies, namely GaAs pHEMT, GaAs HJFET and InGaP HBT. Externally supplied non-linear models were used for the simulations and these were exercised and compared against 2.45 GHz fundamental frequency measurements made as part of this work to first validate the models against IV, S-Parameter and fundamental load-pull data and finally to explore performance variations under 2nd harmonic impedance tuning. The measured harmonic load-pull data pointed to different guidance on how one would match the 2nd harmonic for best performance. With regard to the model validation/assessment work it was found that only in the case of the pHEMT did the available non-linear model provide a good fit to all the different types of measurement data, including 2nd harmonic tuning data. This model was then used to show that even though the 2nd harmonic tuning
xi measurement had a limited maximum reflection coefficient of about 0.8. Simulated results showed that the worst case linearity condition occurred for the same reflection angle as that measured, but that the variation between worst-case and best case linearity under 2nd harmonic tuning grows considerably larger as the magnitude of the 2nd harmonic reflection coefficient approaches 1. A key aspect of the methodology presented in this work is that once a non-linear model is proved to be valid for harmonic tuning conditions it can be used to explore harmonic tuning-related design trade-offs under a much wider range of frequency and tuning conditions than can be practically explored with measurements alone.
1 CHAPTER 1 INTRODUCTION 1.1 Overview In todays portable communication networks, such as cellular telephone or wireless local area networks (WLAN), the power amplifier (PA) consumes a large portion of the supplied DC power , which places an emphasis on the efficiency of the amplifiers used, especially in the transmitter. Efficiency is a key parameter in amplifiers and provides users with longer battery life. To optimize efficiency, proper device selection along with optimal source and load matching networks are used and incorporated into the power amplifier design. However, the optimization of efficiency degrades the linearity of an amplifier, due to competing parameters of device size, bias and a difference in general, of matching impedances needed to minimize harmonic frequencies of the carrier signal and thirdorder intermodulation products for multiple carrier modulation systems. These distortion products interfere with other radio systems, causing the designs to fall short of FCC regulations. Also, with evolving IEEE wireless standards , the limits of linearity are getting stricter. Therefore, its crucial for the PA to maintain high linearity in conjunction with elevated power-added efficiency (PAE), an engineering design trade-off.
2 Fortunately, an amplifiers transistors can be tested for PAE and linearity during the design phase by using a commercially available source and load pull system . Much work has been done in this area to evaluate the influence of optimal source and load tuning on the PAE and linearity. Most studies of the effect of optimal terminations on linearity have focused on the devices carrier frequency and have not concentrated on the output harmonic frequencies for the device under test (DUT). 1.2 Technical Approach The focus of this thesis is to develop and characterize an on-wafer harmonic load pull system, for the purposes of measuring some example devices for linearity under second harmonic loading conditions. In order to achieve this goal, the calibration and measurement correlation of this complex system had to be verified. To this end, a DeltaGt calibration routine is presented that enables precise calibrations  and a method to ensure the validity of fundamental tuning measurements in the system is shown . This thesis also presents comparisons of available non-linear transistor models to the largesignal measurements taken within the harmonic load pull system. From these comparisons, the extent to which the non-linear transistor models predict second harmonic performance is analyzed and limitations are identified.
3 1.3 Contributions of the Work A harmonic load pull system that is able to optimize device performance under varying second harmonic loading conditions was developed. Much of the work in this area has been devoted to the improvement of power-added efficiency; however, this thesis explores linearity enhancement achieved through second harmonic load tuning, which has not been definitively established. This complex system allows independent tuning of second and third harmonic impedances, an extension of the fundamental systems that are used commercially. Available non-linear transistor models for three example devices were exercised for prediction of fundamental and harmonic load pull measurements. The testing of these different models for their prediction of device performance under varying second harmonic load conditions is one of the most interesting and important parts of this thesis. If a non-linear model process can be validated to reliably predict harmonic tuning behavior, its use is considerably more convenient than complex harmonic load pull measurements. 1.4 Organization of the Thesis Chapter 2 provides a review of harmonic tuning, while providing background information on the types of nonlinearity and different amplifier biasing topologies; also, some of the recent examples of harmonic tuning from the literature will be shown. Chapter 3 explores
4 the technologies as related to the devices used in this work and examines the models for the three devices as well. Chapter 4 discusses pulsed IV and S-Parameter methods, including stability and mismatch theory. It also illustrates the harmonic load pull measurement system and theory, and details validation measurements on an example device. Chapter 5 shows the model and simulation comparisons of pulsed IV, smallsignal S-Parameters and 50-ohm gain compression, for an InGaP HBT , GaAs JFET  and a GaAs pHEMT . Chapter 6 compares the measured and simulated results for power, TOI, efficiency and linearity for fundamental and second harmonic load tuning on three selected devices. Chapter 7 provides a conclusion for the work and recommendations for future work.
5 CHAPTER 2 REVIEW OF HARMONIC TUNING MEASUREMENTS AND DESIGN PRACTICE 2.1 Introduction Load Pull measurements have been widely accepted as the method by which to verify the accuracy of non-linear models and to characterize the behavior of various devices that may not have models suitable for power amplifier (PA) design. In the past, these load pull measurements have been restricted to tuning the load and source impedance at the fundamental input frequency. The problem with this method is that, in some cases, the performance is limited by not monitoring or contro lling impedances at harmonic frequency components. With the utilization of a multiplexer, it is possible to independently tune the input or output impedances at harmonic frequencies. Harmonic frequency tuning is often critical to realizing the full potential of a power device, in terms of output power, efficiency and linearity. The second harmonic output frequency, 2fo in particular, has been of considerable interest. It has been shown that 2fo tuning can have a significant influence on optimum power amplifier design . This chapter will explore the measurement practice and detail some examples of harmonic tuning.
6 2.2 Methods to Test Nonlinearity To quantify the amount of distortion present in an amplifier, adjacent channel power ratio (ACPR), noise power ratio (NPR) and continuous wave (CW) testing methods can be used. These measures indicate the degree of distortion present in power amplifier or nonlinear devices. While the scope of this thesis involves only 2-tone CW measurements, ACPR and NPR are important measures to discuss in the context of modern digital communications systems. ACPR measures the amount of a signal that has spread into any adjacent channels, which could cause potential interference . This is a direct consequence of power amplifier nonlinearity and thus is a very important measure that can be used to better develop and model these nonlinear devices. ACPR is defined as the power contained within a specific bandwidth of interest at an offset frequency from the center frequency divided by the power within the desired bandwidth of interest, within which the center frequency resides. The input stimulus frequency for ACPR is a broadband modulated signal (e.g. CDMA modulation is commonly used). NPR determines the amount of in-channel distortion power generated from PA nonlinearities . It is measured by taking part of the input signal, filtering it (using a notch filter) and examining the amount of distortion the fills in the resulting gap in the output spectrum. NPR is defined as the ratio between the noise power spectral density of a white noise signal passing through the amplifier, measured at the center of the notch in the spectrum, to the noise power spectral density without the notch filter. In each case,
7 the amplifier drive level is the same so that a direct ratio comparison can be made and will be valid. Some typical output spectrums for ACPR and NPR, respectively, are shown below in Figures 2.1 and 2.2. Figure 2.1: Output Spectrum for Typical ACPR Measurement  Figure 2.2: Output Spectrum for Typical NPR Measurement 
8 Single-tone CW testing provides information about the devices ability to handle a certain range of input powers. AM-AM and AM-PM conversion information can then be obtained from the amplifier, which helps model the basic nonlinear performance of the device. Also, the amplifiers saturated input/output power and P1dB input/output power can be obtained as long as it is driven well into compression. With two tone CW testing, the second order intercept (SOI) and third order intercept (TOI) of the device can be measured or extracted, and defines how much power the device can theoretically be driven with until the intermodulation distortion products become a major problem. The knowledge of these parameters can significantly improve the transistor model. Finally, load pull measurements can be performed to test the amplifiers power and distortion parameters over large-signal drive levels for different source and load conditions. This can further validate the nonlinear transistor simulation model predictions or reveal inadequacies necessitating model improvements. 2.3 Classes of Operation In Appendix A, a discussion on the origins of distortion is presented, that shows mathematically how gain compression, harmonic levels and intermodulation products arise. We now begin to examine the performance of the power amplifier. The forms of distortion discussed previously are dependent upon the amplifiers quiescent bias, derived from a devices IV curves.
9 Before we delve into amplifier bias topologies, a couple of terms must first be defined. Power-added efficiency (PAE) is defined as the power added by application of an RF input drive level, in ratio to the supplied dc power. The output efficiency is the efficiency at the output terminal of the device (drain or collector, for example) and does not take the RF drive level (i.e. gain) into account : dc out dc RF in RF outP G P P P P PAE ) 1 1 ( / ) (, , = = (2.1) dc RF outP P /,= (2.2) This section will discuss amplifier classes A through F and will cover topics such as operating point selection for each class, conduction angle for amplification, drive level requirements and power performance of the amplifier, all while discussing the levels of distortion present in each amplifier biasing classification. 2.3.1 Overview of Amplifier Topologies A typical RF power amplifier consists of a transistor, a biasing network and a matching network preceded by a filter, as shown for the case of a single-ended transistor amplifier in Figure 2.3. This amplifier can be used as either a Class A, B, AB or C amplifier configuration. These are the most commonly employed types of amplifiers. The amplifier can also be operated for classes D, E and F.
10 Figure 2.3: Typical RF Power Amplifier Circuit with DC Load Line [13, 14] Amplifier classification is defined by its position on the IV characteristic curves and by the amount of the output current cycle for which it conducts, as in Figure 2.3. This is referred as its conduction angle. The conduction angle influences on harmonics present in the device as well as its efficiency performance. In a class A amplifier, the current conducts for the full portion of the output cycle. The RF signal will swing symmetrically as long as it maintained between cutoff and saturation. Ideally, harmonic power is limited until the device is driven with a high enough RF drive level to cause clipping, which makes this a very desirable linear amplifier design. The output power of a class A amplifier is high, and leads to a maximum theoretical output efficiency of 50%. However, they dissipate power at all times, even without an applied RF input signal, keeping the PAE low. Class A amplifiers are utilized in high gain, good bandwidth and high linearity applications.
11 In a Class B amplifier, current conducts for the positive portion of the output cycle. Therefore, the transistor is only active for half of the time and is biased at the threshold of conduction with a minimal quiescent power due to the very small output voltage or current. The class-B configuration achieves output power similar to class A amplifiers for much smaller quiescent supply power, and therefore this configuration can achieve much greater and PAE. In fact, the maximum for a class B amplifier, under idealized conditions and with ideal components, is 78.5% . The reduced conduction angle that produces increased levels of efficiency also results in high levels of distortion, especially harmonic signal levels. This is a major drawback of this type of design. There is ultimately a trade-off that occurs between the amount of distortion that can be tolerated and the amount of efficiency that is needed. Class AB is generally used as a design tradeoff between the high linearity and high efficiency extremes of class A and class B, respectively. In class AB mode, the quiescent bias is set so that the device is operating in the active region for over half but less than a full output cycle. By maintaining this operation, the device can be more efficient than class A amplifiers and have a higher gain than class B amplifiers. Class AB can be a trade-off design between gain and efficiency, especially where RF drive level must be kept constant. However, the PA designer must still endure some problems with harmonic distortion, especially the second harmonic components, which are in phase with the fundamental frequency and detracts from its power. The results presented later in this thesis use a Class AB bias. Class AB was chosen due to its emergence in industrial applications.
12 Class C is an extremely efficient biasing class that generates a great amount of harmonic distortion because it conducts for less than half of the output cycle. The efficiency changes rapidly, and can approach 100% . The efficiency is greatest at the onset of saturation, after which it will gradually and slowly decrease. Since this is not a linear amplifier, the device can be driven harder into saturation without a significant detriment in performance. Class C amplifiers, however, cannot be employed in any system where linearity is a requirement. Also, the output power of a Class C design is significantly reduced compared to Class A, AB and B. Any device with this topology is nonlinear, seen by its use in saturation to achieve higher efficiency levels. Class D amplifiers consist of transistors that act as switches, squaring the output voltage sinewave, which can improve power and efficiency . This provides the PA design engineer with more leverage in a trade-off between efficiency and linearity. An advantage of Class D operation is that within this amplifier, only the fundamental frequency components are passed to the load. With this amplifier acting as a switch, theoretically 100 % efficiency can be gained because current is only drawn from a single transistor. Drawbacks of the Class D amplifier are the losses incurred by switching speed, saturation and drain capacitance, which limits its maximum operating frequency . Class E amplifiers use a single transistor as a switch, minimizing losses due to switching speeds. The output waveform is formed by charging the drain shunt capacitance by RF and DC currents. Class E is a nonlinear amplifier, and any variations in the input envelope produces unwanted distortion. For Class E, is 100%.
13 Class F achieves its higher output power and efficiency by using harmonic resonators at the output of the device, in addition to the fundamental frequency resonance. In this configuration, the transistor acts like a current source, approximating a half sinewave with the voltage approximating a squarewave. The Class F amplifier operates by using the output resonator to reflect voltage at the third harmonic frequency, in such a way as to flatten the voltage waveform. The device is operated in compression to achieve the required harmonic levels needed to flatten the waveform . 2.4 Design Aspects The theory of harmonic load pull is well established . By monitoring the harmonic impedances of a device, the power performance can be improved. This method can also be used to more accurately predict power amplifier performance from a nonlinear device simulator, such as Agilents Advanced Design System (ADS) , provided accurate enough non-linear transistor models are available. There has been work done in this area, with respect to the amount of achievable PAE and/or linearity that can be obtained in an amplifier by utilizing harmonic terminations . Before discussing some of these interesting designs that have been extracted from the literature, though, it is beneficial to talk about some design topics in performing these measurements and achieving accurate and viable results.
14 2.4.1 Active vs. Passive Tuner System Much of the harmonic tuning literature revolves around active harmonic load pull systems, as opposed to the passive load pull system that will be employed for this particular work and shown in Chapter 4. An active system is comprised of an active load that contains a phase shifter, tunable filter, variable attenuator and an amplifier. The active load takes the output signal of the device under test, amplifies it, and feeds the resultant signal back to the output of the device. A microwave transition analyzer (MTA) or a VNA with 4-wave detection capabilities is used to measure the output of the DUT . Passive systems use electro-mechanical tuners to tune for optimum source/load impedances of the DUT . A passive system is shown in Figure 2.4. Figure 2.4: PA Fundamental Load Pull System Utilizing Electro-mechanical Tuners  Using an active system allows a user to access reflection coefficients for all tuners near or beyond the edge of the Smith Chart (| |=1) and does not require precharacterization of the tuners, which saves hours of test time. Active tuner systems are especially useful in harmonic tuning applications, where typically a device needs to see either a short circuit, =1<180, or open circuit, =1<0, to operate at its full potential.
15 The disadvantages of using this setup is the additional equipment that is used, which raises the cost of the setup, as well as the complexity of the setup compared to a passive tuner system since more components are needed. An active tuner system was not available for the described work, so we turn our attention to passive tuning systems. The advantages of using passive tuner systems are reliability, repeatability and simplicity. Although the tuners have to be pre-characterized, these setups require less equipment and thus less calibration and instrumentation expense. The major equipment needed is the tuner controllers, tuners, CW sources, and power meters. For TOI applications, a spectrum analyzer and another CW source will be added to the setup. They are more reliable because they are not dependent on an active load, which depends on the loop amplifier characteristics. Disadvantages are the inability to reach the periphery of the Smith Chart with a passive tuner, especially at harmonic frequencies. Also, the measurements are much slower using a passive system. A triplexer or harmonic resonator is needed to perform harmonic tuning, such as in the Maury Microwave tuning systems, and along with any other losses in the system will further degrade the available tuning range.
16 2.4.2 Source Tuning vs. 50-ohm Source Impedance In power amplifier tuning systems, the primary concern is load tuning. However, an important issue to discuss is whether to use a source impedance tuner or to leave the source impedance at 50 Source tuning can have more of an effect on the amplifier power enhancement than the load tuning, due to the pre-distortion of the input signal to the device. Source tuning is primarily employed to boost the power gain of the transistor. It also can ease the amplifier drive level by reducing the amount of reflected power. When driving a device nonlinearly, the gain becomes less of a priority than Pout, and TOI. Since load pull is a system employing design tradeoffs, source tuning could be used to achieve moderate gain and high efficiency to develop a linear amplifier. One of the problems with source tuning occurs when the conjugate match is at a certain reflection coefficient, such as 0.9, and the tuner is limited to 0.8 (for a passive load pull system). In this scenario, source tuning will improve device performance, but not to an optimum level. Sources maintained at 50 can be used in situations where the device is not highly mismatched at the input. This simplifies calibration and avoids additional system losses associated with the source tuner. Also, for potentially unstable transistors, a 50 source may keep the device from oscillating while the output of the device is optimized.
17 2.4.3 One-tone vs. Two-tone Tuning Single-tone load pull systems allow the user to test the power performance of an amplifier for Pout, P1dB and PAE at both the source and load of a device, for fundamental and harmonic frequencies. Single-tone systems portray information such as the AM-to-AM and AM-to-PM conversion of the amplifier. Single-tone systems also allow direct correlation between small-signal conjugate matches and small-signal tuning conditions. While this is a useful test, it does not give a sufficient view of how the amplifier will behave in a modern wireless communications radio. It can be assured that 2-tone is not sufficient either. The reasoning is that most radio systems now employ multiple-carrier modulation systems, such as OFDM, to transmit data through a communications link. The ability to transmit this data effectively depends on the multiple-carrier performance of the power amplifier. Another important test for the amplifier would be a 2-tone load pull test, which is used in this thesis. Two-tone load pull tests convey information such as the TOI of the amplifier, where the third-order intermodulation product and the carrier signal (theoretically) intercept . The design aspects detailed in this section apply to both fundamental and to harmonic load pull systems. Each is important in determining the conditions for the optimum performance of the power amplifier. The examples in the next section will illustrate the reported amplifier dependence on second harmonic terminations.
18 2.5 Design Examples from the Literature Previous work has been done that shows the significance of harmonic tuning,. These examples have been done on different devices, at different biases, and at different frequencies. Most of these examples are performed in load pull systems that do not employ any source tuning. These examples can provide a baseline for the kind of results that can be achieved by the use of harmonic load tuning measurement technique. Chung et al  investigated the loading effects of an L-band AlGaN/GaN high electron mobility transistor (HEMT) power amplifier over increasing input power and dc bias conditions, ranging from 50% Idss (Class A) to 1% Idss (Class B), with and without harmonic terminations for a single-tone system. The device was optimized for RF output power and power-added efficiency by devising filters and harmonic matching networks so that a short circuit impedance is presented to the second harmonic and an open circuit impedance is presented to the third harmonic frequency. Figure 2.5 shows Pout and PAE for a Class AB bias (25% Idss) vs. Pin and Figure 2.6 shows the results vs. frequency. From Figure 2.5 it can be seen that the peak efficiency of 57% occurs for an input power of 23 dBm and shows an increase of 10% from the same measurements without harmonic terminations. The output power at this same input level has also increased by 0.9 dB, which is not as significant as the PAE improvement, but is still useful.
19 Figure 2.6 shows that the efficiency improvement ranges from approximately 416 percent versus the measurements without harmonic terminations. Likewise, the output power improvement is about 0.4-1 dB versus the measurements without harmonic terminations over the frequency band shown. Figure 2.5: PAE/Pout vs. Pin with/without Harmonic Terminations @ 1.5 GHz  Figure 2.6: Measured PAE/Pout vs. Frequency with/without Harmonic Terminations 
20 Figure 2.7 shows the variation in PAE and Pout, with and without proper harmonic terminations, as a function of dc bias current. As the dc current decreases towards pinchoff, the amount of deviation in PAE and Pout increases. This agrees with theory, which suggests that as conduction angle is reduced, nonlinearities in the device start to increase and thus matching the harmonics will have much more of an effect than a higher conduction angle or Class A bias. It is seen that at 300 mA, or class A bias, the PAE improves by 3% and Pout by 0.3 dBm, whereas at class AB, as shown earlier, there is a 10% increase in PAE and ~1 dB increase in Pout. Figure 2.7: Effects of Harmonic Tuning vs. DC Drain Bias Current @ 1.5 GHz 
21 Rudolph, et al , investigated an active multi-harmonic load pull technique that monitored the influence of harmonic termination impedances on RF output power and PAE. These measurements were performed at 2 GHz on an InGaP/GaAs HBT power cell and a GaAs MESFET medium power transistor. The active tuning system is shown below in Figure 2.8. Figure 2.8: Active Harmonic Load Pull System for Testing HBT and MESFET  In , harmonic load pull simulations were performed using a modified Gummel-Poon model for the HBT and a modified Root model for the MESFET. These simulations were compared to the measurements and show good correlation, as displayed in Figure 2.10 for the HBT and for the MESFET. The modeled curves are shown by solid lines and the circles denote measured curves. The 2nd harmonic reflection coefficient has been kept at =1 while the phase was varied from 0-360.
22 Figure 2.9: Effects of 2nd Harmonic Tuning on an HBT (left) and MESFET (right)  As you can see from Figure 2.9, minimums are seen in the Pout and PAE curves when the devices are presented with short circuit second harmonic terminations, both for measurements and simulations, which correlate very well. The source has been kept at 50 for these measurements, while all harmonics higher than the second have been terminated in a 50 load. Despite the degradation in output power and efficiency near a short circuit, the dependence of the device on the second harmonic termination has been established and shows the technique to be a very successful and important one in the design of linear and power efficient amplifiers. These examples have shown the significance of harmonic tuning experiments, for both active and passive load pull systems. By controlling the impedance presented to the device at the harmonic frequencies, especially the second harmonic, device performance will be affected. With these examples as a baseline, this work will further study the influence of 2-tone harmonic tuning on a few different transistor technologies.
23 2.6 Chapter Summary Measurement techniques that may be used to quantify the harmonic energy, such as TOI have been discussed. Several examples have been shown that demonstrate the influence of harmonic tuning, particularly the second harmonic, which is the focus of this work. Chung et al , has shown that PAE has increased by10% and output power by 1 dB (at 1.5 GHz) by terminating the second harmonic in a short circuit, by using a passive tuner system. It was also shown that PAE increased by 4-16% from 1.2 GHz to 2.2 GHz. Rudolph, et al  used an active tuner system to explore the significance of second harmonic tuning on an InGaP/GaAs HBT power cell and GaAs MESFET medium power amplifier. These experiments show that both devices were sensitive to short circuit impedances on the second harmonic load tuner. Non-linear simulation models predicted these effects relatively well.
24 CHAPTER 3 DEVICE TECHNOLOGY AND MODELS 3.1 Introduction The evolution of the III-V semiconductor growth technology has improved the characteristics of the power amplifier, which is crucial to the design of linear and efficient power amplifiers with acceptable levels of output power, transducer gain and distortion levels. Current trends involve using a heterojunction to facilitate higher electron mobility and better injection properties to improve device power density, speed and integration for a radio-frequency integrated circuit (RFIC) . The choice of transistor depends on the application(s) for which it will be used. To understand the capabilities and characteristics of different power transistors used in this work, this chapter will discuss the device technologies for a HJFET, a HBT and a pHEMT. 3.2 HJFET Device Technology This section will discuss the device structure, principle of operation and advantages of using a heterojunction field effect transistor (HJFET) and will also discuss the specific HJFET to be used in this work.
25 3.2.1 HJFET Device Structure An HJFET is a majority-carrier device that utilizes a wide band gap semiconductor as its gate in order to improve device performance. It is used primarily for low-noise and medium power applications. The HJFET is the simplest type of FET, as it consists of a long channel of doped (n or p-type) semiconductor material with source and drain contacts on either side of the channel. The gate is isolated from the channel through a p-n junction, which also forms the gate contact. This situation differs from a MESFET, which uses a Schottky metal-semiconductor barrier to form the gate for the transistor. An example device structure is shown in Figure 3.1 for an InP-based HJFET. Figure 3.1: HJFET Device Structure  The depletion region is a potential barrier region that is depleted of electron and hole carriers that are needed for conduction in the channel to occur. The depletion region width increases when the HJFET is reverse biased at the gate, which lowers the channel conductance and increases the carrier mobility. The gate voltage, Vgs, has control over the channel conductance and channel current.
26 3.2.2 Principle of Operation for HJFET The HJFET is a depletion mode device, meaning that the channel has a finite cross section at zero gate voltage. This is the only mode in which the HJFET can operate; it cannot operate in enhancement mode. For a HJFET, there is a long, doped semiconductor channel, either n-type or ptype depending on the configuration of the transistor. In other words, if the transistor is an n-FET, the channel will be n-type, for p-FET the channel will be p-type. The depletion region created by the p-n junction spreads into the channel. Without an applied voltage, there will be no current flow through the device. However, under normal operation, a voltage is applied across the channel. This voltage moves electrons through the channel from the grounded source to the higher potential drain. There will then be a current flowing through the device that depends on the conductance/resistance of the channel and the magnitude of the applied voltage. To control the current flow through the transistor, the gate to source voltage Vgs must be manipulated in conjunction with the drain to source voltage, Vds. Upon increasing Vds, there are several effects that occur. First of all, the drain current will increase. With the increase in drain current comes an expansion of the depletion region near the drain contact, resulting in a reduced conductance of the channel semiconductor. Also, the channel will become asymmetrical, since with the positive potential drain
27 voltage induces a reverse bias between the channel and gate junction. As Vds is further increased, the channel near the drain becomes further pinched off until the electron flow from the source to drain will saturate. This saturation is electron flow leads to current saturation, and is referred as the saturated drain current, Idss. 3.2.3 Advantages and Disadvantages of the HJFET Technology There are several advantages of the HJFET technology over the different device technologies that exist in production today. First of all, due to the reverse bias across the gate to source contacts, there is only a small input (leakage) current, which translates to a high input resistance. Also, since the depletion region conductance decreases as the applied voltage increases, the mobility of the carriers (electrons) is much greater in the HJFET. This correlates to increased speed in the device, making it ideal for switching and high speed integrated circuit applications. HJFETs also have excellent noise performance. The HJFET has excellent linearity due to low parasitic losses . Parasitic losses reduce current, lowering gain in a device. Output power is good, but can be affected by degraded breakdown voltage, which competes with speed (Ft) of the device. Power added efficiency is enhanced due to the increased speed and gain of an HJFET. The disadvantages of an HJFET are its poor stability, which has to be compensated for by using feedback circuitry, increasing the complexity and cost of a design, especially when operated as a common source amplifier. The stability problem is
28 overcome by using the HJFET as a common-gate amplifier. However, the noise figure will be sacrificed by switching to this configuration since the input impedance of a common gate amplifier is lower than a common source amplifier . The HJFET can be used in applications such as low-distortion circuits, audio and RF power amplifiers, video amplifiers, high frequency probes, voltage-controlled resistors, and digital circuits . It should be mentioned that HJFETs are usually fabricated using GaAs, due to the small mass of electrons and thus higher electron mobility characteristics. Also, it is possible to fabricate these devices along with ICs using direct ion implantation into a semi-insulating GaAs substrate . 3.2.4 Specific HJFET Device Studied in this Work In this work, a GaAs HJFET was studied. This work on this device was suggested by Allen Podell. The device is an L to S band Low Noise Amplifier (LNA) that is housed in a plastic surface mount package and has a gate length of 0.6 um and a gate width of 400um. The fabrication process was done by ion implantation, which improves RF and DC performance as well as reliability. Its high gain, low noise figure and small form factor make it ideal for commercial applications, such as WLAN.
29 3.3 pHEMT Device Technology This section will discuss the device structure, principle of operation and the advantages and disadvantages of using a pHEMT transistor over a MESFET transistor, and the specific pHEMT used in this work. 3.3.1 pHEMT Device Structure A high electron mobility transistor (HEMT) is a variation of the well-known metal semiconductor field effect transistor (MESFET) device . GaAs-based HEMTs and pseudomorphic HEMT (pHEMT) have taken over military and commercial applications requiring low noise figure and high gain from the MESFET technology . Of special interest is the GaAs pHEMT, which is being used for applications requiring high-efficiency power amplifiers, such as base-stations or wireless networks. Lets first discuss the differences between the MESFET and HEMT device structures and then extend the discussion to the pHEMT device structure. Figure 3.2: MESFET Device Structure 
30 The MESFET device structure is shown in Figure 3.2. The device consists of n+ source and drain regions, which are connected through an n-type channel region. A Schottky barrier is used for the gate contact and regulates the current flow across the channel between the source and drain. A depletion region is formed within the channel. The gate bias voltage changes the thickness of the region, which changes conductivity in the channel and produces an enhanced mobility over the MOSFET device technology. Figure 3.3: HEMT Device Structure  The HEMT structure reveals the physical differences between itself and the MESFET device technology. In this structure, there exists a heterojunction between the n-type AlGaAs (purple) and the undoped GaAs (white). The AlGaAs has a higher bandgap than GaAs, which causes free electrons to diffuse from AlGaAs to the GaAs region to form a thin layer of a 2-dimensional electron gas , which is commonly called 2DEG as seen in Figure 3.3. This 2DEG region significantly enhances electron mobility due to the absence of ionized donors and the lack of scattering in the device,
31 which is the limitation on mobility within the MESFET. The mobility is enhanced by the spacer layer, which further separated the 2DEG from the ionized donors. The pHEMT technology has improved upon the basic HEMT structure by incorporating an InGaAs channel material to form the thin 2DEG layer within the device. This layer has improved transport characteristics over GaAs. InGaAs also has improved carrier isolation, a larger conduction band discontinuity with the heterojunction with AlGaAs. This larger discontinuity leads to higher current density and transconductance, gm. The device structure is shown in Figure 3.4. Figure 3.4: pHEMT Device Structure 
32 To further push the limits of the HEMT technology, there have also been implementations of an InP-based HEMT devices, which further increase the mobility of the electron carriers and improve the high frequency performance of the device by using the InGaAs channel from the pHEMT with an Indium content between 50 and 80% . The pHEMT is garnering interest in microwave and millimeter-wave applications due to its ability to produce high gain, output power and efficiency. Also, since the mobility is greater than that of a MESFET and even of a HEMT, it is useful for RFIC applications. 3.3.2 Principle of Operation for pHEMT The pHEMT, which is based off of the MESFET device technology, can operate in either depletion or enhancement mode. However, this section will describe the pHEMT operating as a depletion-mode device. The depletion-mode pHEMT fabrication and operation is very similar to the depletion-mode MESFET, with the difference being a heterojunction instead of a homojunction, which exists in the MESFET. Before talking about the pure operation of the device, though, lets discuss the fabrication of the device. First of all, the pHEMT is grown on a semi-insulating GaAs substrate, which is formed using either molecular beam epitaxy (MBE) or metal-organic chemical vapor
33 deposition (MOCVD) . A GaAs buffer layer is then grown on the substrate so that the active layers of the transistor can be grown. A superlattice of AlGaAs is then grown to inhibit substrate conduction. The undoped InGaAs channel is grown next. This channel is where the electron conduction (most of it, at least) takes place. The bandgap energy, Eg, lower than the AlGaAs donor layer. This difference in energy gap levels causes the electrons to diffuse from AlGaAs to the InGaAs channel. These electrons are confined to a thin sheet of charge due to a potential barrier. This thin sheet of charge is called the 2-dimensional electron gas or 2DEG, and exists at the top of the channel layer. This portrays the major difference between the MESFET fabrications, where the channel is doped and there are a lot of ionized donors. This lower scattering is what gives the pHEMT much improved mobility over the MESFET. The undoped AlGaAs spacer further separates the 2DEG from ionized donors, to ensure a high level of mobility within the device, at the expense of total charge due to the thickness of the layer. The donor layer, n+ AlGaAs, acts as the source of the electrons in the device. Another AlGaAs layer is grown on top of the donor layer, but has a lower energy gap than the donor, inducing the possibility for electron diffusion. To avoid conduction in this top layer, the donor layer thickness is chosen to ensure that the depletion region of the gate overlaps the depletion region at the AlGaAs/2DEG interface. Finally, the n+ GaAs layer provides low-resistance ohmic contacts.
34 The biasing mechanism for a pHEMT is to provide a negative bias to the gate, which will deplete the Schottky layer. As the bias is further increased, the thin layer of 2DEG becomes depleted as well, which modulates the channel. Gain and amplification exist in this condition until the channel becomes fully pinched off (depleted). The transconductance of the device, gm, which occurs before pinch off is given below: d W v gg sat m/ ) * (= 3.1 In Equation 3.3.1, is the permittivity of the InGaAs undoped channel, vsat is the saturated velocity of InGaAs, Wg is the unit gate width of the pHEMT and d is the distance from the gate to 2DEG layer. The vsat of the pHEMT is larger than the MESFET under high electric fields. Since electron conduction from source to drain is well confined, gm will remain high at low levels of drain current, unlike the MESFET where gm compresses as the distance d increases. The pHEMT takes advantage of a heterojunction between two different bandgap semiconductor layers to enhance electron mobility by the reduction of scattering with ionized donors. The enhanced mobility results in low parasitic resistances at the drain and source, which leads to higher Ft and Fmax. Ft is the highest frequency that the device shows a unity current gain, whereas Fmax is the highest frequency that a device can show a unity power gain. These two indications of high frequency performance are seen below.
35 ) ( 2gd gs m tC C g f + = 3.2 in ds tR g f f 4max= 3.3 The device ft and fmax are affected by the time it takes for the electrons to move from the source to the drain. To increase these frequency standards, it is necessary to shorten the length of the gate. However, upon shortening the gate length, there are parasitic effects, such as channel delays and increased source and drain resistances that need to be accounted for. The device power is also affected, as the breakdown voltage decreases with the shortening of the gate length. 3.3.3 Advantages and Disadvantages of the pHEMT Technology There are several advantages of using the pHEMT technology over that of the MESFET and HJFET discussed earlier. First of all, the heterojunction between the InGaAs channel and AlGaAs donor layer produces the 2DEG channel which reduces scattering in the device and enhances mobility. The mobility in the device is further enhanced by growing buffer layers to isolate the electrons from ionized donors in the device. The better mobility in the pHEMT translates to higher transconductance, current density and transit time for the electrons moving from the source to the drain of the device. Also, the pHEMT has a small source resistance due to the n+ GaAs used for low-
36 resistance ohmic contacts. The increased electron velocity in the device leads to high Ft. The output resistance is high in the HEMT, and the Schottky barrier height is increased due to the use of AlGaAs instead of GaAs. Noise figure is reduced and gain is increased as well. pHEMTs have very good power performance because of increased current densities in the device . Due to their high mobility, pHEMTs also have high levels of gain, leading to high ft and fmax and producing excellent levels of linearity. Linearity can be further enhanced by backing off the output power, which reduces PAE. The disadvantages of the HEMT involve the increased traps in the device, due to the high donor levels in the AlGaAs material. These traps lead to degraded drain current and an increase in low frequency noise, such as 1/f noise. Another problem with pHEMTs is electromigration, which is caused by high current densities. Electromigration occurs when a high electrical current passes through a conductor and brings along some atoms from the metal. It can lead to disconnects in a conductor and can be reduced by limiting the current in a device . Another issue is high temperature device burn-out. 3.3.4 Specific pHEMT Device Studied in this Work In this work, a GaAs pHEMT was studied for the effects of second harmonic load tuning on linearity enhancement. The device has an advanced epitaxial doping profile that enhances linearity, high power efficiency and reliability and reduces distortion.
373.4 HBT Device Technology This section will discuss the device structure of the HBT, its operation and some advantages and disadvantages of this device technology over that of the MESFET and HEMT devices, which were discussed earlier. Also, the specific HBT used in this work will be mentioned. 3.4.1 HBT Device Structure The final device to be discussed will be the Heterojunction Bipolar Transistor (HBT) which is based off of the basic bipolar junction transistor (BJT) configuration, utilizing a heterojunction instead of a homojunction within its device structure. A typical InGaP HBT device structure is shown in Figure 3.5, below. Figure 3.5: HBT Device Structure 
38 The HBT structure differs from the HBT by the use of a wide bandgap emitter and low bandgap base, which represents the heterojunction in the device. This enables a higher injection efficiency of electrons into the base and slows down the process of injecting holes into the emitter. Parasitic resistances and capacitances are lower due to this process. 3.4.2 Principles of Operation for HBT The HBT operation is very similar to that of the BJT, with the difference being the heterojunction formed within the HBT, which boosts the emitter injection efficiency. Let us discuss the flow of electrons within the device. Current transport starts with electron injection from n-type emitter to p+ base under forward bias across emitter-base junction. This voltage is denoted as Vbe. These injected electrons move across the base (for a certain width, denoted Wb) by means of drift and diffusion, and are collected by the reverse biased base-collector junction. A high electric field exists at this junction. During this process, electrons are stored in the base due to their effective velocity. The electrons, as minority carriers with a short lifetime, recombine with majority holes, which produce a small base current. Due to Vbe, there is an abundance of electrons and holes created at the emitter-base junction. This leads to depletion layer recombination , where some of these electrons are lost and are not injected into the base. Another
39 recombination process occurs at the surface of the base and contributes to the recombination current. The importance of the heterojunction is that by choosing one semiconductor layer with a higher bandgap than the other, the energy bandgap difference is large enough to ensure that the emitter injection efficiency can take place irrespective of what the doping levels at the base and emitter are. This allows control of the doping profiles of the base and emitter, which allows lowering of the base resistance, improvement of current gain, increased early voltage and reduced base to emitter capacitance . 3.4.3 Advantages and Disadvantages of the HBT Technology The most important advantage of using HBT technology is the enhancement of emitter electron efficiency. This is accomplished by using a higher bandgap emitter layer which prevents holes from being injected into the base. This allows the base resistance to be lowered by increasing the base doping and the base-emitter capacitance can be lowered by reducing the emitter doping. This also leads to improved (higher) early voltage in the device, very high current gain and high power density. Due to the high current gain, the Ft and Fmax of the device is very high. Also, the semi-insulating substrates on which the device is grown reduce the pad parasitics and thus make the HBT an excellent device to use for an integrated circuit design, such as an RFIC.
40 HBTs have low parasitic losses, and can operate from a single-polarity power supply which not only makes them cheaper, but smaller as well since there is extra cost to facilitate a dual-polarity supply. This also allows the HBT to be manufactured in small geometries, which improves its power density and linearity. The disadvantages for these devices are the current collapses that occur for multiple finger HBTs. This reduces the gain substantially and is monitored from the device IV characteristic curves, where Vce has increased past a certain value where the current drops significantly. The HBT can be used for low-noise, high efficiency and high linearity applications such as for cell phones and WLANs. It shows a very good compromise between linearity and efficiency compared to other devices and its power density can be adjusted to suit any application. Since its gain is very high it can also be used for millimeter wave applications as well as microwave. 3.4.4 Specific HBT Device Studied in this Work In this thesis, an InGaP HBT was studied. The device is a 3 finger device with a 3 um base width and a 45 um base length, for a total emitter area of 405um2. The InGaP process has three levels of interconnecting metal and MOCVD is used to grow the active layers. This process has the advantage of high reliability and thermal stability. The device is operated at current densities between 5 and 20 kA/cm2, which correspond to a collector
41 current between 20 and 80 mA. The InGaP HBT is used for power amplifiers, driver amplifiers and wideband amplifier applications as well as mixer and VCO applications. 3.5 Summary of Non-linear Device Models 3.5.1 TOM Model Figure 3.6 shows the setup for the manufacturer supplied Triquint Only Model (TOM) nonlinear transistor model, which is being used for a GaAs HJFET LNA. The model was created using Series IV Libra, a previous version of the ADS software. This device model can be scaled based on the gate area of the transistor. TOM TOM1 Temp= N= W= Model=TOMM1 Port Drain Num=2 Port Gate Num=1 C CGS_PKG C=0.1 pF L LS_PKG L=0.09 nH L LG L=0.93 nH L LD L=0.4 nH L LD_PKG L=0.18 nH C CDS_PKG C=0.1 pF L LS L=0.25 nH C CGD_PKG C=0.02 pF L LG_PKG L=0.18 nH Figure 3.6: ADS TOM Model for GaAs HJFET LNA
42 The model is valid from 0.5 to 6 GHz, with Vds ranging from 1 to 3 V and Ids varying from 5 to 40 mA, all rated from the device manufacturer. The model, which was last revised in June 1997, was tested for AC, DC, P1dB and Noise performance. 3.5.2 EEHEMT Model Figure 3.7 shows the ADS EEHEMT model setup for the GaAs pHEMT transistor. The device has a unit gate width of 240 microns and ten gate fingers as denoted in the figure. The inductors L1, L2 and L3 represent the bond pad inductance for the gate, drain and source, respectively. The model extraction was performed by Modelithics, Inc.( www.modelithics.com ) The model was developed by taking pulsed IV measurements to form a dynamic model. 2-port S-Parameters from DC to 30 GHz were taken for a Class A quiescent bias. After taking these initial measurements, gain compression measurements were taken, with emphasis on output power, gain, PAE and TOI. Tuning measurements for PAE and TOI were done by using the Maury Microwave load pull system. TOI was measured for 50ohm and optimum loading conditions by using a 100 MHz separation between two tones at 3 GHz. The TOI tuning comparisons are discussed in Chapter 6.
43 ` Figure 3.7: ADS EEHEMT Model for GaAs pHEMT 3.5.3 Gummel-Poon Model The InGaP HBT makes use of a Gummel Poon Model, supplied by the device manufacturer, which is an enhanced version of the standard Gummel-Poon model. The generic SPICE Gummel-Poon (SGP) model is seen below in Figure 3.8. Cde and Cdc are depletion capacitances, whereas Cdife and Cdifc are diffusion capacitances. Re, Rc and Rb are all series resistances for each terminal. The model was extracted by taking SParameters from 0.1-26 GHz with 3 to15 kA/cm2 current densities, which sets the quiescent bias point to either Class A or AB bias.
44 Figure 3.8: Standard SPICE Gummel Poon Model  3.6 Chapter Summary This section has summarized the device structure, operation, advantages and disadvantages of each device technology that is used for this thesis and briefly mentioned the devices and device models that will be used for the work in Chapters 5 and 6. From this analysis, all three devices have been discussed in terms of their respective advantages and disadvantages. As a final discussion, Table 3.1 summarizes the information for the specific commercial devices to be used in this thesis, a GaAs pHEMT, and a GaAs HJFET. The InGaP HBT is a proprietary device, and complete application data was not available at this the time of this publication.
45 Table 3.1: Summary of Commercial Devices used in this Thesis [44, 45] Parameter Description GaAs HJFET GaAs pHEMT InGaP HBT Device Size length x width (units in um) 0.6 by 400 0.3 by 2400 3 finger device; 3 by 45 P1dB (dBm) 1-dB comp. power 16.5 32.5 Not Available G1dB (dB) 1-dB comp gain 17 9.5 Not Available Idss (mA) Saturated drain current 30-120 440-940 Not Available Gm (mS) Transconductance30 480-760 Not Available Vp (V) Pinch off voltage -2 to -0.2 -2.5 to -1 Not Available Rth (C/W) Thermal Resistance 833 15 Not Available Vds (V) Drain-source voltage 4 8 Not Available Vgs (V) Gate-source voltage -3 -3 Not Available Tch (C) Channel Temp. 125 150 Not Available Tstg (C) Storage Temp. -65 to 125 -65 to 150 Not Available Pt (W) Total Power Dissipation 0.15 5.7 Not Available NF (dB) Noise Figure 0.6 0.8 Not Available TOI/IP3 (dBm) Third-Order Intercept Point 23 38-40 Not Available
46 CHAPTER 4 EXPERIMENTAL METHODS AND VALIDATIONS 4.1 Introduction This chapter will discuss the current-voltage (IV) small-signal S-Parameter, source/load pull and triplexer measurement techniques and related theory for the study of nonlinear performance. After the theory is established, tuning measurement validations will be illustrated. For the purposes of brevity, this chapter will demonstrate example data for the GaAs pHEMT example discussed in Chapter 3. Similar data on the other two example device types can be found in Appendix A. 4.2 Pulsed IV Theory For FETs and bipolar transistors, the IV characteristics for RF frequency signals differ from those measured with conventional static DC curve traces. This is known as dispersion, and is caused by self-heating and traps during device operation. The RF characteristics of a device can be measured by applying fast pulses to the input and output terminals and sampling the output current . This method is crucial because it correctly measures the dynamic RF characteristics of a transistor in similar conditions to how the device would be used. This allows the data to be used for design purposes.
47 The IV analyzer that was used for this work was manufactured by Accent Optoelectronics. These analyzers are capable of measuring FETs, HEMTs, HBTs, and either NPN or PNP bipolar transistors. The analyzer has two ports, one for the input (base or gate) and one for the output (collector or drain) of the device. In a static IV setup, assuming a FET for example, the range and step size of Vgs must be set, in addition to the maximum drain current and drain voltage, instantaneous power limit, averaging and sweep rate. However, since static IV curves do not represent RF characteristics, pulsed IV measurements are necessary. The pulsed IV setup is similar to the static IV setup conditions except that there are some additional conditions that must be set. First of all, the quiescent bias point, such as Vgs and Vds (for a FET), must be set. This will be where the pulse is set. The Vds step size is not critical, and is set depending on how smooth the curves need to be. The pulse shape conditions allow the length (microseconds) and separation (milliseconds) of the pulses to be set. These settings can be critical to the effects of self-heating. 4.3 S-Parameter Measurements and Theory To measure the 2-port small-signal S-Parameters of the device illustrated in this chapter, an Anritsu Lightning Vector Network Analyzer (VNA) was used, along with a JMicro Technologies probe station , since the measurements are done on-wafer using two GGB Industries 150um pitch probes . The calibration was performed on a JMicro
48 Technologies Probe Point CM10 (PP CM10) calibration structure substrate , which enables a Short-Open-Load-Thru (SOLT) or a Thru-Reflect-Line (TRL) calibration . The TRL calibration moves the reference plane to the center of the thru standard, and generally offers more precise calibrations. For the pHEMT calibration, SOLT was used for a 2-port calibration on the PP CM10, using the calibration standard definitions obtained from JMicro Technologies. The S-Parameter frequency range was chosen to cover the fundamental frequency of 2.45 GHz and its second and third harmonic frequencies, 4.9 and 7.35 GHz, as displayed in Figure 4.1, below. The calibration routines for the other example device types are discussed in Appendix A. Figure 4.1: 1.75 to 8.75 GHz pHEMT S-Parameters using Lightning VNA
49 22 11 22 11 2 22 2 2 21 2 2 * 11 21 12 22 22 21 12 111 ) 1 ( * 1 ) 1 ( 1 1 S S S S S S G S S S S S S S SL s out in L L s in s t out L in s s s out L L in= = = = = = = + = + = Figure 4.1 shows S12 to be near zero, which means the pHEMT is (approximately) a unilateral transistor for these frequencies, as opposed to a bilateral transistor, where S12 0 . The conditions for a bilateral transistor with maximum transducer gain are given in Equations 4.1-4.4, and the bilateral transducer gain, Gt, is defined in Equation 4.5. For a unilateral transistor, Equations 4.1-4.4 are simplified (S12=0) and defined in Equations 4.6-4.9. (4.1) (4.2) (4.3) (4.4) (4.5) (4.6) (4.7) (4.8) (4.9) The unilateral transducer power gain is the ratio of the power delivered to the load to the available power from the source and can be broken down into 3 components: the source mismatch, the transistor gain and the output mismatch. These components are defined in Equations 4.10-4.12. The source gain component, Gs, represents the mismatch between the source and S11 of the transistor. The gain component, Go, is dependent upon the S21 gain of the transistor.
50 2 22 2 2 21 2 11 2 2 22 2 2 21 2 11 21 1 * 1 1 1 1 1 1L L s s TU L L L o s s sS S S G S G S G S G = = = = The load mismatch, GL, represents the output mismatch of the device. The overall unilateral transducer gain is denoted as GTU and is given in Equation 4.13. Put in terms of an S-Parameter measurement, Gs is the mismatch between the input port of the VNA and the input of the device. Likewise, GL is the mismatch between the device output and VNA output port. Go is the power gain of the transistor. The source and load mismatch circles can be plotted on a Smith Chart using Agilents Advanced Design System software. The values of s and L that produce a constant gain (Gs or GL) lie on a circle in the Smith Chart. (4.10) (4.11) (4.12) (4.13) The small-signal S-Parameters can be used to analyze the stability of a transistor at a particular frequency. Stability analysis of a transistor is very important to determine the passive source and load impedances that cause the device to see a negative resistance.
51 A unilateral transistors stability is characterized as unconditionally stable. Unconditional stability occurs when the magnitude of in and out are less than 1. Equations 4.14-4.17 summarize the reflection coefficient conditions necessary for unconditional stability. (4.14) (4.15) (4.16) (4.17) Through manipulation of equations 4.14-4.17, the unconditional stability can be determined by the transistor k-factor and The K-factor can further be simplified and expresses as Equation 4.19, but only holds if the magnitudes of S11 and S22 are less than unity. Another way to quantify unconditional stability is through the stability measure, B. These conditions are shown in Equations 4.18-4.21. (4.18) (4.19) (4.20) (4.21) 1 1 1 1 1 111 21 12 22 22 21 12 11< + = < + = < < s s out L L in L sS S S S S S S S 0 1 1 0 ) 1 )( 1 ( 1 12 2 22 2 11 21 12 22 11 2 22 2 11 2 2 22 2 11> + = < = > > + = S S B S S S S S S S S K
52 For a potentially unstable transistor, there are values of s and L (passive terminations) that produce in and out values greater than one. To find the values of these reflection coefficients, stability circles must be formed. Stability circles are circles for which the output and input reflection coefficients are equal to one. Once these circles are formed, examination of the center of the Smith Chart ( =0, Z=Zo) will reveal whether the stability region lies inside or outside of the stability circle. In other words, if the center of the Smith Chart has in (equal to S11) and out (equal to S22) values less than one, then the region containing this point is stable. Conversely if these values are greater than one, then the region is unstable. For a potentially unstable transistor, K and must be greater than 1. The input and output stability circles for the pHEMT are illustrated in Figure 4.2. The calculation of Equations 4.19 and 4.20 reveal that this transistor is unconditionally stable. In both the input and output planes, the center of the Smith Chart is stable and thus the inside of the stability circle is unstable. Figure 4.2: pHEMT Source (left) and Load (right) Stability Circles at 2.45 GHz
534.4 Source and Load Pull Measurement Theory and Validations Load Pull is a well-known measurement technique that is used to measure the power performance of a power amplifier/transistor vs. varying termination impedances. A typical (on-wafer) load pull setup is comprised of a fundamental source and load tuner, as well as bias tees, cables, probes and adapters as shown as
54 These losses restrict the tuning range that can be achieved on a typical Smith Chart for a fundamental tuner, and with greater losses at higher frequencies, prevent the harmonic tuners (2fo,3fo) from providing a reflection coefficient near =1 to the device terminals. Figure 4.4: Typical Second Harmonic Load Pull Setup A harmonic load pull system utilizes a triplexer that separates the fundamental path from the second and third harmonic frequency paths. The triplexer will be discussed in detail in Section 4.4. However, in the context of this section, the triplexer adds passive loss to the system on the load side of the device. Figures 4.5 and 4.6 shows typical fundamental and harmonic impedance spreads for an on-wafer measurement in this setup. The maximum reflection for the fundamental tuning in Figure 4.5 are approximately 0.9, while second harmonic tuning is limited to 0.8.
55 Figure 4.5: Fundamental Source and Load Impedance Spreads with System Losses Figure 4.6: Second Harmonic Load Tuner Impedance Spread with System Losses
56 System Operation A 2-tone load pull system operates by combining two continuous wave (CW) frequency signals, which are separated by a specific spacing frequency, usually anywhere between 10 kHz and 100 MHz. The output of each source is isolated and then combined using a 3-dB power combiner. After the power combiner, a preamplifier was used to boost the available power from the source for this example device. Therefore, another isolator is needed to ensure that the source tuner does not load tune the pre-amplifier. The output from the isolator is fed to a bias tee, which provides either the gate (FET) or base (BJT) bias of the device under test (DUT). The signal then passes to the source tuner, where a gain or efficiency boost can be obtained. For an on-wafer setup, the tuners are connected to an ideally low-loss probe assembly that provides the signal path to the drain (FET) or collector (BJT). An identical probe network, consisting of a probe, low loss cable and adapter, is used at the output of the device to connect to the DUT. The output signal connects to the triplexer, which has 3 emerging signal paths. The fundamental path in the triplexer has a bias tee that allows bias to feed through the triplexer . The output of the fundamental path of the triplexer is then attached to the load tuner. The output network also includes a directional coupler, which splits the signal between the spectrum analyzer and the power sensor. The carrier power level and intermodulation levels are measured with the spectrum analyzer and the power is measured with a power sensor, so that bilateral transducer gain, Gt, can be calculated.
57 For the harmonic paths, the signal passes through the appropriate triplexer ports to the harmonic tuner, where the phase of the harmonic termination is varied to observe the linearity improvement in the device. The fundamental source and load tuners as well as the second and third harmonic tuners are terminated in 50-ohms for calibration purposes. System Validation For such a complex setup, it is crucial to verify the power calibration used to perform the measurements, as well as the power measurements themselves. One method that has been developed to verify the validity of the system S-Parameters and calibration is the Delta-Gt calibration technique . The Delta-Gt procedure is an excellent way to check a system setup and to quantify the limit of error in a commercial load pull system. It also can serve as a sanity check in that once all the de-embedding S-Parameter files have been carefully quantified, the optimum transducer gain lies around the matching area that is predicted from the SParameters of the thru file. It is a built-in function for the Maury ATS software. Maury treats the transducer gain as a bilateral gain, but given unilateral transistor S-Parameters, the software can calculate the unilateral transducer gain, GTU.
58 Delta-Gt is calculated as the measured system bilateral transducer gain (Equation 4.5) minus the bilateral transducer gain of the device under test, seen from Equation 4.22. (4.22) In this equation, Gt is the system-measured bilateral transducer gain and Gt(s) is the bilateral gain predicted by the device S-Parameters. For this work, based on the experience and conversations with industry collaborators, a Delta-Gt of less than 1 dB was strived for. The Delta-Gt measurement is performed at a high power level, indicative of the power level used for the device measurements, such as the 1-dB compression power. The results are plotted against the phase of the terminations. The Delta-Gt measurement performed on the Probe Point CM10 calibration substrate used for pHEMT measurements is shown in Figure 4.7. Figure 4.7: Delta-Gt Measurement on Probe Point CM 10 Calibration Substrate ) ( s G G Gt t t =
59 Another system validation involves verifying small-signal VNA measurements with identical Maury ATS load pull system measurements. There are two measurements that can be verified: the 50-ohm power sweep and low-power tuning measurement. The 50-ohm VNA power sweep measurement is performed by using an Anritsu Scorpion, which has a built-in gain compression application . For good resolution, 0.1 dB steps are used with a 25 dB overall dynamic power range. A power calibration is done with an Anritsu power meter at the input reference plane. After the power calibration is done, a response cal is done on a thru, as required by the Anritsu Scorpion. Next, the device is connected, biased and the measurement is taken. The Pin vs. Pout comparisons are shown in Figure 4.8. Figure 4.8: pHEMT Class AB 50-ohm Power Sweep Comparisons b/w Maury and VNA
60 For the power sweep using the load pull system, the tuners are all left at their 50ohm impedances. Since a complete system power calibration has been performed, the device can be biased up and measured for Pout, Gt, PAE, and TOI as well as other power parameters. AM-AM information can be seen from the transducer gain data versus power, but there is no AM-PM information recorded in this configuration. The low-power tuning measurements can be used to compare the conjugate matching conditions at the source and load. The conjugate matching conditions are approximated as s=S11* and L=S22*, but this is an assumption only. It is based off of the condition that S12 is approximately (but not exactly) zero. Under these conditions, the source and load gain circles can be predicted by Equations 4.10 and 4.12. Since the major problem in a load pull system is phase loss, it is important to verify that the conjugate match is correlated to the conjugate match predicted by device S-Parameters. In cases where the available tuning range limits the ability to closely approximate the match, phase correlation between the two measurements is observed. During conjugate source matching, the load is left at 50-ohms and the source is tuned for gain. Then the load is tuned for the conjugate gain match with the source at 50ohms. The conjugate matching results for the pHEMT are shown in Figure 4.9 and 4.10 and summarized in Table 4.1.
61 The conjugate match and input mismatch circles (given by Equation 4.10) predicted by the S-Parameters are shown on the left, while the low-power tuning results, with the load set to 50 ohms, is shown on the right. The source match is limited by the available tuning range in the load pull system, but the phase shows a good correlation. The comparison of load mismatch circles (given by Equation 4.12) to low-power load tuning results, with the source set to 50 ohms, are shown to agree well in Figure 4.10. Figure 4.9: Conjugate Source Matching Comparisons Figure 4.10: Conjugate Load Matching Comparisons
62 Table 4.1: pHEMT Conjugate Source and Load Matching Comparison @ 2.45 GHz VNA Meas., shown in ADS Maury ATS Measurements Source Conjugate Match s=0.923<160.26 s=0.82<159.46 Load Conjugate Match L=0.496<161.28 L=0.479<160.15 With gain compression and low power tuning results indicating good correlations between the VNA and load pull measurement system, we can proceed to large-signal load and source pull with more confidence. In using the Maury ATS software, it is important to discuss the calculation of some key parameters for the characterization of the transistors used in this work. PAE and drain efficiency ( ) calculations, given in Equations 2.1 and 2.2, are the same in the ATS software, as is the bilateral transducer gain calculation, given in Equation 4.5. The Ip3 (TOI and Ip3 can be used interchangeably) and linearity figure of merit, Lip3, calculations have not been discussed and will be revealed here. However, before delving into the equations, the treatment of TOI in this work must be mentioned. TOI in theory is an extrapolated curve based on the 3:1 relationship between a carrier and third-order intermodulation term (hence the 3:1 slope). At the 1-dB compression point, where all devices were measured and device models were simulated in this thesis, TOI becomes more of a calculated parameter than measured value. At this input level, the 3:1 relationship no longer exists. Therefore, the validity of TOI in the compression region is unclear. For this reason, this work will also examine the carrier,
63 IM3 and C/I parameters, because they are absolute levels and are valid at the 1-dB compression power. The carrier signal is the power of one of the two input tones. It is 3 dB lower than the fundamental output power since the power is split between the two tones measured on the spectrum analyzer. The output power is measured as a 1-tone signal with the output power meter from which Gt, PAE and are measured. IM3 is the third order intermodulation product on the same sideband as the fundamental signal. The C/I or carrier to intermodulation level, is the difference between these two parameters. Expressions for calculated TOI and Lip3 are given in Equations 4.23 and 4.24. (4.23) (4.24) (4.25) 4.5 Triplexer Characteristics A triplexer is a 4-port device that is used to separate the fundamental frequency path from the second and third harmonic frequency paths so that each frequency can be independently tuned. Each two-port path of the device was characterized to form a 4-port triplexer matrix. The Maury load pull software uses 2-port S-Parameters from three transmission paths, common-fo, common-2fo and common-3fo, to separate the frequencies for tuning. The transmission responses for these paths are shown in Figure 4.11 in terms of insertion loss (IL) and return loss (RL) for all 3 signal paths. ) ( 3 ) ( ) ( / 3 2 dBm IM dBm Carrier dBc I C Pdc TOI Lip I C C TOI Calculated = = + =
64 Figure 4.11: Insertion Loss for each Path of 2.45 GHz Maury Microwave Triplexer Table 4.2: 2.45 GHz Triplexer Return Loss and Insertion Loss Measurement Fundamental fo 2nd Harmonic freq. 3rd Harmonic freq. Insertion Loss (dB) 0.235 0.248 0.196 Return Loss (dB) 19.77 25.9 14.97 A very important issue to consider when using a triplexer in a harmonic load pull system is the influence that tuning the harmonic frequencies will have on the fundamental tuner impedance and vice versa. This tuning independency is crucial to the performance of a harmonic load pull system and was investigated in our research group .
65 Tuner repeatability was tested by monitoring the variability of a known fundamental load tuner state over time as measured on a VNA. This was done by moving the fundamental tuner to the same state several times and measuring the in of the device at the triplexer common port, which is where the calibration reference plane was established. The tuner repeatability for this study was measured to be about -60 dB. The tuning independence was tested by setting tuner states at the fundamental and third harmonic frequencies and monitoring their deviation as the second harmonic tuner was varied over many states, from 0 to 360 degrees. This was defined as deviation, in dB. The results were shown and are presented below in Figure 4.12. From the figure, movement in the fundamental state was indistinguishable from measurement repeatability. A theoretical prediction also shown indicates the expected deviations in fundamental tuning due to harmonic tuning to be well below measurement repeatability for the triplexer used. Figure 4.12: Tuning Independency Results 
66 Additional studies were performed in ADS to assess the triplexer port isolation and rejection specifications on the tuning independency. This study revealed that a compromise between the isolation and rejection specs could lead to a better triplexer design and that a sacrifice of both parameters leads to degraded tuning independency. From Figure 4.13, isolations under 30 dB cause the max deviation, the maximum amount of movement seen in a set tuner impedance state while load pull is emulated with another tuner, to fall short of the measurement repeatability, 60 dB. The USF 2.45 GHz triplexer under study has isolation of 50 dB and rejection of 59 dB, shown by arrow in Figure 4.13. Figure 4.13: Deviation of Tuner States vs. Degradation in Isolation (MAX Deviation)  USF Triplexer
674.6 Chapter Summary This chapter has detailed the theory behind small-signal S-Parameters and their use in deriving mismatch circles and stability circles for the transistor. It was shown that for a unilateral transistor, the source and load gain matches are dependent on the conjugate of the input and output reflection coefficients of the device. Also, the conditions for unconditional stability and potential instability were examined and methods to identify the stability regions for potentially unstable transistors were established. The source and load pull theory detailed a fundamental and harmonic load pull setup and identified the major contributions of loss to the system and how the losses affect the validity of the results. A calibration validation method, Delta-Gt was introduced and illustrated to be useful in identifying calibration errors in a system. Two methods of measurement verification, power sweeps and conjugate match comparisons were discussed and illustrated using sample data from a GaAs pHEMT. Finally, the characterization of a triplexer was discussed in terms of isolation, rejection, tuner repeatability and tuning independency, which is crucial to a harmonic load pull setup. It was shown that there is a great deal of independency between the tuners and that the tuner repeatability exceeded specifications. A compromise between isolation and rejection could yield an improved triplexer design, which could improve the tunable range, especially at harmonic frequency tuners.
68 CHAPTER 5 MEASURED AND SIMULATED IV AND VNA RESULTS 5.1 Introduction For RF design engineers, who seek to effectively use non-linear simulations, the need to correlate the performance of the power amplifier to a nonlinear transistor model is crucial. The PA is the largest source of distortion in a wireless communications system and is extremely challenging to model. The development of a nonlinear transistor model is based upon IV characteristics and multi-bias small-signal S-Parameters. Power sweep characterizations are often used for model validations. This chapter explores simulations of the available transistor models against device measurements for pulsed IV, SParameters and 50-ohm power sweeps, made by the author. These comparisons are carried out for the GaAs pHEMT, InGaP HBT and GaAs JFET, mentioned in Chapter 3.
695.2 Setup and Basic Simulations: EEHEMT Model for pHEMT 5.2.1 IV and S-Parameter Simulations and Measurements Figure 5.1: Simulated (dashed) vs. Measured (solid) IV Curves (Pulse Conditions: Vds=8 V, Vgs=-0.8 V, Ids=162 mA, NDU=0.081) Figure 5.1, above, shows the comparison between the simulations and pulsed IV measurements. As discussed in Chapter 4, measured pulsed IV data was performed using an Accent Optoelectronics DIVA 265. To generate the IV curves, a Class A quiescent point was set and the gate voltage was varied from pinchoff (-1.4V) to saturation (0V).
70 There is a drain current discrepancy between the simulated and measured DCIV curves of about 40 mA of the saturated drain current (677 mA). This is reasonable because the model was based upon several devices and this is within expected device variations. The comparisons between the simulated and measured IV measurements are summarized in Table 5.1 for a Class A and AB quiescent bias point. Note that Vgs and Ids are not independent variables, so in specifying Vgs to be the same some differences are seen in simulated vs. m easured quiescent current. A normalized difference unit (NDU) can be calculated as the difference between 2 IV curves at a common quiescent bias point. The NDU for these particular IV curves was calculated as 0.081. The NDU function was derived by Charles Baylis during his masters thesis work at USF : (5.1) Table 5.1: Summary of pHEMT Quiescent Bias Points Quiescent Bias Conditions Measured Simulated Class A Vds=8V, Vgs=-0.6V, Ids=282 mA Vds=8V, Vgs=-0.5V, Ids=282 mA Class AB Vds=8V, Vgs=-0.8V, Ids=162 mA Vds=8V, Vgs=-0.87V, Ids=162 mA 11 2 1 == DSmean N i i DS i DSI I I N NDU
71 The Class AB quiescent bias point will be used for the comparisons detailed in the rest of this section. This bias point was used for the tuning experiments and simulations, shown in Figure 5.2, with the measurements covering the fundamental frequency, as well as the second and third harmonics. Table 5.2 summarizes the S-Parameters comparison. Figure 5.2: Comparison of pHEMT Class AB S-Parameters from 1.75 to 8.75 GHz Table 5.2: Measured and Modeled pHEMT Class AB S-Parameters at 2.45 GHz SP comparison S(1,1) S(1,2) S(2,1) S(2,2) Measured 0.923<-160.260.03<5.67 5.18<87.45 0.496<-161.28 Modeled 0.913<-160.200.03<5.202 5.92<84.44 0.445<-156.6 freq (1.750GHz to 8.750GHz)S(1,1) S(3,3) freq (1.750GHz to 8.750GHz)S(2,2) S(4,4) -0.03-0.02-0.010.000.010.020.03 -0.040.04 freq (1.750GHz to 8.750GHz)S(1,2) S(3,4) -8-6-4-202468 -1010 freq (1.750GHz to 8.750GHz)S(2,1) S(4,3)
72 Table 5.2 indicates good agreement with the Class AB S-Parameters at 2.45 GHz, indicating that the model provides a good S-Parameter fit. All phases are within five degrees and the magnitude correlation is very good. The validity of the S-Parameters is also supported by the mismatch and low power tuning comparison in Chapter 4. 5.2.2 50-ohm Power Sweep Simulations and Measurements Using a Class AB bias at 2.45 GHz, a 50-ohm power sweep is performed using the Maury ATS system with 50tuners. The simulations were also done with all tuners set to 50 ohms. Figure 5.3 displays the comparison for this measurement at 2.45 GHz. Linearity and Power vs. Pin 0 5 10 15 20 25 30 35 40 45 -10-5051015 Input Power, dBm TOI, dBm (dBm) 0 5 10 15 20 25 30Pout, dBm Measured TOI Modeled TOI Measured Pout Modeled Pout Figure 5.3: Comparison of Class AB 50-ohm pHEMT Power Sweeps at 2.45 GHz
73 The model is optimistic for lower input powers, seen by the 5 dB discrepancy in TOI at -10 dBm. However, the simulated and measured TOI converge near the P1dB of the device, which is the power that will be used for the tuning simulations/measurements. This could be attributed in part to device variations as the modeled and measured device were likely different. Output power tracks well over the entire input power range (< 1 dB), indicating that the measured gain is in good agreement with the model. A summary is shown in Table 5.3. Table 5.3: pHEMT Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz Gain Pout PAE TOI Lip3 Measured @ 13 dBm 13.3926.39 27.73 32.64 1.23 Modeled @ 13 dBm 13.5326.53 29.40 33.47 1.52
745.3 Setup and Basic Simulations: Gummel Poon Model for HBT 5.3.1 IV and S-Parameter Simulations and Measurements Figure 5.4: Simulated (dashed) vs. Measured (solid) IV Curves (Pulse Conditions: Vce=3.3 V, Ibb=200 uA, Icc=20 mA, NDU=0.184) Figure 5.4, above, shows the simulated (dashed lines) vs. measured (solid lines) IV curves for the InGaP HBT. The measured IV curves were generated with a Class AB quiescent bias point by varying the input current from 100uA to 1mA. The model IV curves predict more dramatic nonlinear effects than the measurements indicate. These nonlinearities cause the discrepancy between the output currents seen in Figure 5.4.
75 Table 5.4: Summary of HBT Quiescent Bias Points Quiescent Bias Conditions Measured Simulated Class A Vc=3.3V, Ib=500uA, Ic=42 mA Vc=3.3V, Ib=400uA, Ic=42 mA Class AB Vc=3.3V, Ib=250uA, Ic=19 mA Vc=3.3V, Ib=150uA, Ic=19 mA The Class AB S-Parameters are representative of a 5 kA/cm2 current density with an emitter area of 405 um2, which correlates to a collector current of 20 mA. The Class AB quiescent bias was used throughout the course of the measurements and simulations discussed in this work. The S-Parameter results are shown in Figure 5.5. Figure 5.5: Comparison of HBT Class AB S-Parameters from 1.75 to 15.75 GHz
76 The S-Parameters measurements compare very well with the simulations at the fundamental frequency of 2.45 GHz as seen in Table 5.5, where the phases of the 2-port S-Parameters are all within 3 degrees of the simulated model results. A conjugate source and load comparison between the S-Parameter mismatch circles and a low-power tune were done to verify the integrity of the results. The S-Parameter mismatch and low-power tuning comparisons are shown in Appendix A. Table 5.5: Measured and Modeled Class AB HBT S-Parameters at 2.45 GHz SP comparison S(1,1) S(1,2) S(2,1) S(2,2) Measured 0.848<-169.01 0.041<11.92 5.82<90.73 0.319<-140.50 Modeled 0.858<-170.06 0.037<10.52 5.23<90.17 0.320<-143.57 5.3.2 50-ohm Power Sweep Simulations and Measurements The Class AB 50-ohm power sweep comparison shown in Figure 5.6 indicates an excellent correlation between the measured and modeled output power, indicating that the gain is also predicted well over the input power range. TOI is decently predicted by the model at lower input levels within 2 dB, converging with the measured TOI at the 1-dB compression power of the device, -2 dBm. The results at P1dB are shown in Table 5.6.
77 Figure 5.6: Comparison of Class AB 50-ohm HBT Power Sweeps at 2.45 GHz Table 5.6: HBT Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz Gain Pout PAE TOI Lip3 Measured @ -2 dBm 13.49 11.49 20.63 21.47 2.13 Modeled @ -2 dBm 13.47 11.47 20.17 33.51 33.82
785.4 Setup and Basic Simulations: TOM Model for HJFET 5.4.1 IV and S-Parameter Simulations and Measurements Figure 5.7: Simulated (dashed) vs. Measured (solid) IV Curves (Pulse Conditions: Vds=3 V, Vgs=-0.5 V, Ids=17 mA, NDU=0.1) The comparisons between the simulated and measured IV results are shown in Figure 5.7 and are summarized in Table 5.7 for Class A and Class AB quiescent bias points. The measured curves were generated by setting a Class AB quiescent bias point and varying the gate voltage from pinch off to saturation (Idss). It should be noted that the IV curves predicted by the model were most likely static curves, since the model was extracted several years ago.
79 Table 5.7: Summary of HJFET Quiescent Bias Points Quiescent Bias Conditions Measured Simulated Class A Vd=3 V, Vg=-0.3 V, Id=35 mA Vd=3 V, Vg=-0.35 V, Id=35 mA Class AB Vd=3 V, Vg=-0.5 V, Id=13 mA Vd=3 V, Vg=-0.54 V, Id=13 mA A Class AB quiescent bias was used to compare the small-signal S-Parameters. The model was simulated at the bias indicated in Table 5.7 and the comparison with measured results is shown in Figure 5.8, below. Table 5.9 summarizes the comparisons. Figure 5.8: Comparison of HJFET Class AB S-Parameters from 1.75 to 5.25 GHz
80 Table 5.8: Measured and Modeled HJFET Class AB S-Parameters at 2.45 GHz SP comparison S(1,1) S(1,2) S(2,1) S(2,2) Measured 0.536<92.53 0.069<47.05 5.53<77.53 0.523<48.81 Modeled 0.612<78.95 0.069<57.02 5.44<109.40 0.628<25.31 As Table 5.8 indicates, there is quite a bit of phase and even magnitude deviation between the measured and modeled Class AB S-Parameters. However, a conjugate source and load comparison between the S-Parameter mismatch circles and a low-power tune showed the measured S-Parameters to be acceptable. The S-Parameter mismatch and low-power tuning comparison is shown in Appendix A. 5.4.2 50-ohm Power Sweep Simulations and Measurements The Class AB 50-ohm power sweep comparisons are shown in Figure 5.11. There is decent agreement between the simulated and measured output power and gain. However, the TOI prediction by the model is not consistent with the measured TOI at all powers. The measured and simulated results are summarized in Table 5.10 and show a 4 dB maximum deviation in the TOI curves.
81 Figure 5.9: Comparison of Class AB 50-ohm HJFET Power Sweeps at 2.45 GHz Table 5.9: HJFET Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz Gain Pout PAE TOI Lip3 Measured @ -1 dBm 13.99 dBm 12.99 dBm 29.39 % 22.0 dBm 2.48 Modeled @ -1 dBm 13.51 dBm 12.51 dBm 23.43 % 23.4 dBm 3.01 5.5 Chapter Summary This chapter has discussed the comparisons between the measured and simulated pulsed IV, small-signal S-Parameters and 50-ohm power sweeps, which are the basis of the nonlinear transistor models discussed in Chapter 3.
82 IV data was predicted well for all 3 nonlinear transistor models. The only major discrepancy occurred for the InGaP HBT, where the nonlinearities from the nonlinear model, such as Cbe, were seen in the model IV simulations. These nonlinear characteristics were not prevalent in the measurements, which showed a near constant current along the entire output voltage range. S-Parameters for the GaAs pHEMT and InGaP HBT were predicted well by the model at 2.45 GHz, which is the fundamental frequency of operation for this work. The GaAs JFET S-Parameters measurements showed discrepancies with the model. However, the S-Parameters were verified with a low-power tune, seen in Appendix A. The simulated and measured power sweeps for all three devices show good correlation with transducer gain, RF output power and power added efficiency. TOI prediction (for all 3 devices) at lower input powers was moderate. However, as the device approached the 1-dB compression power, the measured and simulated results converge and give a much better correlation of the data. The power sweep simulation results for the TOM model, however, predicted TOI data that was inconsistent with the other models.
83 CHAPTER 6 MEASURED AND SIMULATED LOAD PULL RESULTS 6.1 Introduction This chapter continues with the theme from Chapter 5, discussing the measured and simulated results, but now for the fundamental and harmonic tuning performed on the example GaAs pHEMT, InGaP HBT and GaAs JFET devices. The objective of the tuning experiments was to determine the influence of second harmonic load tuning on the linearity of the device. Also, the device non-linear model will be tested to determine to what extent it predicts the measured second harmonic tuning and linearity performance of the different devices. 6.2 pHEMT Measured/Simulated Comparison This section will discuss the tuning comparisons between the measurements on the GaAs pHEMT and the ADS EEHEMT model created by Modelithics, Inc. Fundamental and second harmonic load tuning measurements will be compared in this section. The purpose of the measurements was to optimize linearity.
84 Referring to Chapter 4, TOI is a calculated value, based on the carrier and third order intermodulation (IM3) products. Since the measurement and simulation results presented in this thesis were performed at the 1-dB compression power of the devices, the representation of TOI isnt necessarily complete. However, since the intermodulation products are absolute and valid at all power levels, they can be represented with confidence. 6.2.1 Fundamental Load Pull For the purposes of this device, the source was left at 50-ohms while the output tuners were optimized for TOI and linearity (Lip3). This was done for the purposes of monitoring the output nonlinear effects of the pHEMT. It is also done to prevent the device from potentially oscillating. The fundamental load pull measurements were performed at the 1-dB compression power of the device, 13 dBm, and the simulations were performed to mimic the same input power to get a valid comparison. The fundamental load pull comparisons are seen in Figure 6.1.
85 Figure 6.1: pHEMT Fundamental TOI Load Tuning Comparison @ Pin=13 dBm The fundamental frequency load pull comparison shows excellent agreement between the simulations and the measurements. The simulated optimum reflection coefficient (for TOI tuning) is predicted within 0.2 degrees by the measurements. The gain and output power are predicted within 0.2 dB and the TOI within 0.61 dB, an acceptable agreement. The PAE is predicted within 2.5% which is also reasonable. The measured linearity figure of merit was taken from the raw TOI and Pdc data to be 2.19, while the simulations predicted an Lip3 of 1.92. These results are shown in Table 6.1. Table 6.1: Summary of pHEMT Fundamental Load Pull Comparisons Pout (dBm) Drain Eff ( ) (%) Lip3 (unitless) IM3 (dBc) I3 (dBm) TOI (dBm) Simulations 0.486<154.08 27.443 32.97 1.7 -20.3 4.13 34.577 Measurement 0.43<153.91 27.27 35.34 2.19 -22.42 1.57 35.19 | | 0.163 2.37 0.49 2.12 2.56 0.613
866.2.2 Second Harmonic Load Pull With the fundamental load tuner set to the optimum reflection coefficient for TOI tuning, as seen in Figure 6.1, the second harmonic tuner was tuned and simulated to optimize the TOI and linearity of the device. These simulations and measurements were performed at 13 dBm, the measured 1-dB compression power of the pHEMT device. The second harmonic tuner was optimized in a different manner than the fundamental tuner. Instead of presenting the device with varying magnitude and phase terminations, the device is presented with an (ideally) constant maximum magnitude termination with a phase that is varying between 0 and 360 degrees. This phase variation allows the device to be presented with an op en (0 degrees) and short (180 degrees) circuit in order to determine which termination has the most influence on the linearity enhancement of the device. The comparison between the simulated and measured second harmonic tuning is shown in Figure 6.2 for TOI, followed by the comparison of C/I and IM3 in Figure 6.3. The power and linearity parameters are summarized in Table 6.2.
87 Figure 6.2: pHEMT Second Harmonic Load Tuning Comparison @ Pin=13 dBm Figure 6.3: Comparison of C/I and IM3 vs. Second Harmonic Phase @ Pin=13 dBm
88 Table 6.2: Comparison of pHEMT Class AB Second Harmonic Tuning at Pin=13 dBm Pout (dBm) TOI (dBm) Lip3 (unitless) IM3 (dBc) I3 (dBm) (%) Simulations 0.8<10 27.53 34.952 2.09 20.867 3.65 33.73 Measurements 0.786<4.77 27.33 35.483 2.355 23 0.983 36.04 | | 0.2 0.531 0.265 2.13 2.67 2.31 The encouraging aspect of the results is that the model predicts a similar trait for TOI. There is very good correlation between Pout, Gt, and PAE between the simulated and measured results. Figure 6.3 reveals a good correlation between measured and simulated C/I ratio, with roughly 2 dB of discrepancy, and IM3 is predicted within 3 dB. Another way to view the data is to look at the third order IMD levels in dBc (IM3), as well as the third order power levels (I3) versus the second harmonic tuning phase. The presentation of this data is more useful because TOI is an extrapolated value and theoretically is never achieved due to the compression characteristics of the device. In addition, it is interesting to explore the variation of the tuning performance as the maximum reflection coefficient at the second harmonic tuner is varied. This gives an indication of how the linearity is affected if L2fo=1 was presented to the device. Using the templates presented in Appendix B, the maximum reflection coefficient in the simulation was varied from 0.2 to 1 in steps of 0.2, while the phase was being swept from 0 to 360 degrees in steps of 5 degrees. The simulated results for the third order IMD, I3 power and carrier power level versus the magnitude of the second harmonic reflection
89 coefficient are shown in Figures 6.4-6.6. Drain efficiency is similarly plotted in Figure 6.7, to observe the efficiency performance under second harmonic loading conditions, independent of the RF drive level. Figure 6.4: C/I (dBc) vs. Second Harmonic Tuning Simulations for pHEMT
90 Figure 6.5: IM3 (dBm) vs. Second Harmonic Tuning Simulations for pHEMT Figure 6.6: Carrier vs. Second Harmonic Tuning Simulations for pHEMT
91 Figure 6.7: Drain Efficiency vs. Second Harmonic Simulations for pHEMT These plots reveal that the third order power levels increase by nearly 1 dB if a termination is presented near a short circuit at the periphery of the Smith Chart. This translates to a 1 dB reduction in the IM3 levels and about a 0.2 dB decrease in carrier power (and thus output power), as well as a 1% degradation in the drain efficiency. These results are referenced to L2fo=0.8, which is the maximum achievable reflection coefficient on the test bench. 6.3 HBT Measured/Simulated Comparison This section will discuss and compare the simulated and measured fundamental and second harmonic load tuning results for the InGaP HBT. This device was biased in Class AB mode and was operated at the 1-dB compression power of the device.
926.3.1 Fundamental Load Pull The fundamental load tuner was optimized for power and efficiency for the HBT. There is very good agreement between the optimum reflection coefficients for the measurements and simulation, on the order of 0.05 magnitude and 5 degrees phase angle. The measured PAE was 2% lower than the model, while the output power and gain followed the model within 0.3 dB. TOI, however, was not predicted as well. Table 6.3 summarizes the results. Figure 6.8: HBT Fundamental TOI Load Tuning Comparison @ Pin= -2 dBm Table 6.3: Summary of HBT Fundamental Load Pull Comparisons Pout (dBm) Collector Efficiency ( %) Lip3 (unitless) IM3 (dBc) I3 (dBm) TOI (dBm) Simulations 0.212<90 11.83 23.1 29.678 -46.35 -37.52 32.95 Measurement 0.27<84.2 12.098 25.1 2.355 -26.92 -18.33 22.21 | | 0.27 2% 27.323 19.43 19.2 10.74
936.3.2 Second Harmonic Load Pull The comparison of the second harmonic load tuning measurements and simulations of TOI and PAE is shown in Figure 6.9 and summarized in Table 6.4. Figure 6.9: HBT Second Harmonic Load Tuning Comparison @ Pin= -2 dBm The comparisons show that the model does not predict TOI decently and the model also isnt able to predict the effects of second harmonic tuning either, as TOI has been severely degraded.
94 Table 6.4: Comparison of HBT Class AB Second Harmonic Tuning at Pin= -2 dBm Pout (dBm) TOI (dBm) Lip3 (unitless) IM3 (dBc) I3 (dBm) (%) Simulations 0.8<110 -3.13 10.024 0.147 -32.33 -38.33 0.711 Measurements 0.8<275 12.44 22.66 2.865 -27.17 -18.34 27.2 | | 15.6 12.63 2.72 5.16 20 26.49 6.4 HJFET Measured/Simulated Comparison 6.4.1 Fundamental Load Pull The fundamental load pull for the JFET was simulated and measured for TOI. The measured and simulated optimum reflection coefficients for TOI tuning were near the 50ohm impedance states of the load tuners. Figure 6.10 illustrates this effect. Figure 6.10: HJFET Fundamental TOI Load Tuning Comparison @ Pin= -1 dBm
95 The simulated and measured TOI and Lip3 compare moderately well, with measured TOI over 1 dB lower than the modeled TOI. The Lip3 discrepancy is directly related to the difference in TOI results. The simulated IM3 products are 3 dB lower than the measured IM3 products. The power and linearity results are summarized in Table 6.5. Table 6.5: Summary of HJFET Fundamental Load Pull Comparisons Pout (dBm) Drain Efficiency ( %) Lip3 (unitless) IM3 (dBc) I3 (dBm) TOI (dBm) Simulations 0.106<90 13.104 26.31 3.094 -27.5 -17.4 23.81 Measurement 0.019<-103.2 13.054 31.4 2.71 -25 -15.18 22.402 | | 0.05 5.1 0.384 2.5 2.22 1.41 6.4.2 Second Harmonic Load Pull Utilizing a fundamental load tuner optimized for TOI, which results in a simulated and measured reflection coefficient near the 50-ohm impedance state of the fundamental tuner, the second harmonic was optimized for TOI. The comparisons between the simulated and measured results are shown in Figure 6.11. The gain, power, and TOI show excellent correlation, with the measurements and simulations within 1 dB of each other. Similarly, Lip3 is within 0.5 (unitless) of the simulation results. The measured PAE is higher than simulated PAE by about 5%. However, it is encouraging that the model shows the right trend. The results are summarized in Table 6.6.
96 Figure 6.11: HJFET Second Harmonic Load Tuning Comparison @ Pin= -1 dBm Table 6.6: Comparison of HJFET Class AB Second Harmonic Tuning at Pin= -1 dBm Pout (dBm) TOI (dBm) Lip3 (unitless) IM3 (dBc) I3 (dBm) (%) Simulations 0.8<-70 13.247 24.68 3.803 -28.96 -18.68 27.33 Measurements 0.8<-14.4 13.25 23.31 3.41 -26.12 -16.68 33.64 | | .003 1.37 0.393 2.84 2.0 6.3 6.5 Chapter Summary This chapter has provided a comparison between the measured and simulated results for large-signal fundamental and second harmonic load pull tuning on a GaAs pHEMT, GaAs JFET and InGaP HBT, in order to improve the overall linearity in the
97 device. In comparing the simulations and measurements, the degree to which the models predict TOI under second harmonic load tuning is monitored. In all cases, there is qualitative, if not quantitative, agreement with the observed trends. The GaAs pHEMT comparisons revealed an excellent correlation between the simulated and measured fundamental load tuning experiments, for power and linearity. The model prediction for the second harmonic load tuning results was precise, with a 0.4 dB of improvement in TOI and an improvement of 0.2 in Lip3, near an open circuit. The InGaP HBT provided good correlations between output power, gain and PAE, for the simulated and measured fundamental load pull experiments. However, the linearity of the device is not predicted well by simulated results. This is likely due to limitations with the nonlinear Gummel-Poon model, which is becoming supplanted by more advanced non-linear models . Finally, the JFET exhibits decent accuracy between the measured/simulated power, gain, efficiency and linearity. The second harmonic tuning simulations predicted a 0.7 dB improvement in TOI while the measurements predicted about 0.9 dB. The correlation of the simulated and measured TOI under second harmonic load tuning conditions is within 1 dB, and Lip3 is predicted within 0.4 (unitless). Power and gain are predicted within 0.3 dB, while PAE is only accurate within 5%. The measured third order intermodulation terms (IM3) are predicted within 3 dB of the simulated IM3 terms, leading to a measured TOI that is within 1 dB of the simulated results.
98 CHAPTER 7 CONCLUSIONS AND RECOMMENDATIONS 7.1 Conclusions In order to realize the full potential of an amplifier, it is necessary to properly terminate the output harmonic frequencies of the device. This thesis introduces a harmonic load pull system that is characterized and employed in order to investigate the effects of harmonic loading conditions on linearity performance of three different device technologies, GaAs pHEMT, GaAs HJFET and InGaP HBT. To gain confidence in the proper calibration of a harmonic load pull system, the components of the system must be systematically verified. This is crucial due to the many passive components in the system. Several techniques were identified and performed to validate the system calibration. Delta-Gt was one technique that helps to identify sources of error in a load pull system. Upon use and study of this technique, it has been established that these tests would ideally be run at all gammas for all tuners. Once Delta-Gt was verified, 50-ohm gain compression measurements were taken using both a VNA and the Maury ATS Load Pull setup. Correlation between power parameters showed that the system power calibration was done reasonably well. Once
99 this correlation has been established, small-signal tuning measurements were compared to load and source mismatch circles to verify the conjugate source and load matches predicted by S-Parameters. Externally supplied non-linear device models were used for each example device in order to access the level to which each predicts second harmonic load pull linearity performance. The models varied in their ability to predict measured IV curves and small signal S-Parameters. With one exception, the models were limited in their ability to predict second harmonic linearity performance. The model for the pHEMT device did a reasonable job predicting the 2nd harmonic behavior of the device and it was also observed that it also had the best overall consistency in predicting IV, S-Parameters and fundamental tuning behavior. This model was then used for some further exploration that tested harmonic tuning in various ways that were easier to do in the simulator than on the test bench (e.g. due to tuner and triplexer losses). The measurements detailed in this thesis indicate that the level of second harmonic linearity enhancement or degradation is dependent upon several factors: device technology, RF drive level, the magnitude of second harmonic reflection coefficient and quiescent bias settings. 7.2 Recommendations There are several recommendations for future work in this project. First of all, we have shown ways to validate the fundamental tuning results and ways to validate tuning independency of the harmonic system, but not a way to validate the calibration or
100 measurement of the second harmonic path. There is a method that the calibration can be verified, by extending the Delta-Gt calibration technique to the second harmonic path. To begin this process, the fundamental tuner must be removed and replaced by a 50-ohm termination at the fundamental port of the triplexer. The power meter is then moved to the output of the 2fo tuner. Any source tuner in the system must be characterized at the second harmonic frequency. In the software, the only file for the triplexer must be for the common-2fo port so that it sees this path as a fundamental path. The input signal will be the second harmonic, which for this study is 4.9 GHz. A similar arrangement can be done if a calibration validation is needed for the third harmonic path. The system could also be extended to work on the third harmonic tuning of the device output. This work has concentrated on the second harmonic terminations of a transistor, since it is the closest frequency component (other than IM products) to the fundamental carrier signal. The theory has not been established for the third harmonic, as there is still much research on the topic of second harmonic terminations, as seen in this thesis. However, from a measurement standpoint, it would be interesting to see if additional linearity or efficiency enhancement could be gained by optimizing the fundamental, second harmonic and third harmonic load tuners. This is especially true for Class F device, which operates on the utilization of the third harmonic resonator.
101 Another interesting test would be to extend the system to source tuning, essentially linearizing the device before the distortion generated at the input of the device is amplified. It has been shown in Spirito  that source tuning can have similar effects on device performance as harmonic load pull. The measurements detailed in this thesis were for a 1 dB compressed Class AB transistor. However, upon varying the bias point and backing off or increasing power, conclusions about the device performance under these loading conditions will in general be altered. It would, therefore, also be interesting to monitor the effects that harmonic terminations have on varying amplifier biasing levels, especially Class C, D, E and F, which are all extremely nonlinear. Finally, a nice way to round out the system would be to incorporate the University of South Floridas Vector Signal Analyzer VSA89600 into the harmonic load tuning system to measure communication system measures like Adjacent Channel Power Ratio (ACPR) and Error Vector Magnitude (EVM) under varying source and load harmonic conditions.
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107Appendix A: Additional Measurement Validation Results A.1 Introduction In Chapter 4, the validation of the load pull system was presented through smallsignal load and conjugate match comparisons and 50-ohm power sweep comparisons. These comparisons were illustrated only for an example GaAs pHEMT. This appendix illustrates these same measurements, taken in different measurement sessions, for an InGaP HBT and GaAs HJFET, respectively. These measurements are done at 2.45 GHz. The S-Parameter calibrations for all three device measurements are listed in Table A.1. Table A.1: S-Parameter Calibrations used in this Thesis Device Calibration Type InGaP HBT SOLT, using CS-5 substrate GaAs HJFET TRL, using FR4 59 mil cal. board GaAs pHEMT SOLT, using PP CM10 cal. Substrate A.2 HBT Source and Load Conjugate Match The small-signal conjugate matches predicted by the S-Parameters for the HBT were compared to a low-power tune in the load pull system so that the integrity of the system could be verified. Figure A.1 shows the conjugate source match verification and Figure A.2 shows the conjugate load match verification measurements.
108 Appendix A: (Continued) Figure A.1: Conjugate Source Match of InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA) Figure A.2: Conjugate Load Match of InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA)
109 Appendix A: (Continued) The simulations are shown on the left and the measurements are shown on the right for both figures. As seen from the plots, there is very good agreement between the S-Parameter and load pull predicted conjugate source and load matches, which means the system S-Parameters were measured reasonably well. The comparison of Figures A.1 and A.2 are shown in Table A.2. Table A.2: Summary of Conjugate Source/Load Match for InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA) VNA Meas., shown in ADS Maury ATS Measurements Source Conjugate Match s=0.848<-169.009 s=0.8301<-165.79 Load Conjugate Match L=0.319<-140.502 L=0.3442<-141.38 A.3 HBT 50-ohm Power Sweeps With the small-signal conjugate matches verified, the 50-ohm gain compression measurements will serve as a final system verification to check for similarities between the VNA and Maury Load Pull measured transducer gain, output power and TOI. The TOI is derived from the AM-AM data, as third order products cause gain compression. The data is put into S2D format and simulated to produce the desired data. The VNA and Load Pull measured power sweeps are shown for output power and TOI in Figure A.3 and summarized in Table A.3.
110 Appendix A: (Continued) Figure A.3: 50-ohm Power Sweep Comparisons for InGaP HBT at 2.45 GHz (Class AB Bias Conditions: Vce=3.3 V, Ibb=250 uA, Icc=20 mA) Table A.3: HBT Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz Gain (dB) Pout (dBm) PAE (%) Measured @ -2 dBm 13.49 11.49 20.63 Modeled @ -2 dBm 13.31 11.31 20.57 The power sweep data correlates well, with only the TOI showing any major discrepancy. Output power tracks very well, indicating a reasonable fit to the model.
111 Appendix A: (Continued) A.4 HJFET Source and Load Conjugate Match The small-signal conjugate matches predicted by the S-Parameters for the HJFET were compared to a low-power tune in the load pull system so that the integrity of the system could be verified. Figure A.4 and A.5 show the source and load conjugate matches, respectively. The ADS simulations of the S-Parameters are on the left, with load pull measured data from the low power tune shown on the right. Table A.4 summarizes the conjugate matching conditions. Figure A.4: Conjugate Source Match of GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=-0.41 V, Ids=18 mA)
112 Appendix A: (Continued) Figure A.5: Conjugate Load Match of GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=-0.41 V, Ids=18 mA) Table A.4: Summary of Conjugate Source/Load Match for GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=-0.41 V, Ids=18 mA) VNA Meas., shown in ADS Maury ATS Measurements Source Conjugate Match s=0.536<-92.53 s=0.531<93.32 Load Conjugate Match L=0.523<-48.81 L=0.5212<48.27 As seen from the plots and table, the conjugate match from the low power tune correlates well with the conjugate match from the small-signal S-parameters. The phase match for both the source and the load tuning measurements are within 1 degree of the small-signal S-Parameters. This shows good correlation and allows us to conclude that the system S-Parameters were measured reasonably well.
113 Appendix A: (Continued) A.5 HJFET 50-ohm Power Sweeps Next, the 50-ohm gain compression measurements will verify the correlation between the VNA and Maury Load Pull measured transducer gain, output power and TOI. This is a final check before pursuing large-signal measurements. The same bias is used for the power sweep that was used for the low-power conjugate matching tune. Figure A.6 shows the measurement comparison. Figure A.6: 50-ohm Power Sweep Comparisons for GaAs HJFET at 2.45 GHz (Class AB Bias Conditions: Vds=3 V, Vgs=0.41V, Ids=18 mA)
114 Appendix A: (Continued) Table A.5: HJFET Class AB 50-ohm Power Sweep Comparisons at 2.45 GHz Gain (dB) Pout (dBm) PAE (%) Maury Measured @ -1 dBm 14.99 13.99 29.39 VNA Measured @ -1 dBm 15.39 14.39 26.6%
115Appendix B: ADS Templates used for Non-linear Simulations B.1 Introduction This appendix will briefly discuss the ADS templates used for simulations of the three non-linear device models discussed in this thesis, a EEHEMT, Gummel Poon and TOM model. The templates to be shown cover two-tone power sweep, fundamental load pull and second harmonic load pull. The simulation templates shown were used for the load pull simulations of the MDLX EEHEMT non-linear device model. B.2 Two-Tone Power Sweep Simulation Template The schematic for a 2-tone 50-ohm power sweep at 2.45 GHz is shown in Figure B.1. In this setup, a 2-tone source sets up the 2 carrier frequencies 2.45 and 2.451 GHz. The dc blocks and dc feeds are used as need ed for the input and output bias. The current meters are used so that the power relations can be calculated, using the templates built-in equations. The power sweep is setup for a max IMD order of 7 and the power is swept in two different blocks because a finer resolution is used for the power range containing the P1dB of the device simulation. The VAR1 block sets up the frequency, frequency separation, IMD order and quiescent bias. The VAR 2 block sets the impedances at all frequencies at the source and load up to the 5th harmonic.
116 Appendix B: (Continued) Figure B.1: 2-Tone 2.45 GHz 50-ohm Power Sweep Simulation Template The dataset produced by the simulation will not be displayed for brevity, but includes the information shown in Chapters 4 and 5 for the pHEMT power sweep data. It contains gain compression, IM3 and IM5 data and also PAE curves vs. output power. The data can be updated by a marker that changes the input power level.
117 Appendix B: (Continued) B.3 Fundamental Load Pull Simulation Template The schematic for the fundamental load pull simulations is shown in Figure B.2. This template is similar to the power sweep except that a load tuner block has been added where term 2 appears in Figure B.1. The load frequency is indexed by the VAR block at the top of the figure. It basically contains an array of source and load pull frequencies. Figure B.2: ADS 2.45 GHz Fundamental Load Pull Simulation Template
118 Appendix B: (Continued) The full dataset for this simulation will not be shown for brevity. It does contain load pull data referenced to 50-ohms which was shown in Chapter 6 and also has an option to show load pull data referenced to characteristic impedances other than 50 ohms. The available load impedances are shown in Figure B.3. The impedances are read in the software as rectangular coordinates. Figure B.3: Indexing of Impedances for 2.45 GHz Fundamental Frequency Tuner
119 Appendix B: (Continued) B.4 Second Harmonic Load Pull Simulation Template The final template to be shown is for the second harmonic load pull simulation. The template in Figure B.4 isnt much different from the fundamental setup in Figure B.3 except that now the impedances have been converted to reflection coefficients represented by magnitude and phase. Figure B.4: ADS 4.9 GHz Second Harmonic Load Pull Simulation Template
120 Appendix B: (Continued) Figure B.5 shows the resultant impedance spreads from the simulation. Here, there are several constant magnitude circles which each are stepping the phase from 0 to 360 degrees in steps of 5 degrees. The magnitude is being swept from 0.2 to 1.0 in steps of 0.2. That way, the influence of magnitude change and phase change can be monitored. Figure B.5: Simulated Impedance Spreads from Second Harmonic Template