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Low loss rf/mm-wave mems phase shifters

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Title:
Low loss rf/mm-wave mems phase shifters
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English
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Lakshminarayanan, Balaji
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University of South Florida
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Subjects / Keywords:
Tunable
Transmission lines
Phased array
Calibration
Slow-wave
Dissertations, Academic -- Electrical Engineering -- Doctoral -- USF   ( lcsh )
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government publication (state, provincial, terriorial, dependent)   ( marcgt )
bibliography   ( marcgt )
theses   ( marcgt )
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Abstract:
ABSTRACT: A true time delay multi-bit MEMS phase shifter topology based on impedance-matched slow-wave CPW sections on a 500 m thick quartz substrate is presented. Design equations based on the approximate model for a distributed line is derived and used in optimization of the unit cell parameters. A semi-lumped model for the unit cell is derived and its equivalent circuit parameters are extracted from measurement and EM simulation data. This unit cell model can be cascaded to accurately predict N-section phase shifter performance. Experimental data for a 4.6mm long 4-bit device shows a maximum phase error of 5; and S11 less than -21dB from 1-50GHz. A reconfigurable MEMS transmission line based on cascaded capacitors and slow-wave sections has been developed to provide independent Zo - and -tuning. In the Zo-mode of operation, a 7.4mm long line provides Zo-tuning from 52 to 4 (+/-2;) with constant phase between the states through 50GHz.
Thesis:
Thesis (Ph.D.)--University of South Florida, 2005.
Bibliography:
Includes bibliographical references.
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by Balaji Lakshminarayanan.
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Title from PDF of title page.
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Document formatted into pages; contains 124 pages.

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Low Loss Rf/Millimeter-Wave Mems Phase Shifters by Balaji Lakshminarayanan A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Tom Weller, Ph.D. Larry Dunleavy, Ph.D. Shekhar Bhansali, Ph.D. Srinivas Katkoori, Ph.D. Dennis Killinger, Ph.D. Date of Approval: March 25, 2005 Keywords: tunable, transmission lines, phase d array, electronic calibration, slow-wave Copyright 2005 Balaji Lakshminarayanan

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DEDICATION This dissertation is dedicated to my parents, grand-parents and to my sister for their immense love and support in all my endeavors.

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iTABLE OF CONTENTS LIST OF TABLES ………… ………………………………………………………………........ iii LIST OF FIGURES ……………………………………………………………………….…….. iv ABSTRACT ……………………………………………………………….………………….….. xi PREFACE. ……………………………………………………………………………………….. xii CHAPTER 1 Introduction ….…………………..…………………………………………….... 1 1.1 RF-MEMS Switch ……….……………………………………………….......………….…. 2 1.2 Thesis Organization ……..……………………………………………….......………….…. 6 1.3 Contribution ………. …….……………………………………………….......………….…. 7 CHAPTER 2 Theory of Distributed MEMS Transmission Line ....................................... 8 2.1 Analytical Model of Periodically Loaded Transmission Line ………...……………..…. 9 2.2 Distributed Transmission Line Loss …….………………………………….…….….…… 12 2.3 Circuit Model of DMTL …………………………………………………………..….……. 15 2.4 DMTL Phase Shifter and Results …………………………………………………...……. 17 2.5 MEM Capacitor Design ………………………………………….………….……….…….. 22 2.6 Non-Uniform Transmission Line Loaded Phase Shifter Modeling and Results. ……... 27 2.7 Chapter Summary…………………………………………………...……………….……... 33 CHAPTER 3 Cascaded Slow -wave Phase Shifter Design and Results …….…………….... 34 3.1 Slow-wave Unit Cell Design and Fabrication ………….……………………..….………. 37 3.2 Modeling of Slow-wave Unit Cell ………………………………………….…….….…….. 39 3.3 Optimization ………………………………………………………….………….…….……. 46 3.4 Accurate Slow-wave Unit Cell Model ………...……………………….………….….…… 54 3.5 Phase Shifter Performance (1-bit and 4-bit version) …………………....…………..….. 58 3.6 2nd Generation 1-bit Low Loss Phase Shifter Performance …………………..…….…. 63 3.7 Frequency Scaling ( X and W -band designs) …………………………………..……….… 67

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ii 3.8 Chapter Summary …………………………………………………………….…….…….… 68 CHAPTER 4 Applications of Slow-wave Phase Shifter ……………………….….………… 69 4.1 Reconfigurable MEM Transmission Line with Zo-tuning and -tuning …………..…… 69 4.2 Design and Measured Performance ………………………………………….…….…….... 70 4.3 1-bit Tunable Zo-line and 1-bit Phase Shifter Performance ………..…………………… 73 4.4 Combined Zo -Tuning and -Tuning …………………….………………...……………… 75 4.5 Electronically Tunable Multi-line TRL …………………………………………….….…. 77 4.6 Chapter Summary………………………….……………………………….…………….…. 81 CHAPTER 5 Summary and Future Work ………………………………………..………..… 82 5.1 Future Work ……………………………………..……..................................................... 83 BIBLIOGRAPHY ………………………………………………..………………………………. 87 APPENDICES ……………………………………………………………………………………. 93 APPENDIX A: CPW Transmission Line Loss ……………….……………………………….. 94 A.1 CPW Lines on Quartz …………………………………………………………………….… 94 A.2 CPW Lines on Silicon ….…………………………………………………………………… 96 APPENDIX B: Detailed Fabrication Process …...………………………….……...…………. 99 APPENDIX C: Tunable Bandpass Filt er Using DMTL ..…..………………………….……. 103

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iiiLIST OF TABLES Table 2.1: Effect of series inductance ( Lb) on the Bragg’s frequency. ………….…………. 12 Table 2.2: DMTL phase shifter with 360 phase shift for design parameters on air, quartz and silicon substrates. ……………………………………….……….. 28 Table 2.3: Comparison of the NTL phase shifter performance versus DMTL phase shifter with Zo=70 ……………………………………………….………. 32 Table 3.1: Comparison of current state-of-the-art TTD phase shifter. …………………… 36 Table 3.2: Specifications used in Figure 3.6. …………………………………...…….……… 45 Table 3.3: Maximum CPW width G1 versus dielectric constant. …………...……….……. 49 Table 3.4: Calculated center conductor width ( W and W1) for maximum /dB. ….…. 52 Table 3.5: Calculated parameters for the slow-wave unit cell. ……………...…………….. 53 Table 3.6: Physical dimensions of CPW and MEM bridge. ………………….……………. 56 Table 3.7: CPW and bridge dimensions for de sign 1 and design 2. ………….…...………. 65 Table 3.8: Design parameters for X -band and W -band design used in simulation. ……... 67 Table 4.1: CPW dimensions and bridge capacitance ( Cbs and Cbg) for the slow-wave unit cell that is used in this section. …………………………………………….. 71 Table A.1: CPW dimensions for the lines used in this section. The resistance per unit length of each line is extracted from the measured data. ……………………... 95 Table A.2: CPW footprints used on high resistive silicon ( 2000 -cm) substrate. ….. 97 Table B.1: Sputtered SixNy etch recipe used in this work. ………………..…………….….. 100 Table C.1: Capacitance values for the series /4 sections and the open /2 stubs in the upstate and downstate. .…………………………………………………….… 105

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ivLIST OF FIGURES Figure 1.1: Cantilever MEMS bridge in series conf iguration along a transmission line. 3 Figure 1.2: Circuit model for a series capacitive MEMS switch with the capacitance varying from 20fF to 2pF. ……………………………………..………………… 3 Figure 1.3: Circuit simulation of the series capa citive switch using the model in Figure 1.2. …….…………………………………………………………………… 3 Figure 1.4: Suspended MEMS bridge in shunt conf iguration over a CPW transmission line. …………………………………………………………………..…………….. 4 Figure 1.5: Circuit model for a shunt capacitive MEMS switch with the capacitance varying from 20fF to 2pF. ......…………………………………………………… 4 Figure 1.6: Circuit simulation of the shunt capa citive switch using the model in Figure 1.5. …..……………………………………………………………………... 4 Figure 1.7: Top view of a CPW line periodically loaded by shunt MEMS bridges. …….. 6 Figure 2.1: General model for a periodic loaded transmission line with series impedance Zs and shunt admittance Yp. …………………...………...………… 9 Figure 2.2: Lumped element model of a distri buted MEMS transmission line. The MEMS bridges are represented by a variable capacitor Cb. Lt and Ct represent the per unit length inductance and capacitance of the unloaded transmission line, while s is the periodic spacing between bridges. 11 Figure 2.3: Extracted effective dielectric constant (extract) for the DMTL versus center conductor width at 40GHz. The relative dielectric constant of silicon (r=11.7) and quartz (r =3.8) are shown for reference. ……………… 16 Figure 2.4: Circuit model used for a section in the DMTL simulation. Z0 of the transmission line (t-line) is the unloaded line impedance, s is the periodic spacing of the MEMS bridges, Cb is the MEMS bridge capacitance. ……….. 16

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v Figure 2.5: Measured (a) phase shift ( ); (b) S11 and S21 in the down-state; (c) S11 and S21 in the up-state. The DMTL comprises of 11 bridges (40 m wide) spaced at 700 m (total length = 7.84mm). …………………………………… 18 Figure 2.6: Comparison of phase shift per dB between measured and modeled DMTL phase shifter. ……………………………………………………………...………. 19 Figure 2.7: Capacitance ration versus maximum allowable S11 (dB) for unloaded impedances 80, 90, 100, and 120 ……………..…………………................... 21 Figure 2.8: Effect of Bragg frequency on the linear range of fmax= 40GHz, Zlu=61 s=700 m. …...………………………………………………………….. 21 Figure 2.9: Effect of Bragg frequency on the loaded (solid lines) and unloaded impedance (dashed lines) for fB=1.5 and 1.8 fmax. The model parameters used in Figure 2.5 is used herein. ...…………………………………………….. 22 Figure 2.10: Normalized switch height versus applied voltage (normalization factor = original height=2 m) for L=500 m, W=100 m, w =80 m, E=80GPa, =0.4, t=1 m). …………………………………………………………………… 24 Figure 2.11: Schematic of a digital implementati on using very thick dielectric ( hd) for digital operation. …………………………………………………………………. 25 Figure 2.12: Capacitance ratio versus normalized height of the dielectric. ……………….. 26 Figure 2.13: Unit cell representation of a DMTL th at utilize static capacitor in series with the bridge. This type of config uration is used in a “digital” type tuning. ……………………………………………………..………………………. 27 Figure 2.14: (a) Schematic and fabricated unit cell of two NTL capacitively loaded phase shifter designs; (b) Photograph of the fabricated device (design 1), a 200 m long high impedance ( Zo=66 ) line is used to transition from a 50 feed to the DMTL sections. ………………………………………………... 30 Figure 2.15: (a) Measured differential for the two NTL phase shifter (design 1, design 2 and DMTL with Zo =70 ) on 400 m thick high resistive silicon. The solid line for curve represents EM simulation data and the dashed lines represen t measured data; (b) Worst-case S21

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vi for the phase shifter; (c) Measured S11 in the down state; (d) Measured S11 in the up state. .... 31 Figure 2.16: (a) Extracted effective impedance ( Zeff down) in the down state, (b) extracted effective impedance in the up state (Zeff up) for the capacitively loaded NTL unit cell and uniform Z unit cell. ... 33 Figure 3.1: (a) Net phase shift ( ) versus maximum allowable S11 (dB) assuming CPW on quartz; (b) S11 as a function of minimum and maximum capacitance values for the MEM bridge. The plots pertain to s =200 m and Zo=95 . 37 Figure 3.2: Schematic of the slow-wave structure a) Normal state; b) Slow-wave state (the SiCr bias lines are not shown). ... 38 Figure 3.3: Details of the fabrication process for the MEM structures. The illustration shows a perspective view of a slow-wave unit cell. 39 Figure 3.4: Ideal model for the slow-wave unit cell in both the states. This model does not take into account the parasitics due to the bridge and the discontinuities 40 Figure 3.5: a) Cbs versus center conductor width, W (and G =300 m) for air, quartz, and silicon substrates; b) Cbs versus W for two ground-to-ground spacing on quartz substrate. fB is set to 2.6 fmax=130GHz. .. 42 Figure 3.6: Maximum value of G1 versus substrate dielec tric constant assuming fB =2.6fmax=130GHz. ... 43 Figure 3.7: Calculated phase shift per mm versus the conductor width ( W1) at 50GHz for (a) Air, (b) Quartz, and (c) silicon with G1=300 m and W=100 m. The maximum width W is equal to /5. 5 in each case. The impedance corresponding to the center conductor width is given at the top of each plot. ... 45 Figure 3.8: Calculated phase shift per mm vers us the center conductor width at 50GHz for (a) Air, (b) Quartz, and (c) silicon with G1=300 m. The maximum width W is equal to /5.5. The impedance corresponding to the center conductor width is given at the

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vii top of each plot. For example, for G=300 m on silicon, Zo varies from 203 to 99 ..………………………………………………….…………… 46 Figure 3.9: Measured and calculated uniform CP W line loss versus frequency for a 300 m total width for, a) quartz ( Zo=95 ), b) silicon (58 ). The reference impedance for the measurement is set to the Zo of the line. ……… 48 Figure 3.10: Loaded transmission line loss and loss due to bridge resistance versus a) frequency, b) W = W1=100 m and G = G1=300 m on quartz at 50GHz ( fB = 2.6 fmax = 130GHz). The bridge is comprised of 1 m thick plated Au. 49 Figure 3.11: Calculated phase shift per dB ( /dB) at 50 GHz versus CPW center conductor width ( W and W1) for (a) air, (b) quartz, and (c) silicon substrates. In this calculation the total CPW width G =300 m, fB=130GHz, and G1 value in Table 3.3 is used. ……………………………… 51 Figure 3.12: Calculated ground plan e bridge capacitance (2 Cbg) at 50 GHz versus CPW center conductor width ( W and W1) for (a) air, (b) quartz, and (c) silicon substrates. In this calculation the total CPW width G =300 m, fB=130GHz, and G1 value in Table 3.3 is used. ...……………… 52 Figure 3.13: a) Comparison between measured and calculated (using 3.10) for a 460 m long unit cell, b) Measured S21 in both the states, c) Measured S11 in both the states, d) Photograph of the fabricated device. …. 54 Figure 3.14: (a) Equivalent circuit model for the unit cell in the normal state, (b) Equivalent circuit model for the unit cell in the slow-wave state. ……… 55 Figure 3.15: Comparison between measurement data and model (equivalent circuit and full wave EM simulation), (a) S11 and S21 in the normal state, (b) S11 and S21 in the slow wave state, (c) Phase shift ( ), (d) model parameters. ………………………………………………………………………... 57 Figure 3.16: Schematic and photograph of the fabricated phase shifter. The phase shifter has 10 cascaded slow -wave unit-cells. ………………………………….. 59

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viii Figure 3.17: Comparison between measurements and equivalent circuit model for the 1-bit phase shifter (a) S11 and S21 in the normal state, (b) S11 and S21 in the slow wave state, (c) Phase shift ( ), (d) Phase shift per dB, (e) model parameters. ………………….…………….. 60 Figure 3.18: Measured S21 of the 1-bit phase shifter for both states and a 4.6mm long uniform 50 CPW line. ………………………………………………………….. 61 Figure 3.19: Schematic of the fabricated 4-bit phase shifter. ………………………………. 61 Figure 3.20: Comparison of S11 (dB) and S21 (dB) between measured data and equivalent circuit model; (a) 1st bit (45 ); (b) 2nd bit (90 ); 3rd bit (180 ); 4th bit (225 ). ..……………………………………………………………………. 62 Figure 3.21: Comparison of between measured and modeled data for the multi bit phase shifter. ……………………………………………………………………… 62 Figure 3.22: Calculated parameters for the slow -wave unit cell on quartz with G =300 m and G1=320 m, a) fB using (3.15), b) 2 Cbg. The two designs are marked in the figure. …..…………………………….................................. 64 Figure 3.23: Photograph of the fabricated device, a) design 1, b) design 2. ……………… 65 Figure 3.24: Comparison between measurements a nd equivalent circuit model for the 1-bit phase shifter, (a) S11 and S21 in the normal state for design 1, (b) S11 and S21 in the normal state for design 2, (c) S11 and S21 in the slow wave state for design 1, (d) S11 and S21 in the slow wave state for design 2, (e) and /dB for design 1, (f) and /dB for design 2. ………… 66 Figure 3.25: a) Simulated (Momentum) S11 in both the states for W -band design, b) comparison between simulated (momentum) and calculated …………... 68 Figure 4.1: Microphotograph of the constant tunable Zo slow-wave unit cell (left) and SEM picture of the structure. ……………………………………………… 71 Figure 4.2: Measured S11 (dB) and extracted Zeff in state 1 and state 2 for the 1-bit tunable Zo unit cell. Solid lines represent EM simulation data. …………….. 73 Figure 4.3: Schematic of 10-section cascaded tunable Zo unit cell and a photograph two unit cells in the device. .…………………………………………………….. 74

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ix Figure 4.4: Comparison of measured (dashed) and simulated (solid) S11 (dB) of a 7.4mm long tunable Zoline with constant propagation constant in both states, a) state 1, b) state2. ……………………………………………………... 74 Figure 4.5: Measured performance of the 10-section 1-bit tunable Zo device in both the states, a) S21 of the tunable transmission line and S21 data of a 1.6cm long 50 CPW line, b) in both the states. ...……………………………... 75 Figure 4.6: Comparison between measurements a nd optimized EM simulation for the 10-section device in phase shifter mode operation, a) S11 in the slowwave state, b) S11 in the normal state, c) The solid line in each plot represent EM simulation data and th e dashed line represent measured data. ……………………………………………………………………………….. 76 Figure 4.7: Measured performance of a 10-section device in a bi-modal operation, a) S11, b) Solid lines represent EM simu lation data and dashed lines represent measured data. ………………………………………………………... 77 Figure 4.8: Upper bound error | Sij-Sij ’|max between standard TRL and Tunable TRL. …. 79 Figure 4.9: S11 and S21 of 9mm long verification stru cture The line was measured after a Tunable TRL calibration and a standard TRL on quartz (TRL1). ... 80 Figure 4.10: S11 of a 25 load verification structure on a 700 m thick CS-5 substrate. … 80 Figure 5.1: Momentum simulation of a 1cm long line on 500 m thick quartz with 100 m thick quartz lid at different he ights above CPW line, a) Absolute phase in deg, b) S21 (dB/cm). …………………………………………………… 84 Figure 5.2: Typical setup for power handling measurement of slow-wave phase shifter. 85 Figure 5.3: Schematic of the slow-wave unit cell. ………………………………………….. 86 Figure A.1: Comparison between measured and pred icted loss versus frequency. ………. 95 Figure A.2: Comparison between measured and pr edicted loss at 50GHz versus CPW pitch for 1 m evaporated line. For the data presented herein, four different correction factor is used to match the measured data. The characteristic impedance for the lin es is listed above the plot. ……………… 96

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x Figure A.3: Comparison between measured and predicted loss (dB/cm). …………..…… 96 Figure A.4: Comparison between measured and pr edicted loss at 50GHz versus CPW pitch for 3 m plated lines. ……………………………………………..………... 97 Figure A.5: Comparison between measured and modeled loss (dB/cm) data on a 425 m thick high resistive ( 2000 -cm) silicon substrate, a) W / S / W =17.5/40/17.5, b) W / S / W =100/100/100. …………………………… 98 Figure A.6: Multiplication factor required to match the measured data on high resistive silicon substrate. ……………………………………………………….. 98 Figure A.7: Comparison between measured and pr edicted loss at 50GHz versus CPW pitch. The multiplication factor in Fi gure A.6 is used for the measured data. ……………………………………………………………………………….. 98 Figure C.1: Schematic of the tunable filter utilizing /2-open stubs and /4 series connecting sections [36]. …………………………………………………………. 103 Figure C.2: Schematic of the tunable filter designed with DMTL. ……………………….. 105 Figure C.3: Comparison between measured data and modeled data in the up-state, a) S11, b) S21. Solid lines represent EM simu lation data and dashed lines represent measured data. ………………………………………………………... 107 Figure C.4: Comparison between measured data and modeled data in the down-state, a) S11, b) S21. Solid lines represent EM simu lation data and dashed lines represent measured data. ………………………………………………………... 108

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xiLOW LOSS RF/MILLIMETER WAVE MEMS PHASE SHIFTERS by Balaji Lakshminarayanan ABSTRACT A true time delay multi-bit MEMS phase sh ifter topology based on impedance-matched slow-wave CPW sections on a 500 m thick quartz substrate is presented. Design equations based on the approximate model for a distributed line is derived and used in optimization of the unit cell parameters. A semi-lumped model fo r the unit cell is derived and its equivalent circuit parameters are extracted from measur ement and EM simulation data. This unit cell model can be cascaded to accurately pred ict N-section phase shifter performance. Experimental data for a 4.6mm long 4-bit device shows a maximum phase error of 5.5 and S11 less than -21dB from 1-50GHz. A reconfigurable MEMS transmission line based on cascaded capacitors and slow-wave sections has been developed to provide independent Zo and -tuning. In the Zo-mode of operation, a 7.4mm long line provides Zo-tuning from 52 to 40 (+/-2 ) with constant phase between the states through 50GHz. The same transmission line is reconfigured by addressing the MEM elements differently and experimental data for a 1-bit version shows 358 /dB (or 58 /mm) with S11 less than -25dB at 50GHz. The combined effect of Zoand -tuning is also realized using a 5-bit version. An electronically tunable TRL calibration set that utilizes a 4-bit true time delay MEMS phase shifter topology, is demonstrated. The accuracy of the tunable TRL is close to a conventional multi-line TRL calibration a nd shows a maximum error bound of 0.12 at 40GHz. The Tunable TRL method provides for an efficient usage of wafer area while retaining the accuracy associated with the TRL technique, and reduces the number of probe placements.

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xiiPREFACE I sincerely thank my advisor, Dr. Tom Weller, for allowing me to continue with this thesis topic. When this project started there was little or no progress during the first year and his patience and support was of great help. His technical insight complimented with his understanding and patience make him one of the remarkable persons I have ever met. I sincerely thank him for his contributions to my personal and professional growth. I would like to thank National Science Foundation and Raytheon Systems for continuous financial support since 1999 and USF Center for Ocean Technology for their support in the operation of the lab. Many thanks to Dr. Larry Dunleavy and Dr. Shekhar Bhansali for their suggestions regarding measurements an d fabrication of these circuits. Along with Dr. Weller they were instrumental in pr oviding a good fabrication and measurement capability at USF. I would also thank Dr. Srinivas Katkoori and Dr Dennis Killinger for taking the time to serve on my dissertation committee. A ssociate Dean, Dr. Robert Caranahan was extremely helpful for agr eeing to chair the defense. I ap preciate their contributions for reviewing this dissertation and participating in the oral defense. This research would not have been possible without the support of many graduate students. I am deeply indebted to Mr. Thomas Ketterl, Mr. Jim Culver, Mr. Hari Kannan, Mr. Srinath Balachandran, and Mr. Saravana Natarajan for introducing me to microwave fabrication and modeling. I enjoyed their friendship, support, and their help in maintaining the lab. I hope I was able to pa ss on the knowledge to newer members in the group. Many thanks to Mr. Chris Trent with whom I had numerous discussions and appreciate his willingness to help concerning theoretical techniques. Thanks to my officemates, Dr. Weatherspoon and Mr. Jiang Li u for their interesting conversations.

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xiii I enjoyed working with Mr. Alberto Rodriguez, Mr. Lester Lopez, Mr. Jason Naylor, Mr. Jeff Miner, Mr. John Capwell, Mr. Sriram Sr inivasan, and Mrs. Sa thya Padbanaban in the measurement lab. I am thankful to Alberto and Sathya for allowing me to use their calibration comparison code that is used in this work. I had the opportunity to interact with the member’ s of microsystem’s group. Many thanks to Mr. Raj Popuri, Mr. Kiran Potluri, Mr. Shyam Aravamudhan, Mr. Sriram Akella, Mr. Praveen Shekhar, and Mr. Kevin Luango for their help in thin film deposition. Thanks to Dr. Mamaaza and Dr. Ferekides for providing access to their sputtering tool. Former students of compound semiconductor group were extremely helpful in providing suggestions for processing related questions we had. I am thankful to the clean room staff, Robert, Rich, and Jay for training me on several tools and maintaining these tools. The department staff Becky, Irene, Gayla, Norma, Harris, Mike, and Ch ance for all their help over the years. I had the opportunity to know many outstanding people outside microwave lab who made my stay in Tampa a memorable one. I am gr ateful to my past and present room-mates Raju, Daksha, Harish, Ramesh, Vijay, Venkatesh, Madhan, and Shyam who motivated me. I am thankful to Dr. Venkataramana, Saravana, Hari and Srinath for all their help and for the many fruitful discussions. Finally, I would like to thank my family. My parents, Bhanumathy Lakshminarayanan and K.S Lakshminarayanan, encouraged me at ev ery step and never doubted my ability to complete the task. My grand-parents, Rajaraman’ s and Subramanian’ s who taught me the importance of education and for their love. My sister, Jayanthi and her husband Hari for their encouragement, my uncle Dr. V. Rajaraman for his motivation. Their understanding and loving support was helpful wh en I needed it the most and I will forever be grateful to them.

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1CHAPTER 1 Introduction The field of RF-microelectromechanical system s (RF-MEMS) has seen enormous growth in the past decade due to its potential for hi gh performance in defense and commercial applications. The program objectives of federal agencies DARPA1’s SPO2 and MTO3 is to develop innovative ideas that offer signific ant improvement in technology and to pursue these ideas from the demonstr ation of technical feasibility through the development of prototype systems. Other federal research or ganizations such as NASA, NSF, Airforce Research Labs, Navy and seve ral commercial organizations are actively pursuing the incorporation of MEMS devices for future applications [1]. The strong advantages of RF MEMS are found in terms of low loss, virtually no DC power consumptio n, light weight and can be manufactured on low-cost silicon or glass substrates. At first this interest was driven by the su ccess of low-frequency MEMS devices and their advantage of low-power operation and easy integration with CMOS circuitry. However, most low frequency devices are based on poly silicon structures. The high resistivity of polysilicon at microwave frequencies causes excessive loss and therefore not a suitable material for RF-MEMS. Because of this, most researchers in the field of microwave MEMS devices have used metal structures driven by electrostatic actuation [2]. Most of the research in the microwave MEMS devices ha s focused on the development of low-loss circuits such as single-pole single-throw (SPS T) switches and switched-line phase shifters [30, 18, 60]. The advantage of using MEMS devices over FETs or PIN diodes is their extremely low series resistance, on the order of 0.1 to 0.3 as compared to 2 to 6 and 1 DARPA: Defense Advanced Research Project Agency 2 SPO: Special Projects Office 3 MTO: Microsystems Technology Office

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2their extremely low drive power requirements, on the order of W as compared with mW. Furthermore, due to the fact that MEMS de vices do not contain a semiconductor junction, with the associated non-linearity, they lack any measurable intermodulation distortion [19]. 1.1 RF-MEMS Switch MEMS switches have been fabricated in suspended beam, cantilever, and diaphragm configurations with the bridge height typically 3 to 4 m above the transmission line, resulting in an actuation voltage of 25 to 100 V. Pacheco et al. have shown that low voltage actuation of 9 to 16 V can be achieved with a gap height of 3 m by using serpentine cantilever springs at the ends of the beam [38] This height is necess ary in order to reduce the parasitic capacitance of th e bridge in the OFF-state (bridge up), and results in a capacitance ratio of 50 to 100 for capaciti ve switches. MEMS switches have been demonstrated reliably up to 40 GHz with lo w insertion loss (0.2 to 0.5 dB) and high linearity [30, 19]. The achievable isolation wi th these switches is typically 20 to 40 dB, depending on the size of the MEMS bridge, with an associated reflection coefficient from -15 to -20 dB. Current microwave MEMS switches have been designed in both series and shunt configurations with both cantilever and fixed-fixed beams. In the series configuration, shown in Figure 1.1 with a cantilever beam, the isolation is limited by the parasitic capacitance which allows coupling at high frequencies. This can be seen with a simulation in which the MEMS bridge is represented by a series capaci tor-inductor-resistor combination as shown in Figure 1.2. Figure 1.3 shows the circuit simulation for the isolation when the switch is up and the return loss when the switch is down. As can be seen, for the capacitance values used, the performance at low frequencies is lim ited by the return loss rising to -10 dB around 2 GHz and at high frequencies by the isolation rising above -20 dB around 8 GHz. One of the main problems of series capacitive switches is the high return loss, with the switch down, in the frequency range where the is olation is greatest, with the switch up. In Figure 1.3, this occurs at 0.1-2 GHz. It is fo r this reason that metal-to-metal series MEMS switches are used. Yao et al. presented a series metal-to-metal MEMS switch for use in systems up to 6 GHz with better than 50 dB isolation up to 4 GHz [60].

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3 Substrate Signal Dielectric Figure 1.1: Cantilever MEMS bridge in series configuration along a transmission line. L C R C=20fF, 2pF L=10pH R=0.5 ohm Figure 1.2: Circuit model for a series capaciti ve MEMS switch with the capacitance varying from 20fF to 2pF. Frequency (GHz) 12345678910 S-parameters (dB) -50 -40 -30 -20 -10 0 S 21 (switch up) S 11 (switch down) Figure 1.3: Circuit simulation of the series capacitive switch using the model in Figure 1.2. The shunt switch configuration is shown in Figure 1.4 with a fixed-fixed beam over a CPW line. In this case, the parasitic capacita nce limits the high frequency response when the switch is up by producing unwanted reflections. Again, the MEMS bridge can be modeled by a series capacitor-inductor-resisto r combination as shown in Figure 1.5. The circuit simulation of this model is shown in Figure 1.6 where the return loss, when the switch is up, and the isolation, when the switch is down, is shown. As can be seen, the low frequency limit is set by low isolation wh ile the high frequency limit is set by high return loss. Because of the high frequency of operation of the shunt configuration, the inductance in the MEMS bridge resonates with the capacitance as seen in the isolation curve in Figure 1.6 Goldsmith et al. [19], have developed a shunt capacitive MEMS switch

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4with 40 dB isolation, with the switch down, a nd -15 dB return loss, with the switch up, at 40 GHz. Muldavin et al. have demonstrated that by using several shunt capacitive MEMS switches, the reflections can be tuned out and higher isolation can be achieved as compared to a single switch. The measured re sults demonstrate a return loss below -15 dB from DC-40 GHz with an isolation of better than 40 dB from 16-40 GHz [33]. Substrate W Bridge height G G GroundGround MEMS bridge Figure 1.4: Suspended MEMS brid ge in shunt configuration over a CPW transmission line. L C R C = 20fF, 2pF L = 10pH R= 0.5 ? Figure 1.5: Circuit model for a shunt capacitive MEMS switch with the capacitance varying from 20fF to 2pF. Frequency (GHz) 01020304050 S-parameters (dB) -40 -30 -20 -10 0 S11 (switch up) S21 (switch down) Figure 1.6: Circuit simulation of the shunt capa citive switch using the model in Figure 1.5.

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5The concept of periodically loaded lines has been researched for use as nonlinear transmission lines since about 1960 [29]. In this case, a transmission line is loaded with millimeter-wave Schottky diodes and is used in voltage-level pulse shaping, picosecond-level sampling, and harmonic multipliers [44, 45]. More recently, the periodically loaded line concept has been used in developing microwave phase shifters using varactor diodes as the capacitive loading [35, 36]. However, diode-base d periodically loaded lin es are quite lossy at millimeter wave frequencies, due to the series resistance of the Schottky diodes, and cannot be used in low-loss phase shifters and wide band switches above 26 GHz. For these frequencies, MEMS based designs offer excellent performance. MEMS switch designs have been very simi lar to standard PIN diode or FET switch networks, with the active device replaced by the MEMS switch. This departure from the traditional approach by incorporating the MEMS switches/varactors was first introduced by Barker et al. In this approach, a CPW tran smission line is loaded periodically with MEMS bridges, as shown in Figure 1.7, which act as shunt capacitors/varactors. A microstrip version of the phase shifter was implemented by Hayden et al. The impedance and propagation velocity of the resulting slow -wave transmission line are determined by the size of the MEMS bridges and their periodic spacing. The shunt capacitance associated with the MEMS bridges is in para llel with the distribu ted capacitance of the transmission line and is included as a design parameter of the loaded line. Thus, the height of the MEMS bridge can be lowered from 3-4 m to 1-1.5 m. An advantage of the lowered height is that the pull-down voltage of the MEMS bridge is reduced to 10 to 20 V. By using a single analog control voltage to vary the height of the MEMS bridges, the distributed capacitive loading on the transm ission line, and therefore its propagation characteristics, can be varied. This results in analog control of the transmission line phase velocity and therefore in a true-time delay phase shifter.

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6 S s w W l Figure 1.7: Top view of a CPW line periodically loaded by shunt MEMS bridges. 1.2 Thesis Organization This thesis consists of 5 chapters. Chapter 2 st arts with the theory of periodically loaded lines with extensions for the case of using ME MS bridges as the varactors. Both analytic and circuit models are found which provide for bo th the design and accurate simulation of the distributed lines. Both analog as well as digital true-time-dela y (TTD) phase shifter were measured and it is shown that the results agree favorably with published report. Chapter 3 discusses the design, optimization, fabrication and modeling of a impedance matched phase shifter designed to operate through 50GHz. The concept of slow-wave transmission line has been applied to the design of filters and feeding network. Using the measured results a semi-distributed model for the phase shifter is also presented. Furthermore, design considerations for scaling the 50GHz design to X -band and W -band frequency is suggested. In Chapter 4, the slow-wave unit cell is used in a broad-band tunable transmission line that can provide inde pendent impedance as well as phase tuning. Furthermore, a multi-bit version of the phase shifter is used to realize a on-wafer electronic multi-line TRL calibration set. These circuits are made possible due to the quasi-constant impedance, low loss performance of the slow-wave unit cell. Chapter 5 concludes the thesis with a discussion of the future directions of research for microwave MEMS devices and the distributed MEMS transmission line. Several appendices are included for completeness.

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71.3 Contribution In this work, 1-bit and multi-bit impedance-matched phase shifters are designed on low loss quartz substrate using slow-wave unit cells. Experimental results for a 4.6mm long MEM device indicate 310 /dB for the 1st generation design and 355 /dB for the 2nd generation design. The results represent state-of-the-art performance for TTD phase shifters through 50GHz. There are many applications that utiliz e phase shifter; however, the slow-wave unit cell is applied herein to the design of tunabl e transmission line and an electronic multi-line TRL calibration set. To the be st of author’s knowledge the application demonstrated using tunable slow-wave unit cells is one of the first reported results. The results for the phase shifter indicate 200 % improvement in the figure-of-merit and 40% reduction in size when compared with current state-of-the art designs such as DMTL. However, the number of MEM devi ces per mm is three times more when compared with the designs based on the DMTL topology. The long term reliability, power handling, packaging, temperature, and switching speed issues need to be addressed. Some of these issues are addressed briefly in final chapter but a thorough analysis is required before making this design more viable for commercial applications.

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8CHAPTER 2 Theory of Distributed MEMS Transmission Line Distributed circuits are used in many devices in cluding filters [41], traveling-wave amplifiers [44], phase shifters [36], and non-linear transmis sion lines [44]. The concept is very useful because the parasitics of the discrete componen ts, such as the gate-to-source capacitance of transistors in traveling-wave am plifiers, or the capacitance of Schottky diodes in non-linear transmission lines, are included as part of the periodic transmission line, thereby resulting in very wideband operation. The transmission-l ine dimensions can also be designed such that the resulting periodic tr ansmission line will have a 50 characteristic impedance. The distributed MEMS transmission line (DMT L) consists of a high impedance line (> 50 ) capacitively loaded by the periodic placem ent of MEMS bridges. This could be done with many different types of transmission lines however it is most ea sily implemented using coplanar waveguide (CPW) transmission lines. Figure 3.1 shows the top view of a typical DMTL used in this work. The MEMS bridges have a width w a length l = W + 2S, and a thickness t The periodic spacing between the bridges, s and the number of bridges vary depending upon the application. The DMTL is connected to probe pads via 50 CPW feed lines for the purpose of testing. A result of creating a periodic structure is the existence of a cut-off frequency or Bragg frequency, fB, near the point where the guided wavele ngth approaches the periodic spacing of the discrete components [47]. In many of the distributed circuits mentioned, this cutoff frequency can be designed such that it w ill not limit the device performance since the discrete components will have a comparable maximum frequency [44]. In the case of the distributed MEMS transmission lines used in this work, the self-resonant frequency of the MEMS bridges is not approached and thus the operation is limited by the Bragg frequency of the line.

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92.1 Analytical Model of Peri odically Loaded Transmission Lines The general model of a periodically loaded transmission line is shown in Figure 2.1. Assuming complex propagation constant = + j where is the attenuation per section and is the phase shift per section, a forward wave is represented by: 1 nnVVe (2.1) Using Figure 2.1 the voltages and currents are found to be: ZsYp ZsYp ZsYp ZsYp Yp VinIin Vn-1In-1 VnIn Vn+1 s Figure 2.1: General model for a periodic loaded transmission line with series impedance Zs and shunt admittance Yp. 1 1 1 1 nn n p nn nn nn ssII V Y VV VV IandI ZZ (2.2) Substituting the current equations for In-1 and In into the voltage equation for Vn, the following equation is found [8] 111 222sp nn nZY VV ee cosh() V (2.3) Equation 2.3 relates the propagation constant to the series impedance of the transmission line ( Zs) and the shunt admittance Yp. Using these equations the characteristic impedance of the line is found from Z=Vin/Iin. (assuming the line is matche d). The half-a ngle formula for the hyperbolic sine is used in (2.3), the characteristic impedance of the loaded line is found to be [44]: and given by:

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10 12 11 1 22 1 2 222 1 4n/ nnn s nnnp / ss sp s pV VVV Z Z IVVY ZeZ sinh(/) ZY Z Z Y (2.4) If a section of length s of unloaded line is used with characteristic impedance Zo and effective dielectric constant eff then; stptZjsL;YjsC (2.5) where, 1 2 teffottoCcZandLCZ are the per unit length capacitance and inductance respectively, of the unloaded transmi ssion line. Substituting these values in (2.4) gives 2 2211 4tttt ttBLsLCL Z CC (2.6) where, 2BttsLC is the Bragg’s frequency or the frequency at which the characteristic impedance goes to zero, indicating no power transf er can occur. It can be seen that when s0, B and ttoZL/CZ For a DMTL transm ission line, the MEMS bridge can be modeled as a shunt capacitor, resulting in a loaded line model as shown in Figure 2.2 where Cb is the shunt capacitance due to the MEMS bridge, and s is periodic spacing of the bridges. Using this model the series impedance is t j sL and the shunt admittance istb j sCC. The characteristic impedance found using (4) is given by: 2 211 4ttb tt tbtBsLsCC sLL Z sCCC (2.7) The Bragg’s frequency for a DMTL transmission line is given by:

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11 2B ttbsLsCC (2.8) The time delay per section of the loaded-lin e is determined from (2.3) by assuming a lossless line and using the model in Figure 2.2 [2, 3]. sLtsCtCbsLtsCtCb Figure 2.2: Lumped element model of a dist ributed MEMS transmission line. The MEMS bridges are represented by a variable capacitor Cb. Lt and Ct represent the per unit length inductance and capacitance of the un loaded transmissi on line, while s is the periodic spacing between bridges. 2 1 2 2 22 1 1 6B ttb Bss s cos s sLsCC (2.9) Where, is the time delay per section. From (2.9 ), it is seen that by varying the MEMS bridge capacitance, Cb, the phase velocity of the transmission line () can be varied resulting in a varying delay line or tr ue-time delay (TTD) phase shifter. Since the characteristic impedance ( Z ) of the DMTL affects S11, the lower and upper bound for Z using (2.7) is calculated to be 36 and 69 respectively, for S11 < -10dB. When the line is loaded (or Z =36 ), the maximum value of Cb is typically less than 0.1pF, for s =200m, and an unloaded impedance of 100 To obtain this value of Cb, the width of the bridge ( w ) is typically 20-70m and the length ( l ) is typically less than 300m. Using a quasi-static approximation, th e inductance of the bridge ( Lb) can be calculated by assuming the bridge as a microstrip line suspended on a 2-3m thick substrate with air (r=1) as the dielectric. For the footprints of the bridge aforementioned, Lb is typically within 10-30pH.

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12Table 2.1 shows the calculated Bragg frequencie s versus several values of bridge inductance for a line with an unloaded impedance of 100 a periodic spacing of 200 m, and a bridge capacitance of 40 fF on silicon (r=11.7), quartz (r=3.8), and air dielectric (r=1). It is seen from the table that including th e series inductance of the bridge has a significant effect on the position of the Bragg frequency. Table 2.1: Effect of series inductance ( Lb) on the Bragg’s frequency. Lb (pH)Air ( r=1)Quartz ( r=3.8)Silicon ( r=11.7) 0224GHz145 GHz89 GHz 10189 GHz129 GHz83 GHz 20164 GHz116 GHz77 GHz 30147 GHz106 GHz73 GHz fB (GHz) 2.2 Distributed Transmission Line Loss When the impedance is changed, the loss of the line is also changed due to a change in the amount of current on the line for the same amount of power. For example, if a high impedance line is capacitively loaded to a lower impedance, the current on the lower impedance line will be high er, thus increasing the I2R losses. This can be seen directly by considering the complex propa gation constant for a lossy transmission line. If the transmission line is represented by series inductance and resistance per unit length, Lt and Rt, and by a shunt capacitance and admittance per unit length, Ct and Gt, respectively, then the propagation constant is given by [10]: ttttRjLGjC (2.10) For a low loss line where ttRjL and ttGjC, the propagation constant can be approximated as: 1 2tt tttt ttRG j LCLCj LC (2.11)

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13Assuming the characteristic impe dance can be approximated by ttZL/C the attenuation constant is: 22ttRGZ Z (2.12) In a planar transmission line such as microstrip or CPW, Rt represents conductor loss while Gt represents dielectric loss. For the lines consid ered in this work (on low-loss substrates at mm-wave frequencies), the conductor loss domina tes and the attenuation constant can be approximated as 2tR/Z Thus, a change in the characteristic impedance from a high impedance to a low impedance will increase the loss by a factor of the ratio of the impedances. The transmission loss can also be included in the model of the distributed MEMS transmission line (Figure 2.2) by including a resistance Rs in series with the line inductance, sLt. In this case the series impedance becomes sstZRjsL To find the attenuation constant, (2.3) is expanded to give: 2 2cosh()cosh()cos()sinh()sin() 1 22 12s s BB j RC LC j R j Z (2.13) where L = sLt, C = sCt + Cb, and the low frequency approxim ations have been used for B and Z By equating the real parts and assuming is small (cosh( ) 1), the equation for the phase delay per sect ion is found to be 122122BBcos// .To find the attenuation per section, the imagi nary parts are equated to give: 22Bs s B/R/Z R sinh() sin/Z (2.14) Where Z is now the impedance of the loaded line. This result matches what was derived earlier in the unloaded case. The only di fference is that in the unloaded case, is the

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14attenuation per unit length (Np/m) while in the distributed case, is the attenuation per section (Np). The effect of a series resistance in the bridge can be taken into account by placing a resistor Rb in series with the bridge capacitance in Figure 2.2. In this case, (2.3) becomes: 22 222 2321 2 1 4 12tbbb t bb bb BBtbjsLjsCRC cosh(j)jsC RC RC j ZsCC (2.15) where 2Bttb/sLsCC, ttbZsL/sCC and a low frequenc y approximation has been used for 22211bbRC Using B, the propagation constant is found to be: 232 1 224 12 2 2bb BBtb bb BRC jcoshj ZsCC RZC j (2.16) Combining this loss with th e transmission line loss, the total loss per section for a distributed MEMS transmission line is [44]: 2222sbbRRZC Z (2.17) For a line with an unloaded impedance of 100 an unloaded effective dielectric constant of 2.4, a periodic spacing of 200 m, a bridge capacitance of 34fF, a loss of 0.6dB/cm ( Rt=15 /cm) at 40 GHz for the unloaded line, and a bridge resistance of 0.1 at 40 GHz the loss from the transmission line is 1.6 dB/c m at 40 GHz respectively. While the loss due to the bridge resistance is only 0.07 dB/cm (< 4%) at 40 GHz. Thus, for these typical parameters, the loss is dominated by the transmission line loss. Radiation loss is also present in an unload ed CPW line on a thick dielectric substrate because the wave velocity of the transmission li ne is greater than the phase velocity of the waves in the dielectric [46]. This loss is given by:

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15 2 32 5 rad 3 21 2 1 = 221 2 1r r f (WS) cK(k)K(k) W k WS kk (2.18) where W +2 S is the ground-to-ground spacing of th e CPW line and K(k) is the complete elliptic integral of the first kind. The radiatio n into the substrate primarily occurs around the angle: z dk cos k (2.19) Where kz is the propagation constant of the line and kd is the propagatio n constant in the dielectric. To avoid radiation a nd radiation loss, the wave velocity of the transmission line should be slower than the phase velocity of the dielectric. The angle necessary to phase match the wave on the transmission line to th e wave in the dielectric becomes imaginary indicating that radiation, and therefore radiat ion loss, cannot occur. Alternatively, a slowwave mode propagation (or no radiation) result s if the effective dielectric constant of the DMTL is greater than the relative dielectric co nstant of the substrate. Figure 2.3 shows the extracted effective dielectric constant (extract) of a DMTL versus the center conductor width for three dielectric constant with Z =100 s =200m and Cb= 40fF (assuming maximum loading). As seen in Figure 2.3, extract > r for center conductor widths less than 80m (Z=64 ) on silicon, while extract > r for W 370m (Z=60 ) on quartz and no radiation is possible for the entire range of conductor widt hs on an air substrate. The decrease in extract is because for a given CPW pitc h, the phase shift per unit le ngth decreases as impedance decreases. 2.3 Circuit Model of DMTL While the analytic model presented in sectio n 2.2 provides a good general understanding of the operation of periodically-loaded distributed lines, it is desirable to have a circuit model that can be used in a linear circuit simulato r. The simulator used for the modeling of the DMTL is Agilent’s Advanced Design System (A DS). Using the circuit elements available in

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16ADS, the model for a single section of the DMTL is shown in Figure 2.4. The model consists of a section of physical transmission line to represent the unloaded CPW line and a capacitor-inductor series combin ation shunted across the transmission line to represent the MEMS bridge. The entire DMTL is modeled in the simulator by cascading the necessary number of sections. In this appr oach, the unloaded line impedance, Zo, the spacing of the MEMS bridges, s the number of sections, n and the effective dielectric constant of the unloaded line, eff are determined from the physical dime nsions of the DMTL being modeled. The unloaded line attenuation, A, bridge capacitance, Cb, and bridge inductance, Lb, are all varied to fit the model to the measured data The attenuation in the physical transmission line model is specified at a partic ular frequency and then follows a f variation. Width ( m) 100200300400 extract 0 10 20 30 40 50 Si Quartz Air r =11.7r =3.8 Figure 2.3: Extracted effective dielectric constant (extract) for the DMTL versus center conductor width at 40GHz. The relative dielectric consta nt of silicon (r=11.7) and quartz (r =3.8) are shown for reference. Figure 2.4: Circuit model used for a section in the DMTL simulation. Z0 of the transmission line (t-line) is the unloaded line impedance, s is the periodic spacing of the MEMS bridges, Cb is the MEMS bridge capacitance.

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172.4 DMTL Phase Shifter and Results As mentioned in Section 2.2, the DMTL can be used as a true-time delay (TTD) phase shifter since a change in the MEMS bridge ca pacitance changes the phase velocity of the line (equation 2.9). The change in the bridge ca pacitance is achieved by applying a single bias voltage to the center co nductor of the DMTL with the CP W ground planes acting as a DC ground as well. This application is demons trated in Figure 2.5 (a)–(c). A DMTL phase shifter with 11 bridges (40m wide) spaced at 700m is simulated using the model shown in Figure 2.4. The unloaded line impedance is 65 (W = 60m and S = 180m) with an effective dielectric constant of 6.1. Figure 2.5 (b) and (c) shows the measured and modeled data for S11 and S21 in the high capacitance state (down state) and the low capacitance state (up state) respectively. It is seen from these figures that the S11 of the DMTL in the down state has more closely spaced nulls, indicating th at the line is electrically longer than it is in the up state. Since the physical length of the DMTL has not changed, the phase velocity of the line has decreased, as expect ed. The relative phase between the two states or the net phase shift ( ) is found from the change in the phase constant given by: 12 1211 (2.20) Using (2.9) for the phase velocity and a capacitance ratio Cr (dnupC/C ) per unit length is given by: 11 11borbo tt tt oeff luldCCC LC sCsC Z cZZ (2.21) for three different values of Cr and measured versus frequency is shown in Figure 2.5 (a). The SEM picture of the fabricated device is also shown in this figure. As seen from this figure, increases linearly with frequency as expected for a TTD type phase shifter and is within 5% of the predicted with Cr=1.15. There is some deviation from this linear increase at approximately 30GHz wh ich is a result of approaching the Bragg

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18frequency (calculated to be 67 GHz). The maximum is 170 at 40 GHz with an associated insertion loss of 1.75 dB. Frequency (GHz) 010203040 (deg) 0 75 150 225 300 C r =1.15 C r =1.25 C r =1.3 Meas Frequency (GHz) 010203040 S11 (dB) -40 -30 -20 -10 0 S21 (dB) -6 -5 -4 -3 -2 -1 0 Meas Model (a) (b) Frequency (GHz) 010203040 S11 (dB) -40 -30 -20 -10 0 S21 (dB) -6 -5 -4 -3 -2 -1 0 Meas Model (c) (d) Figure 2.5: Measured (a) phase shift ( ); (b) S11 and S21 in the down-state; (c) S11 and S21 in the up-state, d) SEM picture of the fabric ated device on silicon. The DMTL comprises of 11 bridges (40m wide) spaced at 700m (total length = 7.84mm). The figure of merit for the phase sh ifter is the phase shift per dB ( /dB); this figure is achieved by dividing (2.21) by (2.1 7). Figure 2.6 (a) shows a measured /dB of 97/dB and indicates good agreement with the mode led data from 1-30GHz. However, for frequencies greater than 30GHz the model data is 10-15/dB higher than the measured value. This is because the cl osed-form equations for the conductor loss of the uniform CPW lines sections ( ) used in the ADS circuit simulato r under estimates the measured data. Usually, this is adjusted by multiplying with a constant ( Fc) determined by fitting the model to the measured data. No compensation was used in the modeled data shown in

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19Figure 2.6 ( Fc=1). A detailed analysis of CPW conductor loss and its effect on phase shifter performance is discussed in Chapter 3. The change in bridge capacita nce also changes the characteristic impedance, as indicated in (2.7). This effect can be seen in Figure 2.5 (b) in which the peak in the low-frequency reflection coefficient is seen to change from -18.4 to -12.7 dB. This peak in reflection coefficient occurs at a frequency where the DM TL is a quarter-wave length long and the input impedance, seen from the 50 feed line, is at a maximum given by: 250inZ Z (2.22) Where Z is the characteristic impedance of the DMTL. Thus, the characteristic impedance of the DMTL changes from 56 to 48 The measured DMTL in Figure 2.5 has a capacitance ratio ( Cdn= Cup) of approximately 1.15-1.2, so the impedance change is relatively small. However, if this capaci tance ratio could be made much larger ( Cr >5), the characteristic impedance of the DMTL wo uld change by significant amounts causing undesirably large refl ection coefficients. Frequency (GHz) 010203040 Phase shift per dB ( /dB) 0 30 60 90 120 /dB (meas) /dB (model) Figure 2.6: Comparison of phase shift per dB between measured a nd modeled DMTL phase shifter. In this case, the DMTL should be designed such that the variation in characteristic impedance results in the same maximum allowa ble reflection coefficient in the low and high bridge capacitance states. For example, if it is desired to have the maximum

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20reflection coefficient below -15 dB, then th e characteristic impedance should be 60 in the low capacitance state and 42 in the high capacitance stat e. In general, the upper and lower bounds of the characteristic impedance, for a given reflection coefficient, are given by: 11 22 1111 00 111111 11luldSS ZZ and ZZ SS (2.23) Where Zld and Zlu are the DMTL impedance in the high and low capacitance states, respectively. Using (2.7) and (2.23), the minimum and maximu m bridge capacitances are found to be: 1111 22 111111 11 5050tt mintmaxtsLSsLS CsC and CsC SS (2.24) Using (2.24), the capacitance ratio Cr is found to be: 22 11 11 22 11 111 50 1 1 50 1o max r min oS Z S C C C S Z S (2.25) Where ottZL/C is the characteristic impedance of the unloaded transmission line. Figure 2.7 shows this capacitance ratio versus the maximum allowable reflection coefficient for different unloaded-line impedances. It is no ted that the capacitan ce ratio is independent of the substrate dielectric constant. Furtherm ore, this calculation is based on the lowfrequency impedance and does not account for the effects of approaching the Bragg frequency. It is seen that the usable capacita nce ratio for a maximum reflection of -13 dB is around 3 for a 100 unloaded impedance. The Bragg frequency is an important design parameter and in troduces non-linearity in if fB is close to the maximum frequency of oper ation, thereby reducing the bandwidth of a DMTL as a TTD phase shifter. For the design parameters used in Figure 2.5 and using (2.21) and (2.7) the no n-linear effects due to fB are shown in Figure 2.8. As seen from this figure, for fB=1.5 fmax the linear range of operation is lim ited to less than 20GHz, while the

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21bandwidth is improved up to 25GHz if fB=1.8 fmax. Furthermore, the loaded and the unloaded impedance fall off quickly when fB is closer to fmax as noticed in Figure 2.9. Therefore, to increase the linear range of operation, fB should be increased ( fB 2 fmax). This is achieved by decreasing the spacing between the bridges. The spacing (s) is obtained by solving (2.7) and (2.8), with the assumption that fB is defined at the lowest impedance state ( Zld or high capacitance state). ld BoeffZc s fZ (2.26) Maximum S 11 (dB) -20-18-16-14-12-10 C r =C max / C min 2 4 6 8 10 12 Z =90 Z =80 Z =100 Z =120 Figure 2.7: Capacitance ration versus maximum allowable S11 (dB) for unloaded impedances of 80, 90, 100, and 120 Frequency (GHz) 010203040 (deg) -300 -250 -200 -150 -100 -50 0 Linear Approximation f B =1.5 f max f B =1.8 f max Figure 2.8: Effect of Bragg frequency on the linear range of fmax= 40GHz, Zlu=61 s=700m.

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22 Frequency (GHz) 020406080 Z lu and Z ld 0 10 20 30 40 50 60 Z ld ( f B =1.5 f max ) Z ld ( f B =1.8 f max ) Z lu ( f B =1.5 f max ) Z lu ( f B =1.8 f max ) f B Figure 2.9: Effect of Bragg frequency on th e loaded (solid lines) and unloaded impedance (dashed lines) for fB=1.5 and 1.8 fmax. The model parameters used in Figure 2.5 is used herein. 2.5 MEM Capacitor Design The actuator system used to move the MEMS switches in this work is the electrostatic force. The electrostatic force between the ME MS switch and the sign al conductor of the transmission line is the result of a simple voltage potential between them, as exists between the plates of a capacitor under voltage [26]. This force is found by evaluating the power delivered to the time dependent ca pacitance of the MEMS switch [56]. The capacitance of the MEMS switch is given by: o bfWw CC h (2.27) where W is the width of the signal conductor, w is the wi dth of the MEM bridge, and h is the suspended height as shown in Figure 2.6 (b). The total capa citance of the bridge to the signal conductor is a combination of the para llel plate approximation and the component (Cf), which accounts for the fringing fields. Typically, the value for Cf is found by fitting the two port [S]-parameters of the model (Figure 2.4 with s=0) wi th a full wave electromagnetic simulation. In this work, Cf values were found to vary within 20% to 25% of Cb. The applied force to the MEMS switch is show n below and can be written in terms of the switch’s physical dimensions usin g the capacitance equation above:

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23 22 211 22odCh Ww FVV dh h (2.28) By equating electrostatic force in (2.28) to th e mechanical restoring force of the capacitor at height h, and solving for th e voltage, a closed form soluti on versus the applied voltage up to an instability point is found to be: 2 2 21 2 2o o o oWw Vkhh h khhh V Ww (2.29) Where, ho is the original height, k is the spring constant of the MEMS bridge. The general expression for a suspended beam is [33]: 3 3281 3211 2 22wt Ewt k Lx Lxx (2.30) Where, x =W/L, E is the Young’s modulus of the bridge, is the biaxial residual stress on the bridge, t is the thickness of the bridge, is the Poison’s ratio, L is the length of the bridge. The solution for the voltage versus bridge height is shown in Figure 2.10. In this figure, an instability at 2/3 ho due to the positive feedback results from the constant voltage effect on charge in the bridge. This instability point may al so be found by taking the derivative of (2.29) with respect to h. Because the switch membrane quickly snaps to the signal conductor at this instability po int, it is called the pull-in voltage, Vp. The data in Figure 2.15 below the instability point represen ts the new pull down voltage if, after pulling the switch all the way to the signal conductor, a mechanical stop is placed at a height below the instability point. By definition, the pull-in voltage Vp is found to be: 38 2 327o Po okh VVh Ww (2.31)

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24 Voltage ( v ) 0102030405060 Normalized Bridge height 0.0 0.2 0.4 0.6 0.8 1.0 = 5Mpa = 20Mpa = 80Mpa = 100Mpa 2/3 of h o Residual Stress, (Mpa) k (N/m) 52.6 2010.3 8041.5 10051.9 Figure 2.10: Normalized switch height vers us applied voltage (normalization factor = original height=2m) for L =500m, W =100m, w =80m, E =80GPa, =0.4, t =1m). The pull-in voltage represents a limitation fo r “analog” type DMTL phase shifter design. Due to this instability, it is clear that a switching ratio, Cr, is limited to 1.5 because beyond that voltage, the bridge snaps down and a very high (20-80) capacitance ratio results. For phase shifter based on DMTL topology require ty pical switching ratios (Figure 2.7) of 2-3. The fringing capacitance typically does not change with height, therefore, practical capacitance ratio is around 1.3. An “analog” design consists of any DMTL phase shifter designed for a maximum capacitance ratio of Cr= 1 3. Because the capacitance ratio can be adjusted to be anywhere from 0-1.3 based on the voltage applied, the phase shift which results can be considered analog due to th e infinite number of states obtainable. A more stable design is to use “digital” type tuning because the phase shift and the performance can be predicted wi th greater accuracy than for the “analog” alternatives. The DMTL phase shifter can be made “digital” in several ways; tw o are mentioned here. In the first method, a very thick dielectric is used to limit the travel of the MEMS switch. The capacitance of the MEMS switch in the up and do wn state is (ignoring the effect of fringing capacitance):

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25 groundground signal dielectric hd h Substrate Figure 2.11: Schematic of a digital impl ementation using very thick dielectric ( hd) for digital operation. 11 1 oor up dd oror updn drddWwWw C hhh WwWw C; C hhhh (2.32) Using (2.32) the capacitance ratio Cr (dnupC/C ) is plotted for nitride (r=7.6) and SiO2 (r=4). This method presents a couple of chal lenges, the first of which is the required dielectric thickness. A typical design with capacitance ratio of Cr = 2 5 and a suspended switch height, h of 1.5 to 2m is required for low-voltage el ectrostatic actuation. Using the equation above, oxide di electric must be 1.3-1.5m and the nitride dielectric must be 1.21.6m, which are unrealistically thick. Furthe rmore, thick layers underneath the MEMS switch present additional challenge in MEMS br idge fabrication. Since the sacrificial layer follows the contours of the materials below it a large step height change will result in additional stress in the bridge and one of the reliability concerns from a fabrication standpoint. One of the biggest challenges in using thick dielectrics is the switching ratio instability introduced. If the switch membrane and dielect ric layer below it are not perfectly smooth, the capacitance measured will be quite lowe r than the capacitance expected from the parallel plate approximation. Charge buildup in the dielectric can worsen this condition because moving charges in the dielectric ca use the membrane to move on top of the dielectric, causing the capacitance to chan ge with time. Since a stable down-state capacitance is required for a digital design, it may be argued that the thick dielectric method is not the best solution.

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26 h/h d 1.01.21.41.61.82.0 C r = C dn / C up 1.0 1.5 2.0 2.5 3.0 3.5 4.0 r =4r =7.6 Figure 2.12: Capacitance ratio versus no rmalized height of the dielectric. The second digital implementation method uses a static capacitor, Cs, in series between the MEMS switch and the ground conduc tor. The total load capacitance, CL, on the transmission line is the series co mbination of the two capacitors: bs L bsCC C CC (2.33) There are two states for the MEMS bridge: up and down (pulled down completely by the electrostatic force). When the switch is pulled down, the capacitance is on the order of 1 3 pF whereas in the up state it is on the orde r of 10-100 fF. Therefore, when the MEMS switch is in the down-state po sition, the loaded capacitance, CL, experienced by the line is dominated by the static capacitor, Cs, and CL Cbd Cs. When the MEMS switch is in the up-state position, the capacita nce seen by the line is Cbu in series with Cs. The distributed capacitance can therefore be “discretely” controlled by the independent choice of the MEMS switch upstate capacitance, Cbu and the static capacitance, Cs and tends towards Cbu. Since the desirable switching ratio is on th e order of 2-3, the bridge capacitance is designed to be equal to 1-0.5 times that of th e static capacitor. As a result of adding the static capacitor, the required MEMS switch loading capacitance beco mes larger and thus easier to fabricate. Furthermor e, in comparison to the thic k dielectric method, the stability of down state capacitance is greatly improv ed. The switching ratio could be anywhere between 20-80. The stabilization capacitor makes this factor relatively insignificant because

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27the static capacitance, Cs, dominates in the down-state posi tion and this capacitance can be consistently fabricated. g r o u n d W CsCb Cs t-line (> 50) MEM Capacitor Cb Cs/ 2 Cs/ 2 Figure 2.13 : Unit cell representation of a DMTL that utilize static capacitor in series with the bridge. This type of configuration is used in a “digital” type tuning. When discrete static capacitors are required, th eir loss is of importance, as will be described in the following section. The capacitors can be implemented using standard metalinsulator-metal (MIM) capa citors, or for higher Q, the MIM capacitors ca n be replaced with metal-air-metal (MAM) capacitors. The use of MAM capacitors for improving the Q is discussed in Chapter 3, where these high Q capa citors are used in the design of slow-wave phase shifters. 2.6 Non-Uniform Transmission Line Loade d Phase Shifter M odeling and Results NTL’s have been used widely in many applic ations that include im pedance matching [66], pulse shaping [67], and analog signal proces sing [68]. NTL’s also exist in many VLSI interconnection structures to provide smooth connections be tween high-density IC chips and the chip carriers [70], [71]. This section provides experimental results of distributed MEMS transmission line phase shifters that utilize non-uniform transmission line (NTL) co nnecting sections between MEM capacitors. The NTL based phase shifter use digi tal type varactor tuning as aforementioned and was designed on a 400m thick high resistive silicon substrate ( > 2000-cm). One of the advantages of using silicon as the substrate is that the net phase shift ( ) from equation (2.21) is directly dependent on eff Therefore, a phase shifter on a silicon

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28substrate results in more phase shift per unit length than a DMTL on a quartz substrate. Table 2.2 shows the design parameters for a DMTL phase shifter with S11 <15dB and fB 1.8fmax on three substrates. The optimum choices for unloaded impedance are approximately 107, 95, 71 for air, quartz, and silicon substrates. The optimization procedure is described in Chapter 3. Table 2.2: DMTL phase shifter with 360 phase shift for design parameters on air, quartz and silicon substrates. Substrate Air (r =1)Quartz (r =3.8)Silicon (r =11.7) W ( m) 30010030 S ( m) 10010060 Zo( ) 1079571 Cbo(fF) 1008627 Cr2.152.354.2 Length per 360 (mm) 12.89.37.4 fmax=35 GHz Improvement in is achieved by using NTL sectio ns between the MEM bridges. The schematic (unit cell) of two de signs is shown in Figure 2.14 (a) and the fabricated phase shifter (comprised of 10 cascaded sections) is shown in Figure 2.14(b). In order to use the transmission line model, the impedance variatio n between two discrete points is required and described by the following polynomial: 010cc oZ(x)Z()(kx), xl c (2.34) Where, l is the length of the non-unifo rm transmission line section. Zc(0) is the characteristic impedance at the input to th e NTL. The characteristic impedance at any given point is related to the line parameters by:

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29 () ()000(1) 00 () 0(1)t c t tttc tt t cLx Zx Cx where LxLCZkx LC Cx Zkx (2.35) In design 1, the impedance of a distributed line between two adjacent MEMS capacitor is increased in steps of 10 from 50 to 90 making it a 5–section stepped impedance transformer. Each impedance section is 145m long and the overall length of connecting sections is maintained at 725m. In design 2, a linear taper from 50 to 105 is used. For the two designs presented herein k=1.15 and k=1.52 for design 1 and design 2 respectively. These values of k were chosen such that th e impedance at the mid-point is close to the optimal impedance value for silicon (=70 ). In order to derive the two port S-parameter for the unit cell [S]UNIT, the S-matrix for the NTL ([S]NTL) is required. One approach in solving for [S]NTL is based on a lossless TEM transmission line model. Usin g the transmission line parameters, equation (2.35), and adopting phasor notation for voltage and the current the modified Te legrapher’s equation can be written as: 2 2 2 2 2 21 000 1 000c tt c c tt cZ(x) VV L()C()V Z(x)xx x Z(x) II L()C()I Z(x)xx x (2.36) The solution to (2.36) exists but requir es complex algebraic operations with the involvement of Bessel functions. From (2 .36), the [ABCD] parameters for the NTL ([ABCD]NTL) can be solved. The overall [ABCD] parameter ([ABCD]UNIT) is obtained by multiplying [ABCD]NTL and [ABCD]MEM. Using matrix conversion, [ABCD]UNIT can be transformed to obtain S-parameters of the tw o port network. A simpler alternative to the matrix conversion approach is to use a comm ercial full wave electromagnetic (EM) solver. Agilent’s planar EM solver which is based on Method of Moments (MoM) approach is used

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30for extracting the S-parameter of the unit cell. The S-parameters obtained from EM simulation for a unit cell are th en cascaded in a circuit si mulator (ADS) to predict the performance of the phase shifter. (a) (b) Figure 2.14: (a) Schematic and fabricated unit cell of two NT L capacitively loaded phase shifter designs; (b) Photograph of th e fabricated device (design 1), a 200m long high impedance ( Zo=66 ) line is used to transition from a 50 feed to the DMTL sections. The NTL phase shifter was fabricated on high resistivity silicon. Th e fabrication procedure is illustrated in Appendix C. Measurements we re performed from 5–40GHz using a Wiltron 360B vector network analyzer and 150m GGB microwave probes. A Thru–Reflect–Line (TRL) calibration was performe d using calibration standards fabricated on the wafer. A high voltage bias tee was used to supply volt age through the RF probe to avoid damaging the VNA test port.

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31Figure 2.15 (a) shows the comparis on between measured and simulated for the two NTL designs (design 1 and design 2). The measured and simulated for the DMTL (or uniform Zo =70 ) on silicon is also shown for comparison. The agreement between measurement and simulation results is good (within 5%) through 40 GHz. The worst-case S21 is typically observed when the line is load ed (high capacitance st ate) and found to be approximately -3dB for design 1 and -4dB for design 2 at 40GHz. Frequency (GHz) 10203040 (deg) 0 100 200 300 400 500 Uniform Z Design 1 Design 2 Frequency (GHz) 10203040 S 21 (dB) -5 -4 -3 -2 -1 0 Design 1 Design 2 Uniform Z (a) (b) Frequency (GHz) 10203040 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Design 1 Design 2 uniform Z (=70 Down State Frequency (GHz) 10203040 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Design 1 Design 2 uniform Z (=70 Up State (c) (d) Figure 2.15: (a) Measured differential for the two NTL phase shifter (design 1, design 2 and DMTL with Zo =70 ) on 400m thick high resistive silicon. The solid line for curve represents EM simulation data and the dash ed lines represent measured data; (b) Worstcase S21 for the phase shifter; (c) Measured S11 in the down state; (d) Measured S11 in the up state.

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32The measured S11 plot in Figure 2.15 (c) and (d) indicate S11 < -10dB in both the states up to 35GHz for all the designs. Beyond this frequency, S11 for the NTL designs is higher than -10dB and it is also evident from the pha se shift plot where the non-linearity in is more prominent (equation 2.21). Table 2.3 shows the comparison of th e three designs at fmax=35GHz. When compared with DMTL performance, de sign 1 and design 2 provide 15% and 21% improvement in at 35GHz, respectively. With respect to the uniform Z performance, the phase shift per dB figure of merit ( / dB) for design 1 is relati vely unchanged, while there is 11% decrease in /dB for design 2. This is beca use the NTL designs provide a nonconstant rate of change in the loaded impeda nces. As a result, the Bragg frequency for the NTL designs is much lower than for the uniform Z design. This is evident from Figure 2.16 which shows the extracted effective characte ristic impedance in both the states ( Zeff down and Zeff up) for the NTL unit cell (Figure 2.14) and the uniform Z design under the loading conditions specified in Table 2.3. It is clear from this figure that the NTL designs show a non-linear increase in Zeff for frequencies greater than 25GHz, while, Zeff is almost constant through 40GHz for uniform Z unit cell. Substituting Zeff for Zo in equation (2.21), it is clear that for a given loading conditions, the phase shift increases as characteristic impedance Zo increase. Therefore, more is seen for NTL designs when compared to uniform Z phase shifter. Table 2.3: Comparison of the NTL phase shif ter performance versus DMTL phase shifter with Zo=70 design 1design 2 Uniform Z=70 deg 274 296 233 Max S11(dB) -11.2-10.3-12.5 Worst-case S21(dB) -1.9-2.3-1.6 dB 144 /dB128 /dB145 /dB fmax = 35GHz; Cr = 3.3 (=76fF/23fF) Assuming the MEM bridge to be ideal, th e conductor loss of the transmission line calculated using (2.12) with Gt =0 is approximately equal to 1.15dB at 35GHz (for the uniform Z phase shifter). When compared with th e measured data in Table 2.3, it is seen

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33that the loss contributed by the static MIM capacitors is approximately 0.45dB. The increase in insertion loss for the NTL desi gns is due to the Bragg frequency effects as aforementioned. Frequency (GHz) 10203040 Z eff (ohm) 30 40 50 60 70 80 90 100 design 1 design 2 Uniform Z Down state Frequency (GHz) 10203040 Z eff (ohm) 30 40 50 60 70 80 90 100 design 1 design 2 Uniform Z Up state (a) (b) Figure 2.16: a) Extracted effective impedance ( Zeff down) in the down state; b) extracted effective impedance in the up state ( Zeff up) for the capacitively loaded NTL unit cell and uniform Z unit cell. 2.7 Chapter Summary The theory of Distributed MEMS transmission line is presented and measured up to 40GHz. The DMTLs are fabricated using CPW lines on a 425 m thick silicon substrate with MEMS bridges periodically spaced across the line. An analytic model and a circuit model developed herein agrees well with the measured results. The circuit model consists of a physical length of transmission line for the CPW line and a ca pacitor-inductor series combination to model the MEMS bridge. The circuit model has also b een used to quantify the accuracy of the measured data. Furthermore, for a reliable oper ation a digital type t uning is preferred and achieved by using a series-shunt capacitor arrangement. This capacitor design was used in the phase shifter constructed us ing non-linear transmission lin e. The measured results for the phase shifter show good agreement with the EM simulated results.

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34CHAPTER 3 Cascaded Slow-wave Phase Shifter Design and ResultsThis chapter presents the design and optimization of a TTD multi-bit MEMS phase shifter based on impedance-matched slow -wave CPW sections on a 500 m thick quartz substrate. The development of electronically variable phase shifters has been driven primarily by their use in phased array radars, although they are now used in a wide range of systems including communications and meas urement instrumentation [27]. Most phase shifters currently used can be di vided into either ferrite phase shifters or semiconductor device phase shifters. The ferrite based phase shifters typically work well from 3 GHz to 60 GHz with switching times on the order of a few microseconds to tens of microseconds [21, 22]. Most ferrite based phase shifters are not monolithic and require large switching energies but can handle kilowatts of RF power [9]. Recently, there has been research into the use of the ferroelectric material barium strontium titanate [Ba1~xSrxTiO3 (BSTO)] to produce planar phase shif ters [12]. The designs demonstrate 44 /dB insertion loss at 14.3 GHz, however, they require very high bias voltages (250-400 V) [46]. In [61] authors have demonstrated a BSTO based phase shifter with 90 /dB with lower tuning voltage from 20-160V. On the other hand, semiconductor device based phase shifters have been used up to 100 GHz with switching times well under 10 s [2, 7, 16, 27, 32, 39, 49, 52, 59]. These devices are either hybrid or monolithic with switch ing powers on the order of milliwatts. The hybrid devices (p-i-n or varactor diodes) can handle up to a kilowatt of RF power; however, the monolithic devices can only handle RF powe r on the order of milliwatts to one watt [27]. There are many different designs for the semiconductor device based phase shifters. Some of the more prominent designs are switch ed-line phase shifters [52], loaded-line phase shifters [22, 23], branch line or 3-dB coupler based phase shifters [39, 7, 59], and high-

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35pass/low-pass phase shifters [32]. The load ed-line and high-pass/low-pass type phase shifters are inherently limited to at most 67% bandwidth, where as the switched-line phase shifter is true-time delay with the bandwidth lim ited by the high-frequ ency operation of the switches. Typical figures of merit for the semiconductor device based phase shifters are 144 /dB at 1 GHz [32], 211 /dB at 12 GHz [16], 86 /dB from 16-18 GHz [7], 60 /dB at 60 GHz [39], and 41 /dB at 94 GHz [59]. Recently distributed true-time delay phase shif ters were demonstrated in [31, 32]. These devices are very similar to the distributed MEMS transmission lines, but use varactor diodes rather than MEMS bridges for the variable capacitance. The phase shifters developed in [31] have shown good performance with 86 /dB insertion loss at 20 GHz, or 4.2 dB insertion loss for 360 phase shift. However, the millimeter wave performance of these devices is limited by the se ries resistance of the diodes. For broad band and low loss operation, two co mmonly used true time delay (TTD) phase shifter designs are the switched network a nd the distributed MEMS transmission line (DMTL) [1]. The switched network consists of multiple delay networks that are typically switched using DC-contact series switches. The performance of the switched network is usually better than the DMTL up to 30GHz; however, for broad band operation beyond 30 GHz the DMTL type design is preferred [2].Th e DMTL design has been demonstrated from X-band to W-band [2-6]. Typical measured results for 2-bit X and Ka-band designs on quartz indicate 168 /dB at 13.6GHz and 128 /dB at 37.7GHz respectively [5]. Similar 2-bit and 4 bit designs demonstrate a phase shift of 130 /dB at V-band [2]. The W-band designs in [6] present a slightly lower phase shift (93-100 /dB) on a glass substrate. However, suggestions for improving the phase shift up to 200 /dB were also presented. In [2-6], metal-air-metal capacitors are used to mini mize loss. Table 3.1 shows the measured DMTL performance of the current state of art DMTL phase shifter.

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36Table 3.1: Comparison of current state-of-the-art TTD phase shifter. SubstrateQuartz (Barker/Rebeiz)Glass (Nagra/York)Quartz (Hayden/Rebeiz) S11-13dB-9.6dB-12dB S 21-2dB-1.7dB-2.1dB ( ) 120270180 Length (L)5.4mm8.9mm5.6mm Spacing ( s ) 360um780um400um Freq (GHz)603537.7 As seen in Chapter 2, the DMTL devi ces are often designed such that the S11 is less than 10dB in both phase states, up state (low capacitance state) and down-state (high capacitance state) positions. From equation (2.21), it is clear that for a given unloaded impedance Zo, increases when the loaded impedances (in the high and low capacitance states) are symmetrically farther away from 50 Using (2.21) and assuming no dispersion, the variation in versus maximum allowable S11 is shown in Figure 3.1(a) for three frequencies on a quartz substrate. It is seen from this figure that the amount of phase shift is proportional to the difference in the load ed and unloaded impedances. For example, if S11 less than -20dB is desired then the maximum is only 186 /cm at 50GHz and the loaded impedances should vary by a factor of 55/45.4 Achieving this small variation in the impedance requires tight control over the value of the MEM capacitor. Assuming s =200 m and Zo=95 the capacitance values in the low and high impedance states is approximately /29fF/27fFmaxminCC from Figure 3.1 (b). Furthermore, from this figure it is seen that for the same operating condition, fB decreases from 131/118GHz as the constraint on S11 decreases from -20 to -10dB, indicating that th e usable range of the phase shifter is reduced by the same ratio. This limitation in the capacitively-loaded de sign restricts the amount of achievable per unit length in light of impedance matching co nsiderations. Therefore, a true time delay MEMS phase shifter topology that overcomes th e limitations of the ca pacitor-only DMTL is presented herein. The topology uses cascad ed, switchable slow-w ave CPW sections to

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37achieve high return loss in both states, a large per unit length, and phase shift per dB that is better than previously reported performance. S 11 (dB) -20-18-16-14-12-10 (deg/cm) 0 100 200 300 400 500 f=10GHz f=25GHz f=50GHz 55565861 64 69 45444240 3836 Capacitance (fF) 2224262830323436 S 11 (dB) -20 -15 -10 f B (GHz) 115 120 125 130 135 C min C max f B (a) (b) Figure 3.1: (a) Net phase shift ( ) versus maximum allowable S11 (dB) assuming CPW on quartz. The impedance corresponding to S11 specifications is listed at the top of the plot; (b) S11 as a function of minimum and maximum ca pacitance values for the MEM bridge. The plots pertain to s =200 m and Zo=95 3.1 Slow-wave Unit Cell Design and Fabrication The MEM slow-wave unit-cell shown in Figure 3.2 is designed to provide small variations in the impedances around 50 with a per unit length that is greater than a capacitivelyloaded DMTL that has a worst-case S11 near -10 dB. The unit-cell is 460 m long and consists of two bridges on each ground plane and a shunt bridge that connects the ground planes and is suspended over the center conductor. In the normal state (Figure 3.2a), the bridges on each ground plane are actuated (s olid lines) with electrostatic force applied through SiCr bias lines, while the shunt bridge is in the non-actuated state (dashed lines). In this normal state the signal travels directly from the input to the output. In the slowwave state (Figure 3.2b), the bridges on the ground plane are not-actuated while the shunt bridge is actuated to contact the center conductor. The signal thus travels the longer path through the slot in the ground plane, thereby increasing the time delay. Furthermore, in the slow-wave state the increase in the per-uni t length inductance is compensated by the

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38increase in the per-unit length capacitance (due to the wide center conductor) thereby maintaining the impedance close to 50 Gnd Plane Beam Normal State Input Output S 460 m SiCr Bias Lines Si3N4 gnd isolation layer Shunt Beam Slow-wave State 460m Input Output W (a) (b) Figure 3.2: Schematic of the slow-wave structure a) Normal state; b) Slow-wave state (the SiCr bias lines are not shown). The slow-wave MEM devices used in this work are fabricated on a 500 m thick quartz (r = 3.8, tan =0.0004). The outline of the fabrication process is shown in Figure 3.3. The SiCr bias lines are defined first using the lifto ff technique by evaporating a 1000 layer of SiCr using E-beam evaporation. The measured line resistivity is approximately 2000 /sq. Next a 4000 RF magnetron sputtered SixNy layer is deposited and patterned to form the ground isolation layer. This layer is located where the SiCr bias lines enters the ground conductor (see Figure 3.3(c)). Next the CPW lines are defined by evaporating a Cr/Ag/Cr/Au to a thickness of 150/8000/150/1500 using liftoff technique. Next the sacrificial layer (MICROCHEM PMMA)1, is spin coated and etched in a reactive ion etcher (RIE) using a 1500 Ti layer as the mask. The PMMA layer thickness can be varied from 1.5-2 m by varying the rotational speed of the spinner from 2500-1500 rpm. In this work, the thickness of PMMA is optimized to provide a height of 1.5-1.7 m (for low actuation voltage). The Ti layer is removed and a 100/2000 Ti/Au seed layer is evaporated over the entire wafer and patterned with photoresist to define the width and the spacing of the MEM bridges. The bridges are then gold-electroplated to a thickness of 1 m, followed by removal of the top photoresist layer and seed layer. The sample is then annealed at 105 and 120 to flatten the bridges before removing the sacrificial PMMA

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39layer. The sacrificial PMMA layer is removed and critical point drying is used to release the MEMS structures. Figure 3.3: Details of the fabrication proces s for the MEM structures. The illustration shows a perspective view of a slow-wave unit cell. 3.2 Modeling of Slow-wave Unit Cell The model for a slow-wave unit cell in both the states excluding the parasitics due to the bridge and the discontinuities is shown in Figure 3.4. In the normal state, the model comprises of transmission line of length s with a capacitor to ground due to the shunt bridge ( Cbs). In the slow-wave state, the model comprises of two shunt capacitors to ground due to the ground-plane bridges ( Cbg) separated by the transmission line of length s1 (which is equal to the total leng th through the slot). Using the equations describing the DMTL, the impedance, propagation velocity, and the Bragg frequency for each states of the slow-wave unit cell is given by: 1 1 tnts ns tnbstsbgsLsL Z Z sCCsCC (3.1) 1 11 pnps tntnbs tstsbgs s v v sLsCC sLsCC (3.2)

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40 1122BnBs tntnbs tstsbg sLsCC sLsCC (3.3) where, Ltn, Ctn is the per unit length inductance and ca pacitance in the no rmal state. While, Lts, Cts are the per unit length inductance and capacitance in the slow-wave state. Cbs and s is the bridge capacitance and sp acing between the shunt bridges. Cbg and s1 is the bridge capacitance and spacing betwee n the ground plane bridges. W Figure 3.4: Ideal model for the slow-wave unit cell in both the states. This model does not take into account the parasitics due to the bridge and the discontinuities. The per unit length capacitance and the inducta nce in both the states, has the form given by [42]. 22 tneffontseffos tntnontstsosC/cZ C/cZ LCZ LCZ (3.4) in which eff is the effective dielectric consta nt of the transmission line and c is the free space velocity. Since the slow-wave is constructed using a CPW line, Zo and eff can be related to the physical line paramete rs using conformal mapping [21]:

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41 1 1 21 21 1230 1 1 2 4 4o r effKk Z Kk eff KkKk KkKk W sinh W h k;k G G sinh h (3.5) where, W is the width of the center conductor, G is the ground-to-ground spacing in the normal state, and h is the substrate thickness. The variables W and G are replaced with W1 and G1 for calculating the impedance in the slow-wave state. The design of a slow-wave phase shifter requires the specification of the maximum frequency of operation ( fmax) or Bragg frequency ( fB), dielectric constant (r) and the normal state impedance (>50 ). From these specification s, the maximum ground-toground spacing (W ) in the slow-wave state is calculat ed using (3.6). A ground-to-ground spacing ( W ) of /8 is typical of CPW designs in orde r to limit radiation loss, however, as mentioned in Chapter 2, the periodic struct ures has negligible radiation loss. Therefore a larger W less than /5 is usable; in this work W is set to 65 which translates to / (5.5) at fmax. The total length along the midpoint through the slot is equal to 2ABSS (3.7), where SA is the length of the slot in the north-south direction and SB is the length of the slot in the east-west direction (Figure 3.4). Since the overall length of the unit cell cannot exceed s set by the Bragg frequenc y, the maximum value for SB = s. However, this spacing is fu rther reduced by a factor of 2P S required to accommodate the two ground plane pede stals. In this work, SP is set to 80 m. The approximate signal path through the mid-point in the slot is calculated using (3.8). Therefore, the maximum value for G1 is 2SP. 5555maxeffc W ..f (3.6)

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42 12 2 22AB BsSS WS W S (3.7) 11 122 222PWS W GW ssS (3.8) In equation (3.8), the separation ( s ) is dependent on simultaneous equations (3.1) and (3.3). The Bragg frequency, fB, is selected as per guidelines pr ovided in Chapter 2. Using (3.1) through (3.3), the separation between the shunt bridges and th e bridge capacitance is given by: 2 tn bstn Beff nL c s CsC f Z (3.9) It is seen from (3.9) that s is inversely proportional to the Bragg frequency (fB) and the effective dielectric constant of the substr ate. For a given ground-to-ground spacing (G), and fB=2.6fmax=130GHz, s=734 m on air, 474 m on quartz and 291 m on silicon substrate at fmax. Using (3.9), and for an im pedance matched condition (Zn=50), Figure 3.5 (a) shows Cbs (fF) as a function of W (and assuming G=300 m) for three different substrates (r=1, r=3.8, r=11.7). Figure 3.5 (b) shows Cbs versus W for two different values of G on a quartz substrate. Width ( m) 50100150200250 C bs (fF) 50 100 150 200 r=1 r=3.8 r=11.7 G=300 m Zo=190 Zo=78 Zo=123 Zo=51 Zo=75 Zo=31 Width ( m ) 50100150200250 C bs (fF) 50 100 150 G=500 m G=300 m Quartz (r =3.8) Figure 3.5: a) Cbs versus center conductor width, W (and G=300 m) for air, quartz, and silicon substrates; b) Cbs versus W for two ground-to-ground spac ing on quartz substrate. fB is set to 2.6fmax=130GHz.

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43The impedance matched condition is also a pplied to the slow-wave state and the ground plane bridge capacitance (Cbg) is given by (3.10): 1 2 ts bgts sL CsC Z (3.10) Using (3.2), the phase constants in both the states and the net phase shift ( ) is derived in (3.11) and (3.12) respectively: 1360 1deg/section 2 360 1deg/section 2bs ntntn pntn bg ststs pstsC sLC vC C sLC vC (3.11) 1360 11deg/section 2ns bg bs tntntsts tntsC C sLCsLC CC (3.12) From (3.8), it is seen that maximum value of G1 is related to s, and varies as 1eff/ (Figure 3.6). It is seen from this figure that the maximum value for G1 with fB=2.6 fma (130GHz) on silicon is equal to 200m. Using this equation and (3.5)-(3.10), the phase shift per millimeter ve rsus the conductor width ( W1 ) for the slow-wave unit cell is calculated on silicon, quartz, and air at 50GHz for the specifications listed in Table 3.2. r 12345678910111213 maximum G 1 ( m) 100 200 300 400 500 600 700 Figure 3.6: Maximum value of G1 versus substrate dielectric constant assuming fB =2.6 fmax=130GHz.

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44In this calculation, two different total CPW widths G (300m and 500m) are plotted (Figure 3.7) keeping the spacing G1=300m and the width W =100m constant. As can be seen from Figure 3.7, for a given G the phase shift is much larger for a narrow center conductor width (high impeda nce). This is due to la rger loading capacitance Cbg/ s1 needed to load the line to 50 and therefore the bridge capacitan ce has a larger effect on the phase velocity. It is observed for the same substr ate, at two different impedance values with different total CPW widths G results in same phase shift. For instance, on quartz, for W/ G1=100/300m, W1/ G =109/300m (91), = 150/mm. The same is obtained for W1/G=84/500m (123). Furthermore, for a given W1, W and G1, it is seen that increases as G decreases. For example, for the same W/ G1 ratio on quartz and with W =100m, /mm increases from -124 ( G =500m) to -160 ( G =300m). Therefore, reducing the spacing G results in larger However, one of the limitations in reducing the spacing G is that the pull-in voltage ( Vp) required to actuate the shunt bridge increases as G decreases. For a 1m thick Au platted bridge suspended 2m above the CPW line with residual stress =30Mpa, =0.42, width=100m, and a Young’s modulus E=90GPa; Vp=20V for a 300m long bridge while, Vp= 33V for 200m long bridge. Therefore, for reasonable pull-in voltages Vp ( 30V), the total CPW width G is designed to be 300m. Figure 3.8 shows /mm versus the conductor width ( W ) for the slow-wave unit cell on silicon, quartz, and air at 50GHz for the sp ecifications listed in Table 3.2. In this calculation, two differe nt total CPW widths G (300m and 500m) are plotted keeping the spacing G1=300m and the width W1=100m constant. As can be seen from Figure 3.8, for a given G the phase shift is much larger fo r a wide center conductor width (low impedance). This is due to smaller loading capacitance Cbs/ s needed to load the line to 50 and the bridge capacitance has smaller effect on the phase velocity in the normal state ( n). Therefore, the difference in phase constants be tween the two states increases (see (3.12)). Furthermore, for a given W1, W and G1, it is seen that increases as G decreases. For example, assuming W1/ G1= 100/300m on air, /mm= -193 for W / G =100/300m (147) and /mm=-160 for W / G =100/500m (179).

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45 Width= W 1 ( m) 406080100120140160180200 (deg/mm) -350 -300 -250 -200 -150 -100 -50 0 G =500 G =300 234 210 179158 149 135 192 167 142 203179 147125 116 99 161 135 107 W =100 m G 1 =300 m Width= W 1 ( m) 406080100120140160180200 (deg/mm) -350 -300 -250 -200 -150 -100 -50 0 G =500 G =300 152136 116103 97 88 125 109 92 132 116 9581 75 64 104 87 69 W =100 m G 1 =300 m Width= W 1 ( m) 405060708090100 (deg/mm) -350 -300 -250 -200 -150 -100 -50 0 G =300 G =180 94 88 77 72 84 80 74 81 75 64 58 71 67 61 W =100 m G 1 =300 m Figure 3.7: Calculated phase shif t per mm versus the conductor width ( W1) at 50GHz for (a) Air, (b) Quartz, and (c) silicon with G1=300m and W=100m. The maximum width W is equal to /5.5 in each case. The impedance co rresponding to the center conductor width is given at the top of each plot. From these figures it can be seen that phase shift ( /mm) increases as W decreases, while increases as W1 decreases for a given spacing G and G1. The following section presents optimum widths for W1 and W such that the figure of merit /dB is maximized. Table 3.2: Specifications used in Figure 3.6. Zn =Zs50 fB =2.6 fmax130GHz

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46 Width= W ( m) 406080100120140160180200 (deg/mm) -250 -200 -150 -100 -50 G =500 G =300 W 1 =100 m G 1 =300 m 234210 179158 149 135 192 167 142 203179 147125 116 99 161 135 107 13 2116 9581 75 64 104 87 69 Width= W ( m) 406080100120140160180200 (deg/mm) -250 -200 -150 -100 -50 152 136 116103 97 88 125 109 92 W 1 =100 m G 1 =300 m G =500 G =300 Width= W ( m) 405060708090100 ( deg / mm ) -250 -200 -150 -100 -50 G =300 G =180 94 88 77 72 84 80 74 81 75 64 58 71 67 61 W 1 =100 m G 1 =300 m Figure 3.8: Calculated phase shift per mm versus the center conducto r width at 50GHz for (a) Air, (b) Quartz, and (c) silicon with G1=300m. The maximum width W is equal to /5.5. The impedance corresponding to the cen ter conductor width is given at the top of each plot. For example, for G=300m on silicon, Zo varies from 203 to 99. 3.3 Optimization One of the first reported optimi zation methods based on the work of Rodwell et al. was to minimize the loss in distributed non-linear CP W lines [20]. The distributed line analysis was significantly extended to optimize for the best pha se shift by Nagra et al. [21]. Barker et al. [22, 23] applied a different method to a DMTL in which the MEM device was optimized to provide maximum amount of phase shift for the minimum amount of insertion loss. In this thesis, a method similar to [22] is applied to the slow-wave unit cell so that maximum /dB is obtained. In order to carry out this optimization, analytic expressions for both the phase shift per unit length and the in sertion loss per unit length are required. per

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47unit length is calculated usin g (3.12) and the conductor loss ( ) per unit length is calculated using conformal mapping [21] and reproduced in (3.13). 2 28686 41 2ln 1 41 8686 41 2 ln 1 41seff o seff o.R Wk (W,S) tk SKkKkk .R Wk S dB/length Wtk SKkKkk (3.13) where K ( k ) is the complete elliptic integral of the first kind, 2 kW/(WS), 21 kk, t is the metal thickness, Rs is the surface resistance given by 12 / sRf and is the conductivity of the metal. To verify the accuracy of (3.13), measured S21 data for uniform CPW line on 500 m thick quartz and on 425 m thick high resistive silicon ( 2500 -cm) is compared with the loss obtained from (3.13). Figure 3.9 shows the measured and calculated loss versus frequency for a 300 m total width CPW line with a 100 m wide center conductor on quartz (Zo = 95 ) and on silicon (Zo = 58 ). The reference impedance for the measured data is set to the Zo of the line. It is seen from this figure that (3.13) unde restimates the measured loss on quartz and on silicon substrate as evidenced by the correct ion factor required to match the measured data. The 1 m thick metal line is comprised of evap orated Cr/Au layer and the skin depth ( 1 /f ) at 50GHz is approximately 2.8, while the 3 m thick lines are Au electroplated74110 S/m [22]. According to (3.13) if the metal thickness is increased from 1 m to 3 m the loss would decrease by a factor of 1.12. However, this is not seen in measured data for quartz (Figure 3. 9). This is because (3.13) assumes the metal thickness t to be greater than 4 [27]. For the metallization used herein this condition is violated for freq 30GHz. It was experimentally found that the correctio n factor is not constant versus CPW pitch (Appendix B), therefore, (3.13) is used withou t any modification and therefore will predict

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48higher /dB than measured data. However, fo r calculating the optimal CPW center conductor width ( W and W1) the trend is sufficient. Apart from the conductor loss, the unit cell also has loss due to contac t resistance of the bridge, conductor roughne ss, and leakage via the SiCr bias lines. These effects are difficult to calculate, and as will be seen in the next section, even with full wave EM simulation data a perfect match is not possi ble. Therefore, (3.13) is used to predict the trend of loss versus center conductor width. Frequency (GHz) 01020304050 Loss (dB/cm) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.53 Eq 3.13 (t=1mm) Measured (t=1mm) 1.43 Eq 3.13 (t=3mm) Measured (t=3mm) S / W / S =100/100/100 Frequency (GHz) 01020304050 Loss (dB/cm) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.2 Eq (3.13) (t=1mm) Measured (t=1mm) S / W / S =100/100/100 Figure 3.9: Measured and calculated uniform CPW line loss versus frequency for a 300 m total width for, a) quartz ( Zo=95 ), b) silicon (58 ). The reference impedance for the measurement is set to the Zo of the line. The bridge resistance is calculated usin g (3.14) and included in the analysis: 22 22868 2 8682 2bsnbs bs bgsbg bg.RZC .RZC (3.14) Where, Rbs and Rbg are the shunt and ground plane brid ge resistance. The loss due to the bridge resistance versus frequency is show n in Figure 3.10 for two values of bridge resistance of 0.1 and 0.2 These values for Rbs and Rbg are typical of a MEM bridge with similar footprint [40]. The calculation is for a 300 m total width ( G = G1=300 m) with a 100 m width center conductor ( W = W1=100 m) ( Zo = 95 ). Also shown in this figure is the variation of loaded line loss and the lo ss due to bridge resistance versus center

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49conductor width (assuming G = G1=300 m) at 50GHz on quartz. Furthermore, this calculation is for the slow-wave state, since maximum loss is typically seen when compared with the normal state due to longer signal pa th. From this figure the loss due to bridge resistance ( Rbs) at 50GHz is only 0.05dB or < 10% of the CPW conductor loss. This percentage reduces for W = W1 150 m. Frequency (GHz) 01020304050 Loss (dB) 0.00 0.03 0.06 0.09 0.12 0.15 loaded line loss R bg =0.1 R bg =0.2 Frequency (GHz) 50100150200250 Loss (dB) 0.00 0.03 0.06 0.09 0.12 0.15 Unloaded line loss R bg =0.1 R bg =0.2 Figure 3.10: Loaded transmission line loss and loss due to bridge resistance versus a) frequency, b) W = W1=100 m and G = G1=300 m on quartz at 50GHz ( fB = 2.6 fmax = 130GHz). The bridge is comprised of 1 m thick plated Au. The optimal center conductor width ( W and W1) is found by dividing the phase shift per section by the loss per section to find the pha se shift per dB loss for the unit cell. The total CPW width G is set to 300 m in light of pull-in voltage calculation. G1 depends on fB and r and listed in Table 3.3. Table 3.3: Maximum CPW width G1 versus dielectric constant. r G 1 ( m) 1500 3.8300 11.7200 Figure 3.11 shows the calculation of /dB at 50 GHz for air, quartz, and silicon substrates for fB = 130GHz, G =300 m. It is seen from this figure that maximum phase shift per dB increases as the dielectric constant decreases and is 1219 /dB for air, 717 /dB for quartz, and 300 /dB for silicon. The maximum /dB for the assumed CPW dimensions is

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50listed in Table 3.4. Furthermore, the 0 contour for /dB is due to high Cbs/ s required to load the line to 50 in the normal state offsets low Cbg/ s1 in the slow-wave state. Although such high /dB is theoretically possible, fabric ation related limitations restrict achieving this value. For exampl e, on quartz substrate maximum /dB is obtained for S / W / G / = 25/250/25 and S1/ W1/ S1=125/50/125. For S / W / G / = 25/250/25, Cbs is calculated to be 1.4fF (using 3.9). Achieving su ch small capacitance is not possible (due to fringing effects). Assuming a minimum achievable Cbs =8fF (for a 2 m gap), W is limited to approximately 220 m (Figure 3.5). For this value of W maximum achievable /dB is 640 /dB with W1=50 m. Furthermore, the groundplane bridge capacitance ( Cbg) for this /dB value is calculated to be 71fF (see equa tion 3.10). Assuming the parallel plate approximation and that the gr ound-plane bridge is also 2 m above the line, the required area is 1.58 104 m2. Designing this capacitance requir es unrealistic bridge dimensions considering that the available bottom electrode width ( W1) for two bridges is only 50 m. Therefore, for practical design consideration, W < 200 m and W1 100 m is more practical. These constraints furthe r reduce the maximum achievable /dB to 600 /dB on quartz. It is worth mentioni ng that the design equations do not use the correction factor for conductor loss a nd do not account for parasitics, ther efore, measurable values will be considerably lower than the 600 /dB value as will be seen in the next section. From a design standpoint, an air s ubstrate can potentially provide more /dB, however, air substrates are not practical for MEM circuits. Figure 3.12 shows Cbg values as a function of center conductor widths ( W and W1) at 50GHz for air, quartz, and silicon substrates ( fB = 130GHz, G =300 m). Figure 3.11 and Figure 3.12 and can be used as a guideline for designing a slow-wave unit cell.

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51 400 400 400 400 600 600 600 800 800 1200 1000 1000 1000 1000 200 200 200 800 800 800 0 600 W ( m) 50100150200250 W 1 ( m) 50 100 150 200 250 300 350 400 450 200 200 200 200 300 300 300 300 400 400 400 400 500 500 700 600 600 100 100 100 500 500 0 W ( m ) 50100150200250 W 1 ( m) 50 100 150 200 250 50 50 50 50 100 100 100 100 150 150 150 150 200 200 200 200 250 250 250 300 0 0 W ( m) 6080100120140160180 W 1 ( m) 60 80 100 120 140 160 180 Figure 3.11: Calculated phase shift per dB ( /dB) at 50 GHz versus CPW center conductor width ( W and W1) for (a) air, (b) quartz, and (c) silicon substrates. In this calculation the total CPW width G =300 m, fB=130GHz, and G1 value in Table 3.3 is used.

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52Table 3.4: Calculated center conductor width ( W and W1) for maximum /dB. r /dB W ( m) W1 ( m) 11219250150-200 3.871125055-90 11.731118050-63 fB=130GHz, G = G1=300 m 40 40 40 60 60 60 80 80 80 100 100 100 120 120 120 140 140 140 160 160 160 180 180 W ( m) 50100150200250 W 1 ( m) 50 100 150 200 250 300 350 400 450 10 10 10 10 20 20 20 20 30 30 30 30 40 40 40 40 50 50 50 50 60 60 60 60 70 70 70 70 80 80 W ( m) 50100150200250 W 1 ( m) 50 100 150 200 250 0 0 0 5 5 5 10 10 10 15 15 15 20 20 20 25 25 W ( m) 6080100120140160180 W 1 ( m ) 60 80 100 120 140 Figure 3.12: Calculated grou nd plane bridge capacitance (2 Cbg) at 50 GHz versus CPW center conductor width ( W and W1) for (a) air, (b) quartz, a nd (c) silicon substrates. In this calculation the total CPW width G =300 m, fB=130GHz, and G1 value in Table 3.3 is used.

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53In order to verify the optimal center conducto r width, a slow-wave unit cell was fabricated on a 500 m thick quartz substrate with S / W / S =100/100/100 and S1/ W1/ S1=100/100/100 for the specifications listed in Table 3.2. Using the design equations (3.5)-(3.10), the bridge capacitances ( Cbs and Cbg) and spacing ( s and s1) are calculated and listed in Table 3.5. The comparison between meas ured and calculated (using 3.10) is shown in Figure 3.13. From this figure it is clear that the agreement between the measured (=40.4 ) data and calculated (35.5 ) is within 12% through 50GHz. The discrepancy between the data sets is the calculation does not ac count for additional inductance due to current bending at the junction. An accurate value for fB can be calculated by ta king bridge inductance ( Lb) into account, as presented in section 3.4. This calc ulation is not made here and could be one of the reasons for the differences. From the measured S11 data (Figure 3.13), it is seen that effective impedance in both the states ( Zn, Zs) is close to 50 since S11 < -23dB. Furthermore, worst-case measured S21 is less than -0.13dB translating to 300 /dB. This value is lower than predicted value of 420 /dB, however, the cont act resistance, conductor roughness, and signal leakage vi a SiCr bias lines contribute a dditional loss and reduce the /dB. It is proven via measurement that the design eq uation outlined in this section can serve as a design tool with limited accuracy. A semi-l umped model for the unit cell is presented in the next section to accurately mo del the measured S-parameters. Table 3.5: Calculated parameters for the slow-wave unit cell. Cbs62fF Cbg32fF s 474 m s 1923 m Calculated values

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54 Frequency (GHz) 01020304050 (deg) 0 10 20 30 40 50 (Meas) (calculated eqn. 3.12) Frequency (GHz) 01020304050 S 11 (dB) -50 -40 -30 -20 -10 0 S 11 (Normal) S 11 (Slow-wave) Measurement (a) (b) Frequency (GHz) 01020304050 S 21 (dB) -0.20 -0.15 -0.10 -0.05 0.00 S 21 (Normal) S 21 (Slow-wave) Measurement Ref Plane Ref Plane SiCr Bias Line Shunt beam Ground-plane beam (c) (d) Figure 3.13: a) Comparison be tween measured and calculated (using 3.10) for a 460 m long unit cell, b) Measured S21 in both the states, c) Measured S11 in both the states, d) Photograph of the fabricated device. 3.4 Accurate Slow-wave Unit Cell Model The model for a 460 m long slow wave unit cell in the normal state is shown in Figure 3.14 a. In the normal state (Figure 3.14 a), the model consists of uniform section of 55 transmission line (S/W/S=35/250/35 m) that is 210m long on each side of the shunt bridge. The shunt bridge, which is 40m wi de and suspended 1.82m above the center conductor provides a capacitance ( Cbs) of approximately 8fF (using the parallel plate approximation). Using the per unit length value for line parameters (Capacitance= Ctn, Inductance= Ltn) and a spacing s =460 m for a 55 transmission line, the effective normal state impedance ( Zn) is found to be approximately 50.5 using (3.1) [22]. The effect of bridge inductance is excluded in (3 .1), since the impedance due to Lbs is typically 50x (or

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55more) lower than the bridge capacitance ( Cbs). The bridge inductance ( Lb) and the bridge resistance ( Rbs) are found via circuit optimization using measurement data. The resistance ( Rp) and inductance ( Lp) indicate the signal to ground pa th via ground plane bridges; their values are also found via optimization. Figure 3.14: (a) Equivalent circuit model for the unit cell in the normal state, (b) Equivalent circuit model for the unit cell in the slow-wave state. The model for the slow-wave state (Figure 3.14 b) also includes a 55 transmission line (50 m long) to model the feed section. Since th e signal is routed through the long slot section, the current bending at the j unction is modeled using an inductor Lbend and the value is found via circuit optimization. The total leng th of the CPW line that is routed through the slot is approximately 950m (= s1). The non-actuated gro und-plane bridges provide a total capacitance ( Cbg) of 224fF. A good impedance match in the slow-wave state is made

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56possible by designing the unloaded impedance of the slow-wave section to emulate a 69 uniform CPW line ( S1/ W1/ S1=60/160/60). The effective impedance ( Zs) for the slow-wave unit cell is calculated from (3.1) and found to be approximately 49.54 The electrostatic voltage to pull the shunt bridge is provided via SiCr bias line at the input port which makes direct contact with the center conductor. The signal leakage (when shunt bridge is in DC-contact) through SiCr is modeled as Rbias, and the value for Rbias is typically obtained via circuit optimization. The ma ximum ground-to-ground spacing ( W ) is chosen to be less than g/5 at 50GHz. Measurements were performed from 1–50GHz using a Wiltron 360B vector network analyzer and 150m pitch GGB microwave probes. A Th ru–Reflect–Line (TRL) calibration was performed using calibration standards fabricated on the wafer. A high voltage bias tee was used to supply voltage through the RF pr obe to avoid damaging the VNA test ports. Typical actuation voltages are shown in Table 3.6. Table 3.6: Physical dimensions of CPW and MEM bridge MEM bridgeGround-plane Bridg e Shunt Bridge Width7040 Length285440 V p (volts) 3528 CPWNormal StateSlow-wave State Center conductor W = 250 W1= 160 Slot S = 35 S 1= 60 The unit cell model in Figure 3.14 was op timized to the measured data using ADS1 circuit simulator. A full-wave electromagnetic (EM) simulation (Momentum) of the unit cell in both the states is performed to extract the para sitics and used as the starting value in the optimization routine. The comp arison between equivalent circ uit model, EM simulation and measured data ( S11, S21, and ) for the unit cell in both the states is shown in Figure 3.15. From this figure it is clear that the agreement between the measured data and model 1 ADS, Agilent Technol. Inc, Palo Alto, CA, 2003.

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57(equivalent circuit and Momentum) is good thro ugh 50GHz with a slight discrepancy in the slow-wave state. This discrepancy may be due to the coupling of signal (via the SiCr) underneath the ground plane and/or due to the conductor roughness. Frequency (GHz) 01020304050 S11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -0.4 -0.3 -0.2 -0.1 0.0 Meas Equivalent Ckt Momentum Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -0.6 -0.4 -0.2 0.0 Meas Equivalent Ckt Momentum (a) (b) Frequency (GHz) 01020304050 (deg) 0 10 20 30 40 50 Meas Equivalent Ckt Momentum Normal StateSlow-wave state Rbs= 0.69 Rbg= 0.57 Lbs= 15.2pH Lbg= 18.2pH Cbs= 11.2fF Cbg= 27.9fF Lp=11.7pH Lbend= 15.5pH Rp=0.11 Rbias= 16.5k (c) (d) Figure 3.15: Comparison between measurement data and model (equivalent circuit and full wave EM simulation), (a) S11 and S21 in the normal state, (b) S11 and S21 in the slow wave state, (c) Phase shift ( ), (d) model parameters. The Bragg frequency ( fB) is calculated using (3.15) [22]. For the unit cell as described herein, fB is calculated for the parameters in the slow-wave state due to higher loading capacitance. Assuming a bridge inductance ( Lbg) of 19pH (found from full wave EM simulation); fB using (3.15) is calcul ated to be 126GHz. 2 2 1 2 114 22 4 4B tstsbgbg tststsbgbgbgbbac f a asLCLC bsLCsLCLC c (3.15)

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58It is seen that is approximately 44 at 50GHz and S11 is below -22dB from 1-50GHz. The worst-case S21 is -0.17dB for both states. The measured effective relative dielectric for the uniform CPW feed line was fo und to be 2.43. Using this valu e the effective length of the unit cell in the normal state is 580m and in the slow-wave state it is approximately 1050m, resulting in a slowing factor of 1.81 [7]. 3.5 Phase Shifter Performance (1-bit and 4-bit version) A 1-bit phase shifter is constructed by casc ading 10 slow-wave unit cells (as shown in Figure 3.16). In this config uration, either the ground plane beams or shunt beams in all sections are actuated simultaneously. Typica l height non-uniformities in the bridges is approximately 0.1-0.3m. Therefore, to ensure actuation in all sections, the applied pull-in voltage ( Vp) for both states is 5V higher than that of the unit cell (40V for normal state and 33V for slow-wave state). Figure 3.16 shows a comparison between meas ured and modeled data for the phase shifter in both states. The simulated results were ob tained by cascading the equivalent circuit model for the unit cell in the ADS circuit simu lator. The agreement between the measured data and the model is good through 50GHz. The measured S11 is below -22dB for both states from 1-50GHz. Furthermore, the measur ed and simulated differe ntial phase shift are within 2%, with a measured value of 407 at 50 GHz. The worst-case insertion loss is approximately 1.3dB. The figure-of-merit in degrees per decibels for the phase shifter is approximately 310/dB at 50GHz (consistent with unit cell performance). The discrepancy between model and measurements in S11 (slow-wave state) may be attributed to the height non-uniformities in the MEMS bridges.

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59 4.6mm SiCr Bias Lines L= 4.6mm Reference Plane Reference Plane SiCr Bias Lines Electroplated Au beam Figure 3.16: Schematic and photo graph of the fabricated phase shifter. The phase shifter has 10 cascaded slow-wave unit-cells. Figure 3.18 shows a comparison between the me asured insertion loss for the phase shifter in both states and for a uniform 50 CPW line of equal length. Also plotted in this figure is the EM simulation for the phase shifter in both states. When comparing the measured phase shifter data and the uniform CPW line, it seen that the S21 for the phase shifter in the normal state is 0.9dB at 50 GHz, which is higher than the measured 50 line by 0.45dB. This increase in loss is due the cont act resistance and small signal leakage via the SiCr bias lines. The signal leakage was verified by measuring a series resistor made of SiCr. It was found that the leakage through bias lines was less than -35dB through 50GHz. Figure 3.19 shows the schematic and a photogra ph of the fabricated 4-bit phase shifter. The multi bit version is designed to provide of 45, 90, 180 and 225 at 30GHz. The 4-bit version also consists of 10 cascaded slow-wav e unit cells (or 5 unit cell pair). Each unit cell pair provides a = 45 at 30GHz. For example, in the first bit ( = 45), only one unit cell pair is operated in slow-wave state while the other pairs remain in the normal state. The second bit ( = 90), consists of two unit cell pairs operated in the slow-wave state. The transition from the 1st bit to the 2nd bit is achieved by shorting the unit cell pair using

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60a wire-bond between the DC pads (as shown in Figure 3.19). Since the unit cell pairs are identical, there are five non-trivial phase states. Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -4 -3 -2 -1 0 Model Measurement Frequency (GHz) 01020304050 S11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -4 -3 -2 -1 0 Model Measurement (a) (b) Frequency (GHz) 01020304050 (deg) 0 100 200 300 400 500 Model Measurement Frequency (GHz) 01020304050 (/dB) 0 100 200 300 400 500 Model Measurement (c) (d) Normal StateSlow-wave state Rbs= 0.71 Rbg= 0.64 Lbs= 15.82pH Lbg= 16.9pH C bs= 12.1fF C bg= 28.8fF Lp=11.1pH Lbend= 14.9pH Rp=0.12 Rbias= 21.5k (e) Figure 3.17: Comparison between measurements and equivalent circuit model for the 1-bit phase shifter (a) S11 and S21 in the normal state, (b) S11 and S21 in the slow wave state, (c) Phase shift ( ), (d) Phase shift per dB, (e) model parameters.

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61 Frequency (GHz) 01020304050 S (dB) -2.0 -1.6 -1.2 -0.8 -0.4 0.0 Slowwave (MoM) Slowwave (Meas) Normal (MoM) Normal (Meas) S 21 (50ohm t-line) Figure 3.18: Measured S21 of the 1-bit phase shifter for both states and a 4.6mm long uniform 50 CPW line. Ref Plane Ref Plane 1st bit (45) Pad 2nd bit(9 0 ) 3rd bit (180) 4th bit(225) unit cell pair Figure 3.19: Schematic of the fa bricated 4-bit phase shifter. Figure 3.20 shows a comparison between measur ed multi bit phase shifter and the model for four states. It is seen from these plots that the agreement between measurements and model is good through 50GHz with S11 less than -21dB and worst-case S21 greater than -1.39dB. The comparison of between measured and modeled data is shown in Figure 3.21. The agreement between measured and modeled data is good through 50GHz with phase error less than 5.5 at 30GHz. The increase in S21 (~0.2dB) when compared with the 1-bit version is due to 15% decrease in bias resistance ( Rbias) from 21.5k to 18.3k. Other model parameters were not altere d in the circuit model.

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62 Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -2.0 -1.5 -1.0 -0.5 0.0 45 (Model) 45 (Measurement) Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 S 21 (dB) -2.0 -1.5 -1.0 -0.5 0.0 90 (Model) 90 (Measurement) ((a) (b) Frequency (GHz) 01020304050 S11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -3 -2 -1 0 180 (Model) 180 (Measurement) Frequency (GHz) 01020304050 S11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -3 -2 -1 0 225 (Model) 225 (Measurement) (c) (d) Figure 3.20: Comparison of S11 (dB) and S21 (dB) between measured data and equivalent circuit model; (a) 1st bit (45); (b) 2nd bit (90); 3rd bit (180); 4th bit (225). Frequency (GHz) 01020304050 (deg) 0 100 200 300 400 500 Model Meas Frequency30 GHz 1st bit (45)43.15 2nd bit (90)90.11 3rd bit (180)183.7 4th bit (225)219.5 Figure 3.21: Comparison of between measured and modeled data for the multi bit phase shifter.

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633.6 2nd Generation 1-bit Low Loss Phase Shifter Performance The insertion loss of the phase shifter presen ted in section 3.4 is improved by using 3 m thick plated Au CPW lines. Furthermore, the SixNy layer, previously located where the bias lines enter the ground conductor, is avoided an d biasing to the beams enters through the ground plane cuts. An airbridge (located 2-2.5 m) over the bias lines is used to connect the cut ground planes. It was found via EM simula tions that the groundplane cuts with the air-bridge have negligible effect on the S11 and of the unit cell. The maximum S11 value in the slow-wave state typically increased by a factor of 5dB (or 14% at 50GHz) for the three designs. However, the S11 value remained below -20dB through 50GHz in both the cases. The absolute phase in the slow-wave stat e typically decreased by a factor of 4% (or 1 ). Two phase shifter designs (design 1 and design 2) were fabricated on a 500m thick quartz substrate. The CPW dimensions for the two designs are listed in Table 3.7. From Table 3.4, the optimum width for W and W1 assuming G1= G =300 m indicate W =250 m and W1=50 m. To a 1st order, this is true for a given substrate. Therefore, a large width for W and small width for W1 will be an ideal choice for the 2nd generation design. One of the shortcomings of this approach is that the fB is dependent on the per unit length capacitance and inductance. Using (3.15), fB versus center conductor widths ( W and W1) is shown in Figure 3.22 (assuming G =300 m and G1=320 m). The variation of Cbg versus width ( W and W1) is also shown herein for comparison purposes. It is seen from this figure that calculated fB is dependent on Cbg (ground-plane bridge capacitance) and the Cts (capacitance per unit length of the unloaded line). In this work, footprin ts providing fB lower than 120GHz were not considered. However, more can be obtained if a lower fB can be tolerated. The outline of the fabrication is si milar to Figure 3.3 except that SixNy layer is eliminated. The SiCr bias lines are defined first using the liftoff technique by evaporating a 900 layer of SiCr using E-beam evaporation. Next the CPW lines are defined by evaporating a Cr/Au layer to 1 m using liftoff technique. A 1.8-2 m thick PMMA sacrificial layer is spin coated and etched (2000 Ti is used as ma sking layer) in a RIE chamber exposing the

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64CPW lines and the pedestals where the ground cuts need to be connected. The Ti layer is removed and a 100/1500 Ti/Au seed layer is evaporated over the entire wafer and patterned with photoresist. The sa mple is Au electroplated to 1.8 m thick (total CPW metal is 2.8 m thick), followed by removal of the top photoresist and the seed layer. Another 2000 Ti layer is deposited as a masking layer and the PMMA is etched where the pedestals for MEM bridges are located. The masking layer is then removed and an 80/2000 Ti/Au seed layer is evaporated over the entire wafer. The bridges are then gold-electroplated to a thickness of 1m, followed by removal of the top photoresist layer, seed layer. The sample is released after the two-step anneal. The photograph of the fabricated device is shown in Figure 3.23. 50 150 140 140 140 130 130 130 130 130 120 120 120 120 110 110 110 100 W ( m) 50100150200250 W 1 ( m) 50 100 150 200 250 * 10 10 10 10 20 20 20 20 30 30 30 30 40 40 40 40 50 50 50 50 60 60 60 60 70 70 70 70 80 80 W ( m) 50100150200250 W 1 ( m) 50 100 150 200 250 * (a) (b) Figure 3.22: Calculated parameters for the slow-wave unit cell on quartz with G =300 m and G1=320m, a) fB using (3.15), b) 2 Cbg. The two designs are marked in the figure. The unit cell model in Figure 3.14 was optimized to the measured data (design 1 and design 2) using ADS. A full-wave EM simulation of th e unit cell in both the states is performed to extract the parasitics and used as the starti ng value in the optimization routine. The simulated results for the 10-section phase shifte r were obtained by cascading the equivalent circuit model for the unit cell in the ADS ci rcuit simulator. The comparison between equivalent circuit mode l and measured data ( S11, S21, and ) for design 1 and design 2 in both the states is shown in Figure 3.24.

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65Table 3.7: CPW and bridge dimensio ns for design 1 and design 2. Normal State Slow-wave State ShuntGround-plane W = 100 m W1= 120 m l = 380 m l = 270 m design 1 S = 100 m S1= 100 m w = 120 m w = 90 m V p=28V V p=32V W= 100 m W1= 80 m l = 440 m l = 285 m design 2 S = 100 m S1= 135 m w = 40 m w = 70 m V p=35V V p=28V CPWBridge (a) (b) Figure 3.23: Photograph of the fabricated device, a) design 1, b) design 2. The agreement between the measured data an d the model for both the designs is good through 50GHz. The measured S11 is below -19dB for both states from 1-50GHz. Furthermore, the measured and simulated are within 1% for design1 and 3% for design 2, with a measured value of 391 for design 1 and 407 for design2 at 50 GHz. The worst-case insertion lo ss is approximately 1.1dB for design 1 and 1.15 for design 2. The figure-of-merit in degrees per decibels for the ph ase shifter is also shown herein and indicate a maximum /dB of 345 /dB for design 1 and 354 /dB for design 2. When comparing with the 1st generation phase shifter results (see sect ion 3.4) the current designs provide an improvement of 60% in /dB for f < 30GHz. Beyond 30GHz, there is only 10-15% improvement in /dB.

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66 Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -4 -3 -2 -1 0 Model Measurement Frequency (GHz) 01020304050 S11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -4 -3 -2 -1 0 Model Measurement (a) (b) Frequency (GHz) 01020304050 S11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -4 -3 -2 -1 0 Model Measurement Frequency (GHz) 01020304050 S11 (dB) -60 -50 -40 -30 -20 -10 0 S21 (dB) -4 -3 -2 -1 0 Model Measurement (c) (d) Frequency (GHz) 01020304050 (deg) 0 100 200 300 400 500 Model Measurement deg deg/dB Frequency (GHz) 01020304050 (deg) 0 100 200 300 400 500 Model Measurement deg deg/dB (e) (f) Figure 3.24: Comparison between measurements and equivalent circuit model for the 1-bit phase shifter, (a) S11 and S21 in the normal state for design 1, (b) S11 and S21 in the normal state for design 2, (c) S11 and S21 in the slow wave state for design 1, (d) S11 and S21 in the slow wave state for design 2, (e) and /dB for design 1, (f) and /dB for design 2.

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673.7 Frequency Scaling ( X and W -band designs) The designs presented in the previous sections can be scaled to X -band (8-12GHz) or W band (75-110GHz). The design technique is as follows: The ground-to-ground spacing ( W ) is set to /5. 5 and fB = 2.6fmax. Using (3.9) the spacing ( s ) between the shunt brid ge and the capacitance Cbs is determined. From (3.7), approximate signal path throug h the slot is determined and this value of s1 is used in (3.10) to find the ground-plane bridge capacitance. Accurate value of fB is determined and per section is dete rmined (3.12). The ground-to-ground spacing sh ould be lower for the W -band design to reduce radiation loss. Table 3.8 shows calculated parameters for X and W -band design. Using Momentum and assuming a lossless metallization, the W -band design is simula ted and the results for S11 and is shown in Figure 3.25. It is seen fr om this figure that the agreement between is not good. This may be due to re asons; a) the design equation does not account for inductive effect due to current bending and the parasitics associated with the bridge, b) due to nonlinearity associated with the Bragg frequency beyond 100GHz. Table 3.8: Design parameters for X -band and W -band design used in simulation. X-band W-band S / W /S ( m)100/100/100 ( m)100/100/100 ( m) S1/ W1/S1 ( m)125/220/125 ( m) 50/40/50 s ( m) 1500216 s1 ( m) 3800257 Cbs (fF) 9529 Cbg (fF) 5722

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68 Frequency (GHz) 7580859095100105110 S 11 (dB) -40 -35 -30 -25 -20 S11 (Normal state) S11 (Slow-wave state) Frequency (GHz) 7580859095100105110 (deg) 20 22 24 26 28 30 32 34 36 Momentum Design equations Figure 3.25: a) Simulated (Momentum) S11 in both the states for W -band design, b) comparison between simulated (Momentum) and calculated 3.8 Chapter Summary The analytical model developed herein for the slow-wave phase shifter is based on the quasiTEM approximation for a transmission line. For simplicity, the parasitics associated with the bridge is not included in the derivation. Ho wever, these equations were used to predict the optimal center conductor widths on different substrates. Usin g this as starting values, a semi-lumped model that include parasitics is derived. Experimental results for a 460 m long unit cell on quartz shows good agreement be tween measured and modeled data. A 1-bit (and 4-bit) phase shifter model is constructe d by cascading 10 slow-wave unit cells. The agreement between the measured data and the model is good through 50GHz with 310 /dB at 50GHz. In the 2nd generation design, further improvemen t is seen by plating the lines and indicate loss-per-dB of 355 /dB. The result represent state-of-the-art performance for TTD phase shifter through 50GHz.

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69CHAPTER 4 Applications of Slow-wave Phase Shifter The focus of this thesis is on the applicat ion of impedance matched slow-wave unit cell as low-loss millimeter-wave phase sh ifters. However, there are a number of other applications in which slow-wave unit cell can be useful. Some of the more significant applications are: Reconfigurable MEM transmission lines that can provide characteristic impedance tuning ( Zo-tuning) with constant phase. Electronically tunable multi-line TRL for automatic on-wafer calibration. This chapter presents the results of using sl ow-wave unit cell for these applications, but no attempt is made to achieve the best performance. 4.1 Reconfigurable MEM Transmission Line with Zo-tuning and -tuning The design of reconfigurable, multi-band rada r and communications hardware can require dynamic adjustment of both time de lays and characteristic impedance ( Zo) levels at various points within the signal paths. When considering just phased arrays, the need for time delay control is obvious. One example wherein the control of impedanc e levels is important is in the antenna design. There have been several published examples of reconfigurable antennas comprised of a radiating element(s) and Micro-Electro-Mechanical (MEM) switch(es); in such configurations the resona nt frequency is varied and there may little change in the impedance at the selected oper ating frequency. However, when co-locating a MEMS device with a radiating element is undesi rable, a more suitable solution may be a dynamic impedance-matching network.

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70This section presents a reconfigurable MEMS -based transmission line in which there is independent control of the prop agation delay and the characteristic impedance. Variations of MEMS tuners that have recently been published include: stub-type topologies, with extensive Smith-chart coverage through 20 GHz [51-53]; and low loss, distributed MEM transmission lines (DMTLs), with a 5:1 (50 :10 ) impedance match [54, 55]. The approach presented here differs in that separa te control of inductive and capacitive MEMS devices in discrete unit cells is used either to maintain a constant LC product (constant Zo) or a constant L/C ratio (constant ), while changing the ratio or product, respectively. The tunable Zo-line with constant -mode is complimentary to the slow-wave phase shifter that was presented in chapter 3. The new design uses cascaded metal-air-metal (MAM) capacitors at the input and the output of the slow-wave sections. Expe rimental results for a 1-bit, 7.4mm (10 cascaded unit cells) long line demonstrate a Zo tuning ratio of ~ 1.27 (52 /40 ) through 50GHz with 2 variation over frequency. The 1-bit version can also be operated as a phase shifter by addressi ng the MAM capacitors differently. The measurement result indicate /dB ~358 /dB (or 58 /mm) at 50GHz with S11 < -25dB. In a 5-bit version, the 1st bit is configured as a tunable Zo element and other bits are operated as a phase shifter. Experimental results for the dual mode operation indicate a /dB of ~ 300 /dB and impedance shift of 52 to 40 4.2 Design and Measured Performance The unit cell shown in Figure 4.1 is comprised of a slow-wave section [56] with MAM capacitors at the input and output. The two di stinct phase states of the slow-wave section are the normal state (when the ground plane beams are actuated and the shunt beam is non-actuated) and the slow-wave state (when the shunt beam is actuated and the ground plane beams are non-actuated). The measured performance for the 400 m long slow-wave section indicate =46 S11 < -25dB and worst-case S21 is -0.15dB. These results represent approximately 25% improvement over the 2nd generation slow-wave phase shifter result presented in chapter 3. The footprints of the slow-wave unit cell is listed in Table 4.1. The maximum conductor width (~600 m) is less than g /8 at 50GHz to maintain single-mode

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71operation, and typical actuation voltage for the beams is approximately 28-32V. Furthermore, for the spacing sp ecified herein, the calculated fB is approximately 138GHz. Table 4.1: CPW dimensions and bridge capacitance ( Cbs and Cbg) for the slow-wave unit cell that is used in this section. S / W / S ( m) 50/200/50 S1/ W1/ S1 ( m) 100/120/100 s ( m) 200 s1 ( m) 647 Cbs (fF) 12 Cbg (fF) 31 fB =138GHz Zo-tuning is realized by operating the slow -wave section in conjunction with the MAM capacitors: the lowZo mode ( state 1) corresponds to the normal state with actuated MAM capacitors, while the highZo mode ( state 2) is realized in the slow-wave state with nonactuated MAM capacitors. Maintaining a constant propagation constant ( ) with Zo-tuning is achieved by proper selection of the capacitance ratio ( Cr= Cdn/ Cup) of the MAM capacitor. Specifically, due to the MAM capacitor ( MAM), separated by a 270 m long uniform CPW line, offsets the due to the slow-wave section ( slow-wave). For a given spacing ( s ) between capacitors and the total length ( L ), equation (4.1) is used to calculate Cr. 360 11deg 2tntn bsrbs tntn LC CCC L sCsC (4.1) Where, Ltn and Ctn are the per-unit-length inductance a nd capacitance in the normal state [56]. Using (4.1), Cr=2.6 for =46, s =270 m, Cb=24fF, Ltn=0.33 nH/mm, Ctn=0.07 pF/mm, and L=740 m. The different Zo levels are determined by considering the transmission line section between MAM capacitors (the slow-wave section) as a uniform CPW line. The effective impedances ( Zstate1, Zstate2) for both the states is then calculated using (4.2). For the distributed parameters used herein, these impeda nces can be set to approximately 50 or 38 ; parasitic

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72loading of the shunt beam and ot her discontinuity effects increase the actual levels to the 40/52 values stated above. 12; 1 1tstn statestate bgbs tn 1tnLL Z= Z= CC + + sC sC (4.2) The spacing s1 is total length between the between the capacitors via the slow-wave section. Figure 4.1: Microphotograph of the constant tunable Zo slow-wave unit cell (left) and SEM picture of the structure. The tunableZo unit cells were fabricated on a 500m thick quartz substrate (r=3.8, tan=0.0004) using the basic process described in chapter 3. The SixNy layer previously located where the bias lines enter the gro und conductor, is avoided and biasing to the beams enters through the ground plane cuts (th e ground cuts are connected via air bridge). To simplify fabrication process, the CPW lines are not plated. The DC isolation between the MAM capacitors and the cente r conductor is realized by using a dimple in the slots that is 0.5m higher than the metal laye r and supports an interconn ecting beam (Figure 4.1). Measurements were performed from 1–50GHz using a Wiltron 360B vector network analyzer and 150m pitch GGB microwave probes. Figu re 4.2 (a) shows the measured S11 and extracted Zo (Figure 4.2 (b)) from 2-port S-pa rameter data for the highand lowZo modes (states 1 and 2 in the figure). A full wave EM simulation using ADS Momentum was performed and the results are included in the figure. The difference in S11 between the two Zo-states (~15dB) is due to the change in the characteristic impedance from 40 to 52. Extracted Cr from the measured data is approx 2.57 (=59.8fF/23.2fF) which agrees favorably using (4.2).

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73The measured phase difference between the states was less than 2.5 (< 2%) for l =150 at 50GHz. The worst-case S21 was approximately -0.15dB and -0.25dB for Zeff =52 and 40, respectively. The measured S21 at 50GHz for the MEMS transm ission line is 0.08dB less than a uniform CPW line of equal electrical leng th. The increase in loss may be due to the contact resistance and small leakage in the bias circuitry. Frequency (GHz) 01020304050 S11(dB) -60 -50 -40 -30 -20 -10 0 state1 state2 Frequency (GHz) 01020304050 Zo ( ) 30 40 50 60 70 80 Measurements EM simulation state1 state2 Figure 4.2: Measured S11 (dB) and extracted Zeff in state 1 and state 2 for the 1-bit tunable Zo unit cell. Solid lines represent EM simulation data. 4.3 1-bit Tunable Zo-line and 1-bit Phase Shifter Performance The schematic of the 1-bit tunable Zo line with ten cascaded sections (7.4mm long) is shown in Figure 4.3. As with the unit cell, the MAM capacitors are actuated only when the slowwave section is operated in the normal stat e and remain in the no n-actuated otherwise. Figure 4.4 shows a comparison be tween the measured and simulated S11 data referenced to 50 in both the states. The simulated results we re obtained by cascading full-wave analysis data for the unit-cells in the circuit simulato r. The extracted effective impedance in this case is 52/41 and the worst-case S21 for both the states is approximately 1.23dB and 2.2dB at 50GHz. Assuming an effective relative dielectric cons tant of 2.46 (from Multi-line TRL calibration), the effective length is approximately 1.6c m. The maximum phase difference between the states is less than 3.6% and absolute phase in both the states is shown in Figure 4.5. The measured S21 of the tunable Zo-line is 0.3-0.45dB lower than a uniform CPW line of the same electrical length.

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74 Ref Plane Ref Plane 7 .4mm Figure 4.3: Schematic of 10-section cascaded tunable Zo unit cell and a photograph two unit cells in the device. Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Measurements EM simulation state1 Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 EM Simulation Measurements state2 (a) (b) Figure 4.4: Comparison of measur ed (dashed) and simulated (solid) S11 (dB) of a 7.4mm long tunable Zoline with constant propag ation constant in both states, a) state 1, b) state2. The schematic shown in Figure 4.3 can be reco nfigured to operate as a 1-bit phase shifter with maximum phase shift by actuating the MA M capacitors in the slow-wave state of the slow-wave sections. The limiting factor in this approach is the Bragg frequency ( fB). The calculated fB for the design is approximately 51GHz with the MAM capacitors actuated [23]. The usable frequency range is then only up to 30GHz, since the non-linear effects are prominent around 0.5 fB. Therefore, for 1-50GHz operation, the MAM capacitors remain in the non-actuated state and the phase shift is primarily due to the slow-wave section. A electromagnetic optimization was performed wi th the pedestal height as the variable. A initial guess value of 2m was used and other unit cell para meter was fixed. The pedestal height for the shunt and the ground-plane br idge was varied by the same factor. For

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75example, if the pedestal height for the shunt bridge in the normal state is equal to 2m, then the ground plane bridge for the slow-w ave state also had the same value. The comparison between EM simulation (with gap height of 1.65m) and measured data ( S11 and ) for the unit cell in both the states is shown in Figure 4.6. From Figure 4.6, the measured S11 is below -25dB for both states through 50GHz. Furthermore, the measured and simulated diffe rential phase shift is within 6%, with a measured = 430 at 50 GHz. The discrepancy in the predicted phase shift is due to the non-uniformities in height from unit cell to unit cell and irregu lar dimple height across the length of the transmission line in the fabricated device. Me asured worst-case S21 was equal to -1.2dB at 50GHz, translating to /dB of 360/dB which is 40/dB better than the 1st generation slow-wave results. Frequency (GHz) 01020304050 S21 (dB) -3 -2 -1 0 state1 (meas) state2 (meas) Uniform CPW Line Frequency (GHz) 01020304050 phase (deg) -1800 -1500 -1200 -900 -600 -300 0 state1 state2 (a) (b) Figure 4.5: Measured performance of the 10-section 1-bit tunable Zo device in both the states, a) S21 of the tunable transmission line and S21 data of a 1.6cm long 50 CPW line, b) in both the states. 4.4 Combined Zo -Tuning and -Tuning A 5-bit version of the device in is designed to provide combined Zo-tuning and -tuning. This bi-modal operation is achieved by co nfiguring one bit (2 unit cells) to provide Zotuning and the other four bits to provide -tuning. State 1 is operated such that the first bit acts as a 40 section and bits 2-5 are in the normal phase state. Conversely, in state 2 the first bit acts as a 52 section and bits 2-5 are in the slow-wave phase state. Figure 4.7

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76shows the measured S11 in both states and a comparison of the measured and simulated between the states. This example demonstrat es the ability to contro l phase and impedance independently. Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Measurements Model Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Measurements EM Simulation (a) (b) Frequency (GHz) 01020304050 (deg) 0 75 150 225 300 375 450 Measurements EM Simulation (c) Figure 4.6: Comparison between measurements and optimized EM simulation for the 10section device in phase shif ter mode operation, a) S11 in the slow-wave state, b) S11 in the normal state, c) The solid line in each plot re present EM simulation data and the dashed line represent measured data.

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77 Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Measurement (State 1) Measurement (State 2) Frequency (GHz) 01020304050 (deg) 0 100 200 300 400 500 EM Simulation Measurements (a) (b) Figure 4.7: Measured performance of a 10-s ection device in a bi-modal operation, a) S11, b) Solid lines represent EM simulation data and dashed lines represent measured data. 4.5 Electronically Tu nable Multi-line TRL Considerable effort has been made to develo p accurate techniques for calibrating vector network analyzers (VNAs) based on the use of space conservative standards [57]. The multi-line Thru-Reflect-Line (TRL) method is ve ry accurate for broad band calibration [58]; however the required use of two or more dela y lines can lead to inefficient utilization of wafer surface area. Space conservative calib ration methods such as the SOLT, LRM and LRRM provide accuracy that is close to a mult i-line TRL, provided that broad band models for the standards are available. An alternativ e to reducing the footprint of standards is to use an electronic phase shifter that can represen t multiple delay lines by changing its phase state. It is very important that there be mi nimal variation in the effective characteristic impedance between differe nt phase shifter states, since the delay lines ideally differ only in transmission phase and loss. An added advantag e of the electronic calibration approach is that a minimal number of probe placements is necessary, thereby minimizing this aspect of calibration error. A multi-bit TTD phase shifter with a quasi-co nstant impedance can em ulate multiple delay standards that is required for accurate br oad band (1-50GHz) calib ration. A DMTL based topology cannot be used for such large bandwidth since /cm is only 180 for S11 < -

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7820dB. Typically, a commercial probing station can provide a maximum lateral (x-y) movement of only 1.5-1.6cm. The goal of this work is to demonstrate th e new phase shifter topology in a multi-bit configuration to realize the thru and delay lines of a TRL calib ration set (“Tunable TRL”). Experimental results for the 1st generation 4-bit phase shifter that is 4.6mm-long demonstrate S11 less than -21dB through 50GHz with /dB of approximately 317/dB (or 91/mm) at 50GHz (see chapter 3). The multiple states of the phase shif ter designed in this work provide of 45, 90, 180 and 225at 35GHz. The MEMS tunable 4-bit phase shifter presented herein is used to realize four delay line calib ration standards in a multi-line TRL. The normal-mode operation (or =0) of the phase shifter mimics the th ru standard. The different bits of the slow-wave phase shifter are actuated in or der to emulate the delay line standards. The open standard is realized usin g a separate, uniform CPW line. Th e effective offset lengths of the delay lines extracted from measured at 35GHz are approximately 739m =47), 1460m ( =93), 2931m ( =188) and 3669m ( =235). The results of a Tunable TRL calibration are compared with a calibration performed using uniform CPW line standards on the quartz s ubstrate. The reference planes for both calibrations are established at the probe tips with Zo corrected to 50. Furthermore, same number of line standards was used in both the calibration s. The maximum error bound | SijSij ’|max between multi-line TRL standard on quartz (TRL1) and Tunable-TRL on quartz is computed using the calibration comparison me thod [58]. The comparison was also made between standard TRL on a CS-51 substrate (TRL2) and the Tunable TRL, as illustrated in Figure 4.8. The calibration comparison method is based on the assumption that a perfect multi-line TRL calibration using conventional standards calculates the true sc attering parameters Sij of a device from uncorrected measurement data. However, an imperfect TRL calibration 1 CS-5 is a commercial calibration substrate manufactured by GGB Industries, Naples, FL.

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79based on standards with errors (Tunable TRL) will result in calibration coefficients which differ from those of the perfect calibration. Thes e imperfect calibration coefficients calculate scattering parameters Sij', which differ from the actu al scattering parameters Sij. The calibration-comparison method determines an upper bound for | SijSij'| from differences in the perfect and imperfect calibration coefficients when | Sij| < 1 and | S12 S21| < 1. The upper bounds indicate the maximum possibl e difference in any of the four S -parameters for a 2port passive device. Frequency (GHz) 01020304050 | Sij-Sij '| 0.00 0.03 0.06 0.09 0.12 0.15 TRL1-TunableTRL TRL2-Tunable TRL Repetability Error Figure 4.8: Upper bound error | Sij-Sij ’|max between standard TR L and Tunable TRL. It is seen from Figure 4.8 that the upper bound between TRL1-T unable TRL and TRL2Tunable TRL increases linearly with a ma ximum bound of 0.14 at 50GHz for TRL1Tunable TRL calibration sets. Th e increase in the error bound is due to the slight increase in the insertion loss and a 2% deviation from 50 for the 4-bit phase shifter when compared to uniform CPW line. For completeness, th e repeatability of the two Multi-line TRL calibrations on the quartz substrate is also shown in the figure. In order to verify the accuracy of the predicted error bounds tw o verification devices were measured: a) 9mm long delay line standard on quartz substrate A 9mm long uniform CPW line was measured after performing a Tunable TRL and a TRL1. It is seen from (a) that the measur ement results performed using the Tunable TRL and TRL1 agree well. Furthermore, the maxi mum vector difference between the two measured S-parameters is with in the estimated error bounds.

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80 Frequency (GHz) 01020304050 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Multi-line TRL (TRL1) Tunable TRL Frequency (GHz) 01020304050 S 21 (dB) -2.0 -1.5 -1.0 -0.5 0.0 Multi-line TRL (TRL1) Tunable TRL Figure 4.9: S11 and S21 of 9mm long verification structure. The line was measured after a Tunable TRL calibration and a st andard TRL on quartz (TRL1). b) 25 Load on a CS-5 substrate A 25 load verification structure was measured on 700m thick CS-5 substrate (r=9.9, tan=0.002) after performing a on-wafer calibration (TRL2) using uniform CPW line standards. It is seen from Figure 4.10 that the measurement results performed using Tunable TRL and TRL2 agree well and the maximum vector difference between the Sparameters is within the predicted erro r bound. Several othe r DUT such as 12.5, and 100 load on GaAs substrate was measured a nd it was found that the agreement between Tunable TRL and TRL calibration is within th e error bounds predic ted using calibration comparison method. Frequency (GHz) 01020304050 S 11 (dB) -10.0 -9.8 -9.6 -9.4 -9.2 -9.0 Multi-line TRL (TRL1) Tunable TRL Figure 4.10: S11 of a 25 load verification structure on a 700m thick CS-5 substrate.

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814.6 Chapter Summary In this chapter two novel applications that utilize slow-wave phase shifter is presented. A reconfigurable MEMS transmission line base d on cascaded capacitors and slow-wave sections has been develope d to provide independent Zoand -tuning. Experimental results for the Zo-mode of operation, provides Zo-tuning from 52 to 40 (+/-2) with constant phase between the states throug h 50GHz. The same transmissi on line is reconfigured by addressing the MEM elem ents differently for -tuning. Furthermore, the combined effect of Zoand -tuning is also demonstrated. Furthe rmore, an electronically tunable TRL calibration set that utilizes a 4-bit phase shifte r topology is presented. The accuracy of the tunable TRL is close to a conventional multi-line TRL calibration. The Tunable TRL method provides for an efficient usage of wafe r area while retaining the accuracy associated with the TRL technique, and reduces the nu mber of probe placements. The measured results presented herein is state-of-the-a rt performance for bo th the applications.

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82CHAPTER 5 Summary and Future Work This thesis presented the application of peri odically loaded slow-wave unit cell and focused on the use of this as a millimeter wave ph ase shifter. Optimized phase shifters were developed at 50 GHz with a maximum performance of 350 /dB or 360 phase shift with 1.1 dB loss. These are the lowest loss millimeter wave phase shifters reported to date. Furthermore, for the same the size of these devices are 75% smaller than the state of the art results presented till date. In current phased array systems, there is a PA/LNA chip at each antenna element in order to limit the effect of the loss in the phase shifters. However, with 1 dB insertion loss or less, the number of PA/LNA chips needed could be reduced by using one chip for several antenna elements. This would greatly reduce the cost of large phased array systems which typically have thousands of antenna elements. In addition, the slow-wave phase shifter was a pplied to a tunable transmission line that can provide independent Zo-tuning with a tuning ratio of 1.2 and -tuning with /dB of 300 /dB. Such performance would lead to new innovative designs for phased array systems. An electronically tunable calibration (1-50GHz ) is made possible by realizing all the line standards using the multi-bit phase shifter in a typical multi-line TRL. The Tunable TRL method provides for an efficient usage of wafe r area while retaining the accuracy associated with the TRL technique, and reduces the numbe r of probe placements from five to two (with potentially no change in probe separation distance).

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835.1 Future Work a) Tunable Filter The low loss performance of the slow-wave unit ce ll can be used in a high Q filter design by cascading two or more unit cells to emulate a /4 or /2 open resonators. Conventional tunable filters typically utilize YIG resonators, ac tive resonators or varactors as the tuning element. Varactor-based tunable filters have rela tively low Q values in the range of 2-3 [45], due to the high series resistance of the diodes Tunable filters which maintain excellent filter performance will greatly enhance the functional ity of receiver systems and reduce the need for space consuming filter banks. A 0.1dB Chebyshev prototype bandpass filter is designed on quartz using /2 shunt open stubs and /4 connecting lines. Although, the slow-wave unit cell can be used to implement these transm ission lines, it was not attempted in this work. However, they were implemented on 500 m thick quartz substrate using DMTL. The comparison between measured and EM simu lation is presented in Appendix D. b) Phased Array The applications of phase shifter in high fr equency circuits are numerous, but the most important application is in a pha sed array system. It is easier to integrate the phase shifter described in this work with a planar antenna (example: microstrip, CPW, or slot-line) to realize a phased array system than a waveguide or coaxial based antenna. For example, in a aperture coupled antenna the lid (where the ra diating element is typically located) can act as a package for the MEM device (0-level wafer package) [59]. The design of aperture coupled antenna is given in [59, 60, 61]. Before such integration is atte mpted it is desirable to understand the effect of lid on the phase shif ter performance. As an example, a 1cm long 50 line on quartz (25/250/25) is simulated using momentum with a 100 m thick quartz lid (r=3.8) on top of the CPW line. The lid is simulated with a minimum location of 3 m above the CPW (since MEM structures are located 2 m above the CPW). Quartz lid is chosen so that the mismatch in the dielectric half-space ab ove the CPW plane is minimized. Figure 5.1 shows the simulated data for absolute phase (deg) and S21 (dB/cm). It is seen

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84from this figure that there is 7% change in absolute phase and 10% increase in S21 (dB/cm) when the lid is located at 3 m versus 10 m. Furthermore, it was found that in order to avoid any interference from the lid, a spacing of 20 m or more is required. Experimental verification of the above claim is required before using the phase shifter in an aperture coupled antenna or packaging the devi ce with a quartz lid. Similar studies can be done with other dielectric constant to find the optimum packaging material. Fre q uenc y ( GHz ) 01020304050 Phase (deg/cm) -1200 -800 -400 0 Lid 10um above Lid 3um above Fre q uenc y ( GHz ) 01020304050 S21 (dB/cm) -2.0 -1.5 -1.0 -0.5 0.0 Lid 10 m above Lid 3 m above (a) (b) Figure 5.1: Momentum simulation of a 1cm long line on 500 m thick quartz with 100 m thick quartz lid at different heights above CPW line, a) Absolute phase in deg, b) S21 (dB/cm). c) Power Handling Measurement Power handling measurement of the phase shifter needs to be done. The power handling of the phase shifter can be limited by either the current density on the transmission line causing excessive heating or by the MEMS bridges being pulled down due to the average RF voltage on the line. Since the electrostatic force attracts the bridge towards the center conductor with either a positive or negative vo ltage, it appears as a rectified RF voltage and the average voltage level of the rectified si ne wave due to the RF power on the line is pulling on the bridge (“ self-actuation ”) [32]. The average voltage of a rectified sine wave is given by:

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85 2 01T o avgoV VVsintdt T (5.1) where 2 T. The RF power in terms of the peak voltage, Vo is given by: 22o oV P Z (5.2) Where, Zo is the characteristic impedance of th e transmission line and typically near 50 Using (5.2), the RF power on the DMTL can be written as: 222avgV P Z (5.3) Using this equation, the predicted RF power le vel at which the slow-wave unit cell, with a 25V pull down voltage, will be pulled down is 61.6W while for a pull-down voltage of 20 V, the RF power level is 39.5W. VNA Amplifier DUT Isolator Attenuator Power Meter Figure 5.2: Typical setup for power handling measurement of slow-wave phase shifter. Typical setup for power handling measurement is shown in Figure 5.2 [24]. It is believed that the slow-wave phase shifter can handle high er power than DMTL or other electrostatic based MEM device where the anchor is typica lly located on the CPW ground. This is because, the shunt bridges ( Cbs) is not anchored on the CP W ground and the ground-plane bridges ( Cbg) does not interact with the center conduc tor. Therefore, high power RF signal does not have affect the bridge movement.

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86 CbsCbg Figure 5.3: Schematic of the slow-wave unit cell. However, it is possible that the large amount of RF current in the center conductor can heat up the bridges such that some amount of annealing occurs resulting in a higher pulldown voltage. For quartz based designs, this heating is worse due to low thermal conductivity of quartz (0.014 W/cm-K), compared to the th ermal conductivity of silicon which is 1.5 W/cmC [23].

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87BIBLIOGRAPHY [1] H. A. Atwater, “Circuit design of the loaded-line phase shifter,” IEEE Trans. Microwave Theory and Tech. vol. 33, no. 7, pp. 626-634, July 1985. [2] G. Rebeiz, RF MEMS Theory, Design and Technology, John Wiley & Sons, Inc., New York, 2003. [3] N. Camilleri, D. Lovelace, J. Costa, and D. Ngo, “New development trends for silicon RF device technologies,” 1994 IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium pp. 5-8, May 1994. [4] M. Case, M. Matloubian, H. C. Sun, D. Choudhury, and C. Ngo, “ High-performance Wband GaAs PIN diode single-pole trip le-throw switch CPW MMIC,” 1997 IEEE MTT-S Int. Microwave Symp. Dig. pp. 1047-1050, Denver, CO, June 1997. [5] W. P. Clark, “A high power phase shifter for phased array systems,” IEEE Trans. Microwave Theory and Tech. vol. 13, pp. 785-788, November 1965. [6] C. Chen, W. E. Courtney, L. J. Mahoney, M. J. Manfra, A. Chu, and H. A. Atwater, “A low-loss Ku-band monolithic analog phase shifter,” IEEE Trans. Microwave Theory and Tech. vol. 35, no. 3, pp. 315-320, March 1987. [7] N. S. Barker. Personal communications. [8] R. E. Collin, Foundations for Microwave Engineering, McGraw-Hill, Inc., New York, 2nd edition, 1992. [9] E. K. Chan, E. C. Kan, R. W. Dutton, and P. M. Pinsky, “Nonlinear dynamic modeling of micromachined microwave switches,” 1997 IEEE MTT-S Int. Microwave Symp. Dig. pp. 1511-1514, Denver, CO, June 1997.

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88 [10] L. W. Couch II, Digital and Analog Communication Systems, Macmillan Publishing Company, New York, 4th edition, 1993. [11] F. De Flaviis, N. G. Alexopoulos, and O. M. Stafsudd, “Planar microwave integrated phase-shifter design with high purity ferroelectric material,” IEEE Trans. Microwave Theory and Tech. vol. 45, no. 6, pp. 963-969, June 1997. [12] C. Goldsmith, T. H. Lin, B. Powers, W. R. Wu, and B. Norvell, “ Micromechanical membrane switches for microwave applications,” 1995 IEEE MTT-S Int. Microwave Symp. Dig. pp. 91-94, Orlando, FL, June 1995. [13] J. M. Gere and S. P. Timoshenko, Mechanics of Materials, PWS Publishing Company, Boston, 4th edition, 1997. [14] B. Glance, “A fast low-lo ss microstrip PIN phase shifter,” IEEE Trans. Microwave Theory and Tech. vol. 27, no. 1, pp. 14-16, January 1979. [15] A. M. Dec, Design and Analysis of Microwave Oscillators, PhD thesis, Columbia University, New York, NY, 1998. [16] C. Goldsmith, J. Randall, S. Eshelman, T. H. Lin, D. Dennistor, S. Chen, and B. Norvell, “Characteristics of micromachined switches at microwave frequencies,” 1996 IEEE MTT-S Int. Microwave Symp. Dig. pp. 1141-1144, San Francisco, CA, June 1996. [17] W. E. Hord, “Design considerations for ro tary-field ferrite phase shifters,” Microwave Journal, vol. 31, pp. 105-115, November 1988. [18] R. T. Howe and R. S. Muller, “Resonant-microbridge vapor sensor,” IEEE Transactions on Electron Devices, vol. ED-33, no. 4, pp. 499-506, April 1986. [19] S. Barker, and G. Rebeiz, “Optimization of distributed MEMS transmission-line phase shifters-U-band and W-band designs,” IEEE Trans. Microwave Theory and Tech. vol. 48, pp. 1956-1966, Nov 2000. [20] S. Barker, and G. Rebeiz, “Distributed MEMS true-time delay phase shifters and wideband switches,” IEEE Trans. Microwave Theory and Tech. vol. 46, no. 11, pp. 1881-1889, Nov 1998.

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89 [21] H.T. Kim, J.H. Park, S. Lee, S. Kim, J.M. Kim, Y.K. Kim, and Y.Kwon, “V-band 2-b and 4-b low-loss and low-voltage distributed MEMS digital phase shifter using metal-airmetal capacitors,” IEEE Trans. Microwave Theory and Tech. vol. 50, pp. 2918-2923, Dec 2002. [22] J.S. Hayden, and G. Rebeiz, “Very lo w-loss distributed X-band and Ka-band MEMS phase shifters using meta l-air-metal capacitors,” IEEE Trans. Microwave Theory and Tech. vol. 51, no. 1, pp. 309-314, Jan 2003. [23] J. Hung, L. Dussopt, and G. Rebeiz, “Distributed 2and 3-bit W-band MEMS phase shifters on glass substrates,” IEEE Trans. Microwave Theory and Tech. vol. 52, no. 2, pp. 600-606, Feb 2004. [24] W. E. Hord, “Microwave and millimeter wa ve ferrite phase shifters,” Microwave Journal, vol. 32, pp. 81-89, 1989. [25] S. K. Koul and B. Bhat, Microwave and Millimeter Wave Phase Shifters, volume I, Artech House, Boston, 1991. [26] Kovacs, Micromachined Transducers Source Book, WCB/McGraw-Hill, Boston, 1998. [27] L. E. Larson, R. H. Hackett, M. A. Melendes, and R. F. Lohr, “Micromachined microwave actuator (MIMAC) technology a new tuning approach for microwave integrated circuits,” 1991 IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium pp. 27-30, 1991. [28] C. C. Ling and G. M. Rebeiz, “A 94 GHz planar monopulse tracking receiver,” IEEE Trans. Microwave Theory and Tech. pp. 1863-1871, October 1994. [29] A. Megej and V. F. Fusco, “Low-loss analog phase shifter using varactor diodes,” Microwave and Optical Technology Letters vol. 19, no. 6, pp. 384-386, December 1998. [30] A. S. Nagra, J. Xu, E. Erker, and R. A. York, “Monolithic GaAs phase shifter circuit with low insertion loss and continuous 0-360 phase shift at 20 GHz,” IEEE Microwave and Guided Wave Letters vol. 9, no. 1, pp. 31-33, January 1999.

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90 [31] A. S. Nagra and R. A. York, “Distributed analog phase shifters with low insertion loss,” IEEE Trans. Microwave Theory and Tech. pp. 1705-1711, September 1999. [32] S. Pacheco, C. T. Nguyen, and L. P. B. Katehi, “Micromechanical electrostatic K-band switches,” 1998 IEEE MTT-S Int. Microwave Symp. Dig. pp. 1569-1572, Baltimore, MD, June 1998. [33] C. K. Pao, J. C. Chen, G. L. Lan, D. C. Wang, W. S. Wong, and M. I. Herman, “Vband monolithic phase shifters,” IEEE GaAs IC Symposium Technical Digest pp. 269272, November 1988. [34] D. M. Pozar, Microwave Engineerin g, Addison-Wesley Publishing Company, Reading, MA, 1990. [35] S. Raman, An Integrated Millim eter-Wave Monopulse Radar Receiver with Polarimetric Capabilities, PhD thesis, The University of Michigan, Ann Arbor, MI, 1998. [36] J. B. Hacker, R. E. Mihailovich, M. Ki m, and J. F. DeNatale, “A Ka-band 3-bit RF MEMS true-time-delay network,” IEEE Trans. Microwave Theory and Tech. vol. 51, pp. 305–308, Jan 2003. [37] J. B. Rizk and G. M. Rebeiz, “W-band microstrip RF-MEMS switches and phase shifters,” 2003 IEEE MTT-S Int. Microwave Symp. Dig. Philadelphia, PA, June 2003, pp. 1485–1488. [38] R. J. Roark and W. C. Young, Formulas for Stress and Strain, McGraw-Hill Book Co., Inc., New York, 6th edition, 1989. [39] M. J. W. Rodwell, S. T. Allen, R. Y. Yu, M. G. Case, U. Bhattacharya, M. Reddy, E. Carman, M. Kamegawa, Y. Konishi, J. Pusl, and R. Pullela, “Active and nonlinear wave propagation devices in ultra fast electronics and optoelectronics,” Proceedings of the IEEE vol. 82, no. 7, pp. 1037-1059, July 1994. [40] P. R. Shepherd and M. J. Cryan, “Schott ky diodes for analogue phase shifters in GaAs MMIC's,” IEEE Trans. Microwave Theory and Tech. vol. 44, no. 11, pp. 2112-2116, November 1996.

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91 [41] R. K. Hoffmann, Handbook of Microwave Integrated Circuits, Artech House, Inc., Norwood, MA, 1987. [42] D. B. Rutledge, D. P. Neikirk, and D. P. Kasilingam, “Integrated-circuit antennas,” Infrared and Millimeter Waves, K. J. Button, editor, volume 10, chapter 1, Academic Press, New York, 1983. [43] J. I. Seeger and S. B. Crary, “Stabiliz ation of electrostatically actuated mechanical devices,” 1997 International Conference on Solid-State Sensors and Actuators volume 2, pp. 1133-1136, June 1997. [44] M. J. W. Rodwell, M. Kamegawa, R. Yu M. Case, E. Carman, and K. S. Giboney, “GaAs nonlinear transmission lines for pico second pulse generation and millimeter-wave sampling,” IEEE Trans. on Microwave Theory and Techniques pp. 1194-1204, July 1991. [45] S. M. Sherman, Monopulse Principles and Techniques, Artech House, Dedham, MA, 1984. [46] D.F. Williams et al., “Comparison of On-Wafer Calibrations,” 38th ARFTG Conference Digest pp. 68-81, Dec. 1991. [47] R. B. Marks, “A Multi-line Method of Network Analyzer Calibration,” IEEE Trans. MTT, vol. 39, no. 7, pp. 1205-1215, Jan 1991. [48] V. Sokolov, J. J. Geddes, A. Contolatis, P. E. Bauhahn, and C. Chao, “A Ka-band GaAs monolithic phase shifter,” IEEE Trans. Microwave Theory and Tech. vol. 31, no. 12, pp. 1077-1083, December 1983. [49] S. M. Sze, Physics of Semiconductor Devices, John Wiley & Sons, New York, 2nd edition, 1981. [50] Y. Liu, A. Borgioli, A.S. Nagra, and R.A. York, “K-band 3-bit low-loss distributed MEMS phase shifter,” IEEE Microwave and Guided Wave Letters vol. 10, no. 10, pp. 415417, Oct 2000.

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92 [51] B. Lakshminarayanan, and T. Weller, “D istributed MEMS phase shifters on silicon using tapered impedance unit cells,” 2002 IEEE MTT-S Int. Microwave Symp. Dig. Phoenix, AZ, June 2002, pp. 1237-1240. [52] A. Gorur, C. Karpuz, and M. Alkan, “C haracteristics of periodically loaded CPW structures,” IEEE Microwave and Guided Wave Letters vol. 8, no. 8, pp. 278-280, Aug 1998. [53] H. Kim, S. Lee, J. Kim, J. Park, Y. Kim, and Y. Kwon, “A V-band CPS distributed analog MEMS phase shifter,” 2003 IEEE MTT-S Int. Microwave Symp Dig., Philadelphia, PA, June 2003, pp. 1481-1484. [54] B. Lakshminarayanan, and T. Weller, “MEMS phase shifters using cascaded slow-wave structures for improved impedance matching and/or phase shift,” 2004 IEEE MTT-S Int. Microwave Symp Dig., vol. 2, pp. 725-728. [55] B. Pillans, S. Eshelman, A. Malczewsk i, J. Ehmke, and C. Goldsmith, “Ka-band RF MEMS phase shifters,” IEEE Microwave Guided Wave Letters vol. 9, pp. 520–522, Dec. 1999. [56] S. Uysal, Nonuniform Line Microstrip Directional Couplers and Filters, Artech House, Norwood, MA, 1993. [57] B. Lakshminarayanan, and T. Weller, “Tunable Bandpass Filter Using Distributed MEMS Transmission Lines,” 2003 IEEE MTT-S Int. Microwave Symp Dig., vol. 3, pp. 1789-1792. [58] F. W. Van Keuls, R. R. Romanofsky, N. D. Varaljay, F. A. Miranda, C. L. Canedy, S. Aggarwal, T. Venkatesan, and R. Ramesh, “A Ku-band gold/BaxSr1-xTiO3/LaAlO3 conductor/thin-film ferroelectric microstrip line phase shifter for room-temperature communications applications,” Microwave and Optical Technology Letters vol. 20, no. 1, pp. 53-56, January 1999.

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93 APPENDICES

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94APPENDIX A: CPW TRANSMISSION LINE LOSS A.1 CPW Lines on Quartz This appendix presents measured and pr edicted results for loss (dB/cm) on 500 m thick quartz substrate. For all the measured data presented herein, the line is measured on a 700 m thick air cavity to avoid any excitation of parallel-plate waveguide mode [55] and the reference impedance is set to the line Zo. The conductor loss ( ) calculated from conformal mapping technique in [46] is quoted again in (A.1): 2 28686 41 2ln 1 41 8686 41 2 ln 1 41seff o seff o.R Wk (W,S) tk SKkKkk .R Wk S dB/length Wtk SKkKkk (A.1) where K ( k ) is the complete elliptic in tegral of th e first kind, 2 kW/(WS), 21 kk, t is the metal thickness, Rs is the surface resistance given by 12 / sRf and is the conductivity of the metal. a) 1m thick evaporated metallization (Cr/Au) The CPW lines (in Table A.1) were fabricated on 500m thick quartz (r=3.8) with 200 of Cr and 1m thick evaporated Au. The predicted loss (in dB/cm) using (A.1) versus frequency and the measured data for (Line 1 and Line 7) is shown in Figure A.1. As can be seen, for the same metal thickness, two differe nt correction factors are required to match the measured loss data. This was verified for all the lin es and loss versus CPW pitch ( 2 WWS ) at 50GHz is shown in Figure A.1. The multiplication factor is chosen such that best possible match is ob tained through 50GHz (instead of just matching the 50GHz data point). Therefore, some of the data poin ts shown in this figure is slightly off the predicted curve.

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95APPENDIX A (continued) Table A.1: CPW dimensions for the lines used in this section. The resistance per unit length of each line is extracted from the measured data. WS Line 1 7611210.97 Line 2 1001007.98 Line 3120907.68 Line 4144788.25 Line 5160708.87 Line 61104511.29 Line 7 1403013.92 Line 82303511.15 at 50GHztR /cm Frequency (GHz) 01020304050 Loss (dB/cm) 0.0 0.5 1.0 1.5 1.91 Eqn B.1 1.67 Eqn B.1 30/140/30 76/112/76 Figure A.1: Comparison between measured and predicted loss versus frequency. b) 3m Electroplated metallization (Ti/Au) The CPW lines in Table A.1 was electroplated up to 3m and the comparison of measured and predicted loss (Line 2 and Line 8) versus fr equency is shown in Figure A.3. In Figure A.4 the comparison between measured and pr edicted loss (dB/cm) versus CPW pitch at 50GHz. It is seen that the correction factor required to match the measured data is the same for the lines (except for Line 1 and 7).

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96APPENDIX A (continued) 0.150.300.450.600.750.90Loss (dB/cm) at 50GHz 0.0 0.5 1.0 1.5 2.0 2.5 Zo (ohms) 40 50 60 70 80 90 100 110 1.53 Eqn. B.1 1.67 Eqn. B.1 1.47 Eqn. B.1 1.91 Eqn. B.1 S=200 m S=300 m W/(W+2S) Figure A.2: Comparison between measured a nd predicted loss at 50GHz versus CPW pitch for 1m evaporated line. For the data presented he rein, four different correction factor is used to match the measured data. The characteri stic impedance for the lines is listed above the plot. Frequency (GHz) 01020304050 Loss (dB/cm) 0.0 0.5 1.0 1.43 Eqn B.1 1.43 Eqn B.1 35/230/35 90/120/90 Figure A.3: Comparison between meas ured and predicted loss (dB/cm). A.2 CPW Lines on Silicon This section presents measured and modeled data for CPW lines measured on 425m thick silicon ( 2000-cm). Table A.2 shows the footprints of the lines used in this work. The comparison between measured and modeled loss (dB/cm) data for the two lines (“*” in Table A.2) is shown in Figure A.5. As with th e measured data on quar tz, the loss data on

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97APPENDIX A (continued) silicon required a multiplication factor that varies with CPW pitch (Figure A.6). This multiplication factor is used in calculating th e (dB/cm) versus CPW pitch and the result is shown in Figure A.7. 0.150.300.450.600.750.90Loss (dB/cm) at 50GHz 0.0 0.4 0.8 1.2 1.6 Z o ( ) 40 50 60 70 80 90 100 110 1.43 Eq n., B.1 1.82 Eq n., B.1 1.77 Eq n., B.1 W/(W+2S) Figure A.4: Comparison between measured a nd predicted loss at 50GHz versus CPW pitch for 3m plated lines. Table A.2: CPW footprints used on high resistive silicon ( 2000-cm) substrate. WS Zo ( ) WS Zo ( ) 40 17.546.06804549.6 3022.553.821806042.91 5522.545.21247550.82 403053.84100 10058.81 1703035.9912010054.13 2503534.025410170.05

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98APPENDIX A (continued) Frequency (GHz) 01020304050 Loss (dB/cm) 0.0 0.5 1.0 1.5 2.0 2.5 0.83 Model (17.5/40/17.5) Meas (17.5/40/17.5) Frequency (GHz) 01020304050 Loss (dB/cm) 0.0 0.5 1.0 1.5 2.0 2.5 Model (100/100/100) Meas (100/100/100) Figure A.5: Comparison between measured and modeled loss (dB/cm) data on a 425m thick high resistive ( 2000-cm) silicon substrate, a) W/S/W=17.5/40/17.5, b) W/S/W=100/100/100. W /( W+2S ) 0.10.20.30.40.50.60.70.80.9 Correction Factor 0.5 1.0 1.5 2.0 2.5 Figure A.6: Multiplication fact or required to match the measured data on high resistive silicon substrate. W/(W+2S) 0.10.20.30.40.50.60.70.80.9Loss (dB/cm) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Zo ( ) 30 35 40 45 50 55 60 65 70 75 S=100 S=300 Figure A.7: Comparison between measured a nd predicted loss at 50GHz versus CPW pitch. The multiplication factor in Figure A.6 is used for the measured data.

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99APPENDIX B: DETAILED FABRICATION PROCESS This appendix discusses the fabrication process used for the slow-wave MEMS phase shifter discussed in this chapter 3. The quartz substrate is 500 m thick, 2 inch square, and singlesided polished. 1. Wafer Cleaning: (a) Immerse the wafer for 15-20 sec in 50:1 HF:H2O with gentle agitation. This step is followed by 3 rinse cycles ( 3min) in de-ionized (DI) H2O. (b) Blow dry with N2. Dehydrate bake on a 130 C hotplate for 4 minutes. 2. SiCr bias lines lift-off: (a) Spin coat with NR-3000PY(1) photoresist (PR) at 3000 rpm for 40 sec. (b) Soft bake on a 155 C hotplate for 1 min. (c) Align a clear-field mask, exposing areas where the SiCr bias lines is to be lifted off. (d) Expose at 13-14 mW/cm2 for 17 sec. (e) Pre-develop bake on a 110 C hotplate for 1min. (f) Develop using RD-6(2) developer for 25 sec, rinse in DI H2O for 1min and dry with N2. (g) Evaporate SiCr using E-beam evaporation to 1000-1500. (h) Soak in RR4(3) PR remover at 110 with agitation for 5min in order to lift-off undesired metal, rinse in DI H2O for 1min and dry with N2. 3. SixNy Ground Isolation Layer: (a) Clean in a 200 mT O2 Plasma at 100 W for 90 sec. (b) Spin coat with NR-3000PY photoresist (PR) at 3000 rpm for 40 sec. (1),(2),(3) NR-3000PY, RD-6, RR-4 is manufactured by Futurrex, Inc., Franklin, NJ.

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100APPENDIX B (continued) (c) Soft bake on a 155 C hotplate for 1 min. (d) Align a clear-field mask, exposing areas where the SixNy areas is to be lifted off. (e) Expose at 13-14 mW/cm2 for 17 sec. (f) Pre-develop bake on a 110 C hotplate for 1min. (g) Develop using RD-6 developer for 25 sec, rinse in DI H2O for 1min and dry with N2. (h) Sputter SixNy using RF-magnetron at 3mT, 20SCCM Ar, and 225W RF power to 3000-4000. (i) Soak in RR4 PR remover at 110 with agitation for 5min in order to lift-off undesired SixNy, rinse in DI H2O for 1min and dry with N2. (j) Alternatively, the after step (a) the SixNy can be blanket deposited and etched subsequently using CF4/O2 plasma with the same light-field mask and a positive-tone PR (Shipley-1827). The etch recipe used in this work is listed in Table B.1. Note: The SixNy layer is not used in the 2nd generation slow-wave phase shifter designs. Table B.1: Sputtered SixNy etch recipe used in this work. Gas (in SCCM ) CF4:O2 = 20: 2 Pressure150mT RF Power150W Time 17 min SixNy Etch 4. CPW metal lift-off: (a) Clean in a 200 mT O2 Plasma at 100 W for 90 sec. (b) Spin coat with NR-3000PY photoresist (PR) at 3000 rpm for 40 sec. (c) Soft bake on a 155 C hotplate for 1 min. (d) Align a clear-field mask, exposing areas wher e the CPW metal areas is to be lifted off. (e) Expose at 13-14 mW/cm2 for 17 sec. (f) Pre-develop bake on a 110 C hotplate for 1min. (g) Develop using RD-6 developer for 25 sec, rinse in DI H2O for 1min and dry with N2.

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101APPENDIX B (continued) (h) Evaporate Cr/Au to 1 m thickness. Alternatively, a Cr/Ag/Cr/Au metallization stack can also be used with the 8000 of Ag and 2000 of Au. There was no noticeable difference in the insertion loss for the two cases up to 65GHz. (i) Soak in RR4 PR remover at 110 with agitation for 5min in order to lift-off undesired SixNy, rinse in DI H2O for 1min and dry with N2. 5. Sacrificial Layer Deposition: (a) Clean in a 200 mT O2 Plasma at 100 W for 90 sec. (b) Spin coat adhesion promoter Hexamethyldisilazane (HMDS) at 1600-1700 rpm for 45 sec. (c) Spin coat PMMA (950K, 9% in anisole solvent) at 1600-1700 rpm for 45 sec. (d) Bake on a 180 hotplate for 90-120 sec. (e) Flood evaporate 1500-2000 of Ti. (f) Spin coat HMDS at 3000 rpm for 30 sec. (g) Spin coat with Shipley 1827 PR at 3000 rpm for 30 sec. (h) Soft bake on a 105 C hotplate for 90 sec. (i) Align a dark-field mask, exposing the pedestal areas. (j) Expose at 13-14 mW/cm2 for 22 sec. (k) Develop in MF319 for 70 sec. Rinse in DI and dry with N2. (l) Etch Ti in 1:10 HF:DI for 7-10 sec. Rinse in DI and dry with N2. (m) Flood expose for 50 seconds at 13 mW/cm2. (n) Develop in MF319 for 70 sec. Rinse in DI and dry with N2. (o) Etch PMMA in 50 mT, 100 SCCM O2 plasma 250W, for 12 minutes. (p) Remove Ti in 1:10 HF:DI for 10 sec. Rinse in DI and dry with N2. 5. MEM bridge fabrication and release: (a) Evaporate Ti/Au 80/2000 seed layer using E-beam evaporation. (b) Spin coat with Shipley 1827 PR at 3000 rpm for 30 sec. (c) Soft bake on a 105 C hotplate for 90 sec. (d) Align a dark-field mask, exposing the areas to be electroplated that include pedestal, beam and CPW lines. Expose for 18 sec at 13-14mW/cm2. (e) Develop in MF319 for 60 sec. Rinse in DI and dry with N2.

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102APPENDIX B (continued) (f) Skip hard bake step. Electroplate Au using TG-25E(4) for 30min resulting in 1-1.2 m thick Au layer. (g) Flood expose for 50 seconds at 13 mW/cm2. (h) Develop in MF319 for 60 sec. Rinse in DI and dry with N2. (i) Anneal on 105 C hotplate for 60 sec. (j) Anneal on 120 C hotplate for 90 sec. Allow samp les to reach room temperature. (k) Spin coat with Shipley 1827 PR at 3000 rpm for 30 sec. (l) Align mask and expose for 17 sec at 13-14mW/cm2. (m) Wet etch Au in gold etchant. The etch rate is approximately 28/s at 25 C. (n) Etch Ti in 1:10 HF:DI for 6-8 sec. Rinse in DI and dry with N2. (o) Heat Shipley 1165 to 80 C. Soak the samples completely for 5min. (p) Transfer to Shipley 1165 solution at 40C. Release MEM bridges overnight. (q) Rinse in DI for 5 min. (r) Transfer from DI to IPA and then to fres h IPA to remove all DI. Repeat this step twice. (s) Transfer to methanol and then to fresh methanol. Repeat this process twice. (t) Dry samples using Critical -Point-Drying (CPD) [46]. (u) If necessary, clean the samples in a 200 mT O2 plasma at 100W for 3 min. (4) TG-25E Au plating solution manufactured by Technic Inc., Cranston, Rhode Island.

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103APPENDIX C: TUNABLE BANDPASS FILTER USING DMTL A 0.1dB Chebyshev prototype bandpass filter is designed on quartz using /2 shunt open stubs and /4 connecting lines (Figure C.1). The series and the shunt transmission lines are implemented using DMTL instead. 4 Input Output 2 kY 1 k,kYkY kY kY Figure C.1: Schematic of the tunable filter utilizing /2-open stubs and /4 series connecting sections [36]. The design is carried out first to give /4 length for series a nd shunt short circuit stub sections for a desired pass-ba nd characteristic and bandwidth from the low-pass to bandpass transformation [58]. Then each shunt, qu arter-wave length short-circuited stub of characteristic admittance (Yk) is replaced by a shunt, /2 open-circuited stub having a impedance (Yk) given by: 2 1 2 11 1k kYatan Y atan (5.1) 2 02 acot (5.2) 1 1 k,k k,kA AJ YY Y (5.3) Where, 1102 and 10is the bandwidth and is the frequency at which the shunt lines present short circui ts to the main line and cause attenuation. In this work, the value of Yk = Yk

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104APPENDIX C (continued) The bandpass filter presented herein consists of nine reactive elements: six open stubs that are /2 long and three series /4 long connecting lines betw een the open stubs (Figure C.2). The open stub design is preferred over a short end /4 stub design beca use it is easier to DC bias the circuit using coaxial bias t ees. The series connecting sections (unloaded Zo~80 ) are periodically loaded with three shunt capacitors, each spaced by 850 m The shunt /2 stubs (unloaded Zo~70) utilize four capacitors with a separation of 350 m The beams used for the capacitors in the series and shunt sections are approximately 755 m and 970 m long, respectively; the beam width is held constant at 35 m. The overall footprint of the filter is 8mm 4.7mm and a total of 33 capacitive bridges are used. The widths of the center conductor and the slot for the feed are 300 m and 30 m, respectively. The series DMTL section is required to be approximately /4 long at each design center frequency. For an unloaded line on quartz the corresponding le ngths would be 2220m at 22GHz and (2200+741=) 2961 m at 16.5GHz. The phase shift required to emulate the additional length of 741 m at 16.5GHz is found to be approximately 20. The required phase shift ( ) as a function of the CPW line charac teristic impedance can be calculated using equations presented in chapter 2 [22]. Three capacitive bridges separated by 850 m provide the necessary variation in characteristic impedance and result in a 90 phase shift at each of the desired frequencies (22GHz when MEM bridge in the up-state a nd 16.5GHz when MEM bridge in the downstate). The upstate and the downstate values of each MEMS capacitor are approximately 0.07pF and 0.1pF, respectively. The shunt open stubs are /2 long at each design center frequency (5942 m at 16.5GHz; 4456 m at 22GHz). The length difference translates to a 44 phase difference at 16.5GHz. In this case, four capaciti ve bridges separated by 350m are used. The upstate and the downstate capacitance for these capacitors ar e approximately 0.2 and 0.4pF, respectively. The higher capacitance values, relative to those used in the series sections, are used for two

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105APPENDIX C (continued) reasons: to reduce the size of the filter by in creasing the loading, and to reduce the number of required bridges. It was also found that the increased distributed loading yields a better response than that obtained with a comp arable design using shunt stubs that are terminated in large, single ca pacitors for length reduction. Shunt open stub Series Lines 2 4 2 2 8mm Al sputtered beam Si3N4 MIM Top plate Cyclotene polymer dielectric (a) (b) Figure C.2: Schematic of the tuna ble filter designed with DMTL. Table C.1 gives the capaci tance values for the series and shunt sections. In order to design low capacitance ratios that are feasible to fabr icate, MIM capacitors are used in series with the MEM bridges [59]. The MIM capacitors are placed 40-50m away from each MEMS capacitor (Figure C.2(b)). Table C.1: Capacitance values for the series /4 sections and the open /2 stubs in the upstate and downstate. Cup [pF]Cdown [pF] Series /4 sections 0.070.1 Shunt /2 sections 0.20.4 The starting values for the admittances of th e shunt stubs were calculated using equations given in [8]. The final values of the admittances were found by circuit level simulation, after accounting for parasitics extr acted via numerical EM simulation. Full-wave simulations were performed using ADS Momentum™. The para sitic effects due to the cross and the teejunction discontinuities required the length of the shunt and series sections to be adjusted.

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106APPENDIX C (continued) The filter is fabricated on a 480m thick quartz substrate (r=3.78, tan=0.0004). The fabrication steps are as follows: A 0.5um thick Si3N4 is blanket deposited using RF magnetron sputtering to improve the adhesion of metal lines on the quartz. Al ternatively, a thin Cr layer can be used but this approach requires etching in subsequent fabrication steps. Lift–off processing is used to defi ne metal lines to a thickness of 1m (Cr/Ag/Cr). A 3m thick photosensitive cyclotene™ polymer (r=2.7) is used to form a MIM capacitor dielectric layer. A 0.5m thick Si3N4 is deposited using RF magnetron sputtering. Contact pads (0.2m thick) comprised of Cr/Au are formed using liftoff processing for RF probing. Pedestal areas are patterned with photoresist and the 3m thick cyclotene™ polymer is used to form the posts. A 0.8m thick Al layer is sputtered on top the sacrificial photoresist layer and subsequently etched to form the capacitor beam geometry. The sacrificial photoresist is removed and critical point drying is used to release the MEMS capacitors. Measurements were performed from 10 –30GHz using a Wiltron 360B VNA and 250m pitch GGB microwave probes. A Thru–Reflect–L ine (TRL) calibration was performed using calibration standards fabricated on the wafer. A high voltage bias tee was used to supply voltage through the RF probe to avoid damagi ng the VNA test port s. Typical actuation voltage of the beams is approximately 45-50V. This is because the Al sputtered beam after release had some amount of tensile stress and buckle up by a factor of 0.3-0.5 m (10-16% of 3 m height). Further optimization of process parameter to make the bridge flat was not attempted since the sputtering chamber wa s not available for metal deposition. Figure C.3 shows the comparison between the me asured and simulated filter response in the upstate. The measured response has S11 < -19dB and a maximum S21 of -3.3dB in the pass-

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107APPENDIX C (continued) band. The relative bandwidth of the filter in the upstate is approximately 16.5% (20.424GHz) and the out of band rej ection is better than 25dB over the measured frequency range. The measured data shows a larger bandwidth and higher insertion loss when compared to the simulation re sults. The increased bandwidth is attributed to fabrication tolerance, resulting in a higher capacitance of the MEM bridges. The higher insertion loss is due to the resistance of the bridges (not accounted for in the simulations). Frequency (GHz) 1015202530 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Measurement EM Simulation Frequency (GHz) 1015202530 S 21 (dB) -60 -50 -40 -30 -20 -10 0 Measurement EM Simulation (a) (b) Figure C.3: Comparison between measured da ta and modeled data in the up-state, a) S11, b) S21. Solid lines represent EM simulation data and dashed lines represent measured data. Figure C.4 shows the comparison between the measured and simulated data in the downstate. The measured S11 is less than -30dB and S21 is approximately -2.3dB in the pass-band (15.7-17.8GHz). The me asured and the modeled filter results exhibit a spurious response above 25GHz that is associated with the 20 pass-band characteristic. The relative bandwidth of the filter is approximately 11.5% The absolute bandwidth in the upstate and downstate is approximately 3.6GHz and 2.8GHz, respectively. In order to maintain ab solute bandwidth in both the states, independent and Zo-tuning of the /2 and /4 section is required. However, DMTL implementation such as shown herein, can provide only -tuning with dependent Zo levels. Therefore, maintaining absolute bandwidth between tunable states becomes di fficult. However, the slow-wave unit cell

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108APPENDIX C (continued) configured in a manner similar to the tunable MEMS transmission (see chapter 4) can be used in the filter design resulting in constant bandwidth be tween tuned states. Frequency (GHz) 1015202530 S 11 (dB) -60 -50 -40 -30 -20 -10 0 Measurement EM Simulation Frequency (GHz) 1015202530 S 21 (dB) -60 -50 -40 -30 -20 -10 0 Measurement EM Simulation Figure C.4: Comparison between measured da ta and modeled data in the down-state, a) S11, b) S21. Solid lines represent EM simulation data and dashed lines represent measured data. In order to maintain ab solute bandwidth in both the states, independent and Zo-tuning of the /2 and /4 section is required. However, DMTL implementation such as shown herein, can provide only -tuning with dependent Zo levels. Therefore, maintaining absolute bandwidth between tunable states becomes difficult. However, the slow-wave unit cell configured in a manner similar to the tunable MEMS transmission (see chapter 4) can be used in the filter design resulting in constant bandwidth be tween tuned states.

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ABOUT THE AUTHOR Balaji Lakshminarayanan received his BS and MS degrees in 1995 and 1999 respectively. His research interests are in the area of RF-MEMS techniques for microwaves, application of micromachining for mm-wave circuits, and electromagnetic modeling of VLSI and microwave circuits.


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ABSTRACT: A true time delay multi-bit MEMS phase shifter topology based on impedance-matched slow-wave CPW sections on a 500 m thick quartz substrate is presented. Design equations based on the approximate model for a distributed line is derived and used in optimization of the unit cell parameters. A semi-lumped model for the unit cell is derived and its equivalent circuit parameters are extracted from measurement and EM simulation data. This unit cell model can be cascaded to accurately predict N-section phase shifter performance. Experimental data for a 4.6mm long 4-bit device shows a maximum phase error of 5; and S11 less than -21dB from 1-50GHz. A reconfigurable MEMS transmission line based on cascaded capacitors and slow-wave sections has been developed to provide independent Zo and -tuning. In the Zo-mode of operation, a 7.4mm long line provides Zo-tuning from 52 to 4 (+/-2;) with constant phase between the states through 50GHz.
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