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An implementation of the usf/ calvo model in verilog-a to enforce charge conservation in applicable fet models

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Title:
An implementation of the usf/ calvo model in verilog-a to enforce charge conservation in applicable fet models
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English
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Nicodemus, Joshua
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University of South Florida
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Subjects / Keywords:
Transcapacitance
Modeling
Nonlinear
Small signal
Large-signal
Inconsistency
Discrepancy
Dissertations, Academic -- Electrical Engineering -- Masters -- USF   ( lcsh )
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government publication (state, provincial, terriorial, dependent)   ( marcgt )
bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

Notes

Abstract:
ABSTRACT: The primary goal of this research is to put into code a unique approach to addressing problems apparent with nonlinear FET models which were exposed by Calvo in her work in 1994. Since that time, the simulation software for which her model was appropriate underwent a significant update, necessitating the rewriting of her model code for a few applicable FET models in a Verilog-A, making it more compatible with the new versions of software and simulators. The problems addressed are the inconsistencies between the small-signal model and the corresponding large-signal models due to a factor called transcapacitance. It has been noted by several researchers that the presence of a nonlinear capacitor in a circuit model mathematically implies the existence of a parallel transcapacitor, if the value of its capacitance is a function of two bias voltages, the local and a remote voltage.
Thesis:
Thesis (M.S.E.E.)--University of South Florida, 2005.
Bibliography:
Includes bibliographical references.
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System requirements: World Wide Web browser and PDF reader.
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Mode of access: World Wide Web.
Statement of Responsibility:
by Joshua Nicodemus.
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Title from PDF of title page.
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Document formatted into pages; contains 62 pages.

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oclc - 62587484
usfldc doi - E14-SFE0001107
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ABSTRACT: The primary goal of this research is to put into code a unique approach to addressing problems apparent with nonlinear FET models which were exposed by Calvo in her work in 1994. Since that time, the simulation software for which her model was appropriate underwent a significant update, necessitating the rewriting of her model code for a few applicable FET models in a Verilog-A, making it more compatible with the new versions of software and simulators. The problems addressed are the inconsistencies between the small-signal model and the corresponding large-signal models due to a factor called transcapacitance. It has been noted by several researchers that the presence of a nonlinear capacitor in a circuit model mathematically implies the existence of a parallel transcapacitor, if the value of its capacitance is a function of two bias voltages, the local and a remote voltage.
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An Implementation of the USF/ Calvo Model in Verilog-A to Enforce Charge Conservation in Applicable FET Models by Joshua Nicodemus A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Arthur David Snider, Ph.D. Lawrence P. Dunleavy, Ph.D. Thomas M. Weller, Ph.D. Date of Approval: March 11, 2005 Keywords: transcapacitance, modeling, non linear, small signal, large-signal, inconsistency, discrepancy Copyright 2005, Joshua Nicodemus

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DEDICATION To my Lord and Savior, Jesus Christ, who has kept me from falling and has given me a new purpose and meaning in my life and for whom I live.

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ACKNOWLEDGEMENTS I would like to express my appreciation and heartfel t gratitude to my major Professor Dr. Dave Snider who has been my source of inspiration, has given me the right direction and has been helpful more than my words can express. I would also like to thank my committ ee members Dr. Dunleavy and Dr. Thomas Weller for their valuable guidance and support throughout the course of my thesis. I would like to than k Jiang Liu for his he lp with the code simulations and William Clausen for providing us with the required parameters. Also I would like to th ank Ms.Norma Paz from the EE department, Kris hna Barri for their support a nd encouragement during these times. I would like to express my gratitude to my aunt and uncle fo r their support and encouragement during my Masters degree. I am grateful to my parents for their patience and prayers. I would like to expr ess a special thanks to my br other who has been a motivating factor. Im appreciative of all my friends who have been with me all throughout.

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i TABLE OF CONTENTS LIST OF FIGURES ii ABSTRACT iv CHAPTER 1 INTRODUCTION 1 CHAPTER 2 DESCRIPTION OF MIRIAM CALVOS NONLINEAR FET MODELS 5 CHAPTER 3 CAPACITANCE AND CH ARGE SOURCE EQUATIONS FOR A CLASSI C NONLINEAR FET MODEL 13 3.1 Capacitance Equations 13 3.2 Charge Source Equations 14 CHAPTER 4 CODE DESCRIPTION 17 CHAPTER 5 SIMULATION RESULTS 22 5.1 Angelov Model Simulations for the Capacitance Model 22 5.2 Angelov Model Simulations for the Charge Model 28 5.3 Angelov-Calvo (New) Model Simulations for the Capacitance Model 32 5.4 Angelov-Calvo (New) Model Simulations for th e Charge Model 38 CHAPTER 6 RECOMMENDATIONS AND CONCLUSIONS 42 REFERENCES 44 APPENDICES 46 Appendix A: CODE 47

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ii LIST OF FIGURES Figure 2.1 Traditional Small Signal MESFET Model 8 Figure 2.2 Industry-Standard Small Signa l Intrinsic Model for the MESFET 9 Figure 2.3 Classical Large Signal MESFET Model 9 Figure 3.1 Bias Dependent Charge Source 15 Figure 3.2 Bias Dependent Capacitance 15 Figure 3.3 Classical Small Signal ME SFET Model 15 Figure 3.4 Classical Large Signal MESFET Model 16 Figure 5.1 I-V Curves for a GaAs Angelov MESFET Model 22 Figure 5.2 Schematic for a GaAs Angelov MESFET Model 23 Figure 5.3 S11 & NF Graph for a GaAs Angelov MESFET Capacitance Model 24 Figure 5.4 S12 & NF Graph for a GaAs Angelov MESFET Capacitance Model 25 Figure 5.5 S21 & NF Graph for a GaAs Angelov MESFET Capacitance Model 26 Figure 5.6 S22 & NF Graph for a GaAs Angelov MESFET Capacitance Model 27 Figure 5.7 S11 & NF Graph for a GaAs Angelov MESFET Charge Model 28 Figure 5.8 S12 & NF Graph for a GaAs Angelov MESFET Charge Model 29 Figure 5.9 S21 & NF Graph for a GaAs Angelov MESFET Charge Model 30 Figure 5.10 S22 & NF Graph for a GaAs Angelov MESFET Charge Model 31 Figure 5.11 I-V Curves for a GaAs Angelov-Calvo MESFET M odel 32 Figure 5.12 Schematic for a GaAs Angelov-Calvo MESFET Model 33

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iii Figure 5.13 S11 & NF Graph for a GaAs Angelov-Calvo MESFET Cap Model 34 Figure 5.14 S12 & NF Graph for a GaAs Angel ov-Calvo MESFET Cap Model 35 Figure 5.15 S21 & NF Graph for a GaAs Angel ov-Calvo MESFET Cap Model 36 Figure 5.16 S22 & NF Graph for a GaAs Angel ov-Calvo MESFET Cap Model 37 Figure 5.17 S11 & NF Graph for a GaAs Angel ov-Calvo MESFET Charge Model 38 Figure 5.18 S12 & NF Graph for a GaAs Ange lov-Calvo MESFET Charge Model 39 Figure 5.19 S21 & NF Graph for a GaAs Ange lov-Calvo MESFET Charge Model 40 Figure 5.20 S22 & NF Graph for a GaAs Ange lov-Calvo MESFET Charge Model 41

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iv AN IMPLEMENTATION OF THE USF/ CALVO MODEL IN VERILOG-A TO ENFORCE CHARGE CONSERVATION IN APPLICABLE FET MODELS Joshua Nicodemus ABSTRACT The primary goal of this research is to put into code a unique approach to addressing problems apparent with nonlinear FET models which were exposed by Calvo in her work in 1994. Sinc e that time, the simu lation software for which her model was appropriate underwent a signific ant update, necessitating the re writing of her model code for a few applicable FET models in a Verilog-A, making it mo re compatible with the new versions of software and simulators. The problems addressed are the incons istencies between the small-signal model and the corresponding large-si gnal models due to a factor call ed transcapacitance. It has been noted by several researchers that the presen ce of a nonlinear capacitor in a circuit model mathematically implies the existence of a pa rallel transcapacitor, if the value of its capacitance is a functio n of two bias voltages, the local and a remote voltage. As a consequence, simulating small-signal excurs ions with a nonlinear model produces data which are inconsistent with the simulations using the linear model, if the latter does not include the transcapacitance, wh ich is inevitably present. The Calvo model attempted to

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v improve the performance of these models by modifying terms in the charge source equations which minimize these transcapacitanc es. Thanks to the present effort, Calvos theory is now incorporated in the Angelov Mode l and can also be impl emented in some other popular existing models su ch as Curtic, Statz and Parker Skellern models.

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1 CHAPTER 1 INTRODUCTION It has been noted by several resear chers [1-6] that the presence of a nonlinear capacitor in a circuit model mathematica lly implies the existence of a parallel capacitor or transcapacitor, if the value of its capacitance is a function of a remote voltage. This situation occu rs in common FET modeling ap plications. The extracted values of all three capacitances, gate-to-s ource, gate-to-drain a nd drain-to-source (C gs C gd and C ds ) in the simplified small-signal MESFET model are functions of two voltages, local and remote volta ge (usually taken to be V gs which is the gate-to-source voltage and V ds which is the drain-to-source voltage for the gate-to-source capacitor) and, therefore, the effects of transcapacitance must be considered. Otherwise, simulating small-signal excursions with a non-linear model may produce data that is inconsistent with the simulations of the corresponding small-signa l model (associated linear model). In the next section we will review the ma thematical and physical origins of these discrepancies. The subsequent section cri tiques the methods usually implemented to overcome these difficulties. Finally we present the solution to the problem proposed by Calvo ; it imposes no additi onal complexity on the parame ter extraction process, it renders the linear and nonlinear models c onsistent, and as seen by Calvo in her simulations, it vastly impr oves the convergence of the harmonic balanc e algorithm. This research was carried out in an attemp t to put this technique into code for an already existing Angelov transistor model in a software Verilog-A. In this document, we will show the tech niques that can be used to alter empirical nonlinear models of MESFETS (metal-semiconductor field-effect transistor) to improve their performance, which we documen t in the subsequent chapters. Broadly, models are categorized as physical models, empirical models and data based models each of which is used for different applications and has its own advantages and disadvantages [1].

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2 We deal with empirical models in this document. Most of th e traditional models referred to have similar circuit topology but differ in the analytic formulas that describe the circuit elements as functions of bias [1]. Most models work fairly well describing the performance of a device with large signals. However, implicit errors arise because of the way the nonlinear capacitors are modeled. The normal approach of modeling three nonlinear capacitances with only two elements in the nonlinear simulator forces interrelationships between the capacitances to make sure they obey charge conservation [1]. There is no certain ty that the extracted capacitances will obey charge conservation at different bias values and for various devices. This ultimately causes inconsistency between the large signal and small signal models. These discrepancies arise due to the fact that the capacitances have bivariate dependence. These capacitance values not only depend on the vol tage across their own terminals but also depend on another vo ltage in the circuit called the remote voltage. While modeling these capacitan ces, another capacitive element called transcapacitance must be included in the sm all signal model [1]. This is the primary cause for the inconsistency between the large signal model a nd its corresponding small signal model. Inserting this transcapacitance in the small signal models is difficult for various reasons which will be described in the subsequent chapter. Leaving the transcapacitance out also may cause the divergence of harmonic balance as observed by Calvo: this is not dealt in this document. Calvo formulated a mathema tical solution which reduces the effects of transcapacitance immensely and virtually sets it equal to zero at the quiescent or bias point. She used the continuous bound integr als in her charge source equations extracted from capacitance equations. We take advantage of her contribution to tweak the existing charge source e quations in applicable FET models and minimize the ill effects of transcapacitance. The simulating so ftware which was being used at the time by Calvo is not being implemented as much now, necessitating th e rewriting of the equations in this software Verilog-A. The latter is more simulator independent and portable which in turn makes the usability factor much higher.

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3 In this research chose a typical case to observe how this stratagem works and to show how effective it would be with this new technique. We recode the charge source equations in the Angelov model with certain mo difications in an attempt to make it more charge conservative and minimize the ill eff ects of transcapacitance. We ran two test cases, one with the charge model and the ot her being the capacitance model. We used Calvos stratagem to modify the charge source equations in order to make the two above mentioned models perform closer to each other than they did prior to these modifications. This technique can be applied to a lot of applicable FET models, which have their charge source equations derived from the corresponding capacitance equations. This trick can also be used to model other bivariate capacitances and bivariate inductances [1]. In the following chapter, we will show the origins of these discrepancies, followed by traditional methods which are cu rrently being implemented to avoid this situation and the complications arising from them. Then we will present our implementation of Calvos solution to this pr oblem along with some simulations to check our theory. In chapter 3 we describe the way the char ge source equations are worked out from the capacitance equations and suggest how the equations in certain popular models like Angelov, Curtice, Parker-Skellern etc. can be modified to obey charge conservation. Unfortunately, there does not seem to be any other way of getting around these restrictions by measuring the combined e ffects of the two capacitors without much complexity. As will be shown in chapter 3, modeling elements that are functions of a remote voltage causes mathematical complicat ions that make the large signal and small signal inconsistent. Therefore, we illustra te how Calvos mathematical construction removes this error at the DC quiescent bias point and minimizes the associated errors as the signal swings away, ensuri ng better charge conservation. Chapter 4 describes th e code we modified using Calv os strategy, which accounts for the transcapacitance by mathem atically finessing the charge source equations. We describe how the modified code works in the proximity of the operati ng bias voltages and ensures charge conservation. Also, we do cument charge sour ce equations from a fe w other applicable

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4 FET models and apply our stra tagem to those formulas. They now account for the ignored transcapacitance. To test that the stratagem works we desc ribe in chapter 5 how we simulate using the original Angelov code with small a nd large signals, not accounting for the transcapacitance; and we simulate using our co de with the same small and a large signals accounting for those elements. We show the out put curves of the revised model for both, capacitive and the charge models. Chapter 6 concludes the document and su ggests the scope of usage of this mathematical formulation in some other applicable FET models.

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5 CHAPTER 2 DESCRIPTION OF MIRIAM CALVOS NONLINEAR FET MODEL A Field Effect Transistor (FET) is basically a voltage-controlled resistor, as the word transistor itself was derived by putti ng together transfer resistor. So, a FET essentially is a three terminal device inside which the transfer of charge or current through any two nodes or terminals is contro lled by the potential at the third terminal. It has been noted by several researchers th at the presence in a FET of a nonlinear capacitor in a circuit model mathematically implies the existence of a transcapacitor in parallel with the primary cap acitor, if the value of the capacitance depends on a remote voltage [8].We note that a nonlinear capacitanc e whose value is C changes with bias and has to be interpreted as a small-signal linea rization of a nonlinear charge source Q, with C as the derivative of Q with respect to the terminal voltage or local voltage or applied voltage V l as seen in equation 2.1: dQ = C(V 1 ) dV 1 = (dQ / dV 1 ) dV 1 (2.1) But, if the remote voltage has an effect on C, Q automatically changes and its mathematical relationship becomes : dQ = ( Q(V 1 V r ) / V 1 ) dV 1 + ( Q(V 1 ,V r )/ V r ) dV r (2.2) Comparing both equations we understand that the value of the capacitor has to paired with a transcapacitor C T as written in equation 2.4. C = ( Q (V 1 ,V r ))/ V 1 (2.3)

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6 C T = ( Q(V 1 ,V r ))/ V r (2.4) As a consequence of this, large signal simulation of small signal excursions by various modelers yields data inconsistent with their simulations on their small signal models, if the latter do not consider the transcapacitance [8]. The Equating mixed partial condition by which equations ( 2.3) and (2.4) are interlocked to ensure charge cons ervation is shown below in (2.5): C/ V r = C T / V 1 (2.5) This means that the original capacitor should be paired with it s corresponding transcapacitance delivering charge in accordance with the equation: dQ transcap = C T dV r [6] (2.6a) The total charge then would be equa l to dQ shown in equation (2.6b): dQ = dQ cap + dQ transcap = C dV l + C T dV r (2.6b) Root and Hughes [9] acknowledge this inconsistency and insert the transcapacitance in th eir small signal models to reso lve the discrepancy. However the inclusion of a transcap acitor is undesirable for the following reasons: [1] 1. The inclusion of the transcapacitance does not guarantee the improvement in the small-signal models ability to simulate sm all signal performance of that device. 2. The inclusion of the transcapacitance auto matically increases the complexity of the small signal model topology. 3. The values of transcapacitance can only be extracted from the small signal measurements with difficult y, using optimization codes. 4. Even under the assumption that the trans capacitance can be ex tracted there is no guarantee for the transcapacitance to obey charge conservation (equality of mixed partials of Q. See equation 2.5 or the compatibility c ondition) with its corresponding capacitance due to experimental error, and numerical smoothing as described in [16] will be needed in orde r to compute the values for the charge source Q.

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7 5. (For reasons not known) previous atte mpts to incorporate transcapacitance seemed to confound the convergence of the harmonic balance simulation algorithm for large signals in nonlinear simulations [8]. 6. Closed-form schemes for extracting element values from S-parameter measurements have not been worked out with these additional circuit elements [6]. We now wish to interject several observations concerning the need, the interpretation and the importance of the transcapacitance[6]. 1. The effect of transcapacitance in ever y nonlinear two-voltage model is not optional but, it is an inevitable feature wh ether or not explicitly recognized. The math undeniably implies that the nonlinea r charge source Q which depends on the local and remote voltage is governing th e charge transfer according to equation 2.2 and not 2.1. Modelers do not have a choice as to whether or not to incorporate transcapacitance in their non linear models, as it already exists. Therefore for a linear model to be consistent with its corresponding nonlinear model which we call mother model, the former must in corporate the transcapacitance element. 2. Root and Hughes [9] have stated in th eir work that Greens theorem, when applied to the loops traversed in the ( V l V r ) plane during an alternating current operation, implies that the ne t transfer of charge acr oss the charge source per cycle need not be zero, if the mixed partia l condition (2.5) is violated in the largesignal model. They term it the violation of charge conservati on but Snider and Calvo in [6] suggest as an alternate nome nclature, invalidation of charge as state variable, as they believe that charg e conservation in the physics community means something different. 3. At any rate, we agree that a nonzero transfer of Q (any small amount of charge) Coulombs per cycle across a MESFET ga te is undesirable in a simulator, inasmuch as it is nonphysical (such behavi or would more than likely drive a real transistor into cutoff or saturation.) [6]. 4. A transparent physical model of a capaci tance which is dependent on a remote voltage was described in [10], where the remote voltage controls a motor which

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relocates a dielectric slab between the capacitor plates. The analysis reinstate the importance of the compatibility condition (2.5) for the conformity to charge as a state variable. Now we would like to consider the customary small-signal model for Fig 2.1; its large-signal version appears as Fig 2.3. Fig 2.2 is the Industry-Standard small-signal intrinsic model for the MESFET. Figure 2.1 Traditional Small Signal MESFET Model (SSM) [6] 8

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Figure 2.2 Industry-Standard Small Signal Intrinsic Model for the MESFET Figure 2.3 Classical Large Signal Intrinsic MESFET Model (Simplified) [6] We shall now describe Calvos mathematical solution for the (nonlinear) transcapacitance which renders the transcapacitance equal to zero at a selected operating 9

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10 (quiescent) point. This results in the transcap acitance being negligible for moderate signal excitations therefrom (and thus validates the omission of the transcapacitance from the small-signal model, at the operating point) [8]. For this reason, we now pick a classic example from the work of Calvo and Snider [6] to show that the numerical value of the capacitance itself can differ based on what the reference remote voltage was taken to be. We consider, for example, the gate-drain charge source in Fig. 2.3: Q gd = Q gd (V gs V ds ) (2.7) For our demonstration purpos es, the functional form Q gd (V gs ,V ds ) = V m gs / V n ds (2.8) was postulated in [6,2] Here the local voltage is: V gd = (V gs V ds ) (2.9) We defines V gs as the remote voltage here, so the s ource formula (2.8) is rewritten as Q gd (V l V r ) = V r m / (V r V l ) n (2.10) Therefore the equations of the capaci tance and transcapacitance look like: C = Q gd / V l = nV r m / (V r V l ) n+1 = nV gs m / V ds n+1 (2.11) C T = Q gd / V r = ... = mV gs m 1 / V ds n nV gs m / V ds n+1 (2.12) On the other hand if assume V ds to be the remote voltage here, the source formula (2.10) changes to the form Q gd (V l V r ) = (V l + V r ) m / V r n (2.13) and C = Q gd / V l = m(V l + V r ) m-1 / V r n = mV gs m-1 / V ds n (2.14) C T = Q gd / V r = mV gs m-1 V ds n nV gs m / V ds n+1 (2.15) As we see here clearly, the numerical value of the capacitance has changed. Transcapacitance, too, can be shown to cha nge by picking a different drain to source voltage.

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11 Therefore when considering n onlinear systems controlled by two control voltages, we should not presume that the capacitance is reality-based and th e transcapacitance as mathematical constructed; both of them are mathematical constructions [6]. So, we observe that the inte grity of charge as a state variable depends upon equation (2.5) If the charge source given is Q gd ( V l V r ), C and C T are given by equations (2.14), (2.15); but if only C is given, the compatible C T is only unique up to a function f(V r ) of V r [6]. OUR APPROACH IN RESOLVING THESE INCONSISTENCIES Rather than starting from a small-signa l model containing transcapacitance, our approach is to redesign the charge-source function Q( V l V r ), mathematically, in such a way that its associated transcapacitance is negligible. (We were motivated by the observation that, since most transistor models neglect the transcapacitance and many of them are fairly successful, the value of C T is probably small.) Essentially, we exploit the freedom allowed in the selection of the initial point for the integration of relation (2.5) as shown below [1,6]. Specifically, the procedure is to 1. Neglect C T in the element extraction process and obtain values for C (and the other circuit elements) from S-parameter measurements as usual, using the model in Fig 2.1, for a number of bias voltages, local and remote voltages. 2. Curve-fit these values with any analytic function C ( V l V r ) for an applicable FET Model 3. Compute the charge source function for the large signal model according to the formula: Q(V 1 ,V r ) = V10 V1 C( V 1 ,V r )dV 1 (2.16) where V l0 is the value of the local voltage at the terminals of the desired capacitor when the FET is biased at the quiescent (operating) point. Note that the measured values of the capacitance C ( V l V r ) are recovered exactly; (2.16) implies (2.3). The transcapacitance is derived from (2.4): C T (V 1 V r ) = V10 V1 [ C (V 1 V r ) / V r ] d V 1 (2.17)

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12 The resulting linear model is then that of Fig. 3, with the transcapacitance values calculated from (2.17) and the othe r element values unaltered from their prior determination via 1 or 2. The merits of this procedure[1,6]: 1. Since the constant of integration in the inte gral for Q has no effect on the circuit (it corresponds to charge transfe rred prior to initialization), we are free to set the lower limit in equation 2.16 arbitrarily. Many authors ta ke it to be zero. But note that with the choice V l0 we ensure that Q is very small; compare Q (V 1 V r ) = V10 V1 C( V 1 ,V r )dV 1 = O(V 1 V 10 ) = O( V 1 ) (2.18) But Q (V 1 V r ) = 0 V1 C (V 1 V r ) dV 1 = O(V 1 ) (2.19) More importantly, the resulti ng numerical value of the tran scapacitance (2.17) is also O( V l ) and very small (zero, in fact, at the quiescent point). Thus the small-signal models of Figs. 1 and 3 are nearly the same This is the justification for neglecting transcapacitance in th e initial element-extraction process [6]. 2. Since the identities (2.3, 2.4) are valid, the compatibil ity condition ( 2.5) is now met exactly Thus charge will be a genuine state va riable (charge conservation) in the linearized model of Fig. 2.3, and consequent ly very nearly so in Fig. 2.1 [6]. 3. Because the transcapacitance is sma ll, the charge transferred by it ( Q = C T V r ) is extremely small of order O( V l V r ). Apparently this mollifies the deleterious effect of transcapacitance on the harmoni c balance algorithm [1]. In short we have constructed, from our presumed linear (small-signal, transcapacitance-free) model, a nonlinear mother model which imposes negligible transcapacitance on its lineariza tion and is thus (nearly) co nsistent with the presumed linear model. To check our theory, we simulated the re sponses of Angelov model to the same stimulus first a small signal input with the original charge and capacitance models, and then replacing his charge source equations with our new equations, we repeated the same simulations.

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13 CHAPTER 3 CAPACITANCE AND CHARGE SOURCE EQUATIONS FOR A CLASSIC NONLINEAR FET MODEL To confirm this theory, Calvo and Snider in one of their earlier works simulated responses for three models to the same small signal stimulus input. The first was a linear model shown in Fig 3.3. The second model was the associated nonlinear model shown in Fig 3.4 constructed from its corresponding linear m odel using charge source equations described in the previous chapter. The th ird model was the associated nonlinear model constructed in the customary manner [4]. The values for C gs and C gd are consistent with typical graphs presented in some classic MESFET models earlier. The value of C ds is rarely discussed in the literature and is usually assumed to be constant [5]. Expressions have been published to describe C gs and C gd as functions of bias voltages by various authors. Ho wever, these formulas have pol es and/or singularities that can thwart the convergence of harmonic ba lance simulators discussed by Calvo and Snider in work which is not dealt in this document [5]. The formulas presented herein are bounded, continuous, differentiable, and integrab le, so they can readily be adapted to accommodate nonlinear transcapacitance and char ge source formulations [1, 4, 6]. Every term in these formulas described belo w is designed to control a particular behavior/pattern in the curves We would like to mention that the parameters in these equations are not the same for all the subseque nt equations; that is to say, the parameter a in the first set of equations is different from the second and so on.

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14 3.1 Capacitance Equations [5] The C gs formula for the gate-source capacitance as a function of the bias voltages is: C gs (V gs V ds ) = d + c e bVgs (1 + tanh (a V ds )) (3.1) The parameters {a,b,c,d} therein should be fitted to data using one of the standard procedures, such as least-squares. However, values can be extracted using as few as four measurements. Both the extracted and optimized formulas were plotted with th e data in Calvos work [1, 6]. The C gd formula for the ga te-drain capacitance is: C gd (Vgs, V ds ) = a + [e + bsech (dV gs )][1/ (1 + c e f Vgs V ds 2 )] (3.2) The 6 parameters in the formula can be extracted from the values of C gd measured at the six bias voltages). Curves for th ese extracted values, and subsequently optimized values, were displayed in their work in [5]. The C ds formula in the equation (3.3) is the drain-source capacitance. C ds (V gs V ds ) = f + c sech (eV gs ) + a sech (dV gs ) sech (bV ds ) (3.3) The six parameters in this formula can be obtained from the measured values at six bias points [5]. 3.2 Charge Source Equations [5] Their corresponding charge source equa tions for these capacitances are : Q gs = d [V gs V gs0 ] + ( c/d) [ 1 + tanh (a V ds )][ e bVgs e bVgs0 ] (3.4) Q gd = a [ V gs V gs0 V ds + V ds0 ] + [(e + bsech dV gs ) / ce f Vgs/2 )] ln [ ( c e Vgs/2 V ds + 1+ce fVgs V ds 2 ) / ( c e fVgs/2 (V ds0 V gs + V gs0 ) + (1+ ce fVgs (V ds0 V gs + V gs0 ) 2 (3.5) Q ds = [ f + c sech(eV gs )] [ V ds V ds0 ] + (a/b) sech( dV gs ) [arctan (sinh bV ds ) arctan (sinh b V ds0 )] (3.6) These equations are referenced with V gs as the remote voltage. The input signal here was biased at the quiescent point while computing the charge function Q. It was

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15 igure 3.2 Bias Dependent Capacitance demonstrated earlier by Calvo and Snider in [6] that the large signal models tracked the small signal models fairly accurately, in contrast to the other models which showed discrepancy. Also, when the input bias voltage swayed away even by about 33.3% the above model showed a lot more accuracy than the other models under test then. A simple figure for a Bias Dependent Charge Source and a Bias Dependent Capacitance are depicted in Figs 3.1 and 3.2 to help the reader visualize better. Figure 3.1 Bias Dependent Charge Source F Figure 3.3 Classical Small Signal MESFET Model [6]

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16 Figure 3.4 Classical Large Signal MESFET Model [6]

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17 CHAPTER 4 CODE DESCRIPTION We begin by taking a different stand on compatibility condition for charge conservation from the one used by Angelov in his GaAs FET model in [11]. We advocate using Calvos cross partial comp atibility equation as stated in equation (4.2) instead of the mixed partial condition shown in equation (4.1) considered by Angelov. We base our stand on the explanati on in chapter 2. Cgd / Vgs = Cgs / Vdg (4.1) Cgs / Vgd = CT gs / Vgs (4.2) where Cgs is be the gate-to-source capacitance, Vgd is gate-to-drain voltage, Vgs is gate-to-source. o ensure charge conservation (or, rather to avoid invalidati on of charge as a state variable) we modified Angelovs char ge source equations, as extracted from his corresponding capacitance equations. Thus we account for the transcapacitance but ensure that it is negligible in the small signa l model, and in fact would be zero at the quiescent bias point (as explaine d in the earlier chapters). Following Calvos logic, we re-set the lo wer limit of the integral in the charge source formula equal to the lo cal bias voltage of the capacitor in equations 4.9 and 4.10, when the input signal of the FET was biased at the operating point. Angelov in his work takes the lower limit to be zero. But note that, with the choice Vl0 (local bias voltage) as the lower limit of integration, we ensure that all as seen earlier in (2.18) and (2.19). We display our new charge source equati ons in (4.7) and (4.8) below, as we incorporated them into the Angelovs code The details of their calculations follow. to-source voltage and C T gs is transcapacitance from gate T Q is very sm

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18 The capacitance and charge source equations documented below are taken from Angelovs work in his GaAs FET model [11] Cgs = Cgsp + Cgs0 (1 + tanh [P10 + P (1 + tanh [P20 + P21 Vgs]) (4.3) Cgd = nh [P40 + P41 Vdg]) (4.4) Here P10, P11, P20, P21, P30, P31, P40,41 are parameters defined by Angelov. We us as set as the upper limit of integration). Qgs = [Cgs (Vgs, Vds) dVgs] = Cgsp Vgs + Cgs011gs11 11) rce and gate-to-drain are then gsp Vgs0 + Cgs0 Vgs0 + (log [cosh [P10 + P11Vgs0]]) / P11 + Vgs0 tanh [P20 + Qgd = [Cgd (Vgs, Vgd) dVgd] integrated from Vgd0 through Vgd 11 V gs ]) C gdp + C gd0 (1+ tanh [P 30 + P 31 V ds ]) (1-ta P ed values for these parameters supplied by Clausen. The indefinite integrals of the capacitances in (4.3, 4.4) are read off from Angelovs code where V gs and V gd respectively were the terminal voltages to which these capacitances have been integrated (or, w V gs + (log [cosh [P 10 + P V ]]) / P + V gs tanh [P 20 + P 21 V ds ] + (log [cosh [P 10 + P 11 V gs ]] tanh [P 20 + P 21 V ds ]) / P (4.5 Q gd = [C gd (V gs V gd ) dV gd ] = C gsp V gd + C gd0 V gd + (log [coshP 40 + P 41 V gd ]) / P 41 + V gd tanh [P 30 + P 31 V ds ] + (log [cosh[ P 40 + P 41Vgs ]] tanh [P 30 + P 31 V ds ]) / P 41 (4.6) Our new charge source equations for ga te-to-sou given by: Q gs = [C gs (V gs V ds ) dV gs ] integrated from V gs0 through V gs = C gsp V gs + C gs0 V gs + (log [cosh [P 10 + P 11 V gs ]]) / P 11 + V gs tanh [P 20 + P 21 V ds ] + (log [cosh [P 10 + P 11 V gs ]] tanh [P 20 + P 21 V ds ]) / P 11 C P 21 V ds ] + (log [cosh [P 10 + P 11 V gs0 ]] tanh [P 20 + P 21 V ds ]) / P 11 (4.7)

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19 = Cg tanh [P30 + P31Vds]) / P41 Cgsp Vgd0 + Cgd0 Vgd0 + (log [coshP40 + P41Vgd0]) / P41 + Vgd0 tanh [P30 + P31Vds] Here Vgs0 and Vgd0 are the local bias voltages (which were set as the lower limit of i nd -3.25V in agd0 was rea Vgs0 = Vgd0 + Vds0 (4.9) rmed the original Angelov model but our m parable results. This techniq charge source equations have been extr acted from their co rresponding capacitance formula with all the terminal voltage values replaced by the local bias voltage values. Thi ge conservation. Another advantage of this method is that it does not require any new parameter extracti A few examples to which this technique can be adapted are documented below E the charge sourcea / 10) equation (4.11). sp V gd + C gd0 V gd + (log [coshP 40 + P 41 V gd ]) / P 41 + V gd tanh [P 30 + P 31 V ds ] + (log [cosh[ P 40 + P 41Vgs ]] + (log [cosh[ P 40 + P 41Vgd0 ]] tanh [P 30 + P 31 V ds ]) / P 41 (4.8) ntegration) at the capacitor terminals V gs0 and V gd0 were set to -0.25V a ccordance with the equation (4.9) where V ds0 was a known value and the value of V d off from an Angelov output. The simulation results are shown in following chapter. Regretably, due to time limitations we did not find an ideal test case in which our model outperfo odel was able to produce com ue is immediately adaptable for other applicable FET models whose equations. The existing charge source formul as have to be diminished by the same s should help minimize the ill effects of ignoring transcapacitance and char on (as would be the case if transcapacitance has to be estimated in the small signal model). but were not coded. In the normal operating mode of a FT in Parker-Skellern m odel in [12] e qution from gate-to-source is (4.10): Q gs = 2C gs (1(1-V gs ) + C gd .V gd (4. Our stratagem when applied to this gate-to-source charge equation would result in

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20 2 (1-V / ) where Vgs0 is the local bias voltage at that capacitor terminal. It appears that Parker and Skeller The charge source equation for a FET biased (4.12) (Vgs/ -Fc)2/(4(1-Fc)3/2) + (Vgs/ -Fc)/ (1-Fc) (Vgs0/ Fc)2/(4(1-Fc)3/2) + e next consider a charge source equa tion (4.14) from gate-to-drain extracted from it d as shown in (4.15) so that the transcapacitance is ac [Cgd0 / (1-( Vds/ VB1)).Vgd0] (4.15) Q gsNEW = 2C gs (1(1-V gs / ) + C gd .V gd C gs (1(1-V gs / ) C gd .V gd = 2C gs (gs / + (1-V gs0 (4.11) n formed (4.10) by integrating a univariate capacitance formula, which did not require transcapacitanc e, followed by artificially introduc ing a transcapacitance equal to the gate-to-drain capacitance. The disappearance of the transcapacitance in this case will be discussed in another paper. in the Parker-Skellern model in [12] when forward is (4.12). Q gs = C gs {2 (1(1-F c ) + (V gs0 / F c ) 2 / (4(1-F c ) 3/2 ) + (V gs0 / -F c )/ (1-F c )} + C gd .V gd Our modification when applied to equation (4.12) would cha nge shape to (4.13), accounting for the ignored transcapacitance. Q gsNEW = C gs {2(1(1-F c ) + (V gs / -F c ) 2 /(4(1-F c ) 3/2 ) + (V gs / -F c )/ (1-F c )} + C gd .V gd [C gs {2(1(1-F c ) + (V gs0 / F c ) /(4(1-F 2 c ) ) + (V 3/2 gs0 / -F c )/ (1-F c )} + C gd .V gd ] = C gs { (V gs0 / -F c )/ (1-F c )} (4.13) W s corresponding charge equation in the Curtice model taken from [14,15]. Q gd = Cgd0 / (1-( V ds / V B1 )).V gd (4.14) Using our stratagem, this equation can be m odifie counted for. Q gdNEW = Cgd0 / (1-(V ds / V B1 )).V gd

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21 source and gate-to-drain used in the own below: p Vgs) / P tanh [P20 +P2 [ QgsNEW = Cgsp Vgs + Cgs0 Vgs + (ln [cosh [P10 + P11Vgs]]) / P11 ) (1 + tanh [P20 20))]] / P11] (4.18) P ) [C V + Cg V + P (ln [cosh [P + P V ]]) / P ) (1 + tanh [P31gsgd0400 40 30414 The charge source equations for gate-toChlamers MESFET Model described in [15] are sh Q gs = C gs + C gs0 V gs + (ln [cosh [P 10 + P 11 V gs ]]11 ) (1 +1 V ds ] C gs0 ln [cosh (P 10 (1+ tanh P 20 ))]] / P 11 (4.16) Q gd = C gdp V gd + C gd0 V gd + P 400 (ln [cosh [P 40 + P 11 V gd ]]) / P 41 ) (1 + tanh [P 30 + P 31 V gs ]) (C gd0 P 400 [ln [cosh (P 40 (1+ tanh P 30 ))]]) / P 41 (4.17) Where P 10 P 11, P 20 P 21 etc.. are polynomial coefficient parameters for the capacitances described in [15]. Charge source equations after modification using our stratagem are shown in (4.18) and (4.19). . +P 21 V ds ] C gs0 [ln [cosh (P 10 (+ tanh P 20 ))]] / P 11 [C gsp V gs0 + C gs0 V gs0 + (ln [cosh [P 10 + P 11 V gs0 ]]) / P 11 ) (1 + tanh [P 20 +P 21 V ds ] C gs0 [ln [cosh (P 10 (1+ tanh P Q gdNEW = C gdp V gd + C gd0 V gd + P 400 (ln [cosh [P 40 + P 11 V gd ]]) / P 41 ) (1 + tanh [P 30 + 31 V gs ]) (C gd0 P 400 [ln [cosh (P 40 (1+ tanh P 30 ))]]/ P 41 gdpgd0d0gd0400 4011gd041 30 + P V ]) (C P [ln [cosh (P (1+ tanh P ))]]) / P ] (.19)

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CHAPTER 5 SIMULATION RESULTS 22the same outputs to test her Transcapacitance theory. In section 5.1 we show the output hence the outputs did not differ but were comparable throughout. We picked our output curves shown below based on the fact that Calvo had used curves for the Angelov capacitance model. For the simulations we ran, transcapacitance was not crucial and 5.1 Angelov Model Simulations for the Capacitance Model Figure 5.1 I-V Curves for a GaAs Angelov MESFET Model

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Figure 5.2 Schematic for a GaAs Angelov MESFET Model 23

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Figure 5.3 S11 & NF Graph for a GaAs Angelov MESFET Capacitance Model 24

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igure 5.4 S12 & NF Graph for a GaAs Angelov MESFET Capacitance Model F 25

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Figure 5.5 S21 & NF Graph for a GaAs Angelov MESFET Capacitance Model 26

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igure 5.6 S22 & NF Graph for a GaAs Angelov MESFET Capacitance Model F 27

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285.2 Angelov Model Simulations for the Charge Model F igure 5.7 S11 & NF Graph for a GaAs Angelov MESFET Charge Model

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Figure 5.8 S12 & NF Graph for a GaAs Angelov MESFET Charge Model 29

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igure 5.9 S21 & NF Graph for a GaAs Angelov MESFET Charge Model F 30

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Figure 5.10 S22 & NF Graph for a GaAs Angelov MESFET Charge Model 31

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325.3 Angelov-Calvo (New) Model Simulations for the Capacitance Model F igure 5.11 I-V Curves for a GaAs Angelov-Calvo MESFET Model

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igure 5.12 Schematic for a GaAs Angelov-Calvo MESFET Model F 33

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ap Model Figure 5.13 S11 & NF Graph for a GaAs Angelov-Calvo MESFET C 34

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igure 5.14 S12 & NF Graph for a GaAs Angelov-Calvo MESFET Cap Model F 35

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Figure 5.15 S21 & NF Graph for a GaAs Angelov-Calvo MESFET Cap Model 36

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Figure 5.16 S22 & NF Graph for a GaAs Angelov-Calvo MESFET Cap Model 37

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385.4 Angelov-Calvo (New) Model Simulations for the Charge Model Figure 5.17 S11 & NF Graph for a GaAs Angelov-Calvo MESFET Charge Model

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igure 5.18 S12 & NF Graph for a GaAs Angelov-Calvo MESFET Charge Model F 39

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F igure 5.19 S21 & NF Graph for a GaAs Angelov-Calvo MESFET Charge Model 40

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F igure 5.20 S22 & NF Graph for a GaAs Angelov-Calvo MESFET Charge Model 41

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42 CHAPTER 6 RECOMMENDATIONS AND CONCLUSION We have made use of Calvos mathematical formulation applying it to Angelovs charge model to reduce the ill-effects of th e (inevitable) presence of transcapacitance when modeling a nonlinear capaci tor for a large-signal mode l essentially rendering the value of the transcapacitance equal to zero at a prescribed quiescent point. Calvo has pointed out that applying this scheme to a nonlinear bias dependent FET modeling applications has the following advantages: 1. All three capacitors can be modeled inde pendently with any desired accuracy (as opposed to other procedures where capaci tors are NOT modeled independently [1]). 2. The integrity of charge as a state variab le (charge conservation) is maintained. 3. Simulations of small-signal excursions using large signal models are rendered consistent with their corresponding small signal models (up to negligible error). 4. This technique does not require any new parameter extraction (as would be the 5. The convergence of harmonic balance simula tions at very high power levels is improved in some models [1]. To summarize, a precise method of dea ling with two-parameter bias dependent capacitors has been formulated such that the large signal model accurately tracks the small signal model performance. Furthermore, the method appears to improve the convergence range of harmonic balance simu The technique is general and is immediat ely adaptable for other applicable FET models such as Curtic, Statz and Parker Skelern models whose charge source formulas case if transcapacitance was inserted in the small signal model). lations of large signal FET models. l

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43 have been obtained by integrating thei r corresponding capacitance formulas as shown in the earlier chapters. Also, an entirely dual cons truction can be worked out for inductances to account for the transinductances as well, if the nonlinear inductance (L) depends on a local and remote current L(I1, I2). Then the flux will be conserved over cycles if L is accompanied ia equation (6.1) [2] : by a transinductance L T (I 1 I 2 ) derivable from a flux function (I 1 I 2 ) v V = / t = / I 1 dI 1 /dt + / I 2 dI 2 /dt = L dI 1 /dt + L T dI 2 /dt (6.1) This can prove to be an effective stratagem and is recommended for future work to model nonlinear inductances.

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44 Transistor Models, PhD Dissert ation, University of South Florida, May 1996. [2] A. D. Snider, Charge Conservation and the Transcapacitance Element: An ider, "Math Methods in Transistor Modeling II: Simp le, to IEEE Trans. Microwave Theory and Techniques. [4] M. V. Calvo, A. D. Snider and L. P. Dunleavy, Resolving Capacitor Discrepancies between Large and Sm ll Signal FET Models, IEEE Microwave Theory and Techniques Symposium Digest, pp. 1251-1254, June 1995. [5] M. V. Calvo, A. D. Snider (Correspondi ng Author) Math Methods in Transistor Modeling IV: New Formulas for MESFET Elements with Improved Robustness, submitted to IEEE Transactions on Microwave Theory and Techniques. [6] M. V. Calvo and A. D. Snider, "Math Met hods in Transistor Mode ling II: Simple, Accurate Enforcement of Charge Conservation and Transcapacitance," submitted to IEEE Trans. Microwave Theory and Techniques. [7] A. D. Snider, Three New Mathematical Techniques for Field Effect Transistor Modeling and Analysis. [8] M. V. Calvo and A. D. Snider, "Resolution of Linear/Nonlinear Inc onsistencies in Charge Conservative FET Models. An Abstract presented at Southeastcon [9] D. Root and B. Hughes, Principles o Nonlinear Active Device Modeling for Circuit Simulation, 32nd AR FTG Conference Dige st, December 1988. [10] M. V. Calvo, P. Winson, and A.D. Snider, Mechanistic Interpretati on of the Transcapacitance Element, IEEE Southeastcon, 1993. REFERENCES [1] M.V. Calvo,Resolving Nonlinear/Linear Inconsistencies in Char ge-Conservative Exposition, IEEE Transactions on Education, Vol. 38, No. 4, November 1995. [3] M. V. Calvo and A. D. Sn Accurate Enforcement of Charge Conservation and Transcapacitance," submitted a f

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45 [11] I. Angelov, N. Rorsman, J. Stenarson, M. Garcia and H. Zirath An Empirical Table-Based FET Model, IEEE Transa ctions on Microwave Theory and Techniques, Vol. 47, No. 12, December 1999. [12] Anthony Edward Parker, David Jame s Skellern, A Realistic Large-Signal MESFET Model for SPICE IEEE Transactions on Microwave Theory and Techniques, Vol. 47, No. 9, September 1997. W [13] W.R.Curtice, GaAs MESFET Mode ling and Nonlinear CAD, IEEE Transactions on Microwave Theory and Techniques, vol.36, no.2, Feb.1988 [14].R.Curtice, A MESFET Model for use in the Design of GaAs Integrated Circuits, IEEE Transaction on Microwave Theory and Techniques, Vol. MTT -28 pp.448-456, May 1980. [15] Jaakko Ala-Paavola, Martti Va ltonen, Antti Kallio Chlamers MESFET Model in APLAC Circuit Theory Laboratory Report Series, Espoo, February 2000. [1 6] A. D. Snider and P. Winson, Math Methods in Transistor Modeling I: A Generalized Dirichlet Principle for Smoothing Small Signal Measurements, submitted to IEEE Transactions on Mi crowave Theory and Techniques.

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46 APPENDICES

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47 Appendix A: CODE Angelovs Code of a Gallium Arsenide Field fect Transistor modified using Miriam Calvos Technique. The Modifications and changes in the code are in bold. /* Copyright 2002, 2003 Tiburon Design Automation, Inc. All rights reserved. This software has been provided pursuant to a License Agreement containing restrictions on its use. This software contains valuable trade secrets and proprietary information of Tiburon Design Automation, Inc. and is protected by law. It may not be copied or distributed in any form or medium, disclosed to third parties, reverse engineered or used in any manner not provided for in said License Agreement except with the prior written authorization from Tiburon Design Automation, Inc. Verilog-A definition of Angelov GaAsFET $RCSfile: angelov.va,v $ $Revision: 1.14 $ $Date: 2003/12/15 19:21:45 $ */ `include "disciplines.vams" `include "constants.vams" `include "compact.vams" `define SCALE_T_LINEAR_REL(x, s) x (1 + s delta_T) module angelovmiriamnew_va(d, g, s); // %%DEVICE_CLASS=FET(NFET,PFET)%% // Instance parameters parameter integer NFET = 1 from [1:1]; parameter integer PFET = 0 from [0:0]; // Only NFET supported parameter real W = -`NOT_GIVEN from (0:inf]; // Unused: gate width parameter real Ng = -`NOT_GIVEN from (0:inf]; // Unused: gate fingers parameter integer Mode = 1 from [0:1]; // Unused parameter integer Noise = 1 from [0:1]; // Unused parameter integer Noimod = 1 from [0:1]; // Unused parameter integer Selft = 0 from [0:1]; // Flag for self-heating parameter real Trise = 0.0 from [-inf:inf]; // Difference sim. temp and device temp, [C deg] parameter real Temp = `NOT_GIVEN from (-`P_CELSIUS0:inf]; //Device temp (only used if Trise is zero) [C] parameter integer Idsmod = 0 from [0:1];// Ids Current Model (0 or 1) Ef

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48 Appendix A ( Continued ) el [0:2] parameter real Vgs0 = -0.25; // operating voltage Vgs0 [V] parameter real Vgd0 = -3.25; // operating voltage Vgd0 [V] er real Ipk0 = 0.5671; // Current for max. transconductance [V] nel channel aturation parameter alpha_r parameter real Vkn = 0.8; // Knee voltage [V] arameter real Lambda = 0.02398; // Channel length modulation eter parameter real Lambda1 = 0.0; // Channel length modulation // Coeff for channel length modulation .88662; // Unsaturated coeff B1 for P1 or P1 [1/V] arameter breakdown model parameter [V] ace breakdown model parameter [V] from [0:inf]; // Zero-bias D-S junc 249.92e-15; // Gate-source pinch-off ernal G-D rameter Cgdo parameter integer Igmod = 0 from [0:1]; // Select gate diode model [0:1] parameter integer Capmod = 1 from [0:2];// Select cap mod paramet Ipk [A] ax parameter real Vpks = -0.17223; // Gate voltage Vpk for m transconductance [V] parameter real Dvpks = 0.5454; // Delta gate voltage at peak gm nnel parameter real P1 = 0.887161; // Polynomial coeff P1 for cha current [1/V] han parameter real P2 = -0.323231; // Polynomial coeff P2 for c current [1/V^2] parameter real P3 = 0.284378; // Polynomial coeff P3 for current [1/V^3] parameter real Alphar = 0.096189; // S [1/V] parameter real Alphas = 0.4742; // Saturation parameter alpha [1/V] p ram pa parameter .0; parameter real Lvg = 0 parameter parameter real B1 = 1 parameter real B2 = 0.67592; // Saturated coeff B2 f parameter real Lsb0 = 0.5; // Soft breakdown model p parameter real Vtr = 17.6; // Soft parameter real Vsb2 = 0.0; // Surf parameter real Cds = 707.752643e-15 on capacitance [F] ti parameter real Cgspi = 2 capacitance [F] parameter real Cgs0 = 3.39891e-12; // Gate-source capacitance parameter [F] parameter real Cgdpi = 180.428772e-15; // Gate-drain pinch-off capacitance [F] parameter real Cgdpe = 270.002e-15 from [0:inf]; // Ext Capacitor [F] parameter real Cgd0 = 0.0; // Gate-drain capacitance pa [F] parameter real P10 = 0.00015731; // Polynomial coeff P10 for capacitance parameter real P11 = 1.086932; // Polynomial coeff P11 for pacitance ca parameter real P20 = 1.3259488; // Polynomial coeff P20 for capacitance

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49 tance nce Ohm] stance [s] ] ond ] t hm] e [F] or Ipk Ipk Appendix A ( Continued ) parameter real P21 = 0.001938; // Polynomial coeff P21 for capacitance parameter real P30 =9.1385e-005; // Polynomial coeff P30 for tance capaci parameter real P31 = 0.0666; // Polynomial coeff P31 for capacitance rameter real P40 = 0.0001243; // Polynomial coeff P40 for pa paci ca parameter real P41 = 1.04754; // Polynomial coeff P41 for capacitance parameter real P111 = 1e-005; // Polynomial coeff P400 for capacitance parameter real Ij = 0.02 from [0:inf]; // Gate fwd saturation current [A] parameter real Pg = 15 from [0:inf]; // Gate current parameter parameter real Ne = 1.3 from [0:inf] exclude 0; // Gate p-n emission coeff parameter real Vjg = 0.9 from [0:inf] exclude 0; // Gate current parm [V] parameter real Rg = 0.35 from [0:inf]; // Gate ohmic resistance [Ohm] parameter real Rd = 0.6336 from [0:inf]; // Drain ohmic resista [Ohm] parameter real Ri = 0.25 from [0:inf]; // Input resistance [ parameter real Rs = 0.561 from [0:inf]; // Source ohmic resi [Ohm] parameter real Rgd = 0 from [0:inf]; // Gate resistance [Ohm] parameter real Ld = 0 from [0:inf]; // Unused: Drain ohmic inductance [H] parameter real Ls = 0 from [0:inf]; // Unused: Source ohmic inductance [H] parameter real Lg = 0 from [0:inf]; // Unused: Gate ohmic inductance [H] parameter real Tau = 4.2787e-12 from [0:inf]; // Device delay parameter real Rcmin = 10 from [0:inf]; // Min value of Rc [Ohm parameter real Rc = 54 from [0:inf]; // R for freq dep output c [Ohm] parameter real Crf = 10000e-12; // C for freq dep output cond [F parameter real Rcin = 100.0e3 from [0:inf]; // R for freq dep inpu cond [Ohm] parameter real Crfin = 0.0 from [0:inf]; // C for freq dep input cond[F] parameter real Rth = 15 from [0:inf]; // Thermal resistance [O parameter real Cth = 10e-6 from [0:inf]; // Thermal capacitanc parameter real Tcipk0 = -0.00181; // Linear temp coef TIpk f [A/K] parameter real Tcp1 = -0.00031; // Linear temp coef TIpk for [A/K]

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50 real Tccgd0 = 0.0; // Linear temp coef Cgd0 parm real NoiseP = 1.0 from [0:inf); // Gate noise coeff se coeff q [Hz] real Af = 1.0 from (0:inf]; // Flicker noise exponent r real Ffe = 1.0 from (0:inf]; // Flicker noise parameter [C] real Td = 25.0 from (-`P_CELSIUS0:inf]; // Equiv temp [C] eff al Klf = 1.0e14 from [-inf:inf]; // Flicker noise ter real Fgr = 60.0e3 from [-inf:inf]; // G-R freq corner [Hz] parameter real Np = 0.3 from [-inf:inf]; // flicker noise freq exp ameter real Tnom = `NOT_GIVEN from (-`P_CELSIUS0:inf); // param real alpha, alpha_s, x, x_2, x_3, x_4, x_5, y; _1, psi, L_sd1, L_sb, V_dgt; _gs; real psi_1, psi_2, psi_3, psi_4, psi_11, psi_44 ; tanh1, tanh2, tanh3, tanh4, cosh0, cosh1, lc1, 4, lc44, lc40; Appendix A ( Continued ) parameter real Tccgs0 = 0.0; // Linear temp coef Cgs0 parm parameter parameter real Tclsb0 = 0.0; // Linear temp coef Lsb0 parm parameter real Tcrc = 0.0; // Linear temp coef Rc parm parameter real Tccrf = 0.0; // Linear temp coef Crf parm parameter real NoiseR = 0.5 from [0:inf); // Gate noise coeff parameter parameter real NoiseC = 0.9 from [0:inf); // Gate-drain noi parameter real Fnc = 0.0 from [0:inf); // Noise corner fre parameter real Kf = 0.0 from [0:inf]; // Flicker noise coeff parameter paramete parameter real Tg = 25.0 from (-`P_CELSIUS0:inf]; // Equiv temp parameter parameter real Tdl = 0.1 from [-inf:inf]; // Equiv temp [C] parameter real Tmn = 1.0 from [-inf:inf]; // noise fitting co parameter re exponent parame parameter real Lw = 0.1 from [-inf:inf]; // effective gate noise width [ mm] par meas T [C] electrical d, g, s, di, gi, si, gdi, gsi, bi, rf, p_avg_i, t; real Vgs, Vgd, Vds, Vdg; real Igs, Ig d; real Vth, T_nom, T, delta_T; real V_pk, P real Ids, P_avg, pg_param, tanh_gs, tanh_gd; real Q_gd, Q real Ipk0_T, Lambda_T, Psat_T, B1_T; real Rc1, Lsb0_T, Cgs0_T, Cgd0_T, Rc_T, Crf_T; real P1m, P1_T, Vpkm; rea l T0, T1, T2; real lambda_n, lambda_n1; real lambda_p, lambda_p1; real psi _n, alpha_n, Idsp, Idsn; real tanh_psi, tanh_psi_n, tanh_alpha_vds, tanh_alpha_n_vds; real cosh11,lc11, 10, lc lc real Qgs0, Qgd0, Vgsc, Vgdc; analog begin Vgs = V(gi,si);

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51 a_T = T T_nom; if (delta_T || Rth > 0) begin P1_T = `SCALE_T_LINEAR_REL(P1, Tcp1); Lsb0_T = `SCALE_T_LINEAR_REL(Lsb0, Tclsb0); 0); LINEAR_REL(Rc, Tcrc); EAR_REL(Crf, Tccrf); // Default value pg_param = 0.5 / Ne / Vth; else ; // Take the given value Appendix A ( Continued ) Vgd = V(gi,di); Vdg = -Vgd; Vds = V(di,si); Vgsc = V(gsi,si); Vgdc = V(gdi, di); // Temperature effects if (Temp == `NOT_GIVEN) T = $temperature + Trise; else T = Temp + `P_CELSIUS0; if (Tnom == `NOT_GIVEN) T_nom = `DEFAULT_TNOM + `P_CELSIUS0; else T_nom = Tnom + `P_CELSIUS0; if (Selft) T = T + V(t); Vth = $vt(T); delt Ipk0_T = `SCALE_T_LINEAR_REL(Ipk0, Tcipk0); Cgs0_T = `SCALE_T_LINEAR_REL(Cgs0, Tccgs0); Cgd0_T = `SCALE_T_LINEAR_REL(Cgd0, Tccgd Rc_T = `SCALE_T_ Crf_T = `SCALE_T_LIN end else begin Ipk0_T = Ipk0; P1_T = P1; Lsb0_T = Lsb0; Cgs0_T = Cgs0; Cgd0_T = Cgs0; Rc_T = Rc; Crf_T = Cr f; end // If Pg is not given but Ne is given, Pg = 1/(2*Ne*Vt) if (Pg == -`NOT_GIVEN) begin if (Ne == -`NOT_GIVEN) pg_param = 15.0; else end pg_param = Pg

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52s); (1 + B1 / (T0 T0)); ks + Dvpks tanh(Alphas Vds) Vsb2 dg Vtr); T2 + P3 T1 T2; h_psi; tanh_alpha_vds = tanh(alpha Vds); ds xp(Vdg Vtr)); lse begin Vpkm; T2 = T1 T0; (T0 + P2 T1 + P3 T2); ); a_vds) xp(Vds / Vkn pk0_T tanh_psi_n (1 tanh_alpha_n_vds) _n Vds lambda_n1 limexp(Vds / Vkn p Idsn); gmod == 0) begin T0 = exp(pg_param tanh(-2 Vjg)); Vjg)); xp(-pg_param Vjg); Appendix A ( Continued ) T0 = cosh(B2 Vd P1m = P1_T Vpkm = Vpks Dvp (Vdg Vtr) (V T1 = Vgs Vpkm; T2 = T1 T1; psi = P1m (Vgs Vpkm) + P2 i = 1 + tanh(psi); tanh_ps alpha = Alphar + Alphas tan if (Idsmod == 0) begin Ids = Ipk0_T tanh_psi tanh_alpha_v (1 + Lambda Vds + Lsb0_T lime end e T0 = Vgd T1 = T0 T0; psi_n = P1m tanh_psi_n = 1 + tanh(psi_n alpha_n = Alphar + Alphas tanh_psi_n; tanh_alpha_n_vds = tanh(alpha_n Vds); lambda_n = Lambda + Lvg tanh_psi_n; lambda_p = Lambda + Lvg tanh_psi; lambda_n1 = Lambda1 + Lvg tanh_psi_n; lambda_p1 = Lambda1 + Lvg tanh_psi; Idsp = Ipk0_T tanh_psi (1 + tanh_alph (1 + lambda_p Vds + lambda_p1 lime 1)); Idsn = I (1 lambda 1)); Ids = 0.5 (Ids end // Leakage diodes if (I tanh_gs = tanh(2 (Vgsc Vjg)); tanh_gd = tanh(2 (Vgdc end else begin T0 = e tanh_gs = tanh(Vgsc Vjg); anh_gd = tanh(Vgdc Vjg); t end Igs = Ij (exp(pg_param tanh_gs) T0); Igd = Ij (exp(pg_param tanh_gd) T0);

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53s; psi_2 = P20 + P21 Vds; tanh2 = 1 + tanh(psi_2); Vds; h(psi_3) P111; gspi Vgsc; dpi Vgdc; ependent capacitance Cgs0_T tanh1 tanh2) Vgsc; + 2 P111)) Vgdc; ergence) s); c40 = ln(cosh0); cosh1 = cosh(psi_4); cosh11 = cosh(psi_44); tanh3 / P41 + 2 4 + lc44 Qgd0) tanh3 ,si) <+ Igs; Appendix A ( Continued ) // Charge model psi_1 = P10 + P11 Vgsc + P111 Vd psi_11 = P10 + P11 Vgs0 + P111 Vds; tanh1 = 1 + tanh(psi_1); psi_3 = P30 P31 tanh3 = 1 + tan psi_4 = P40 + P41 Vgdc P111 Vds; 111 Vds; psi_44 = P40 + P41 Vgd0-P tanh4 = 1 + tanh(psi_4); Rc1 = Rcmin + Rc_T / (1 + tanh1); case(Capmod) 0: begin // Linear capacitance Q _gs= C Q_gd= Cg end 1: begin // Bias d Q_gs = (Cgspi + Q_gd = (Cgdpi + Cgd0_T (tanh3 tanh4 end 2:begin // Charge-based (best conv tanh2 = tanh2 P111; cosh0 = cosh(P10 + P111 Vds); lc10 = ln(cosh0); cosh1 = cosh(psi_1); cosh11 = cosh(psi_11); lc1 = ln(cosh1); lc11 = ln(cosh11); Qgs0 = P10 + P111 Vds + lc10; Q_gs = Cgs0_T ((psi_1 + lc1 Qgs0) tanh2/P11 + 2 P111 Vgsc) + Cgspi Vgsc (Cgs0_T ((psi_11 + lc11 Qgs0) tanh2/P11 + 2 P111 Vgs0) + Cgspi Vgs0); cosh0 = cosh(P40 P111 Vd l lc4 = ln(cosh1) ; lc44 = ln(cosh11); Qgd0 = P40 P111 Vds + lc40; 0) Q_gd = Cgd0_T ((psi_4 + lc4 Qgd P111 Vgdc) + Cgdpi Vgdc (Cgd0_T ((psi_4 111 Vgd0) + Cgdpi Vgd0); / P41 + 2 P end endcase I(di,si) <+ Ids; I(gsi

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54 (g,di)); ds); ); in; V(gi,gdi) <+ I(gi,gdi) Rgd; si,s) Rs; Tau ddt(P_avg); "Rs"); "Rd"); (t)); s Vgsc; Appendix A ( Continued ) I(gdi,di) <+ Igd; I(gdi,di) <+ ddt(Q_gd); I(gsi,si) <+ ddt(Q_gs); I(g,di) <+ Cgdpe ddt(V I(di,si) <+ Cds ddt(V I(di,rf) <+ Crf_T ddt(V(di,rf) I(bi,gi) <+ Crfin ddt(V(bi,gi)); V(rf,si) <+ I(rf,si) Rc1; V(bi,si) <+ I(bi,si) Rc V(gi,gsi) <+ I(gi,gsi) Ri; V(si,s) <+ I( V(di,d) <+ I(di,d) Rd; V(g,gi) <+ I(g,gi) Rg; vg_i) <+ Vds Ids V(p_a // Add noise I(di,si) <+ flicker_noise(Kf pow(Ids, Af), 1.0, "flicker"); V(si, s) <+ white_noise(4.0 `P_K T (Rs) V(di,d) <+ white_noise(4.0 `P_K T (Rd), if (Selft) begin I(t) <+ Cth ddt(V I(t) <+ -Ids Vds + I g I(t) <+ V(t) / Rth; end end endmodule