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Tetali, Bhaskar Reddy.
Stability studies of CdTe/CdS thin film solar cells
h [electronic resource] /
by Bhaskar Reddy Tetali.
[Tampa, Fla.] :
b University of South Florida,
Thesis (Ph.D.)--University of South Florida, 2005.
Includes bibliographical references.
Text (Electronic thesis) in PDF format.
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Document formatted into pages; contains 155 pages.
ABSTRACT: CdTe/CdS solar cells have shown great potential for terrestrial solar power applications. To be commercially viable they need to operate efficiently for about 30 years. CdS/CdTe solar cells fabricated at USF have shown record efficiencies upto 16.5% . This research involves the study of thermal stress (TS) and light soaking (LS) on the stability of high efficiency (> 10%) solar cells. The change in key electrical parameters Voc, FF, Jsc, A and Jo are quantified for more than 2000 hours of stressing. The device degradation was found to increase with stress temperature for TS. Below 100oC, the changes were due to collection and recombination losses. Above 100oC, shunting mechanisms were found to start affecting the device performance. A fast drop in performance within the first 500 hours was observed. It is believed to be due to an increase in deep-level Cu-related defects that increase with stress temperature.Diffusion of Cui+ ions from the back contact along CdTe grain boundaries had been previously reported . An increase in light/dark J-V crossover and bulk Rs with stress time and temperature was observed. A slow degradation component attributed to Cu-related substitutional defect  formation/diffusion to the junction and CdS is proposed. This should compensate the CdS over time and increase its photoconductivity/resistivity. An improvement in the current collection and FF within 100 hours of LS was observed. This is possibly due to the enhancement of Cui+ diffusion into the junction and CdS during LS as previously reported . A reduction in light/dark J-V crossover was observed, possibly due to an increase in CdS doping and reduction in the CdS/SnO2 front contact barrier. However, a fast decrease in Voc and increase in recombination current was also observed in the first 1000 hours of LS.
Adviser: Christos Ferekides.
x Electrical Engineering
t USF Electronic Theses and Dissertations.
Stability Studies Of CdTe/CdS Thin Film Solar Cells by Bhaskar Reddy Tetali A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Christos Ferekides, Ph.D. Don Morel, Ph.D. Yun-Leei Chiou, Ph.D. A.N.V. Rao, Ph.D. Richard Gilbert, Ph.D. Date of Approval: March 25, 2005 Keywords: II-VI devices, illumination, therma l, lightsoak, stress, degradation, solar Copyright 2005, Bhaskar Reddy Tetali
DEDICATION This dissertation is dedicated to my parents and brother for their immense love and support in all my endeavors and to my dear wife for the help and motivation towards the end.
ACKNOWLEDGEMENTS I am greatly indebted to my major professor, Dr. Chris Ferekides. His invaluable support and guidance during the course of this researc h and during some tough personal times is very much appreciated. I would also like to express my gratitude to Dr. Don Morel for his advice and support during my involvement in the compound semiconductor lab. I would like to thank my committee members Dr. Y.L. Chiou, Dr. Richard Gilbert and Dr. A.N.V. Rao for agreeing to be a part of the committee in evaluating my research. I would like to acknowledge Dr. Sally Ashe rs (of NREL) invaluable assistance with SIMS analysis, Bob, Jerry & Bryan at the works hop and Mike at the glass shop for their expertise and help in the construction of annealing, light soaking and various other chambers. I thank my colleagues Vijay, Valery, Harish, Krishna, Priya, Sujatha, Namrata, Pushkar, Ramesh, Robert, Zhao at the compound semiconduc tor lab for making my stay at USF such a pleasurable experience. I wish to thank my roo mmates at various times Arun, Suresh, Krishna, Ramamurthy, Lolla and Antara for their help. Finally, I wish to thank Balaji for all the help and assistance. This research was supported by Nationa l Renewable Energy Laboratory of the Department of Energy (NREL/DOE).
iTABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES v ABSTRACT x CHAPTER 1 INTRODUCTION CHAPTER 2 SEMICONDUCTOR THEORY AND DEVICE PHYSICS 2.1 Carrier Action 2.1.1 Drift 2.1.2 Diffusion 2.1.3 Recombination-Generation (R-G) 2.2 p-n Junctions 2.2.1 p-n Junction Under Forward Bias (FB) 2.2.2 p-n Junction Under Reverse Bias (RB) 2.3 Solar Cells 2.3.1 Introduction 2.3.2 Operation 2.4 Heterojunction Solar Cells 2.4.1 Interface States 2.4.2 Collection Function 2.4.3 The Effect of Temperature and Illumination on Cell Efficiency CHAPTER 3 REVIEW OF CdTe/CdS THIN FILM SOLAR CELLS 3.1 Front Contact 3.2 CdS Layer 3.3 CdS/TCO Interface 3.4 CdS/CdTe Interface 3.5 CdTe Layer 3.6 Back Contact 3.7 Factors Affecting Stability 3.8 Spatial Variation of Device Pa rameters in Polycrystalline CdTe/CdS Solar Cells 3.9 Defects in CdTe/CdS Solar Cells 3.10 Current Literature on Stress Te sting of CdTe/CdS Solar Cells 1 4 8 8 9 10 12 13 14 15 15 16 21 24 25 27 30 30 31 32 35 37 40 41 42 44 49
iiCHAPTER 4 EXPERIMENTAL 4.1 Device Structure & Fabrication 4.2 Thermal Stress (TS) 4.3 Illumination Stress or Light Soaking (LS) 4.4 Characterization Techniques 4.4.1 J-V Measurements 4.4.2 C-V Measurements 4.4.3 Spectral Response Measurements 4.5 Device Analysis of USF Cells 4.5.1 I-V Analysis 22.214.171.124 Temperature I-V Analysis 126.96.36.199 Light & Dark J-V Analysis 4.5.2 Spectral Response Analysis CHAPTER 5 RESULTS AND DISCUSSION 5.1 Thermal Stress 5.1.1 Effect on Open-Circuit Voltage (Voc) 5.1.2 Effect on Fill Factor (FF) 5.1.3 Effect on Short-Circuit Current Density (Jsc) 5.1.4 Effect on Shunt Resistance (Rsh) 5.1.5 Effect on Series Resistance (Rs) 5.1.6 Diode Quality Factor, A & Reverse Saturation Current Density, Jo 5.1.7 Dark J-V Analysis 5.1.8 Light J-V Analysis 5.1.9 Capacitance-Voltage Measurements (C-V) 5.2 Illumination Stress 5.2.1 Effect on Open-Circuit Voltage (Voc) 5.2.2 Effect on Fill Factor (FF) 5.2.3 Effect on Short-Circuit Current Density (Jsc) 5.2.4 Effect on Shunt Resistance (Rsh) 5.2.5 Effect on Series Resistance (Rs) 5.2.6 Diode Quality Factor, A & Reverse Saturation Current Density, Jo 5.2.7 Dark J-V Analysis 5.2.8 Light J-V Analysis 5.2.9 Capacitance-Voltage Measurements (C-V) 5.3 SIMS Analysis of Thermal Stress Devices 5.4 Effect of Re-contacting Thermal Stress Samples 5.5 Comparison of Thermal Stress & Light Soak Results 5.6 Acceleration Factor for Thermal Stress 5.7 Simulation 5.8 Summary CHAPTER 6 CONCLUSIONS REFERENCES ABOUT THE AUTHOR 64 64 67 68 69 70 70 70 70 71 71 71 73 74 74 75 76 77 80 83 84 85 88 89 93 93 98 103 106 108 109 110 113 114 117 123 125 130 131 131 135 137 End Page
iiiLIST OF TABLES Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Deep Levels Found in the Polycrystalline CdS/CdTe Thin-Film Solar Cells  Change in Voc at 500 Hour Intervals Change in FF at 500 Hour Intervals Rsh @ Jsc Variation over Time FF Variation over Time Rsh @ Jsc and Rsh @ -2V after Thermal Stress at Various Temperatures Rsh @ High Current for Thermal Stress at Various Temperatures A and Jo for Thermal Stress at Various Temperatures Change in Voc at Room Temperature and 70oC Change in Voc for Various Stress Periods Change in FF @ 25oC and 70oC for LS Devices Change in FF @ 25oC over Various Stress Periods Change in Jsc for Control and Lightsoak Samples Change in Rs for Control and Lightsoak Samples Change in A and Jo for Control and Lightsoak Samples NA and Depletion Width of Witness and Lightsoak Samples Effect of Re-contacting on Device Parameters Device Parameter Comparison 46 76 77 80 81 83 84 85 95 95 102 102 105 108 109 117 123 125
ivTable 19 Table 20 Acceleration Factor for Degradation of Voc and FF Comparison of Voc and FF Before and After Degradation 130 131
vLIST OF FIGURES Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Figure 16 Figure 17 Figure 18 DOS, Fermi Distribution, Carrier Density and Energy Band Diagram of an Intrinsic Semiconductor  DOS, Fermi Distribution, Carrier Density and Energy Band Diagram of n-type Semiconductor  DOS, Fermi Distribution, Carrier Density and Energy Band Diagram of p-type Semiconductor  p-n Junction in Equilibrium  p-n Junction Under FB  p-n Junction Under RB  Standard AM1.5 Spectrum  I-V Curves for a p-n Junction Diode in the Dark and Under Illumination Diode Quality Factor, A vs Voltage  Inverted Maximum Power Rectangle Equivalent Circuit of a Solar Cell with Series and Shunt Resistances, Rs & Rsh Energy Band Diagram of Two Heterojunction Forming Materials Energy Band Diagram of Heterojunction at Equilibrium The Bias Dependence of Collection Function, H(V)  Bias Dependent SR of a CdS/CdTe Heterojunction  Quasi Fermi Levels Under Illumination  Superstrate Structure General Band Diagram for the Proposed Model  6 6 7 12 13 14 15 17 18 19 20 21 22 25 27 28 30 34
viFigure 19 Figure 20 Figure 21 Figure 22 Figure 23 Figure 24 Figure 25 Figure 26 Figure 27 Figure 28 Figure 29 Figure 30 Figure 31 Figure 32 Figure 33 Figure 34 Figure 35 Figure 36 Figure 37 Figure 38 Light Induced Barrier Modulation  Illustration of Band Bowing Due to Sulfur (%) Incorporation in CdTe  Typical Absorption Coefficient for CdTe and CIGS Solar Cells  Simultaneously Collected AFM Topography and CP-AFM Current Mapping Images of the Standard CdTe/CdS Cell Schematic Illustration of Electron Energy (vertical) vs Spatial (horizontal) Coordinate of CdTe Grains in the Solar Cell  Comparison of Cu SIMS Profiles in CdTe with Different Degree of Crystallinity  CdS/CdTe Structure  Summary of Deep Levels Observed in the Polycrystalline CdS/CdTe Thin-Film Solar Cells  Outdoor Performance of CdTe Submodule  Performance History of Two CdTe Submodules  Relative Change in Efficiency for Devices with Different Contacts After Stressing at Bias Shown in Light for 10 Days at 100oC FF and Voc for Devices with 0 or 6nm Cu After Stress @ FB in the Dark at 60oC for 10 Days Analysis of Dark J-V Curve as DV/DJ PL Spectra of CdS Layers from Non-Contacted, Contacted and Stressed CdTe/CdS Cells  Front-wall LBIC Images of Cu/H gTe/Graphite Contacted Cells Recorded Following: a) 0, b) 18, and c) 35 Hours  Te 3d 5/2 Region of XPS Spectra of the CdTe Surface, from Beneath the Back Contacts of Cells  Schematic Representation of Mechanisms Explaining the Behavior of CdTe/CdS Cells  Conventional CdTe/CdS Solar Cell (Superstrate Structure) CSS Deposition Chamber  Thermal Stressing Chamber 35 37 38 39 40 42 45 47 48 48 50 51 51 54 56 57 60 64 65 67
viiFigure 39 Figure 40 Figure 41 Figure 42 Figure 43 Figure 44 Figure 45 Figure 46 Figure 47 Figure 48 Figure 49 Figure 50 Figure 51 Figure 52 Figure 53 Figure 54 Figure 55 Figure 56 Figure 57 Figure 58 Figure 59 Figure 60 Figure 61 Illumination Stressing Chamber Temperature Dependence of Jo  Rollover Observed in I-V Curves Crossover of Dark & Light I-V in USF Cells  Normalized Voc vs Time at Various Stress Temperatures Normalized FF vs Time at Various Stress Temperatures Normalized Jsc vs Time at Various Stress Temperatures SR of a Witness Sample stored at Room Temperature in a Desiccator SR of Device Stressed @ 70oC Before and After 3600 Hours Stressing SR of Device Stressed @ 120oC Before and After 3600 Hours Stressing FF vs Rsh @ Jsc of Devices Stressed to 3600 Hours and Simulations J-V Curves of TS Devices to 3600 Hours at Various Temperatures Ln(J)-V and Linear J-V in the Dark for a Witness Device Stored @ Room Temperature Ln(J)-V and Linear J-V in the Dark for TS Device at 70oC Ln(J)-V and Linear J-V in the Dark for TS Device at 120oC Light J-V for a Witness Device Stored at Room Temperature Light J-V of a TS Device at 70oC & 120oC NA-V in the Dark for a Witness Device NA-V in the Dark for a TS Device at 70oC NA-V in the Dark for a TS Device at 100oC Normalized Voc @ Room Temperature vs Time Normalized Voc @ 70oC vs Time Voc @ Room Temperature and 70oC vs Time During LS @ Voc 68 71 72 72 75 76 78 78 79 80 81 82 85 87 88 88 89 90 91 92 94 94 96
viiiFigure 62 Figure 63 Figure 64 Figure 65 Figure 66 Figure 67 Figure 68 Figure 69 Figure 70 Figure 71 Figure 72 Figure 73 Figure 74 Figure 75 Figure 76 Figure 77 Figure 78 Figure 79 Figure 80 Figure 81 Figure 82 Figure 83 Figure 84 Figure 85 Voc @ Room Temperature and 70oC vs Time During LS @ Voc, Vm and Voc Normalized FF @ Room Temperature vs Time Normalized FF @ 70oC vs Time During LS @ Voc Normalized FF @ 70oC vs Time During LS @ Voc, Vm and Voc Normalized Rsh @ Jsc at 70oC vs Time During LS @ Voc, Vm and Voc Normalized Jsc @ 25oC vs Time for LS Samples SR Comparison of Witness and LS Samples Normalized Jsc of LS Samples at 70oC Normalized Rsh @ Jsc of LS Samples at 25oC Normalized Rsh @ Jsc at 70oC of LS Samples at Voc Normalized Rsh @ Jsc at 70oC of LS Samples at Voc, Vm and Voc Ln(J)-V and Linear J-V in the Dark for Witness Device Stored @ Room Temperature Ln(J)-V and Linear J-V in Dark of LS Device at Voc Ln(J)-V and Linear J-V in the Dark for LS Device at Voc, Vm and Voc Light J-V of a Witness Device Stored at Room Temperature Light J-V of a LS Device @ Voc NA-V in the Dark for a Witness Device NA-V in the Dark for a LS Device @ Voc SIMS Analysis of Non-contacted Substrates Thermally Stressed to 1500 Hours SIMS Comparison of Cl Content Before and After Thermal Stress SIMS Comparison of Cu Content Before and After Contacting SIMS Comparison of Cu Content Before and After Thermal Stress SIMS Analysis of Non-contacted Sample SIMS Analysis of a Contacted Sample 97 98 99 99 101 103 104 105 106 107 107 110 111 112 113 113 115 116 118 119 120 121 122 122
ixFigure 86 Figure 87 Figure 88 Figure 89 Figure 90 Figure 91 Figure 92 Ln(J)-V and Linear J-V in the Dark for Re-contacted Device Light J-V for Re-contacted Device J-V Comparison of LS and TS Device at 70oC J-V Comparison of TS Device Under Band Pass Filters FF Variation of TS Device Under Various Band Pass Filters J-V Comparison of LS Device Under Band Pass Filters FF Variation of LS Device Under Various Band Pass Filters 124 124 127 128 128 129 129
xSTABILITY STUDIES OF CdTe/CdS THIN FILM SOLAR CELLS Bhaskar Reddy Tetali ABSTRACT CdTe/CdS solar cells have shown great potentia l for terrestrial solar power applications. To be commercially viable they need to operate efficiently for about 30 years. CdS/CdTe solar cells fabricated at USF have shown record effi ciencies upto 16.5% . This research involves the study of thermal stress (TS) and light soaking (LS) on the stability of high efficiency (>10%) solar cells. The change in key electrical parameters Voc, FF, Jsc, A and Jo are quantified for more than 2000 hours of stressing. The device degradation was found to increas e with stress temperature for TS. Below 100oC, the changes were due to collection and recombination losses. Above 100oC, shunting mechanisms were found to start affecting the de vice performance. A fast drop in performance within the first 500 hours was observed. It is belie ved to be due to an increase in deep-level Curelated defects that increase with stress temperature. Diffusion of Cui + ions from the back contact along CdTe grain boundaries had been previously reported . An increase in light/dark J-V crossover and bulk Rs with stress time and temperature was observed. A slow degradation component attributed to Cu-related substitutional defect  formation/diffusion to the junction and CdS is proposed. This should compen sate the CdS over time and increase its photoconductivity/resistivity.
xiAn improvement in the current collection and FF within 100 hours of LS was observed. This is possibly due to the enhancement of Cui + diffusion into the junction and CdS during LS as previously reported . A reduction in light/dar k J-V crossover was observed, possibly due to an increase in CdS doping a nd reduction in the CdS/SnO2 front contact barrier. However, a fast decrease in Voc and increase in recombination current w as also observed in the first 1000 hours of LS. This is possibly due to the existence of highe r concentration of Cu-related deep level defects at the junction. A larger decrease in Voc was found for LS than TS at the same operating temperature. A continuous drop in performance over time is observed for both TS and LS. The existence of a slow degradation component invo lving the formation/diffusion of Curelated substitutional defects at the junction and CdS is pr oposed. The concentration of this defect is probably not high enough in CdS for LS samples to affect their photoconductivity and cause light/dark J-V crossover in 2000 hours.
1CHAPTER 1 INTRODUCTION In a continuing quest to find alternate ener gy sources to fossil fuels, mankind has tapped into various other natural sources like solar-thermal, ocean-thermal, wind, nuclear, biomass, solar-photovoltaic etc. A photovoltaic phenomenon is the conversion of light energy to electricity, exhibited by some semiconductor materials. Devices exhib iting this property are called solar cells. The commercial viability of solar cells depend on the following: (1) cell efficiency, (2) manufacturing cost, and (3) operating lifetime. To be economically competitive with conventional fossil fuels for terrestrial applications, solar arrays with conversion efficiencies in excess of 15% are required . Semiconductors with bandgaps of around 1.5eV are optimum in terms of solar cell efficiency. This led to the study of materials with bandgaps between 1.1-2.0eV like Si, InP, GaAs, CdSe, CdTe, CIS, CIGS etc. for solar cell applications. Various device structures are used as solar cells, the most common being a p-n homojunction. Heterojunction devices, metalsemiconductor junctions (schottky diodes), metal-in sulator semiconductor (MIS) structure etc. are other structures in use. Single crystalline silic on has a low absorption coefficient requiring a relatively large thickness to absorb light. High pur ity silicon is necessary for high efficiency cells but sophisticated processing technology has made the production costs too high. Direct gap thin
2film semiconductors have high absorption coeffici ents. This means that a thin layer of a few microns ( m) of these films is sufficient to absorb the same amount of light, as it would take about a hundred microns ( m) of silicon. Thus, only a fraction of these materials is necessary compared to Si solar cells. Materials like amor phous Si, CdTe, CIS, CdSe etc. are direct gap semiconductors. Various low cost processing tec hniques such as close-spaced sublimation (CSS), evaporation, sputtering etc. are used to deposit these thin films in the polycrystalline form. They can also be deposited on various substrates (polymers, steel, glass, metal foils etc.) that are low cost and flexible leading to innovative new appli cations such as folding solar cell panels on satellites, solar cell blinds in homes etc. The lo w cost processing techniques and low material costs have made thin film technology lucrative. St udy of these thin film materials is necessary to continue photovoltaic t echnology development. Cadmium Telluride (CdTe) is one of the prom ising thin film materials identified for solar cell fabrication because of its high absorption coe fficient and its near ideal bandgap of 1.45 eV, giving it high theoretical photovoltaic conversion efficiency. Cadmium Sulfide (CdS), with a wide bandgap of 2.42eV, has been found to be the most successful heterojunction partner as a ntype window layer material to date. The fabrication of CdTe solar cells invol ves low-cost processing techniques. CdS/CdTe thin film solar cells with world record effici encies > 15% have been obtained on high purity borosilicate glass (7059) substrates with solutio n grown CdS and CSS-deposited CdTe films [1,46] and large area module efficiencies > 10% ha ve been demonstrated . For the financial viability, it is necessary that thin film solar cells are stable and have a field lifetime of > 30 years. Outdoor testing of CdS/CdTe solar cell m odules had shown great promise . Thus, commercialization of CdS/CdTe thin film solar ce lls has shifted focus of the research community from efficiency to efficiency/stability. It is im portant to study the degradation rates of these devices so that we can predict and extent their lifetimes. Accelerated testing procedures must be
3developed, as well as understanding mechanisms/process es that lead to degradation is essential to achieve this goal. The focus of this thesis is to contribute to these key aspects of CdS/CdTe technology i.e accelerated testing and degradation mechanisms. A solar cell depends on sunlight for its opera tion. During this process there are two major factors influencing its operation. The primary fact or is illumination. The secondary factor is the ambient temperature of the device. The device is expected to operate at temperatures over the ambient temperature due to heat dissipation. In th is study the effects of the above two factors on device behavior and degradation are studied. Th e thesis is based on two key experiments (1) Temperature Stress (no light) (2) Light Soaking.
4CHAPTER 2 SEMICONDUCTOR THEORY AND DEVICE PHYSICS Semiconductors are materials with electronic pr operties in between metals and insulators. They can be elemental (Si, Ge), compound (e x: II-VI, III-V compounds i.e. CdS, CdTe, GaAs, InP etc.) or compounds (ex: AlxGa1-xAs, Hg1-x CdxTe etc.). Semiconductor materials can be classified based on their structure and purity. Materials are classified based on degree of atomic order as: a) Amorphous (no recognizable order), b) Polycrystalline, and c) Crystalline (entire material is made up of atoms in an orderly array). They can also be classified on purity as: a) Intrinsic (pure material i.e no foreign atoms), b) Extrinsic (impurity or dopant atoms present). The extrinsic property of semiconductors is wh at makes them remark able. It allows the modulation of electronic properties of these materials altering their conductivity useful for a wide range of applications. One key difference of semi conductors is that both electrons and holes act as current carrying species, unlike metals where onl y electrons exist for current transport. The dominant or majority carrier in the material de termines whether a semiconductor is p-type (holes) or n-type (electrons). Doping is the addition of impurity atoms to a semiconductor material to manipulate its electronic properties or current carriers. Silicon (Si) is a group IV element and in its intrinsic form
5has four electrons contributing to its intrinsic carrier concentration (ni cm-3). Adding a group V element like Phosphorus (P donor impurity) will cause an increase in electrons making the material n-type. A group III element like Boron (B acceptor impurity) will cause a reduction in electrons i.e. increase in hole concentration of the material making it p-type. Thus, the conductivity of a semiconductor material can be c ontrolled by the amount of dopant used. This remarkable discovery was inst rumental in starting the Digital Revolution. Semiconductor materials and their compounds and alloys spur ned the growth of electronic industry with applications like sensors, diodes, transistors to name a few. The density of states (DOS), g(E) in a semiconductor shows how many states exist at a given energy E. gc(E) and gv(E) define the number of available states in conduction and valence band. A fermi function, f(E) specifies the probability that an available state at energy E is filled with an electron under equilibrium conditions. f(E) = 1/[1+ e(E-E F )/kT ] where EF = Fermi energy or Fermi level, k = Boltzmann constant (k = 8.62 x 10-5 eV/K), T = temperature in Kelvin (K). The DOS, Fermi function and energy band diagram for an intrinsic semiconductor in equilibrium can be shown in figure 1. Ec is the conduction band, Ei is the intrinsic Fermi level and Ev is the valence band. The fermi level is presen t at the center of the bandgap with an equal number of electrons and holes being present.
6 Figure 1. DOS, Fermi Distribution, Carrier Dens ity and Energy Band Diagram of an Intrinsic Semiconductor  Figure 2. DOS, Fermi Distribution, Carrier Density and Energy Band Diagram of n-type Semiconductor 
7For a n-type semiconductor the fermi level is close to the conduction band with the number of electrons higher than holes as shown in figure 2. Figure 3. DOS, Fermi Distribution, Carrier Density and Energy Band Diagram of p-type Semiconductor  For a p-type semiconductor the fermi level is close to the valence band with the number of holes higher than electrons as shown in figure 3. For a nondegenerate semiconductor i.e. Ev + 3kT < EF < Ec 3kT, the carrier concentrations of electrons and holes are given by the expression, kT E E CC Fe N n/ kT E E VF Ve N p/ where Nc and Nv are effective density of states in the conduction and valence band. Highly doped semiconductors with EF less than 3kT from the valence or conduction band are called degenerate semiconductors. The above expressions for carrier concentrati ons in nondegenerate semiconductors can be modified as kT E E ii Fe n n/
8 kT E E iF ie n p/ where ni is the intrinsic carrier concentration and Ei is the intrinsic energy level. Two other intrinsic carrier based expressions are kT E V C iGe N N n2 / 2 / 1 showing its relationship to temperature, where EG is the bandgap of the semiconductor and 2 in np For doped semiconductors with ND-NA~ ND >> ni or NA ND ~ NA >> ni the expressions for carrier concentration simplifies to n~ ND, D iN n n /2 and n~ NA, A iN n p/2 It should be noted that all semiconductors at sufficiently high temperatures would become intrinsic as ni >> (ND NA). 2.1 Carrier Action There are three types of carrier action o ccurring in semiconductors: (a) drift, (b) diffusion, and (c) recombination-generation. Th e carrier action will be discussed for electrons. The discussion can be extended to holes by analogy. 2.1.1 Drift Drift is defined as the motion of a charged particle in response to an electric field. When an electric field, E is applied to a semiconduc tor the force on the ca rriers acceler ates the positively charged holes (+q) in the direction of the electric field and negatively charged electrons (-q) in the direction opposite to the electric fi eld. The carrier in motion collides with ionized
9impurities and thermally agitated lattice atoms causing scattering on a microscopic scale. However, a resultant motion occurs for each carrier type on a macroscopic level and is defined in terms of a constant drift velocity, vd. It is defined by the expression, vd = nE where n is the mobility of electrons. The electron current density, JN/drift is defined as JN|drift = qnnE The mobility of carriers can be influenced by three factors: (1) Thermally agitated lattice atom scattering or ionized impurity scattering can reduce carrier mobility, (2) Increased doping concentration monotonically can decrease mobility, and (3) Higher temperature can decrease the mobility for lower doped semiconductors but the sensitivity to temperature drops for higher doping levels. Resistivity is a defined as the inherent resistance of a material to current flow. It is shown as, E = J where E is the electric field in the material, J is the total current density and is the resistivity. In a nondegenerately doped n-type mate rial, resistivity is shown as, = 1/qnND 2.1.2 Diffusion Diffusion is a process where particles tend to redistribute from regions of high concentration to regions of low particle con centration due to their random thermal motion to obtain equilibrium by uniform distribution of particles in the system. Note that the diffusing species moves due to thermal motion and not due to interparticle repulsion and so do not have to be charged. The electron diffusion current density, JN|diff = qDN n
10where DN is the electron diffusion coefficient and n is the concentration gradient for electrons. For similar concentration gradient of holes, the di ffusion of holes occurs in the same direction but the current flow is opposite to the flow of elect rons. As a result of electron or hole diffusion, a nonzero electric field exists inside a nonuniformly doped semiconductor under equilibrium conditions. However, the total carrier currents should be zero due to equilibrium conditions. Thus, JN|drift+ JN|diff = 0 This can be simplified to, DN/n = kT/q called the Einsteins relationship for electron states. Similar relationship can be ge nerated for holes. Einsteins relationship is deduced for equilibrium conditions but it can be extended to nonequilibrium conditions. It is not valid for degenerate semiconductors. 2.1.3 Recombination-Generation (R-G) Generation occurs when charge carriers (electrons and holes) are created and recombination occurs when they are annihilated or destroyed. When light or heat energy greater than the bandgap of the semiconductor is absorbed it excites an electron from the valence band into the conduction band generating an electron-hol e pair called direct generation. The opposite effect of carrier annihilation is called direct recombination. This is however not the dominant mechanism in semiconductors. A second mechan ism called indirect generation-recombination due to thermal excitation is the dominant process in semiconductors at all times. This occurs by the assistance of R-G centers present at energy levels between the va lence and conduction bands. Thus carrier generation is a two-step process of an electron exciting or trapped into an R-G center from the valence band before being excited into the conduction band. The opposite process
11occurs for indirect recombination. R-G centers are physical impurity atoms or lattice defects present in the semiconductor material which form d eep defects states close to mid-gap. It is desirable to keep R-G centers or traps to a minimum in functional devices. R-G processes are never-ending but to attain equilibrium the ther mal recombination and generation rates balance each other. Photo-generation process causes an equal number of electrons and holes to be created. The carriers generated are a function of distance the light has penetrated into the material and the wavelength of light. Low-level injection in a semiconductor o ccurs when a perturbation like thermal excitation causes no significant change to the ma jority carrier concentration but increases the minority carrier concentration by many orders of magnitude. The change of minority carrier concentration (ex: electrons in p-type material) due to thermal R-G process is defined as n/ t|thermalR-G = n/ n where n is the electron lifetime. This can be extended to holes in p-type materials. The minority carrier lifetime can be defined as the average ti me an excess minority carrier will live in a sea of majority carriers . The average distance the minor ity carrier (ex: electron in a p-type material) can travel before recombination is defined as its diffusion length given by LN = (DN n)1/2 With the three main processes for carrier acti on introduced, it is relatively simple to put together each of these individual components to fo rm the full set of continuity equations for carrier action in semiconductor materials. Further study of these continuity equations and the application of boundary conditions to indivi dual cases of perturbation can be found in any semiconductor textbook .
122.2 p-n Junctions When two oppositely doped semi conductors are brought in contact with each other, a p-n junction is formed. The p-type material has high c oncentration of holes and n-type material has a high concentration of electrons. When they are brought together, the diffusion of electrons from n to p-type material and holes from p to n-type ma terial takes place. Thus diffusion current flows through the junction. But diffusing holes leave behind ionized acceptors and electrons leave behind ionized donors. The ionized acceptors and do nors at the junction develop an electric field opposite to the diffusion current. The field initiates a drift current opposite to the diffusion current of each type of carriers. This continues until a equilibrium develops between the diffusion and drift current. The electric field exists in the re gion of uncompensated carri ers called the depletion region or space charge region at the junction. Figure 4. p-n Junction in Equilibrium 
13Figure 4 shows p-n junction formed between a lowly doped p-type Si and a highly doped n-type Si. xp and xn are the depletion widths in the p and n side. The space charge region extends predominantly into p-type material due to its low doping to maintain charge neutrality. The direction of the electric field in the space charge region is from uncompensated donors in the nregion to uncompensated acceptors in the p-region. This results in a potential difference to exist between the two sides shown by built-in potential (Vbi). It can be calculated by the expression, Vbi = kT/q ln[NDNA/ ni 2] The band bending ensures the fermi level stay s constant throughout the material as expected from a p-n junction in equilibrium. 2.2.1 p-n Junction Under Forward Bias (FB) Figure 5. p-n Junction Under FB  When a p-n junction is forward biased (figure 5), the biasing potential causes majority carriers to flow towards the junction. This resu lts in some donors and acceptors at the junction being compensated causing a reduction in deplet ion width. The built-in potential and band bending are also reduced causing an increase in mi nority carrier diffusion w.r.t the carriers in the
14opposite direction. The non-equilibri um condition of bias causes the fermi-level to split into quasi fermi levels. The difference between fermi levels in n and p-type is equal to the applied voltage, V. Thus, forward bias results in an increase in majority carrier transport across the junction, which increases the dc current in the diode. 2.2.2 p-n Junction Under Reverse Bias (RB) Figure 6. p-n Junction Under RB  When a p-n junction is reverse biased (figure 6), the biasing potential causes majority carriers to be pulled away from the junction. This results in more ionized dopants to be uncompensated in the space charge region. Th is increases the space charge region causing an increase in built-in potential and band bending at th e junction. The majority carrier flow across the junction is minimal as shown and the difference in quasi-fermi levels is equal to the applied bias. The current present in the diode is the reve rse saturation current of a reverse biased diode and is independent of applied bias.
152.3 Solar Cells 2.3.1 Introduction The intensity of solar radiation in free space at the average distance of the earth from the sun is defined as the solar constant with a value of 1353W/m2. This is known as the AM0 condition which represents the solar spectrum outsi de earths atmosphere and is relevant for satellite and space-vehicle applications. Sunlight at its peak on the earth surface is represented by AM1 condition. AM1.5 condition (sun at 45o above the horizon), as shown in figure 7, is an energy weighted average for terrestri al applications, typically 1000W/m2. Spectral irradiance is the power per unit area per unit wavelength. Figure 7. Standard AM1.5 Solar Spectrum  When light is incident on a semiconductor, part of it is reflected and the rest is transmitted or absorbed. Light transmitted by a semiconductor follows the equation, It = Io et
16where Io is the intensity of light incident on the semiconductor, is the absorption coefficient of the semiconductor, t is the depth of the semiconduc tor material from the su rface of incidence and It is light in the semiconductor at a depth, t, fro m the surface. The energy of incident light in terms of wavelength in the light spectrum can be obtained by the relationship, m h c 24 1 where is the frequency in hertz, h is the photon energy in eV. If the energy of photons is less than the bandgap of the material, the light p asses through the material. The photons are absorbed by the semiconductor if the energy is equal to or greater than the bandgap of the material. Energy, Eg is sufficient in the creation of electron-hole pair and all the excess energy in the photon is dissipated as heat. The photon generated carriers ar e responsible for a rise in the photocurrent at the junction terminals. 2.3.2 Operation One of the key applications of p-n junction di odes is solar cells. The photovoltaic effect is utilized for the operation of a solar cell. Under illumination, photo-generated minority carriers with sufficient lifetime travel towards the juncti on and get swept across the junction with its builtin field. These minority carriers reach the othe r side of the junction becoming the majority carriers. These excess majority carriers accumulate at the external contacts creating a voltage to build across the junction. This photo-generated volta ge can be utilized to drive loads in various applications. A solar cell operation is evaluated by its electrical performance characteristics described below. Current-Voltage curves in the dark and light are shown in the figure 8. The total current of an ideal solar cell is given by,
17I = Io LI eAkT qV 1 where IL is the light generated current or photocurrent. Short circuit current, Isc, is defined as the current flowing in the circuit with no voltage a pplied to the cell. The product of voltage and current in the fourth quadrant is negative signifyi ng that this is the output power delivered by the solar cell. Figure 8. I-V Curves for a p-n Junction Diode in the Dark and Under Illumination Several parameters are involved in the char acterization of a solar cell. The open-circuit voltage, Voc, is the voltage output at the device terminals w ith infinite load attached to it. This is physically equivalent to leaving the terminals of the device open or unconnected and measuring the voltage across it. Voc is given by, Voc = Ao 1 ln *o scI I q kT where Io is the reverse saturation current or dark current at the junction and Ao is the diode quality factor showing the perfectness of the junction. Voc attains its highest value for a perfect -0.05 -0.03 -0.01 0.01 0.03 0.05 -0.500.51 Voltage, (V)Current, (A) DARK LIGHT VocIscPmImVmIo
18junction at Ao = 1 and it decreases as Ao increases. This is because Ao & Io are interdependent  and Io increases with increasing Ao, which results in lower Voc. Io should be as low as possible as can be seen in the expression. The bandgap of the material and temperature affect the dark current. Io can be decreased by increasing the bandgap or decreasing the temperature of the material thus increasing Voc . This can be observed in the expression for Jo (Io/area of device) given below . Jo = e bi iV V WkT n) ( 2 where W is the width of depletion region, k is bo ltzmann constant, T is absolute temperature, and e is the electron lifetime. Typical values of Jo are 1.13e-11 1.6e-12 . Jo is influenced by two mechanisms: a) Recombination currents in the j unction due to traps and deep level defects b) shunting leakage currents at the grain boundaries (GB) due to GB defects. The diode quality factor, Ao, in the current equation, has also been found to be voltage dependent due to change in recombination center density. Ao vs Voltage for a theoretical homojunction is given in the figure 9. Figure 9. Diode Quality Factor, Ao vs Voltage 
19 The short circuit current, Isc, is determined by the spectral response of the cell. A good spectral response over the entire visible spectrum signifies the generation of high currents. An ideal spectral response is a step function that equals zero for wavelengths > Eg and unity for wavelengths < Eg . The material properties namely bandgap, absorption coefficient etc. directly influence the spectral response of a solar cell. It can be improved by increasing the diffusion length and reducing the surface recombination losses of charge carriers in the material. In the figure 10 below, Isc & Voc are short-circuit current and open-circuit voltage of the cell and Im & Vm are the current and voltage corresponding to the maximum power point. The maximum power point shows the maximum power that can be generated by a device. This power is the product, Im*Vm. The fill factor, FF, is another importa nt parameter of interest given by, FF = sc oc mI V VmI Figure 10. Inverted Maximum Power Rectangle IscImVmVocMax. Power Point
20The photovoltaic conversion efficiency ( ) of a solar cell is a measure of light energy successfully converted to electrical energy. = in oc sc in mP V I FF P P** where Pm is the area of the maximum power rectangle, Pin is the incident power input to the solar cell. Figure 11 below represents an equivalent circuit for a solar cell with series resistance, Rs and shunt resistance, Rsh acting on the device. For an ideal solar cell, Rs 0 and Rsh The series resistance depends on the ohmic losses in the front surface and the shunt resistance depends on the leakage currents. Figure 11. Equivalent Circuit of a Solar Cell with Series and Shunt Resistances, Rs & Rsh Defects like pinholes in the solar cell are respons ible for decrease in shunt resistance. FF & Voc are the parameters directly affected by low Rsh. Low shunt resistance leads to current losses in the form of leakage current. Thus, Isc is also affected by Rsh. Series resistance is generally affected by contacts and resistance in the bulk of the device material. FF & Isc decreases for high Rs in a device. Thus, the practical total current of a device is modified to
21 l sh s AkT IR V qI R IR V e Io Is 1) ( with the series and shunt resistance losses being applied to the ideal equation. 2.4 Heterojunction Solar Cells The advantage of using a heterojunction (H J) with a large band gap window material and a small band gap absorber material is to minimize the surface recombination losses that might otherwise dominate direct bandgap materi als, enhance short wavelength response, and lower bulk series resistance (usi ng thin-film materials). A win dow layer is a semiconductor material which is transparent to incident light with low absorption coe fficient. An absorber layer is a semiconductor material with high ab sorption coefficient and capability to form a heterojunction with the window layer. The energy band diagram of an abrupt HJ and an HJ in equilibrium is shown in figure 12. Figure 12. Energy Band Diagram of Two Heterojunction Forming Materials 1m1 Eg12m2EcEg2EvVacuum Ec1Ec2Ef1Ev1Ef2Ev2 Electron Energy
22 Figure 13. Energy Band Diagram of Heterojunction at Equilibrium The two materials have different bandgaps, Eg1 & Eg2, different electron affinities, 1 & 2, different work functions, m1 & m2 and different permittivities 1 & 2. The energy required to remove an electron from the bottom of the conduction band, Ec is called electron affinity, while the energy needed to remove an electron from the fermi level, Ef is called work function, m. 1m1 Eg12m2EcEg2EvVacuum Ec1Ec2Ef1Ev1Ef2Ev2 Electron Energy
23The basic model as a result of bringing two semiconductors together and lining up the fermi levels is shown in the figure 13. This model called the Andersons model assumes that no interface states are present and that current tran sport is via injection into the quasi-neutral region(QNR) or by recombination/generation in th e depletion layer. The relation between various quantities is given by: Ec = ( 12)q Ev = ( 21)q+Eg2-Eg1 qVd = qVd1+qVd2 = Eg1-n-p+ Ec The presence of discontinuities in the c onduction band and valence band and possible interface dipole layers complicate the theory of HJs. The spike impedes the flow of minority carriers across the junction from the p-type to th e n-type regions and the photocurrent will be reduced. The distribution of interface states may be electrically charged which further distorts the junction profile. Thus, the theory of HJs is not yet as firmly based as that for homojunctions. The Anderson band profile is modified to include the effects of electrically charged interface states and dipoles. These changes, plus the introduction of various tunneling mechanisms bring the theory of HJs to follow experimental observations. The carrier transport properties of HJs ar e dominated by phenomena in the interface region. The current transport in the depletion region is attributed to recombination, tunneling or to combination of both involving energy levels n ear the interface. The diffusion current has an exponential dependence on qV/kT. Th e reverse saturation current Jo ni 2 meaning this mechanism is predominant in sma ll bandgap materials with high ni like silicon. Jo for recombination current is linearly dependent on ni given by Jo = qniW/ e under the assumption that recombination occurs throughout the space charge region. The temperature dependence of Jo is given by
24Jo = J(T) e-Eg/2kT Tunneling current is given by Jt = BNt exp((Vbi+V)) where Nt is the density of interface states, B & are constant with temperature, Vbi does not havea a significant temperature dependence. T hus, tunneling current h as weak temperature dependence. 2.4.1 Interface States The effect of lattice mismatch between the two components of the HJ and impurities or defects introduced during fabrication result in extr insic imperfection energy levels in the vicinity of the interface. These interface states may or may not be electrically active. The lattice mismatch in HJs produces a periodic array of dangling bonds or edge dislocations. Such dangling bonds may be elect rically active themselves or act as sites for impurity segregation. Interfaces can be efficient recombination centers because they introduce deep trap levels in the bandgap. They can also provide sites for quantum mechanical tunneling processes, which is important for current loss m echanisms across the junction. The interface traps degrade the performance of a solar cell and it b ecomes essential to produce HJs with low density of interface traps. Electrically active interface states provide two mechanisms on HJs: a) Qss, charge stored in the states distorts the band profile, raising or lowering the conduction band at the interface w.r.t. its equilibrium fermi level, b) The states provide a large density of recombination centers needed to explain the high Jo values observed. The effective interfacial recombination velocity S1 quantifies the recombination behavior of the interface states. Both, Qss and S1 vary with illumination and bias conditions.
252.4.2 Collection Function In practical solar cells with lattice mism atch at the heterojunction, the quantum efficiency, Q is decreased by forward bias, resulti ng in reduced fill factor and open circuit voltage. The analysis of these junctions is difficult due to lack of concrete information about the properties of the material in the depletion layer. The effect of bias and wavelength perturbation on the Q.E. expression is captured by a factor called collection function H( ,V) that multiplies the ideal cell current JL, given by J = Jo[exp(qV/AkT)-1] H( ,V) JLo where JLo is the H=1 value of the light current. JLo can be sometimes calculated by measurement at large reverse bias. The effect of H<1 is show n in figure 14, where the value of light generated current is reduced w.r.t. that generated in the ab sorber, especially in the forward bias. As a result Voc is reduced slightly and there is a consider able reduction in fill factor. The reduction in Jsc is quite small in efficient cells. Figure 14. The Bias Dependence of Collection Function, H(V) 
26 Collection function analysis of CdS/ CdTe ce lls was carried out by Mitchell et. al. (1977)  where major light absorption o ccurs in the CdTe layer of depletion region. No appreciable absorption takes place in the CdS window layer, and Jo and A are almost independent of light intensity. The collection function H is a product of two factors: 1) g( ,V), representing absorption and recombination in the bulk, and 2) h(V) showing the bias dependence of interfacial recombination loss. The collection of photo-generated carriers fro m the thick quasi-neutral region (QNR) is given by: g1( ,V) = exp[( ) Wd(V)]/[1+1/ ( )Ln] for xp
27 Figure 15. Bias Dependent SR of a CdS/CdTe Heterojunction  The SR in figure 15 showed that h(V) was constant with wavelength. The shape of the SR curve was wavelength dependent and voltage independent which means g = g( ) and g g(V). Thus, the change in H( ,V) was observed to be from bias dependent interface recombination losses. Forward bias may influence th e lifetime in the absorber QNR and alter the J-V characteristics. 2.4.3 The Effect of Illumination and Temperature on Cell Efficiency The effect of illumination on the quasi-fermi le vels of electrons and holes was illustrated by Fahrenbruch and Bube as shown in figure 16.
28 Figure 16. Quasi Fermi Levels Under Illumination  A forward biased heterojunction with a p-type absorber layer is shown. The depletion widths xp and xn are the depletion regions on the p and n side from the junction interface xi. Efp represents the equilibrium Fermi level on the p-side and Efn is the equilibrium Fermi level on the n-side. Both should be at the same level at e quilibrium but the offset shown indicates that the device is forward biased and is equal to the applied bias. Efno in the p-type material is the equilibrium fermi level of minority carrier electr ons on the p-side. During illumination, energy is absorbed by the p-type absorber material and generates an equal number of electron-hole pairs. The majority carrier hole concentration is not significantly altered so the Efp remains unchanged. However, there is a significant increase in the minority carrier electrons which changes the electron Fermi level represented by the quasi-fermi level, Efno on the p-side. Illumination level and/or wavelength ha ve been found to vary the diode Jo and A of some heterojunctions, MIS cells and CuxS/CdS cells. This occurs when trapping centers at or near the
29junction are not in good thermal communication w ith the conduction or valence bands and can have their occupancy and hence charge changed by illumination. Optical absorption by states at the interface, in the bulk material near the junction could cause the change in Jo and A. This change in CuxS/CdS structure is due to the change in ionized donor or acceptor density on illumination. The temperature dependence of the solar effici ency can be interpreted in terms of the individual temperature dependence of Jsc, Voc and FF. The primary dependence of Jsc on temperature is through the minority carrier diffusion length: L = ( kT /q)1/2. A cell with high initial QE is not substantially affected by changes in L with temperature. The changes in minority carrier lifetime with temperature depends on the relative location of the energy levels of the recombination centers and the quasi-Fermi levels along with the dependence of the recombination cross sections of the centers themselves. The Voc and FF decrease with temperature primarily due to changes in ni. Jo increases exponentially with temperature causing Voc to drop almost linearly with increasing T. Jo = BT3(D/ )1/2exp[-Eg/kT] Voc = (Eg/q) (kT/q)ln[D/ )1/2T3B/Jsc] where B is a temperature independent constant, D is the debye length and is the minority carrier lifetime. FF decreases quite strongly with temper ature. Contacts may become non-ohmic at low temperatures causing large losses in FF.
30CHAPTER 3 REVIEW OF CdTe/CdS THIN FILM SOLAR CELLS This chapter reviews the properties of all the materials in a CdS/CdTe heterojunction solar cell which are relevant to device performance and stability. The superstrate device structure (figure 17) used in this research consists of a front contact layer (SnO2), n-type layer (CdS), ptype layer (CdTe) and a back contact laye r (graphite paste doped with HgTe:Cu) on 7059 borosilicate glass substrate. Silver Paint HgTe:Cu doped Graphite Paste CdTe CdS SnO2SnO2:F Glass Substrate InIn Light Source Figure 17. Superstrate Structure 3.1 Front Contact The properties expected of a front contact material are high transmission, high conductivity, efficient transport of carriers collected from the p-n junction to the device terminals (i.e. no surface recombination losses) and chemical stability to subsequent processing conditions.
31They are called transparent conducting oxides (TCO) and as the name suggests are typically made from highly doped oxides like fluorine doped Tin Oxide (SnO2:F), Tin doped Indium Oxide (ITO), Fluorine doped Indium Oxide (INO), Cadmiu m Stannate (CTO). Routine high efficiency CdS/CdTe solar cells have been most successfully fabricated using SnO2 as TCO . Device with record efficiency of 16.5% was achieved using a CTO/ZTO layer . A bilayer of low resistance SnO2:F deposited on glass followed by high resistance SnO2 is used in the current research. A typical film thickness of 0.7-1m and sheet resistance of 8-10 was used. Typical doping concentrations of 1019-1020 /cm3 are obtained making it a degenerate. SnO2:F has been found to be chemically non-reactive at its inte rface to CdS and no interdiffusion was observed . 3.2 CdS Layer The main function of a window layer in a superstrate structure is to be a good heterojunction partner to the p-type absorber layer with minimal lattice mismatch to minimize defects like interface states and dangling bonds at the metallurgical interface, and be transparent to incident light. Both these roles have been su ccessfully played by cadmium sulfide resulting in fabrication of high efficiency thin-film CdTe/C dS solar cells. In spite of the 9.7% lattice mismatch between hexagonal CdS and cubic CdTe, high efficiency devices are made with this junction probably due to interdiffusion at the CdS/CdTe interface. The CdSxTe1-x layer formed during this interdiffusion will be discussed in S ection 3.4. The CdS layer thickness has to be optimized to make it as thin as possible to sustai n the heterojunction. This is required to minimize the photocurrent losses due to absorption in CdS. Such interdiffusion is enhanced by the postdeposition CdCl2 heat treatment . It is thought to enhance CdTe grain growth, help grain recrystallization and improve p-doping (by creating a shallow acceptor complex, VCd ClTe).
32Cadmium Sulfide (CdS) gets its n-type c onductivity due to the presence of sulfur vacancies (native defects formed during processing) which act as ionized donors. Typical donor concentrations of 1016-1017 /cm3 are obtained. The doping concentration of this layer can be altered by acceptor type impurity and defect compensation. Intrinsically Cdi ++ acts as a donor like defect and Si -will exist as an acceptor like defect. The speci es of interest in this study are Cu, Cl and their defect complexes. Cu can exist in many forms in CdS. As an in terstitial, Cu can exist as a neutral atom or as an ionized donor Cui +. Copper is also known to occupy cadmium vacancies VCd, acting as an ionized acceptor like defect. Similarly Cl can exist as a neutral atom or a more stable Cli as an acceptor. Cl also substitutes sulfur vacancies forming donor like defects. Several acceptor like defect complexes have also been identified to exist such as [CuCd Cl+ Te], [V2Cd 2ClTe +], [CuCd Cui +] etc. The increase in acceptor like def ects in CdS will result in compensation effects that increase the CdS resistivity. This work as well as other research groups  have shown large accumulation of Cu and Cl at the junc tion interface and in CdS. This is possibly due to higher GB and lattice defects at the metallurgi cal interface and the fact that CdS grains are much smaller compared to CdTe resulting in a larger grain boundary area. Thus ionic dopant species like Cu and Cl and their complexes accumu late at these interfaces and GBs due to GB diffusion. CdS film resistivities of 106 -cm as deposited and 102-103 -cm after CdCl2 anneal were observed . 3.3 CdS/TCO Interface The front region of the CdS/CdTe solar cell has been studied extensively by Dan Oman  on USF samples. A light sensitive series resist ance component was observed in the CdS layer. Using a 450nm band pass filter (prima rily absorbed in CdS layer), samples were exposed to blue light varying in intensity from dark to 1 Sun. This showed Rs variation from 1.85 in the dark to 1.45 at 1 Sun intensity. This behavior could not be repeated using a red light of 600nm or for
33very thin CdS layers with >30% transmission at 450nm. Thus some excess CdS bulk beyond the metallurgical junction is essential for the light sens itivity to occur, meaning all CdS should not be utilized in the formation of the CdSxTe1-x layer. Exposure to 10 times lower intensity of blue light than red light, had shown smaller J-V crossover for blue light due to its absorption in CdS. This shows the photoconductive nature of CdS and its sensitivity to blue light. A device was forward biased to 0.885V (the turn-on portion of light J-V) and exposed to equal intensities (1/10000th of 1 Sun) of various wavelengths of light. The hi ghest increase in light generated current was observed at wavelengths <500nm which represents light absorbed in the CdS layer. Based on these observations the dark vs light J-V crossove r was modeled to be a front contact leaky diode opposite to the main junction of CdTe/CdS . A contact barrier of 0.2eV is expected between the fermi level in CdS and SnO2 due to electron affinity mismatch. In the dark when the main junction Rsh is 106-109 the front contact diode Rsh is approximated at 103 Under illumination, when the main junction Rsh decreases to 103 the front contact diode Rsh possibly drops to ohms or tenths of or less. At this point the current will bypass this diode going through a light activated shunt path . The front region of CdS/CdTe solar cells has also been modeled by Agostinelli G. et. al. . The model proposes the presence of a modul ated barrier photodiode (MBP) in series with the main junction at the front as a consequence of compensation of CdS, which induces crossover of light/dark J-V and in worst cases rollover. It also proposes the presence of a buried homojunction (type converted CdTe intermixing layer).
34 Figure 18. General Band Diagram for the Proposed Model  The CdS layer (compensated by accep tors) in between the n-type CdTe1-x Sx layer and ntype ITO maybe intrinsic or maybe slightly ptype. In these conditions, the CdS layer is fully depleted and is sandwiched between degenerate ITO (N+) and n-doped CdTe1-x Sx layer. This creates a hump in the band diagram (figure 18) acting as a potential barrier for electrons and potential minimum for holes. Accumulation of Cu in CdS from contacts can result in the compensation of CdS by its acceptor type defect s. Under illumination, photogenerated holes in CdS will move towards this minimum. They can then recombine with electrons trapped by acceptor defects causing an electronic doping effect in CdS (figure 19).
35 Figure 19. Light Induced Barrier Modulation: Accumulation of Photogenerated Holes Neutralizes Some of the Ionized Negative Charge in the La yer and Leads to Lowering of the Bulk Barrier  Both the above models explain observati ons in CdS/CdTe devices and are actually interrelated. The presence of an entire layer of type-converted CdTe intermixed layer has been disproved for typical USF devices by Visoly-Fisher et. al. . Conversion of CdS to p-type has been excluded by AES, which showed Te/S ratio in the CdS layer of <0.6. A ratio of 0.8 is required to type convert CdS. 3.4 CdS/CdTe Interface The CdS/CdTe interface is one of the critical device regions in CdTe solar cells. Te-rich and Cd-rich ternary compounds of CdTe and CdS ha ve been reported by various groups at this interface . The intermixing of CdS and Cd Te is believed to be enhanced by CdCl2 heat
36treatment [21, 47]. This intermixing was found to correlate with high efficiency CdS/CdTe devices. High CdTe deposition temperatures are favorable towards formation of high quality junctions . The intermixed layer is believed to improve device performance by: a) Reducing the lattice mismatch between CdTe and CdS b) Reducing the interface defect density and d ecrease in leakage current caused by tunneling and interface recombination. However, the intermixed layer could also have the following detrimental properties that can decrease the device performance . a) Reduction in window layer transmission reducing maximum Jsc b) Doping level changes causing junction and SCR width variation possibly reducing Voc c) Composition and bandgap changes cause shift in junction location and affect the built-in voltage d) Rapid GB diffusion (ex: S in CdTe) may cause increased shunting due to reduced bandgap or formation of metallic-like alloy causing performance degradation This shows that the CdS/CdTe interface and its pr operties are not clearly understood at this time and its influence on device stability still unknown. The intermixing layer CdTe1-xSx alloy with x<0.25 is know n to have smaller bandgap than CdTe as shown in figure 20 . The width, structure and composition of this layer is found to depend strongly on the pos t-deposition treatment paramete rs and the individual layer deposition process.
37 Figure 20. Illustration of Band Bowing Due to Sulfur (%) Incorporation in CdTe  Study of USF devices has also shown that high resistivity (HR) SnO2 in the bilayer SnO2 used is electronically similar to CdS and he lps support the junction photo-voltage or band bending . This means the thin CdS layer is fu lly depleted with space charge region extending into HR SnO2 layer. It was also shown that the photovoltaic and metallurgical junctions coincide. 3.5 CdTe Layer The primary purpose of an absorber layer is to efficiently collect the light energy incident on it and convert it to electricity. CdTe was found to be an ideal junction partner for CdS with an electron affinity mismatch of only 0.3eV. The eff ect of this lattice mismatch is alleviated by the formation of an intermixing layer of CdS and CdTe enhanced in the presence of CdCl2. CdTe can exist both as n-type and p-type material. The presence of VCd as native defects is what makes it ptype. It has a high absorption coefficient of 104 to 105 cm-1 which means only 1-2 m thick CdTe is enough to absorb all the incident light above its bandgap of 1.44eV. CdTe is therefore one of the leading materials for solar cell applicati ons with a very high theoretical photovoltaic conversion efficiency . Typical absorption co efficients for CdTe is shown in figure 21.
38 Figure 21. Typical Absorption Coefficient for CdTe and CIGS Solar Cells  The penetration depths of photons for diffe rent wavelengths (inverse of absorption coefficient) varies from ~0.1 m for blue light of 450nm, ~0.2 m for 600-700nm, ~0.47 m for 788nm, ~1.4 m for 820nm to 34.6 m for 855nm . Typical dopant concentrations are ~1014 to 1015 cm-3 for polycrystalline CdTe which is limited by the number of VCd present in intrinsic CdTe . The limiting factor for extrinsic p-ty pe doping of CdTe is not having a dopant with both high solubility and shallow acceptor level  Some of the defects have shallow acceptor levels but their defect formation energies are t oo high (eg. CdTe:N, CdTe :P). Other dopants have low formation energies but their acceptor level is too deep (eg. CdTe:Cu) . This being two orders of magnitude less than its heterojunction partner CdS, the junction is one-sided with the depletion region extending ~ 2 to 3 microns into the CdTe layer. This is advantageous for carrier collection since most of the light is absorbed very close to the space charge region of the junction. Structurally CdTe is known to form columnar gr ains of > 1um in size . Unlike single crystal material, a polycrystalline thin film of CdTe will have grain boundary (GB) effects also contributing to the device performance. GBs have been known to act as traps and recombination centers for minority carriers, potential barriers for the majority carrier transport or as shunt paths
39causing substantial reduction in device performance [2 3]. The interaction of GBs with free charge carriers, native point defects such as vacancies and interstitials, free charge carriers in the bulk etc. are to be considered. The conduction properties of the material are significantly altered when permanent trapping of charge carriers at GB form a potential barrier that hinders the flow of free carriers through the grain boundary. GB defects may act as gettering sites for undesirable impurities in the bulk thus improving the bulk electronic properties. This has been confirmed by studies of Visoly-Fisher et. al. on USF samples . It was shown that there is a barrier for hole transport across GBs causing GBs to be depleted. Figure 22. Simultaneously Collected AFM Topography and CP-AFM Current Mapping Images of the Standard CdTe/CdS Cell It was also observed that inversion of GBs after CdCl2 treatment occurs possibly due to the presence of ClTe donor like surface defects. This should reduce the current collection of the device. However polycrystalline CdTe/CdS solar ce lls have been found to perform better than their single crystal counterparts with higher current collection. Simultaneous atomic force microscopy (AFM) and conductive probe AFM (C P-AFM) measurements have shown (figure 22) surprising result of higher currents at the GBs than bulk CdTe crystals . The current transport in polycrystalline CdTe solar cells have been modeled as shown in figure 23.
40 Figure 23. Schematic Illustration of Electron Energy (vertical) vs Spatial (horizontal) Coordinate of CdTe Grains in the Solar Cell  The CdS is in front of the plane of the pape r. Blue/red circles show holes/electrons, and blue/red arrows show their direction of movement. Ec and Ev stand for the conduction band bottom and the valence band top. The scheme illust rates proposed electronic energy variations near CdTe GBs, resulting in th e separation of photo generated el ectron-hole pairs near GBs and funneling of electrons into and their channeling along GB core  It is proposed that the electrons are drawn to the depleted GB core and flow along GBs to the junction while holes are transported through the grain bulk towards the back contact. The charge separation along with reduced recombination in grain bulk (reduced defects in bulk) and in GBs causes reduction in net recombination and improved collection of photogenerated carriers. 3.6 Back Contact The formation of a stable, low resistance contact to p-type CdTe is a major challenge due to high work function of CdTe and the inabilit y to obtain low resistivity (high level doping) CdTe. The work function of CdTe is ~5.9eV. Th e work function of commonly used metals range from 4.2-5.6eV. Thus no metal exists that can make a barrier free or at least quasi-ohmic contact to CdTe. Most metal contacts to CdTe are rectifying.
41Doping polycrystalline CdTe at the contacting interface is probl ematic due to the existing potential barrier. The barrier height is contro lled by impurity/dangling bond states and carrier density in the bulk adjacent to the barriers. Co mpensation of the dopant by oppositely charged grain boundary states also exists. The effective ca rrier density and effective mobility are reduced due to the presence of grain boundaries. This barrier height has to be minimized to reduce the surface recombination velocity and improve device efficiency. The most common and successful approach to obtain ohmic or pseudo-ohmic contacts to CdTe has been to modify the CdTe surface to make it Te rich or Cd deficient (P+). This promotes tunneling carrier transport between the semic onductor and metal. Graphite paste doped with HgTe:Cu is used in this research and has been pr eviously used to obtain world record efficiencies . Formation of p-type Cu2Te and Hg1-xCdxTe interlayers help tunneling of holes across the contact. Details of other contacting proc edures and contacts can be found in . 3.7 Factors Affecting Stability It has been well known that routine fabrication of high efficiency CdTe/CdS devices has been only possible with the help of Cu doped back contacts. Some groups have demonstrated Cu free back contacts with high effi ciencies recently [21,24], however their long term stability has not yet been established. Preliminary stability stud ies have shown back c ontact degradation under thermal stressing . Research to-date have propos ed that Cu, Cl and their defect complexes are the key factors of degradation . The most su spected cause of cell instability is the diffusion of Cu from the back contact into the junction and the CdS region. Cu is known to be a fast diffuser in CdTe. Grain Boundary (GB) diffusion is the most likely mechanism of transport of Cu into the cell junction. Because Cu+ and Cd2+ ions are similar in size, Cu+ was thought to substitute readily for Cd2+ in CdTe. However lattice defects are slow diffusers compared to defects at GB. Cu doping of the entire CdTe layer should be obser ved and indeed Cu has been detected at the
42CdS/CdTe interface. Cu was proposed to form re combination centers and shunt pathways limiting the lifetime of the cell. It has already been established that GB diffusion is the main mode of Cu diffusion into the CdTe, CdS layers and CdTe/CdS inte rface  as shown in figure 24. Figure 24. Comparison of Cu SIMS Profiles in Cd Te with Different Degree of Crystallinity  Within polycrystalline CdTe films smaller grain sizes have shown several orders of magnitude higher Cu concentrations throug hout the whole film. The same GB diffusion mechanism is believed to be the mechanism of Cl movement into the CdTe layer and the junction interface during CdCl2 treatment. 3.8 Spatial Variation of Device Paramet ers in Polycrystalline CdTe/CdS Solar Cells Uniformity of solar cell parameters was previously studied and reported  on high efficiency USF samples. Scanning for Voc, Jsc, FF, Rsh with a helium-neon laser of spot size diameter 1mm at regions 1mm apart on the ce ll showed localized good and bad regions.
43Localized micro defects like pi nholes, GB defects are responsible for the bad regions which also affect the overall performance of the device. This was confirmed by work of Rangaswamy A . A high efficiency CdTe/CdS device (Voc > 800mV, FF > 60%) was found to degrade severely after 1000 hours of light stress (Voc ~ 270mV, FF ~ 29%). Upon breaking up the device into two halves, the first half showed Voc ~ 810mV, FF ~ 64% and the second half showed Voc ~ 160mV, FF ~ 28%. This shows the necessity of opt imizing the fabrication process and starting materials/device layers to prevent such defect form ation. This goal is more complicated due to the fact that low cost processing techniques are requi red to make polycrystalline solar cells cost effective which inherently are more defect prone. Device structure has to be optimized to prevent such localized defect formation even duri ng device operation to enhance device stability. Further investigation into spatial parame tric variation with spot sizes up to 1 m was reported by Hiltner J.F . Large number of lo cal electrical defects were found in CdTe cells causing a reduction in current collection. The most common cause of local reductions in current collection was due to local variations in series r esistivity of the material. These high resistivity regions appear to be more strongly alloyed w ith sulfur as measured by the degree of bandgap variation. Wavelength dependence of collection near and slightly below the CdTe bandgap was attributed to local variations in the bandgap due to formation of CdTe1-xSx. This observation is supported by PL measurements on CdTe by others . Comparison of identical samples with and without post deposition CdCl2 treatment has shown that CdCl2 treatment improves uniformity of collection for photons with energies above the CdTe bandgap. However, the treatment was also found to increase the spatial variation of CdTe bandgap. The low bandgap regions did not show evidence of high resistance suggesting that lo wer bandgap regions do not directly increase the series resistance. Elevated thermal stress produced lo cal increases in the resistivity of the material in regions of lower bandgap i.e. higher sulfur alloying. The correlation between variations in bandgap and increase in series resistance is possibly due to non-uniform penetration of both
44CdCl2 (which enhances the alloying) and of contam inants from the back contact. This suggests the same root cause exists for both lowering of bandgap regions and the formation of high resistance regions during contact anneal or thermal stressing . 3.9 Defects in CdTe/CdS Solar Cells Imperfections in a crystal lattice are called de fects. Individual atomic or complex-related defects are called point defects. The followi ng three defects fall into this category: 1) Vacancies missing atom from the lattice 2) Interstitials extra atom between normal lattice sites 3) Substitutionals an atom occupying another elements lattice site Vacancies and self-interstitials are called intrinsic defects while substitutional and external interstitial atoms are called extrinsic defe cts. Schottky defects involve vacancies like an anion or cation or both missing from the lattice (ex: Cd or Te vacancy in CdTe). Frenkel defects are formed when an atom migrates from its lattice site to an interstitial position (ex: Cadmium vacancy and cadmium interstitial). Point def ects are the main dopants in thin film semiconductors. Complex defects formed by combin ation of atomic defects also exist such as [CuCd Cl+ Te], [V2Cd 2ClTe +], [CuCd Cui +] etc. Dislocations are 1-D defects and are caused by a line of defects. Grain boundaries, stacking faults, interfaces and twin boundaries ar e 2-D defects. Grain boundaries are a source of high densities in polycrystalline CdTe . The defects of interest for this study are intrinsic cadmium vacancies, extrinsic copper interstitials and complexes as well as chlorine rela ted defects. The density of these defects found in CdTe/CdS polycrystalline structures have been found to exceed or equal intrinsic layer doping concentrations of CdS or CdTe. The formation ener gy of a particular defect is the change in
45energy of the crystal between initial and final stat es. Thus, a defect with high formation energy is less likely to form or exist. Figure 25 shows the defect sites present in the heterojunction CdS/CdTe structure. Figure 25. CdS/CdTe Structure  CdTe is a called a defect semiconductor becau se its native defects are responsible for its electrical properties i.e. donor-like cadmium interstitial, Cdi + (donates an electron to the lattice) for its n-type conductivity, and acceptor-like cadmium vacancies, VCd (accepts an electron from the lattice) account for its p-type conductivity. Various native defects possible in CdTe are Cadmium vacancy, VCd -/2-, cadmium interstitial, Cdi +/2+, tellurium vacancy, VTe +/2+, tellurium interstitial, Tei -/2-. These can also form complexes with residual impurities or dopants. The existence of metastable states  have been found changing fro m shallow to deep traps or vice versa with or without change in charge  Illumination and thermal excitation could cause these metastable transitions. Deep Level Transient Specstroscopy (DLTS) is one way to identify these defects, though it is not as straightfo rward as in single crystalline structures. Cu and Cl are common elements found in CdTe as both are used during the fabrication process. Cu is used during the back cont act process and Cl is used during the CdCl2 high temperature anneal. The diffusion of Cu to the junction is believed to be responsible for the
46instability of CdTe/CdS solar cells . The pres ence of Donor-Acceptor pair transitions due to cadmium vacancy coupled to some unknown donor is expected. Various Cu complexes are also likely to be formed (Cui+-Vcd -)-. These complexes could act as acceptor states to explain the observed increase in carrier concentration with Cu diffusion. Light Soaking or electric field could split the complexes to Cui ++VCd -, (2Cui +-Vcd -) or Cu clusters to reduce the carrier concentration and formation of traps and recombination centers. This discussion underscores the comple x defect mechanisms involved in the polycrystalline CdS/CdTe structure. The degrad ation mechanisms are neither quantified nor completely understood at this time. A review of existing literature on the defects in CdTe/CdS solar cells is discussed next. Komin, V  had studied the defects pr esent in CdTe/CdS solar cells by DLTS technique. A summary of all defects are shown in table 1 and figure 26. Table 1. Deep Levels Found in the Polycrys talline CdS/CdTe Thin-Film Solar Cells  EA [eV] n [cm-2] Chemical nature H1 0.120 1.0E-16 Trigonal symmetry At-center (VCd 2ClTe +)H2 0.140 4.0E-17 (VCd 2-Cui +), (2CuCd VTe +)or complexes involved VCd 2or VTe + H3 0.200 3.0E-16 growth process H4 0.320 8.0E-16 growth process, TeCd --complex, after CdCl2 anneal: TeCd VCd 2+ Tei H5 0.330 8.0E-18 AgCd H6 0.270 0.35 3.9E-19 9.5E-16 CuCd -, (Cui + 2CuCd -)H7 0.430 1.0E-14 isolated VCd 2H8 0.760 6.0E-13 complex of VCd 2and an impurity E1 0.140 5.0E-18 DX2-state of (VCd 2--ClTe +); Cui +-related E2 0.640 2.0E-13 isolated Cdi 2+ E3 0.790 4.0E-14 A-center (VCd 2--2ClTe +)0 E4 1.100 1.0E-13 isolated VTe +
47 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5E [eV] H1 120 meV 110-16cm2H2 140 meV 410-17cm2H3 200 meV 310-16cm2H4 320 meV 810-16cm2H5 330 meV 810-18cm2H6 270350 meV (0.048)10-16cm2H7 430 meV 110-14cm2H8 760 meV 610-13cm2E1 140 meV 510-18cm2 E2 640 meV 210-13cm2E3 790 meV 410-14cm2E4 1.1 eV 110-13cm2ECEVEIEF CdI 2+ VCd 2-(VCd 2--2ClTe +)0VTe +DX2(VCd 2--ClTe +)-VCd -(VTe --D)-AgCd -CuCd -VCd -growth process Figure 26. Summary of Deep Levels Observed in the Polycrystalline CdS/CdTe Thin-Film Solar Cells  Standard CdTe/CdS solar cells fabricated at USF have shown defects H4-H6 and H8 . Admittance spectroscopy studies of unstressed a nd stressed CdTe solar cells showed that the total concentration of different types of tr aps can exceed the doping level of CdTe . The characteristic times of traps vary widely along with their energy level positions. High concentrations of slow (deep) traps can be attri buted to grain boundary states. Trap bands found with energies Ev + 0.35eV are attributed to CuCd substitutionals. The energy level of these traps is a band with a width of about 0.05eV. Self-compensation is another mechanism that is present in the devices. Species like Cu have been found to self compensate. This means th ere are equal levels of Cu-related donor defect states (ex: Cu interstitials) as acceptor defect states (ex: cadmium substitutionals) in a material
48and thus the net doping concentration of the material remains unchanged. Studies on single crystal CdTe intentionally doped with Cu was found to self-compensate 99% of the time for concentrations up to 1x1019 cm-3 . Even in the presence of complex degrada tion mechanisms, there is evidence that polycrystalline CdS/CdTe solar cells are stable under outdoor (figure 27) and indoor (figure 28) testing [45,4]. This data reiterates the promise s hown by CdTe for fabrication of thin film solar cells and emphasizes the need to understand the underlying degradation mechanisms to help sustain its long term usage. Figure 27. Outdoor Performance of CdTe Submodule  Figure 28. Performance History of Two CdTe Submodules 
493.10 Current literature on Stress Testing of CdTe/CdS Solar Cells With the success of fabricating high efficiency thin film solar cells, the CdTe research community has now shifted focus on understanding the degradation mechanisms involved to increase their longevity and make them cost effe ctive. This section will summarize stress analysis of only CdTe solar cells under various stress c onditions like temperature, illumination, bias and ambience. Hegedus et.al.  have studied the stressinduced degradation of CdS/CdTe solar cells at elevated temperatures and bias, both in the dark and under illumination. Three degradation modes had been identified: 1) Formation of a blocking back contact, 2) Higher junction recombination, and 3) Increased dark resistivity. The blocking back contact was the result of forward bias stressing. Both high temperat ure and forward bias was required for junction degradation. Recontacting the device after stress removed the blocking behavior with no further junction degradation. Devices without Cu in the contact had poor initial performance with degradation independent of bias. Initial efficienci es of 10-12% were obtained for devices with Cu in the back contact and 7-9% for Cu-free back contacted devices which also showed blocking behavior. Uncontacted CdS/CdTe structures were stressed @ OC at 100oC. Contacting these substrates after stress resulted in Voc~0.8V whic h is comparable to the initial performance of standard unstressed devices. When the CdS/CdTe/6 nmCu structure was subjected to similar stress and contacted, the Voc of the device dropped to 0.65V. The intrinsic CdS/CdTe junction is stable but the presence of Cu during stress causes junc tion degradation. The relative change in efficiency after stress for devices with various contacting processes stressed at reverse bias (RB), short circuit (SC), maximum power point (M P) and open circuit voltage (OC) at 100oC in dry air is shown in figure 29.
50 Figure 29. Relative Change in Efficiency for De vices with Different Contacts After Stressing at Bias Shown in Light for 10 Days at 100oC Degradation was maximum in the presence of Cu in the back contacts @ OC and minimum @ SC. There was degradation in devices with no Cu in the back contacts, however it was relatively independent of bias during stress. J-V comparison of SC stressed devices showed large cross-over of dark/light curves though the device degradation was minimum, indicating a large photoconductivity effect. This was attributed to Cu doping of CdS . The effect of forward bias (FB) during stress in the dark @ 60oC for both Cu and Cu-free contacts was studied with bias stress extended to 2.5V (figure 30). Degradation was negligible upto 1V of FB stress and increased drastically at higher bias. Cu-free back contacted devices show no bias dependence to degradation. The effect of temperature, bias, and time are separated in the dark J-V comparison of a device stressed @ +2V. The device was initially stressed for 1 day @ 28oC, then stressed for 1 day @ 60oC and then finally for 10 days. Then the device was recontacted.
51 Figure 30. FF and Voc for Devices with 0 or 6nm Cu Afte r Stress @ FB in the Dark at 60oC for 10 Days Figure 31. Analysis of Dark J-V Curve as DV/DJ. The Slope is AkT/q and Intercept is Rs and Curvature at Large J Indicates a Blocking Contact a) has A=1.6, Rs=4 -cm2 b) has A=2.2, Rs= 9 -cm2
52Bias stressing at 28oC in the dark for 1 day created a blocking contact. Raising the temperature to 60oC the following day resulted in higher recombination currents, higher A, and increase in Rs along with the existence of the blocki ng contact and remained the same for the remaining 9 days (figure 31). Recontacting after stress eliminated the contact barrier but the bulk and junction characteristics of Rs and A remained unaffected. Degradation is predominant and fast in Cu doped devices @ OC or FB compared to SC. Both junction and back contact degradation occurs rapidly (<24 hours). Glancing incident X-ray studies of CdTe surface before and afte r stress showed c uprous telluride, Cu2Te, present initially converting to cupric telluride, CuTe, after stress. It was proposed that the Cu ions liberated by this process could be moved by field-driven diffusion along GBs or electromigration. While Cu2Te is a highly conductive p type material making good ohmic contact, CuTe is a poor conductor that can cause the blocking behavior at the back contact after degradation. Though this model explained some of the results, it also raised a fe w questions on the electromigration of Cu. It does not explain why the Cu free devices degrade, why the degradation is not monotonic with bias (showed least degradation @ SC) and why large photoconductivity developed fo r stress at SC and RB. The degradation of Cu free de vices can be explained by the results of this research where Cu was found by SIMS analysis at the junction of Cu-free devices coming from starting materials and contamination at various processing steps. The back contact barrier opposes the main junction. This should result in Cu ions drifting in the opposite direction at the back compared to the main junction at a given bias. Thus electromigration of Cu along GBs may be plausible, it is possibly not the only degradation mechanism. Thus three degradation mechanisms are identifie d: 1) Cu-related field driven diffusion at FB occurs within hours increasing recombination a nd is partially reversible with field, 2) Formation of a blocking contact in a few hours due to loss of Cu from the back contact which is
53not reversible with field (Recontacting with Cu-fr ee contact eliminated the blocking contact), 3) A slower process not Cu related causing photoconductivity in CdS or CdTe. It was proposed that the Cu++ ions are liberated from Cu2Te and moved via GBs under forward bias. The concentration gradient driven diffusion lengths for Cu in bulk CdTe and along GBs for 1 hour @ 100oC results in 0.3 m for bulk and 30 m for GBs. Clearly GB diffusion is the dominant mechanism. Visoly-Fisher et.al.  studied the degrad ation of CdS/CdTe devices in the dark to thermal stress @ 200oC under different environments (N2 and air) and under illumination (N2). Thermal stressing in dry N2 in the dark for > 50 hours was shown to result in minimal or no degradation. 50% of the cells stressed in dry N2 showed decrease in effi ciency by 10-20% due to drop in FF and Jsc. Rollover was not observed with longer stress times. Increase in dark Rs with significant increase in dark/light J-V crossover wa s observed with stress times. No changes to Laser Beam Induced Current (LBIC) image of th e cell was seen compared to unstressed device. SIMS analysis showed low levels of Cu in the CdTe (1017 Cu atoms cm-3) in a non-contacted CdS/CdTe substrate but a higher level in CdS (9 x 1019 Cu atoms cm-3). Thus, Cu was present in the cell in significant amounts even prior to contacting, originating from impurities in starting materials. Accumulation of Cl in the CdS layer (1020 Cl atoms cm-3 compared to 1019 Cl atoms cm-3 in the CdTe layer) from the CdCl2 treatment was observed. Contacting with Cu-doped graphite paste results in further accumulation of Cu in the CdS. The Cu concentration increases to 1.5 x 1020 atoms cm-3 compared to 3 x 1018 atoms cm-3 in the CdTe. The accumulation of Cu was verified by Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS) analysis. Cu clearly exhibited high affinity towards small grained polycrystalline CdS diffusing rapidly through the CdTe layer. Study of Cu diffusi on in CdTe/TCO/glass structure showed no accumulation profile but a U-shaped profile with hi gh levels of Cu in CdTe/TCO interface. This represented a profile when a diffuser is reflected at the diffusion barrier. No significant increase
54in Cu levels in the CdTe layer was observed with 15 hours of thermal stress @ 200 C in dry N2. There was a slight increase in Cu levels to 2-3.5 x 1020 atoms cm-3. This can further increase with higher stress times. Similar observations are noted during stressing in air, which implies Cu diffusion through CdTe/CdS structure is thermally accelerated. No pattern of Cl accumulation (increase or decrease) with stress was observed. SIMS analysis of CdS layer after stress showed significant Cu accumulation at the CdS/TCO interface, increasing with stress time. Photoluminescence analysis of non-contacted, cont acted and thermally stressed device is shown in figure 32. Figure 32. PL Spectra of CdS Layers from Non-Contacted, Contacted and Stressed CdTe/CdS Cells. Stressing was Performed at 200oC in Dry N2 in the Dark for 16 Hours  The non-contacted substrate showed a sp ectrum with two bands at 680nm and 750nm. The 680nm band was assigned to a (Cls VCd) type complex. Contacting the substrate results in reduction in the 680nm band and formation of a new band at 790nm instead of 750nm band. This peak is assigned to CuCd-related transition. Stressing reduces the 680nm band further and it was observed to drop with increasing stress time in comparison the 790nm band. The spectrum of a non-contacted substrate did not change after th ermal stress irrespective of ambient conditions.
55The effect of Cl was investigated in cells prepared without CdCl2 treatment. This resulted in poor quality devices with efficiencies of 2-3.5%. Stressing caused degradation of Voc from ~800mV to ~650mV but no rollover at forward bias was observed. Dark Rs increased with stress. SIMS analysis of these untreated and non-contacted substrates showed low levels of Cl (~2 x 1017 cm-3) throughout the cell with some accumulation in the CdS layer. The origin of Cl is possibly from the commercial TCO layer as an impurity left from the manufacturing process. Cl levels in CdTe did not vary with co ntacting or stress. Cu levels are similar to CdCl2 treated samples. The only difference is that the peak of Cu accumula tion appears to be located at the CdS/CdTe interface. Following stressing, the profiles obtained b ecome similar to the standard cells with Cu accumulation throughout CdS region. Since these devices had not received CdCl2 treatment, the extent of CdTe/CdS intermixing is expected to be less than standard devices. Therefore, after contacting Cu accumulates at the CdTe side of the interface. Stressing causes this interface to further intermix and Cu to diffuse through the CdS region. PL spectra of CdS for these cells before CdCl2 treatment was very different from sta ndard cells. Weak peaks at ~600nm and 640nm and a very weak and broad band centered at ~760nm was present in this spectrum. No change in this spectrum was observed after contac ting. Stress caused a new and very intense band at 790nm to form. This was found to correlate with SIMS analysis of non-CdCl2 treated cells, which showed low levels of initial Cu accumulatio n in the CdS after contacting. Only stressing caused the CdS layer to be doped by Cu (forming CuCd complexes). Thus Cl may be involved in Cu-doping of CdS. Thermal stressing @ 200oC in air after ~20 hours resulted in rollover causing reduction in the FF, Jsc, and Voc. Increase in Rs due to photodoping of CdS and hence dark/light J-V crossover is observed which increased with stress time. Degr adation rates are initially faster and slow upon continued stress. SIMS analysis shows no differe nce in Cu distribution within the cell in the presence of air or dry N2. Stressing in humid air increased the degradation accompanied by
56increased rollover. Storing samples in room temp erature under humid conditions for several days showed degradation of device parameters espec ially FF. Recontacting stressed devices without first etching the exposed CdTe surface showed no change in cell J-V and rollover. Etching of CdTe prior to recontacting however improved J-V and reduced rollover. LBIC image comparison at 0, 18 and 35 hours of air stress is shown in fi gure 33. Image is bright and homogeneous before stress with small dark area (low current) due to regions of poor contact or mechanical damage. An increase in dark regions along with a reduction in overall image contrast was observed with stressing, indicating low currents in localized areas and decrease in current over the whole sample. Both electronic and mechanical degrad ation are possible reasons for loss in current. Figure 33. Front-wall LBIC Images of Cu/HgTe/Gr aphite Contacted Cells Recorded Following: a) 0, b) 18, and c) 35 Hours Air Stressing in the Dark at 200oC  LBIC changes from pre-stress samples were smaller for thermal stressing in dry N2. Changes to the CdTe back surface chemistr y was investigated using XPS analysis. Unstressed cells, cells stressed in dark in dry N2 and in air were compared (figure 34).
57 Figure 34. Te 3d 5/2 Region of XPS Spectra of the CdTe Surface, From Beneath the Back Contacts of Cells a) Air-Stressed in the Dark (33 h), b) N2-Stressed in the Dark (33h), and c) Unstressed Cells  The CdTe Te peak in each sp ectrum was accompanied by an additional Te peak at a higher binding energy (BE) corresponding to oxidized Te. The BE refers to electron binding energy and is defined as the energy required to free an electron from the coulombic attraction of the atom. The separation in BEs is 3.7 0.1 eV, suggesting the presence of TeO2 or CdTeO3 on the surface (before sputtering). The intensities of the Te(oxide)-related peak in the non-stressed and N2-stressed samples are much smaller (~1/3) than in air stressed ones. After short sputtering, the separation between the Te BEs decreased (3 .2 0.1 eV). This suggested the presence of CdTeO3 or CdTe2O5 in the air-stressed sample after sputtering. No Te oxides were found in the non-stressed and N2-stressed samples after sputtering. Stressing @ 200oC in N2 under illumination at Voc caused device degradation. The degree of degradation varied from 10-20% in good cells with >9% initial efficiency to upto 50% for initially poor cells. The greatest drop was observe d in FF. Both efficiency and FF dropped gradually during 50 hours stressing unlike the air-s tressed cells in dark with rapid initial drop. Some rollover in about half of the devices was observed following illumination stress. SIMS
58analysis showed Cu content to be higher in light stressed cells in all areas of the device, especially CdS. This indicates enhanced Cu in-diffusion during light stressing. Degradation under illumination was found to be reversible for cells stressed for short period of time (~20 h) under ambient conditions (order of days), or by heat treatment at 200oC in dry N2 in the dark. Degradation was permanent for longer stress periods. Thermally stressed and degraded samples have shown recovery (up to 50% recovery of efficiency loss) upon light stressing due to increase in Jsc and Voc. Decrease in dark Rs and reduction in dark/light J-V crossover was al so observed due to decrease in photoconductivity. The PL spectrum of CdS layer from a contacted, unstressed cell was significantly different from a non-contacted substrate. The chang es in the spectrum were assigned to effects of Cu ions diffusing into the bulk of the CdS grains, forming ClS-CuCd complexes and CuCd centers at the expense of ClS-VCd complexes. Cells with no CdCl2 treatment have shown that Cl affects Cu diffusion and doping of CdS during contact formation. The presence of Cl in CdS may accelerate the rate of Cu doping of CdS layer, as CuCd is known to complex with ClS in CdS, which causes increased co-solubility of Cu and Cl. The amount and extent of Cu doping in the CdS increases significantly with stress with less cha nge in its levels in CdTe layer. The PL results showed a decrease in the intensity of ClS-VCd transition with increasing in tensity of the transition ascribed to the CuCd complex. The observed changes in PL and SIMS are due to back contact effects and not due to changes to CdS induced by the stress conditions. The high affinity of Cu for polycrystalline CdS is due to the greater ch emical stability of Cu-S bonds over Cu-Te bonds as a possible driving force. Cl is shown to enha nce Cu diffusion in CdS and is involved with Cu in co-doping of CdS. Recrystallization of CdS in the presence of Cu and Cl results in photoconducting CdS. Stressing of cells with signi ficant concentrations of Cu and Cl in CdS layers is expected to increase photoconductiv ity. Increasing photoconductivity of CdS and hence the dark resistivity of the material will not a ffect the illuminated J-V until the resistivity under
59illumination remains low. Higher dark Rs causes decrease in slope of dark J-V and higher dark/light crossover. It was proposed that this photoconductivity may be related to stability during stress in dark due to complexes of Cl and Cu related defects in CdS possibly ClS-CuCd. This complex may prevent Cu from acting as a deep tr ap in CdS assuming Cu levels in CdS to be lower than or of same order of magnitude as Cl (shown by contacted and dark-stressed cells in SIMS analysis). As PL and SIMS analysis of thermally stressed devices in both N2 and air show same behavior of Cu, it is deduced that degradation seen during stressing in air is a result of back contact/junction degradation driven by atmosphe ric humidity. Data shows 50% of thermally stressed devices in dry N2 have 10-20% degradation. Therefore the assumption of minimal degradation during thermal stressing in N2 is questionable. Cell degradation is accelerated by illumination during stress @ Voc. The process is similar to a forward bias stressing which causes a reduction in electrostatic barrier to Cu+ ion drift at the junction and promoting accumulation in Cd S. The built-in voltage of the heterojunction slows the concentration gradient driven diffusion towards CdS in equilibrium while forward bias and/or light lowers this barrier for diffusion. Similar Cu accumulation was also observed in stable cells thermally stressed in the dark. However, excess Cu accumulation shown in SIMS analysis for light stressing can form deep acceptor states which act as recombination centers and decrease the effective donor concentration of the CdS. Enhanced Cu diffusion into the CdS can be correlated with Cu depletion at the back contact forming a barrier for current transport. This explains the small rollover seen in light stressed devices. Partial or full recovery of light-stress (short period ~ 20h) induced degradation by storage or anneal in the dark is possible due to dissociation of the acceptor defects in CdS (CuCd, VCd-Cui type defects dissociating into VCd + Cui) and back diffusion of Cu+ driven by concentration gradient and the restored junction field. The permanent degradation of longer stress times suggest that the level of Cu concentrations causing degradation are critical and above a thres hold value back diffusion/drift does not assist in
60performance recovery. Heat treatment of devices in the dark before light stressing was found to stabilize their performance. It was suggested that th is is due to the completion of contact anneal which may have been too short. Sufficient Cu and Te are converted to relatively more stable Curich Cu2-xTe known to form a good ohmic contact to high efficiency CdTe. This will result in less Cu+ ions available for diffusion which slows dow n Cu diffusion into the junction compared to Te-rich Cu telluride. Further studies and chemical analysis is necessary to verify this theory. Oxygen migration through the back contact a nd formation of insulating oxide layer on the CdTe surface is postulated to be the main r eason for degradation of unencapsulated cells in air. CdTeO3 (stable thermal oxide of CdTe) decreases the hole current from p-CdTe in a p-CdTeoxide-metal junction. Thus the probability of tu nneling is lowered with increasing oxide thickness and the contact barrier height is increased due to trapped charges in the oxide causing rollover. This barrier can also explain increase in Rs in the dark. Thus humidity accelerates the oxidation of CdTe causing larger degradation during thermal stressing in air. The following degradation mechanisms are postulated based on the results described above. Figure 35. Schematic Representation of Mechanisms Explaining the Behavior of CdTe/CdS Cells Under Various Stress and Recove ry Conditions (Layer Thicknesses are not to Scale) 
61The proposed changes are: a) Stress in dark, inert atmosphere. Observed behavior: no degradation, light/dark J-V crossover. Mechanism: Cu diffusion and doping of CdS b) Stress in dark, O2/H2O-containing atmosphere. Observed behavior: severe degradation, JV rollover. Mechanism: Oxidation of CdTe/back contact interface c) Stress in light, inert atmosphere. Observed be havior: degradation, slight J-V rollover. Mechanism: Enhanced Cu diffusion into CdS, loss of favorable Cu2-xTe at the CdTe/back contact interface d) Recovery after light stress degradation, in ambient atmosphere at room temperature or by heat treatment in inert atmosphere. Observed behavior: J-V recovery. Mechanism: dissociation of Cu-related defects in CdS, back diffusion of Cu out of CdS, Cu2-xTe restored. The cell returns to a state similar to case (a) Thus, presence of Cu is NOT a dominant factor in initial degradation modes of thermal stressed devices. Significant levels of Cu and Cl in CdS increase its photoconductivit y. This increases the dark resistivity of CdS causing an increase in da rk/light J-V crossover. This change does NOT affect the light J-V characteristics of the devi ce. However, excessive Cu doping of CdS during light stressing is found to degr ade device performance due to creation of deep acceptor states in CdS and decrease its ef fective donor concentration. The role of ambient atmosphere on unencapsulated devices during stress is seen in the back contact degradation due to oxidation of CdTe back surface when exposed to air. Townsend S.W  had studied the effect of bias stress on CdTe solar cells. Ionic diffusion of Cu into CdS was proposed to be th e root cause of bias degradation of CdS/CdTe solar cells based on the results. This along with back contact degradation was found to increase device Rs. The difference in dark and light Rs was attributed to highly resistive CdS where trap concentration is above the carrier concentration. Degradation due to bias stress was found to be
62different from studies of Hegedus and Visoly -Fisher discussed previously. Most severe degradation was found to occur under RB stress. Similar reduction though not as drastic was seen under OC and minimal loss in efficien cy was observed under FB stress. Voc was still found to drop considerably with FB stress along with an increase in diode quality factor, A. The apparent doping density within CdTe layer was lowered at FB and increased near the back contact. This increased the zero bias depletion width from 1.5um to 2.7um accompanied by an increase in current collection of long wavelengths. RB caused an increase of apparent doping density within CdTe causing a reduction in depletion width and decrease in current collection of long wavelengths. Back contact barrier lowered from 0.34eV (unstressed) to 0.30eV with FB stress and increased to 0.51eV with RB stress. The doping concentration at the back contact interface did not change significantly with FB, but decreased with RB stress. The increase in barrier height explains the increase in Rs observed with RB stress. Enhanced recombination occurs with FB stress with diode quality factor >2.0 after stressing, which implies a tunneling enhanced recombination mechanism evolving with stress under reduced electric field. Both OC and RB stress showed an increase in Rs attributed to highly resistive Cu doped CdS film. Changes to CdTe region outside the depletion width also ad ds to this resistance. PL spectra showed the presence of Cu on the grain boundaries in CdS. Wh en CdS is treated with Cu along with CdCl2 treatment it results in the spectra changing, wh ich shows Cu present in CdS bulk with reduction in the peak of Cu on the grain boundaries. RB st ress has Cu within the bulk CdS due to high electric field. Photoconductivity effect was obser ved in CdS films intentionally doped with Cu. Thus devices with Cu within CdS layer ar e expected to exhibit a difference in Rs from dark to light measurements. This effect was observed in actual devices. Cells completed with intentionally Cu doped CdS layer showed many si milarities to RB stressed devices such as drop in FF and increase in Rs. Thus stress-induced degradation of CdS/CdTe devices is in part due to the changes to CdS layer during stress. The change s to back contact barrier are attributed to
64CHAPTER 4 EXPERIMENTAL 4.1 Device Structure & Fabrication A conventional CdS/CdTe solar cell structure with the n-type window layer of CdS and p-type absorber layer of CdTe is shown in the figure 36. Silver Paint HgTe:Cu doped Graphite Paste CdTe CdS SnO2SnO2:F Glass Substrate InIn Light Source Figure 36. Conventional CdTe/CdS Solar Cell (Superstrate Structure) Light enters these cells through the transp arent substrate (glass) and is called the backwall or superstrate configuration. The TCO layer of SnO2:F film is the frontwall contact. The doped graphite paste and silver paint forms the back contact to the cell. The fabrication process of devices used in th is study begins with the deposition of a degenerately doped layer of SnO2:F on a clean 7059 glass substrate which provides films with a sheet resistivity of the about 7-10 /sq. The film serves as a transparent conducting oxide (TCO)
65which conducts the current from the CdS/CdTe junction to the front metal contacts around the cell. This film is deposited by MOCVD tec hnique. Halocarbon 13B-1 serves as a source of fluorine (dopant) and tetramethyltin (TMT) provides Sn. He and O2 are ambient gases for the deposition. The final thickness of SnO2 films are about 0.8-1 m thick. CdS films were deposited using chemical bath deposition (CBD). Cadmium acetate (CdAc) the Cd ion source, thiourea the sulfur ion source, and the buffer ammonium acetate (NH3Ac) and ammonium hydroxide (NH4OH) constitute the reactants. A solution containing measured amounts of CdAc, NH3Ac and NH4OH is prepared along with a solution of thiourea. The deposition process involves immersing the SnO2:F coated substrates held by a glass holder into a beaker with water an d heating the solution to 90 C. The temperature is maintained constant throughout the deposition. The rate of formati on of CdS can be adjusted by varying the concentration of ammonia and its salts in the solution. Homogeneous formation of CdS in the solution produces CdS precipitate whereas hete rogeneous formation produces adherent CdS deposits on the substrate surface. Thus, the homogenous process which yields powdery, nonadherent films on the substrate is undesirable. This is suppressed using conditions for the formation of CdS at low rates like low temperature, high concentration of NH3 and NH4 salt, and low concentration of Cd salt and thiourea. Figure 37. CSS Deposition Chamber 
66 The CdTe film is deposited over the Cd S film by the CSS technique. The deposition setup for CSS process is shown in figure 37. The substrates are annealed in H2 for 10 minutes at 400 C before CdTe deposition. The CdTe depositio n by CSS is its sublimation from a 99.999% pure CdTe source. The deposition is done at source temperature of 600 to 680 C and substrate temperature of 500 to 600 C for 1-7 minutes in the presence of He/O2 as ambient gases. Films of 4-10 micrometers thickness are obtained. The cadmium chloride (CdCl2) treatment of a heterojunction is essential to increase the grain size of CdTe films, which reduces grain boundaries, potential shunting paths and recombination centers which effect cell performance. It is also believed to improve the interface between CdS and CdTe enhancing the open circuit voltage of the device. The treatment involves the evaporation of CdCl2 and annealing the substrate at 400 C in the presence of He and O2 for 45 minutes. Excess CdCl2 is removed by rinsing the samples in methanol and then treating with bromine solution leaving a smooth Te rich surface for contacting. The final step in the fabrication of this cell involves contacting. Graphite paste doped with HgTe:Cu is painted on the CdTe film and the substrates are annealed at 250 C in He ambient. The graphite contact is then coated with a thin conductive layer of silver paint. This completes the back contact for the solar cell. The CdTe around the cell is removed, exposing the SnO2:F surface. Indium solder is applied to this film, which serves as a front metal contact. This completes the fabrication of a CdS/CdTe solar cell.
674.2 Thermal Stress (TS) Figure 38. Thermal Stressing Chamber Thermal degradation of CdS/CdTe solar cells was accelerated by stressing cells at higher temperatures than they are likely to operat e under normal operating conditions. The annealing process is carried out in a vacuum chamber in an inert ambient of UHP He at temperatures of 60o, 70o, 80o, 90o, 100o & 120oC. A schematic drawing of the cham ber is shown in figure 38. Inside the chamber are six zones of quartz heating lamps individually controlled by temperature controllers. Above each zone a graphite boat w as placed which could hold 15-20 cells to be thermally stressed. A thermocouple was attached to the boat which enabled the temperature control of each zone to a unique temperature. The chamber has an outlet connected to a vacuum pump at the bottom. An inlet for UHP Helium on one side of the chamber was used to purge the system before starting an annealing process. Each run is started with a purge and backfill of the chamber with UHP He to remove any adsorbed mo isture and air in the chamber. The chamber is LAMP LAMP LAMP LAMP LAMP LAMP To Vacuum Pump Thermocouple to Temperature Controlle r Wires of Heating Lamps to Temperature Controller Graphite Boat with Samples UHP He Inlet Vacuum sealed sample inlet door
68filled with UHP He to a positive pressure of 20 psi before start of thermal stressing. Due to malfunctioning of the temperature controller at 60oC, the temperature of this zone could not be controlled constantly and thus resu lts from samples in this zone are discarded from our analysis. Stressing for gradually increased from 1, 2, 3, 4, 8, 16, 32 hours. Light/Dark J-V and C-V analysis was performed after each stress period. 4.3 Illumination Stress or Light Soaking (LS) Figure 39. Illumination Stressing Chamber A schematic of illumination stressing chamber is shown in figure 39. It consists of a vacuum sealed quartz tube which allows illumina tion of the solar cells inside and keeps out moisture, humidity and air. Samples are mounted in the chamber with outlets for electrical wires to monitor device performance and a thermocouple to monitor the temperature of the devices under stress. The solar cell simulator based on tu ngsten halogen quartz lamps is calibrated to ~AM1.5 conditions. Lightsoaking is performed in a N2 ambient. Continuous flow of N2 gas is maintained from the inlet during stressing whic h enables cooling the device under stress and Cell Output wires Solar Simulator N2 Inlet N2 Outlet Cells Thermocouple Quartz Tube
69helps keep air and humidity out of the cham ber. Stressing was performed initially for small periods of 2, 4, 6 hours and increased to 8-10 hours/day after 50 hours. Light J-V testing was performed everyday during stressing @ 70oC. Dark J-V testing was performed before the start of stressing each day. Room temperature J-V testi ng was performed infrequently at ~200 hour stress periods. 4.4 Characterization Techniques During the light-soaking and thermal stressing of the CdS/CdTe solar cells, the following measurement techniques were used to characterize the device performance. Current Voltage (IV), Capacitance Voltage (C-V), Capacitance Frequency (C-F) and Spectral Response (SR) measurements taken intermittently are used to study the device behavior. 4.4.1 J-V Measurements Dark and light J-V measurements were performed on the devices, both initially and during the various stages of annealing and light so aking. Many important device parameters can be deduced from this data. From a typical light J-V curve, apart from measuring the values of diode parameters Voc, FF, Jsc and it is possible to extrapolate sh unt and series resistance values. Shunt resistance is calculated by taking the slope of J-V in the reverse bias condition while series resistance can be obtained from the slope at hi gh forward bias region. The shunt resistance @ Jsc is measured by taking the slope of the J-V curve between voltages of 100mV and the series resistance is measured from the slope of the J-V curve between currents of 90-100mA. Diode leakage current, Jo, can be deduced from the extrapolation of the slope of dark ln(J) vs V curve between 0.2V and 0.6V to zero bias. The diode quality factor, A, is deduced fro m the dark J-V curve using the simplified diode equation,
70A = V/(kT/q* ln(ABS(Jo1/Jo2))) Plotting A vs Voltage between 0.3V and 0.6V, the minima of the curve is calculated. Shunt and series resistance affect the value of diode qua lity factor below 0.3V and above 0.6V. A is typically between 1.5 0.2 for CdTe devices. The dependence of A on voltage and light intensity was discussed in the theory section. This results in questioning the accuracy of measuri ng A. This is especially true of the degraded devices measured in this study with severe s hunting or high leakage currents or presence of a collection function. The value of Jo and A are in doubt simply due to the fact that recalculation of Jo from the Voc of the cell results in different values than the extrapolated Jo. 4.4.2 C-V Measurements Capacitance measurements are performed in the dark at a high frequency of 300kHz. The doping concentration, NA and Vbi of the device can be obtained from the C-V measurements for uniformly doped materials. Slope of (A/V)2 curve at reverse bias provides NA and the intercept on the x-axis provides the Vbi. 4.4.3 Spectral Response Curves Spectral response (SR) is used to measure the Jsc of the device. The current generated from an incident light source of 400nm to 900nm is collected to calculate the Jsc of the device. 4.5 Device Behavior of USF Cells This section discusses the CdS/CdTe cells fabricated at USF and summarize their behavior studied in the past.
714.5.1 I-V Analysis 188.8.131.52 Temperature I-V Analysis The reverse saturation current variation with temperature was measured by Chris Ferekides  as shown in figure 40. Jo values were obtained from y-intercept of dark J-V curves. The exponential dependence of Jo on 1/T indicates that the cells are not dominated by tunneling currents. The standard recombina tion model predicts a slope of Eg/2 (0.72eV) for this graph. The measured slope of 0.66eV is close indicating that recombination current dominates device behavior above 220K. Figure 40. Temperature Dependence of Jo  184.108.40.206 Light & Dark J-V Analysis The typical light J-V curves of USF cells do not have any roll over at forward bias, indicating a quasi-ohmic back contact to CdTe. An example of a device with a non-ohmic back contact with rectification or roll-over is shown in figure 41. The device has an ohmic back contact initially, which degrades under thermal stress showing a rollover effect.
72 Figure 41. Rollover Observed in J-V Curves The crossover behavior of dark and light JV of USF cells is illustrated in figure 42. Figure 42. Crossover of Dark & Light J-V in USF Cells  1-4B-7A2C(100C)-1.60E-02 -1.10E-02 -6.00E-03 -1.00E-03 4.00E-03 -0.4-0.200.20.40.60.81 Voltage(V)Current(A) initial 612 hrs 1068 hrs
63electromigration of CuCd over Cu+ i. FB stress assists the electromigration of negatively charged species towards the back contact and RB deplet es it from the back contact causing formation of back barrier. Morgan D.T  also studied the degrada tion of CdS/CdTe solar cells under bias stress conditions in the dark and light. The highest degr ee of degradation of all parameters was observed for RB in the dark. Doping levels and magnitude change significantly with bias stress and this change was proposed to be the major determining factor of degradation. The bias dependence of degradation clearly shows a considerable role of electromigration of charged impurities and defects (Curelated) in device degradation. Gilmore A.S  observed that samples str essed under OC (which improved efficiencies) exhibited an increase in the defect state density of the shallow defect state (associated with CuCd). Samples stressed under RB (-2V, which decreased e fficiency) showed a marked decrease in the density of defects associated with the same le vel. Neither stress condition changed the defect density of deep level associated with cadmium vacancies. These observations also point towards the migration of copper and its defects under stress. Its depletion at the back contact is proposed to cause the degradation in device performance. It is clear from the above studies that Cu and its defect complexes have been identified as the primary factor responsible for degradation. Ho wever, the nature of the mobile species and the mechanism of its transport (electromigration or field assisted diffusion) and the degraded layer (CdTe or CdS) is widely debated and still specu lative based on the results of individual research groups.
73 Extensive study of this behavior was done by Dan Oman . The bias and spectral dependence of the dark J-V has shown the exis tence of a front junction at the CdS/SnO2 interface opposing the main junction. The front junction however has very low Rsh in light making its effect negligible under illumination. The J-V of a good device with efficiency > 10% can be simulated from the equation given below. I = Io[e q(V-IRs)/AkT 1] IL (V-IRs)/Rsh 4.5.2 Spectral Response Analysis It was observed that USF cells showed no voltage dependent collection for unstressed devices . This suggests that expanding the SCR into the bulk CdTe does not collect any additional carriers. This observation agrees w ith the capacitance measurements, which have shown that SCR extends more than 1 m into the bulk.
74 CHAPTER 5 RESULTS AND DISCUSSION 5.1 Thermal Stress This section discusses the effects of thermal stress on device performance. The degradation process was accelerated by stressing cel ls at higher temperatures than they are likely to reach under normal operating conditions. A few wi tness samples were put aside in a desiccator at room temperature. Devices from the same substrates were subsequently used for thermal stress. The stressing process was carried out in a vacuum chamber in an inert ambient of UHP He at temperatures of 70o, 80o, 90o, 100o & 120oC. It was observed that temperatures above 100oC degraded the silver epoxy contact, resulting in stressing and peeling of underlying films from the substrate. Due to the peeling of backcontacts at high temperatures, the current cell design cannot be used for accelerated stress testing above 100oC, in order to study the intrinsic junction and back contact degradation mechanisms. The cells have been characterized using J-V, SR and C-V measurements. The first set of data summarizes the performance changes in the device short circuit current (Jsc), open-circuit voltage (Voc), fill factor (FF), cell efficiency ( ), diode quality factor (A) and reverse saturation current density (Jo) after stressing for 3600 hours at various temperatures. Each datapoint for stressed devices in figures 43, 44 & 45 indicates the normalized parametric change and is an average of change observed in three samples. Th e datapoint for witness samples is an average of change in two samples.
75 5.1.1 Effect on Open-Circuit Voltage (Voc) A general trend of decreasing Voc with increasing stress temperature was found. Figure 43 shows a normalized change in Voc with time for devices with various stress temperatures. Witness samples do not degrade over time for Voc. In stressed devices, the most significant drop in Voc occurred within 500 hours of st ressing irrespective of the stress temperature. Subsequently the Voc leveled off over time. Total drop in Voc was less than 4% up to 100oC stress temperature, but jumped to 11% at 120oC. Figure 43. Normalized Voc vs Time at Various Stress Temperatures The change in Voc at 500 hour intervals is tabulated in table 2. Typically there was a decrease in Voc, though there are instances of increase. It is not exactly clear if this recovery is real on all occasions as this is within the range (10-15mV) of measurement error. However, such Normalized Voc vs Time 0.85 0.9 0.95 1 1.05 0500100015002000250030003500 Time, HoursNormalized Voc 25C 70C 80C 90C 100C 120C Witness Samples
76 recovery in device parameters had been observed by others  in polycrystalline devices due to relaxation of defects at the junction. Table 2. Change in Voc at 500 Hour Intervals The drop in Voc increases with high stress temperatures and is a result of increasing recombination losses and reverse saturation current, Jo along with junction shunting as will be shown later during the J-V analysis. 5.1.2 Effect on Fill Factor (FF) Normalized FF vs Time 0.5 0.6 0.7 0.8 0.9 1 1.1 0500100015002000250030003500 Time, HoursNormalized FF 25C 70C 80C 90C 100C 120C Witness Sam p les Figure 44. Normalized FF vs Time at Various Stress Temperatures Stress Period, Hrs0-500 500-10001000-15001500-20002000-25002500-30003000-3600AverageTotal Temperature, C 25 -3.2 70-11.46.2-3.2-5.5-6.2-2.34.0-2.6-18.4 80-11.75.4-5.6-14.6-220.127.116.11-3.6-24.9 90-18.104.22.168-13.02.4-3.4-1.2-4.5-31.6 100-22.214.171.124-13.83.1-10.29.4-5.2-36.4 120-70.211.4-12.8-10.5-9.1-4.35.4-12.9-90.0 Note: "-" shows DECREASE, "+" shows INCREASE
77 The fill factor showed significant degradation due to thermal stressing. The figure 44 shows changes observed over time. Most of the decrease is early, similar to Voc, but takes 1000 hours instead of 500 hours. A linear degradation can be seen over time for each temperature. A drop of 7% @ 70oC to 36% @ 120oC can be seen within the first 1000 hours. From 1000-3600 hours the rate of degradation decreases to 3% @ 70oC to 7% @ 120oC. A tabulation of the absolute FF variation over 50 0 hour intervals is shown in table 3. The variation ranges from 1.5% for an unstressed device to 31% for a device stressed at 120oC. Table 3. Change in FF at 500 Hour Intervals The FF degradation is a result of several factors: increasing Rs, decreasing Rsh, and increase in collection losses, which will be discussed in the later subsections discussing the effect of thermal stress on Rs, Rsh, and Jsc. 5.1.3 Effect on Short-Circuit Current Density (Jsc) No significant change in Jsc was observed for the witness samples. Degradation is most prominent within the first 1000 hours for stressed devices. A linear and slow degradation is observed thereafter at all stress temperatures. Jsc losses range from 2% at 70oC to 23% at 120oC (figure 45). Stress Period, Hrs0-500 500-10001000-15001500-20002000-25002500-30003000-3600Averag e Total Temperature, C 25 -1.5 70-2.9-2.3-2.71.8-0.3-0.8-0.3-1.1-7.5 80-8.7-3.9-6.81.5-2.1-0.40.6-2.9-20.0 90-9.4-4.0-2.91.3-3.4-0.10.6-2.6-18.0 100-16.7-4.8-4.31.3-3.9-0.60.9-4.0-28.2 120-24.6-1.3-2.90.4-2.70.4-0.7-4.5-31.4 Note: "-" shows DECREASE, "+" shows INCREASE
78 Normalized Jsc vs Time 0.75 0.8 0.85 0.9 0.95 1 1.05 0500100015002000250030003500 Time, HoursNormalized Jsc 25C 70C 80C 90C 100C 120CWitness Samples Figure 45. Normalized Jsc vs Time at Various Stress Temperatures CdTe#9-29A-10A(Rm) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 400500600700800900 wavelength (nm)Q.E. A-0(22.4mA/cm2) A-3600 hrs(23mA/cm2) Figure 46. SR of a Witness Sample Stored at Room Temperature in a Desiccator
79 The Jsc of a witness sample from SR measurements is shown in figure 46. A small improvement of 0.6mA/cm2 in Jsc was observed. The increase comes mostly from the improved collection of deeply generated carriers due to possi ble changes to the nature of the defects that lead to stronger electric fields (higher depleti on). The doping profile generated from C-V analysis showed increase in depletion region of CdTe. The performance improvement has been observed in the past in CdTe devices fabricated at USF . CdTe#9-29A-11A(70oC) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 400500600700800900 wavelength (nm)Q.E. A-0(22.9mA/cm2) A-3600(22.7mA/cm2) Figure 47. SR of Device Stressed @ 70oC Before and After 3600 Hours Stressing A minimal change in spectral response w as observed in devices stressed up to 80oC. A representative sample SR of a device stressed at 70oC is shown in figure 47 where the initial and final SR responses are essentially identical. Above 80oC degradation in Jsc was observed, which accelerated significantly at higher stress temperatures. The SR of a device stressed at 120oC is shown in figure 48. Predominant collection losses occurred in the red region sugges ting changes deep in bu lk CdTe, away from the depletion region. This means that the lifetime of photo-generated carriers deep in the CdTe is significantly reduced. The carriers are lost to recombination before reaching the space charge region (SCR) and being swept by the electric field.
80 CdTe#11-17A-1C(120oC) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 400500600700800900 wavelength (nm)Q.E. C-0(23.1mA/cm2) C-3600(21.1mA/cm2) Figure 48. SR of Device Stressed @ 120oC Before and After 3600 Hours Stressing 5.1.4 Effect on Shunt Resistance (Rsh) The shunt resistance of devices drastically decreases with increasing stress temperature. Table 4 shows the variation in Rsh @ Jsc over time for a representative sample from each stress temperature and table 5 shows the variation in FF over time for the same samples. The effect of Rsh on FF becomes significant below values of 1.5k -cm2. Below this value the FF decreases drastically by >20%. Table 4. Rsh @ Jsc Variation over Time TemperatureSample# 0580126030003600% Change 25oC 9-29A-10A41883275-22% 70oC 9-29A-11A33434733331932742034-39% 80oC 9-29A-8D3371267894613901063-68% 90oC 9-29A-11B4230248212211086750-82% 100oC 9-29A-10C7116790379304262-96% 120oC 9-29A-11C3634161163144146-96% Note: "-" change indicates DECREASE, "+" change indicates INCREASE Rs h @ Jsc, ohm-cm2# of Hours in thermal stress
81 Table 5. FF Variation over Time TemperatureSample# 0580126030003600% Change 25oC 9-29A-10A0.710.70-2% 70oC 9-29A-11A0.730.720.700.690.68-7% 80oC 9-29A-8D0.720.660.610.580.58-19% 90oC 9-29A-11B0.740.660.620.570.57-23% 100oC 9-29A-10C0.740.530.450.380.39-47% 120oC 9-29A-11C0.740.480.450.430.44-40% Note: "-" change indicates DECREASE, "+" change indicates INCREASE FF, % # of Hours in thermal stress The FF vs Rsh are plotted in the figure 49 from meas urements taken for the above devices at various times during stress. A drastic decrease in FF for Rsh < 1.5k -cm2 was observed. FF vs (Rsh @ Jsc) 0.3 0.4 0.5 0.6 0.7 0.8 02000400060008000 Rsh @ Jsc, ohm-cm2FF Measured FF FF(sim) @ Rs = 2 ohms FF(sim) @ Rs = 4 ohms FF ( sim ) @ Rs = 6 ohms Figure 49. FF vs Rsh @ Jsc of Devices Stressed to 3600 Hours and Simulations In the same figure, the FF vs Rsh @ Jsc profile simulated from the J-V equation of a diode with varying Rs is plotted. The FF closely matches simulations at high Rsh (typical USF device Rs ~ 2 ) which represent data points before the devices were stressed. The lower Rsh @ Jsc <2k are measured after stressing devices at various temperatures. The FF does not match simulations at low Rsh below 2k Along with the reduction in Rsh, the Rs of degraded devices had increased up
82 to 6 The simulated FF for low Rsh and Rs of 6 is higher than measured FF. Thus, it can be concluded that there are other factors causing the reduction in FF. Collection losses are found to be the third factor responsible for reducing FF. When photogenerated carriers are lost to recomb ination centers that lead to lower Jsc, they cause a drastic reduction in FF. Forward bias decreases th e collection field increasing the losses. This effect can be verified by measuring the reverse bias Rsh of the device at 2V. Reverse bias makes the depletion width wider. Due to the N+-P structure of CdS/CdTe solar cell, the depletion width modulation occurs predominantly in the CdTe. Th is helps collect more photogenerated carriers in the bulk CdTe that are lost to recombination at zero or forward bias. Thus studying the variation in Rsh @ 2V and @ Jsc will clearly show if any collection effects are dominant in the degraded devices. The J-V curves of devices thermally stressed for 3600 hours is shown in figure 50. J-V Curves after Thermal Stress -0.025 -0.023 -0.021 -0.019 -0.017 -0.015 -2-1.5-1-0.500.51 V, VoltsJ, mA/cm2 70C 80C 90C 100C 120C Figure 50. J-V Curves of TS Devices to 3600 Hours at Various Temperatures
83 The reduction in Rsh @ Jsc due to increasing collection losses at higher thermal stress are tabulated in table 6 along with the FF degradation. Table 6. Rsh @ Jsc and Rsh @ -2V after Thermal Stress at Various Temperatures It is clearly evident that up to 100oC the Rsh @ -2V is higher than 1k which means the devices are not shunting. The low Rsh @ Jsc is the effect of collection losses deep in the CdTe layer. The device degradation at 120oC is caused by severe shunting, resulting in high leakage currents. Thus shunting effects outweigh co llection losses at high stress temperatures. 5.1.5 Effect on Series Resistance (Rs) Another parameter that has a direct influen ce on the FF of a device is its series resistance. Bulk Rs can be deduced from the slope of the li ght J-V at high forward currents. The Rs @ Voc is a good indicator of the presence of back contact barri er in the device which may not be captured by measuring Rs at high forward currents. Table 7 indicates the changes in Rs at high forward current for a representative sample at each stressing temperature. A clear increase in Rs was measured over time with higher stress temperatures. Witness sample shows minimal change. Sample# Rsh @ Jsc (ohm-cm2) Rsh @ -2V (ohm-cm2) Rsh @ Jsc / Rsh @ -2VFF 9-29A-11A(70oC) 333354350.610.69 9-29A-8D(80oC) 78137740.210.57 9-29A-11B(90oC) 90125970.350.57 11-17A-2C(100oC) 52612660.420.48 9-29A-11C(120oC) 1431341.070.42
84 Table 7. Rs @ High Current for Thermal Stress at Various Temperatures TemperatureSample# 0580126030003600Change25oC 9-29A-10A2.72.4-0.370oC 9-29A-11A2.12.02.42.52.80.680oC 9-29A-8D126.96.36.199.32.91.290oC 9-29A-11B2.02.63.14.03.71.7100oC 9-29A-10C188.8.131.52.15.94.0120oC 9-29A-11C184.108.40.206.44.32.4Note: "-" shows DECREASE, "+" shows INCREASE # of Hours in thermal stress Series Resistance @ High Current, Ohm-cm2 The Rs increases up to 6 with increasing stress temperatures after 3600 hours. Simulation of Rs vs FF in Figure 49 and Rsh @ -2V in Table 6 show that the change in Rs does not completely explain the loss in FF due to thermal st ress. The FF is lower than the simulated values for Rs of 6 and Rsh of 1k which means collection losses as explained in section 5.1.4 contribute to device degradation along with Rs and Rsh effects. 5.1.6 Diode Quality Factor, A & Reverse Saturation Current Density, Jo A & Jo do not show significant degradation up to thermal stressing of 70oC. However, high leakage currents cause A & Jo to increase at 80oC and above. Higher recombination losses at low bias voltages result in deducing accurate A & Jo values extremely difficult as seen in table 8 where unrealistic A values above 2 are calculated from the data. A discussion of these results can be found in the next section 5.1.7.
85 Table 8. A & Jo for Thermal Stress at Various Temperatures TemperatureSample# Change in A Change in Jo0360003600 25oC 9-29A-10A1.61.70.01.9E-115.0E-11 x 2.6 70oC 9-29A-11A220.127.116.11.2E-114.0E-10x 12.5 80oC 9-29A-8D18.104.22.168.0E-064.4E-09x 1466 90oC 9-29A-11B22.214.171.124.6E-119.0E-10 x 34 100oC 9-29A-10C126.96.36.199.5E-113.9E-08 x 2600 120oC 9-29A-11C1.715.013.31.4E-106.0E-04 x 4.3E6 Note: "-" shows DECREASE, "+" shows INCREASE # of Hours in thermal stress A Jo, A/cm2 5.1.7 Dark J-V Analysis Dark J-V curves for a witness sample is shown in figure 51. Figure 51. Ln(J)-V and Linear J-V in the Dark for a Witness Device Stored @ Room Temperature There were no significant changes in the da rk J-V behavior as shown in the ln J-V & linear J-V data. The J-V characteristics of a device stressed @ Voc in the dark at 70oC is shown in figure 52. The ln J-V curve in figure 52 shows possi ble increased shunting with time. However, Rsh @ Rm(9-29A-10A) 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 0.0001 0.001 0.01 0.1 1 00.20.40.60.811.21.4 Voltage, (V)ln(dark J) start present Rm(9-29A-10A) 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 0.18 00.20.40.60.8188.8.131.52.82 Voltage, (V)Current Density, (A/cm2 ) start present
86 2V for this device measured at >3k ohms afte r 3600 hours of stressing (Table 6). This suggests that the increase in current is not shunting. Thus the increase in recombination current is most likely associated with the creation of d eep-level defects that cause a drop in Voc over time. Several acceptor like defects related to Cu, Cl and their complexes were detected by DLTS studies of CdS/CdTe solar cells at USF . An increase in concentration of these defects is postulated to be the root cause for increase in Jo and decrease in Voc. The nature of these defects will be discussed later in the literature. Another key change to note is that the major increase in Jo occurs within the first 500 hours of stressing whic h subsequently saturates. This agrees with the observation of a rapid drop in Voc initially and its leveling after ~1000 hours of thermal stress. The linear J-V curve also captu res an interesting trend where the knee or turn-on of J-V shifts towards higher voltages over time. The presence of a barrier at CdS/SnO2 interface against the main junction and the change in photoc onductivity of CdS is believed to be associated with this J-V behavior [7, 16]. This results in a dark J-V turning ON after the breakdown of this blocking diode at voltages higher than Voc causing a crossover of dark and light J-V. Thus, the shift suggests an increase in the bloc king barrier. This can occur if th ere is a drop in concentration of CdS w.r.t SnO2. If the high level of acceptor like defects (Cu and Cl complexes) accumulate in CdS, it will reduce the net doping of CdS by compensation. The shift of the knee is gradual over time, however the corresponding FF levels off after 1000 hours. This means the front contact barrier changes may not be influencing the device under illumination. Two simultaneous effects can be deduced from the dark J-V curves. a) A fast process (that occurs within the fi rst 500 hours of stress) leads to increased recombination currents, and b) A slow process (that appears to be on-going throughout the entire stress period of 3600 hours) that results in increased compensation of CdS, leading to a larger barrier between CdS and SnO2.
87 Based on the discussion above, we can conclude that higher recombination currents are the root cause of degradation. The photoconductive nature of CdS has been well documented and crossover of varying degrees has been observed in high efficiency CdS/CdTe solar cells [7,16]. Since changes to the front contact barrier have not sign ificantly altered the light J-V characteristics of the device they may not be playing a role in de gradation. However, continual compensation of CdS increases its resistivity causi ng an increase in the device Rs and reducing the FF. Figure 52. Ln(J)-V and Linear J-V in the Dark for TS Device at 70oC Consider the J-V behavior of a device stressed at 120oC in figure 53. An increase in leakage losses and a consequential reduction in Voc was observed, as can be expected for higher thermal stressing. Severe shunting was also ob served within the first 500 hours of stressing at 120oC and was verified by measuring Rsh @ -2V. We observe a worsening of the front contact barrier with the dark J-V gradua lly deteriorating from a shift to a collapse over time. Junction shunting is believed to be the primary cause of device degradation due to a large drop in Voc & FF observed within the first 500 hours of thermal stressing at high temperatures. Secondary effect of continual compensation of CdS exist, causing deterioration of CdS/SnO2 barrier, but most 70oC(9-29A-11A) 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 0.0001 0.001 0.01 0.1 1 00.20.40.60.811.21.4 Voltage, (V)ln(dark J) start 580 hrs 1260 hrs 3600 hrs 70oC(9-29A-11A) 0 0.05 0.1 0.15 0.2 0.25 00.20.40.60.8184.108.40.206.82 Voltage, (V)Current Density, (A/cm2 ) start 580 hrs 1260 hrs 3600 hrs
88 importantly increasing the Rs of CdS layer, causing FF deterioration over time. The increase in Rs @ Voc shown later in the light J-V indicat es a possible back contact degradation. Figure 53. Ln(J)-V and Linear J-V in the Dark for TS Device at 120oC 5.1.8 Light J-V Analysis The witness device showed no significant change in performance over time as seen from figure 54. Figure 54. Light J-V for a Witness Device Stored at Room Temperature 120oC(9-29A-11C) 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 0.0001 0.001 0.01 0.1 1 00.20.40.60.811.21.4 Voltage, (V)ln(dark J) start 580 hrs 1260 hrs 3600 hrs 120oC(9-29A-11C) 0 0.05 0.1 0.15 0.2 0.25 0.3 00.20.40.60.8220.127.116.11.82 Voltage, (V)Current Density, (A/cm2 ) start 580 hrs 1260 hrs 3600 hrs Rm(9-29A-10A) -0.05 0 0.05 0.1 0.15 0.2 -0.500.511.52 Voltage, (V)Current Density, (A/cm2 ) start present
89 Figure 55. Light J-V of a TS Device at 70oC & 120oC By comparing the light J-V characteristics of samples stressed at 70oC & 120oC (figure 55), a decrease in Voc and FF with increasing stress temperature is evident. A gradual increase in light Rs under illumination was observed. This change mi rrors the increase in dark J-V crossover. These two effects are related and are attributed to CdS compensation by deep level defects that form or mutate during the stress process. This forms the slow component of FF degradation. The faster component of degradation is most likely due to changes in CdTe and CdS/CdTe junction. Up to 90oC, collection and recombination losses are dominant as seen in the light J-V. Over 100oC, junction shunting also contributes to the performance degradation along with possible back contact degradation within 500 hours of thermal stress. 5.1.9 Capacitance-Voltage Measurements (C-V) With a typical CdTe acceptor concentration of ~1014/cm-3 and CdS donor concentration of ~ 1016/cm-3, the depletion width will extend predomin antly into CdTe and thus, biasing will 70oC(9-29A-11A) -0.05 0 0.05 0.1 0.15 0.2 0.25 -0.500.511.52 Voltage, (V)Current Density, (A/cm2 ) start 580 hrs 1260 hrs 3600 hrs 120oC(9-29A-11C)-0.05 0 0.05 0.1 0.15 0.2 0.25 0.3 -0.500.511.52 Voltage, (V)Current Density, (A/cm 2 start 580 hrs 1260 hrs 3600 hrs
90 result in modulating the depletion width into CdTe Thus changes in capacitance will be primarily an effect of changes in bulk CdTe. Figure 56 shows the net acceptor concentration (NA) calculated for the control sample using C-V measurements at 300kHz The data suggest s that the net acceptor concentration at the junction had dropped from ~7E13 to 3E13 due to an increase in SCR width, but the bulk concentration had increased from 1.5E14 to 2E14. Th is is a result of the aging effect previously discussed, where defect rearrangement and diffusion of ionic dopant species like Cu, Cl or their defect complexes occur even at room temperature over time, resulting in passivation of existing defects or compensation. This reduction in NA at zero bias with time w ill result in an increase in the depletion width into CdTe. This should cause an increase in current collection especially in the red region in CdTe. The SR in Figure 46 clearly shows this improvement in collection for this witness device. Note that the grading in the doping profile had increased as a result of the changes in the defect structure of the CdTe. This is due to the diffusion of dopant species such as Cu from the back contact into the CdTe, junction a nd the CdS as observed in SIMS analysis. 9-29A-10A (Control) 1E+13 1E+14 1E+15 -2-1.5-1-0.500.5 Bias Voltage, VAcceptor conc., NA (/cm3) initial final Figure 56. NA-V in the Dark for a Witness Device
91 The effect of stress temperature on the C-V behavior is shown in figure 57. Changes in both bulk CdTe, SCR and CdS were observed for 70oC stressing. There is a gradual reduction in NA at reverse bias (~1.4E14 to 4.9E13) over time. The shift in linear dark J-V to the right with thermal stress suggests photodoping of CdS by Cu related defects. The gradual increase in Rs for light J-V suggests increase in bulk resistivity possibly from both CdTe and CdS compensation. The SCR width changes from ~3.3m to 0.9m (NA changes from ~8E13 to 5E13) at zero bias, suggesting an increase in recombination current as seen in the ln dark J-V data. No significant collection losses were observed in the SR discussed earlier in figure 47. 9-29A-11A (700C) 1E+13 1E+14 1E+15 1E+16 -2-1.5-1-0.500.5 Bias Voltage, VAcceptor conc., NA(/cm3) initial 580 hrs 1260 hrs 3600 hrs Figure 57. NA-V in the Dark for a TS Device at 70oC Changes are more drastic when stress temperatures are higher than 90oC. As can be noted from the profile below for a device stressed at 100oC, bulk doping is close to initial values (changes from ~1.3E14 to 1.7E14) however NA drastically increases at the junction (changes from ~5.8E13 to 1.5E14). At high stress temperatures, clearly a high level of deep level defects exist at the junction and bulk. These defects contribute to the higher capacitance at both zero bias and reverse bias. This should result in signifi cant reduction in depletion width (from ~4m to
92 1m) causing an increase in collection losses. Th e spectral response in Figure 48 depicts a large drop in red region current due to these change s in the high temperature stressed devices. The increase in capacitance values with stress temp eratures can also be caused by increasing front contact barrier capacitance. Thus, the C-V data can only be used to make qualitative conclusions but may not be accurate quantitatively, as the C-V model predicts changes only to the main diode. 9-29A-10C (100oC) 1E+13 1E+14 1E+15 1E+16 -2-10 Bias Voltage, VAcceptor conc., NA(/cm3) initial 580 hrs 1260 hrs 3600 hrs Figure 58. NA-V in the Dark for a TS Device at 100oC The collection losses are most likely due to activation or creation of Cu and Cl related acceptor like defects . Large quantity of Cu was found to accumulate at the junction during device formation as shown later by SIMS analysis It had been shown to exist as an ionized interstitial (shallow donor) diffusing via GBs in to the bulk CdTe, junction and CdS bulk during the contact anneal. During the thermal stressing pr ocess, Cu can diffuse into the grains from their GBs readily substituting VCd due to its similar atomic size to Cd. CuCd acts as an acceptor like defect. This will cause an increase in doping concen tration of the CdTe layer and compensate the CdS layer. This clearly explains the increase in CdTe doping concentration especially close to the
93 junction where the highest concentration of Cu exists. The continual compensation of CdS explains the increase in dark J-V cross-over w ith time and the increase in bulk series resistance. It is postulated that the continual device de gradation during thermal stressing is due to creation and activation of acceptor-like substitu tional defects of Cu and its complexes. 5.2 Illumination Stress Illumination studies were performed in a v acuum sealed quartz tube. The setup involved cooling of illuminated devices with jets of N2 gas to maintain the cells at a desired temperature. All the devices loaded for testing were generate d from the same substrate and had high starting conversion efficiencies of 10.6-12.5%. An uns tressed witness device (9-29A-7E) from the same substrate was stored in a desiccator. Four ce lls (9-29A-7D, 9-29A-7B, 9-29A-7F, 9-29A-7C) were stressed @ Voc conditions under 1 Sun intensity for ~10 hours each day. After 850 hours, resistive loads were applied on two devices and maintained @ Vm (9-29A-7F, 9-29A-7C). After another 400 hours & 650 hours, the devi ces were brought back to stressing @ Voc (9-29A-7C & 9-29A-7F). The dark J-V and C-V measurements we re taken at room temperature. The light J-V measurements were carried out in termittently at room temperat ure under a solar simulator after the devices were allowed to cool down by the ambient N2 gas. Most cases were measured at operating temperature of 70oC during light soaking. The temperature of the devices was monitored using stick-on thermocouples glued to their back surface. The changes to key parameters are described below. 5.2.1 Effect on Open-Circuit Voltage (Voc) There was a clear reduction in Voc observed due to light soaking in all four devices. Normalized Voc reduction is shown in figure 59 for room temperature measurements. No significant reduction in Voc was observed in the unstressed sample.
94 Figure 59. Normalized Voc @ Room Temperature vs Time All four stressed samples had shown a Voc reduction of ~5%. A linear drop of ~3% was observed within the first 500 hours. The Voc was found to level off at ~1000 hours. Normalized Voc @ 70C 0.85 0.90 0.95 1.00 1.05 0500100015002000 Time, HoursNormalized Voc 9-29A-7D 9-29A-7F 9-29A-7B 9-29A-7C Figure 60. Normalized Voc @ 70oC vs Time Normalized Voc @ Rm Temp 0.90 0.92 0.94 0.96 0.98 1.00 0500100015002000 Time, HoursNormalized Vo c 9-29A-7D 9-29A-7F 9-29A-7B 9-29A-7C 9-29A-7E
95 The average Voc drop of ~ 5% was observed in the devices at 70oC as shown in figure 60. This change is tabulated in table 9 showing a reduction in Voc by 43mV. Table 9. Change in Voc at Room Temperature and 70oC No significant effect on the net Voc was observed even in the devices stressed for some time at their maximum power point, Vm. The reduction in Voc can be attributed to increase in recombination currents in the device during str essing as will be shown later in the J-V curves. Table 10. Change in Voc for Various Stress Periods ConditionNo Stress At Voc2100hrs At Voc2100hrs At Voc-850hrs, Vm-650hrs, Voc-600hrs At Voc-850hrs, Vm-400hrs, Voc 850hrs Mean Change (Lightsoak Samples) Sample#9-29A-7E9-29A-7D9-29A-7B9-29A-7F9-29A-7C Change in Voc Rm Temp ( mV ) -8-39-44-40-48-43 Change in Voc 70oC (mV) -31-58-36-49-43 Note: "+" indicates "INCREASE", "-" indicates "DECREASE" Part#Condition0-600 600-10001000-1600 1600-2114AverageTotal 9-29A-7E No Stress -7.80 9-29A-7D At Voc2100hrs -21.72-18.9110.22-8.50-9.73-38.92 9-29A-7B At Voc2100hrs -24.80-16.0117.83-21.17-11.04-44.15 9-29A-7F At Voc-850hrs, Vm-650hrs, Voc-600hrs -18.17-3.54-1.73-16.76-10.05-40.20 9-29A-7C At Voc-850hrs, Vm-400hrs, Voc-850hrs -28.260.583.86-24.56-12.10-48.38 Note: "+" indicates "INCREASE", "-" indicates "DECREASE" Stress Period, Hours
96 The breakdown of parametric change over tim e is shown in table 10. It is hard to conclude if the drop in Voc is gradual or abrupt from this tabulation as the drop in Voc at each point is so close to measurement error of 10-15mV. Figure 61. Voc @ Room Temperature and 70oC vs Time During LS @ Voc The Voc trend of a representative sample @ Voc (9-29A-7D) throughout the stressing period is shown in figure 61. It shows a linear degradation of Voc within the first 1000 hours and a subsequent leveling off both at room temperature and at 70oC. The Voc trend of a sample stressed first @ Voc for the first 850 hours, then at its maximum power point for 400 hours and then brought back to Voc for another 850 hours (9-29A-7C) is shown in figure 62. A linear drop in Voc can be seen during the first 850 hours. A sudden drop in Voc by ~15mV can be noted during its presence @ Vm (maximum power point) when current flows through the device under stress. However, the Voc still levels off following the same trend of the devices under stress at Voc. The Voc recovers by ~10mV after the device is brought back to being stressed at Voc instead of Vm. This phenomenon is most likely due to the field assisted migration of charged impurities like Cu, Cl-rela ted defects into the bulk and junction during Room Temp 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 05001000150020002500 Time, (Hours)Voc ,(V ) 9-29A-7D 3 per. Mov. Avg. (9-29A-7D) 70C 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 05001000150020002500 Time, (Hours)Voc ,(V ) 9-29A-7D 10 per. Mov. Avg. (9-29A-7D)
97 stress at Vm as there is continuous flow of current in the device, causing increased recombination losses. The recovery in Voc and FF when brought back to stressing at Voc indicates that the losses are reversible. Figure 62. Voc @ Room Temperature and 70oC vs Time During LS @ Voc, Vm and Voc The sudden drop in Voc of this device at ~1900 hours is due to increased leakage current caused by shunting observed in this device. Due to the polycrystalline nature of this junction, migration of ionic impurities and interstitial defects can form shunting paths along the grain boundaries causing sudden deterior ation in device performance. Cases where shunted devices recover over time have also been observed. This la tter drop could also be due to a local defect (some type of catastrophic event) that simply brought down the performance. Study of micrononuniformity of CdS/CdTe polycrystalline devices cl early show that small defective regions on the order of a few microns can cause a signi ficant drop in performance because they act like shunting weak diodes . Room Temp 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 05001000150020002500 Time, (Hours)Voc ,(V) 9-29A-7C 3 per. Mov. Avg. (9-29A-7C) VocVmVoc 70C 0.65 0.67 0.69 0.71 0.73 0.75 0.77 0.79 0.81 0.83 0.85 05001000150020002500 Time, (Hours)Voc ,(V) 9-29A-7C 10 per. Mov. Avg. (9-29A-7C) VocVmVoc
98 5.2.2 Effect on Fill Factor (FF) A net reduction in fill factor was observed due to light soaking. The normalized FF over time from room temperature measurements are shown in figure 63. The witness sample showed a 3% reduction in FF. Figure 63. Normalized FF @ Room Temperature vs Time An average reduction of ~5% was observed for the light soaked devices at room temperature. This reduction has occurred within the first 1000 hours. The fill factor has leveled off between 1000-2100 hours for devices stressed at Voc. The fill factor shows an abrupt increase when maintained at Vm for two devices 9-29A-7F & 9-29A-7C. As soon as the devices are returned to Voc, fill factors also drop to the previous values. Normalized FF @ Rm Temp 0.85 0.90 0.95 1.00 1.05 0500100015002000 Time, HoursNormalized F F 9-29A-7D 9-29A-7F 9-29A-7B 9-29A-7C 9-29A-7E
99 Normalized FF @ 70C 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0500100015002000 Time, HoursNormalized FF 9-29A-7D 9-29A-7B Figure 64. Normalized FF @ 70oC vs Time During LS @ Voc The normalized FF for devices maintained at Voc (9-27A-7D, 9-29A-7B) at 70oC is shown in figure 64. An interesting detail captured here that was missed in the earlier normalized plot at room temp. is the increase in FF by 3-10% during the initial 100 hours of light soaking. A linear drop was observed after this initial increase. Normalized FF @ 70C 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0500100015002000 Time, HoursNormalized FF 9-29A-7F 9-29A-7CVm startVm end Figure 65. Normalized FF @ 70oC vs Time During LS @ Voc, Vm and Voc
100 The normalized FF of the other two devices (9-29A-7F, 9-29A-7C) showed a similar trend for the first 850 hours when they were stressed at Voc. When the devices were subjected to a load keeping them at the maximum power poi nt, there was an abrupt drop in FF at 70oC. The FF also recovered over time moving towards its original value when stressed at Voc. This data at 70oC conflicts with the FF data at room temperature (figure 65), where it was observed to have shown some recovery @ Vm. This could be a result of lattice scattering in the materials at higher temperatures that will affect the carrier mobility. It could also be a result of deep level defects being active at higher temperature and inactive at room temperature changing the FF. The drop in FF is recoverable. One device (9-29A-7C) return s to its original value as soon as it is brought back to stressing at Voc. The FF of device 9-29A-7F is more uns table and takes longer to return to its original value. The increase in FF within the first 100 hours can be clearly explained by examining the Rsh @ Jsc which is a good indicator of collection losses of the devices. Figure 66 of representative sample 9-29A-7C suggests the Rsh @ Jsc exhibits a rather fast increase from about 500 to 2000 -cm2 in the first 100 hours and then app ears to steadily decrease (the data scattering observed is due to noise in the light J-V data near Jsc). This change appears to mirror the improvement observed in the FF suggesting improved collection. The increase in depletion width from C-V analysis shown later suppor ts this observation. An increase in Jo which is directly proportional to the widening of SCR was also observed . The sudden drop in FF, when a device was stressed at Vm, can also be explained by the sudden drop in Rsh @ Jsc seen below at 70oC. The Rsh @ Jsc trend at room temperature does not show this drop explaining the higher FF measured at room temperature (figure 63) during this stress period. The deep level defects are most likely activate at 70oC but not at room temperature. Since the room temperature measurement in figure 63 is taken after allowing the device to cool down and recover for at least 810 hours, this drop in FF is not observed. The decrease in Rsh @
101 Jsc suggests an increase in the collection losses possi bly due to the field assisted migration of charged impurity defects to the SCR causing it to shrink. A decrease in the leakage currents can be seen from the dark J-V curves. The degradation at Vm are reversible as observed in figure 66 when the device is brought back to light soaking at Voc. Figure 66. Normalized Rsh @ Jsc at 70oC vs Time During LS @ Voc, Vm and Voc The average reduction in absolute % of FF is ~3% at both room temperature and 70oC. The FF in a device is affected by reduction in Rsh @ Jsc (collection losses) and increase in Rs. A linear decrease in Rsh @ Jsc was observed after the initial increase for the first 100 hours which explains the drop in FF. A point to be noted from the above results is that the initial increase in FF seen here cannot be expected for all light stressed sampl es, though similar improvement in efficiency was reported by BP solar in CdTe modules . Light stress studies done on similar USF samples  have not shown this effect. 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 05001000150020002500 Time, (Hours)Rsh @ Jsc, (ohm-cm2 ) 9-29A-7C 10 p er. Mov. c
102 Table 11. Change in FF @ 25oC and 70oC for LS Devices ConditionNo Stress At Voc2100hrs At Voc2100hrs At Voc-850hrs, Vm-650hrs, Voc-600hrs At Voc-850hrs, Vm-400hrs, Voc 850hrs Mean Change (Lightsoak Samples) Sample#9-29A-7E9-29A-7D9-29A-7B9-29A-7F9-29A-7C Change in FF Rm Temp (%) -2-3-2-3-5-3 Change in FF 70C ( % ) -4-3-2-3-3 Note: "+" indicates "INCREASE", "-" indicates "DECREASE" The change in FF for light soaked devi ces as shown in table 11 decreases by ~3% irrespective of the light soaking conditions. The breakdown of this absolute FF variation over time is shown in table 12. The changes observed have already been described while discussing the normalized trend plot. Table 12. Change in FF @ 25oC over Various Stress Periods Part# Condition 0-600 600-10001000-16001600-2114Avera g eTotal 9-29A-7E No Stress -2 9-29A-7D At Voc2100hrs -4-2-13-1-3 9-29A-7B At Voc2100hrs -3-3040-2 9-29A-7F At Voc-850hrs, Vm-650hrs, Voc-600hrs -21-87-1-3 9-29A-7C At Voc-850hrs, Vm-400hrs, Voc-850hrs -32-51-1-5 Note: "+" indicates "INCREASE", "-" indicates "DECREASE" Stress Period, Hours
103 5.2.3 Effect on Short-Circuit Current Density (Jsc) Two distinct changes were observed in Jsc at room temperature and 70oC. An increasing trend was observed from room temperature measure ments for the stressed devices. No significant change was observed to the Jsc of the unstressed device. Figure 67. Normalized Jsc @ 25oC vs Time for LS Samples This observation was confirmed by spectral response (SR) measurements of the devices. SR measurements were taken only at the beginning and end of the stressing period; no SR data is available during the light soaking period. A repr esentative SR plot of device 9-29A-7D is shown in figure 68. Normalized Jsc @ Rm Temp 0.90 0.95 1.00 1.05 1.10 0500100015002000 Time, HoursNormalized Js c 9-29A-7D 9-29A-7F 9-29A-7B 9-29A-7C 9-29A-7E
104 9-29A-7D 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 400500600700800900 Wavelength, nmQ.E. 7E-no LS(initial)-23mA/cm2 7E-no LS(final)-23.1mA/cm2 7D-LS(initial)-22.5mA/cm2 7D-LS(2160 hours)-23.6mA/cm2 Figure 68. SR Comparison of Witness and LS Samples No significant change in Jsc is seen for the unstressed witness sample 9-29A-7E. The lightsoaked device shows an increase in Jsc by 1.1mA/cm2. The SR plot also shows clearly the increase in current collection in the red region. The normalized Jsc at 70oC is shown in figure 69. The sudden jump in Jsc at ~250 hours is due to a change in the light source. The gradual drop in Jsc over time is not consistent with the Jsc measurements at room temperature. This result could not be validated by high temperature SR measurements as the capability currently does not exist at USF. This observation can be an artifact caused by the aging of the light bulbs used for light soaking or it could also be due to reduced mobility of charge carriers due to lattice scattering at high temperature or activation of deep level defects at high temperature.
105 Normalized Jsc @ 70C 0.80 0.85 0.90 0.95 1.00 1.05 1.10 1.15 1.20 0500100015002000 Time, HoursNormalized Jsc 9-29A-7D 9-29A-7F 9-29A-7B 9-29A-7C Figure 69. Normalized Jsc of LS Samples at 70oC Table 13 outlines the change in Jsc observed in each of the devices at room temperature. An increase in Jsc is observed possibly due to the wi dening of SCR and improved collection shown by C-V measurements. Table 13. Change in Jsc for Control and Lightsoak Samples ConditionNo Stress At Voc2100hrs At Voc2100hrs At Voc-850hrs, Vm-650hrs, Voc-600hrs At Voc-850hrs, Vm-400hrs, Voc 850hrs Mean Change (Lightsoak Samples) Sample#9-29A-7E9-29A-7D9-29A-7B9-29A-7F9-29A-7C Change in Jsc (SR) ( mA/cm2 ) 0.11.10.51.20.70.9 Change in Jsc Rm Temp ( mA/cm2 ) 0.40.90.91.01.81.1 Note: "+" indicates "INCREASE", "-" indicates "DECREASE"
106 5.2.4 Effect on Shunt Resistance (Rsh) The normalized Rsh @ Jsc for room temperature measurements is shown in figure 70. The Rsh @ Jsc values are indicative of collection losses but cannot explain changes to leakage currents in the device as previously discussed. Thus, an increase in Rsh @ Jsc suggests improved collection of photo-generated carriers and a d ecrease suggests higher collection losses. Figure 70. Normalized Rsh @ Jsc of LS Samples at 25oC The general trend showed an initial improveme nt in collection and subsequent drop after the first 1000 hours. The data is noisy due to noise in light J-V at Jsc. The witness device also shows an improved collection possibly due to passivation of deep level defects. The normalized Rsh at 70oC is shown in figure 71 for devices at Voc. Normalized Rsh @ Rm Temp 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 0500100015002000 Time, HoursNormalized Rsh @ Js c 9-29A-7D 9-29A-7F 9-29A-7B 9-29A-7C 9-29A-7E
107 Normalized Rsh @ 70C 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0500100015002000 Time, HoursNormalized Rsh @ Jsc 9-29A-7D 9-29A-7B Figure 71. Normalized Rsh @ Jsc at 70oC of LS Samples at Voc The data shows an initial jump in Rsh @ Jsc of ~250-300% within the first 100 hours of lightsoaking. This explains the jump in FF a nd improved collection observed. Subsequently, a linear decrease is observed over time with Rsh @ Jsc values still higher than the start. This means after the initial passivation effects seen due to light soaking, there is a second slower degradation mechanism working towards increasing th e collection losses of the device. Normalized Rsh @ 70C 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0500100015002000 Time, HoursNormalized Rsh @ Jsc 9-29A-7F 9-29A-7CVm End Vm Start Figure 72. Normalized Rsh @ Jsc at 70oC of LS Samples at Voc, Vm and Voc
108 The normalized Rsh at 70oC for devices whose stress conditions was shifted to Vm from Voc after 850 hours shows a sudden drop (figure 72). Increase in deep level defects causing a reduction in SCR and increasing collection losses is the possible cause for this drop in Rsh and FF as seen from C-V behavior later. This degradati on is reversible as shown when the devices were brought back to light soaking at Voc. 5.2.5 Effect on Series Resistance (Rs) The change in series resistance at room temper ature due to stressing is shown in the table 14. Rs @ Voc and Rs at high currents show both increase and decrease for various devices. The net change is within 1 -cm2. The unstressed device showed improvement in Rs, however this does not result in an increase of FF. We can conclude from these results that the variation in Rs is minimal to cause a significant effect on the device performance. Table 14. Change in Rs for Control and Lightsoak Samples ConditionNo Stress At Voc2100hrs At Voc2100hrs At Voc-850hrs, Vm-650hrs, Voc-600hrs At Voc-850hrs, Vm-400hrs, Voc 850hrs Mean Change (Lightsoak Samples) Sample#9-29A-7E9-29A-7D9-29A-7B9-29A-7F9-29A-7C Change in Rs @ Voc (ohmcm2 ) -0.850.030.500.000.180.18 Change in Rs @ High Current (ohmcm2 ) -0.55-0.350.52-0.030.160.08 Note: "-" indicates "INCREASE", "+" indicates "DECREASE"
109 5.2.6 Diode Quality Factor, A & Reverse Saturation Current Density, Jo These two parameters can be deduced from the dark J-V curves for normal devices as shown in table 15. Table 15. Change in A and Jo for Control and Lightsoak Samples An increase in Jo & A is observed causing degradation in Voc & FF. The Jo values extrapolated from slope of dark ln J-V plots @ 0.35-0.55V are good qualitative indicators but not accurate quantitatively. Though the projected ta bulation for 9-29A-7B shows a reduction of Jo after stressing, the ln dark J-V plot shows a defin ite increase in recombination current after stress. In devices with high recombination currents, when A is deduced from dark J-V at low forward bias, unrealistic numbers above a typical of 1-2 are observed along with higher Jo. Stress Condition No Stress At Voc2100hrs At Voc2100hrs At Voc-850hrs, Vm-650hrs, Voc-600hrs At Voc-850hrs, Vm-400hrs, Voc 850hrs Sample#9-29A-7E9-29A-7D9-29A-7B9-29A-7F9-29A-7C A-initial1.91 1.562.112.30 2.20 A-final2.28 2.811.602.40 2.20 Chan g e in A0.381.25-0.510.100.00 Jo-initial 2.03E-092.76E-111.38E-081.01E-08 6.73E-08 Jo-final 3.62E-073.41E-084.74E-099.57E-084.55E-08 Chan g e in Jo x 100x 1000x 10x 9x 2 Note: "+" indicates "INCREASE", "-" indicates "DECREASE"
110 5.2.7 Dark J-V Analysis The dark J-V curves for a witness device are shown in figure 73. Figure 73. Ln(J)-V and Linear J-V in the Dark for Witness Device Stored @ Room Temperature From the ln J-V plot, an increase in the r ecombination current was observed despite being under no stress. This is not due to shunting as no significant change to light J-V was observed. The increase in recombination current is due to increase in SCR possible due to CdTe compensation as seen in the C-V analysis shown late r. An increase in the series resistance is also observed from the linear dark J-V response. The dark J-V curves of a device stressed at Voc is shown in figure 74. The ln J-V curve clearly showed higher recombination current w ith time. The increase in recombination current should result in drop of Voc over time as already observed. The linear J-V curve in the dark had shifted to the left. The turn-on of initial JV was higher than what one would expect from an ideal CdTe device. This turn-on behavior has been previously explained by Dan Oman  as coming from the CdS/SnO2 interface acting as a blocking diode against the main junction. This results in the dark J-V turning ON after the breakdown of this bl ocking diode at voltages 7E (dark JV) 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 0.0001 0.001 0.01 0.1 1 00.20.40.60.811.21.4 Voltage, (V)ln(dark J) start finish 7E (dark JV)0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 00.20.40.60.811.21.4 Voltage, (V)Current Density, (A/cm2 start finish
111 higher than Voc of the device, resulting in the crossover of dark and light I-V. Thus, the shift suggests a reduction of this barrier which can occu r: 1) if the CdS doping is enhanced 2) if the barrier can be overcome by tunneling mechanisms SIMS analysis of lightsoaked devices have shown large accumulation of Cu in CdS in qua ntities higher than during thermal stress . Figure 74. Ln(J)-V and Linear J-V in Dark of LS Device at Voc This is due to the diffusion of Cu ions into the bulk CdTe, CdS and junction. GB diffusion of Cu ions is known to be the dominant mechanism. Thus Cu interstitial accumulation will increase the CdS doping, as it acts as a shallo w donor. Another possibility is that Cu could exist as a substitutional impurity compensating CdS initia lly. This explains the shift of J-V to the right initially. Upon light soaking, the Cu could possibly convert to an interstitial impurity species reducing the CdS compensation. This can explain the shift in dark J-V to the left within the first 100 hours of light soaking. A device stressed at Voc for 850 hours, then at Vm for 400 hours and returned back to Voc for the remaining 850 hours is shown in figure 75. From the ln J-V curve below it can be noted 7D (dark JV) 1E-11 1E-09 1E-07 1E-05 0.001 0.1 10 00.20.40.60.811.21.4 Voltage, (V)ln(dark J) start 600 hrs 1000 hrs 1492 hrs 2114 hrs 7D (dark JV) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 0.18 0.2 00.20.40.60.811.21.4 Voltage, (V)Current Density, (A/cm2 ) start 600 hrs 1000 hrs 1492 hrs 2114 hrs
112 that this device was shunted initially with high l eakage currents. The start of lightsoak stressing had resulted in a recovery of this device and a reduction in the leakage current possibly due to localized defect rearrangement. However this recovery was not permanent and the device was shunted again towards the end. The linear dark J-V curve showed a very interesting behavior. First, a decrease in slope was observed by light soaking due to reduction in Rs reducing dark & light J-V cross-over. Figure 75. Ln(J)-V and Linear J-V in the Dark for LS Device at Voc, Vm and Voc However, when the device is maintained at Vm with current flowing in the device under load, the Rs increases and shifts the curv e to the right again. An immediate recovery from this effect is seen when the device is brought back to stressing under Voc. The Rs variation is possibly due to Cu related defect morphing in Cd S. Initially and during light soaking at Vm, Cu related defects possibly compensate CdS, increasing its Rs. During light soaking at Voc, reduction in CdS compensation occurs possibly due to Cu related interstitial defects. 7C (dark JV) 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 0.0001 0.001 0.01 0.1 1 00.20.40.60.811.21.4 Voltage, (V)ln(dark J) start 600 hrs 1000 hrs 1492 hrs 2114 hrs 7C (dark JV) 0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 0.16 00.20.40.60.811.21.4 Voltage, (V)Current Density, (A/cm2 ) start 600 hrs 1000 hrs 1492 hrs 2114 hrs c
113 5.2.8 Light J-V Analysis From this J-V curve of the witness device (figure 76), no significant changes in Voc & FF can be seen. A small increase in Rs was observed from both the dark and light J-V, but no significant change in performance was seen. Figure 76. Light J-V of a Witness Device Stored at Room Temperature Figure 77. Light J-V of a LS Device @ Voc 7E @ rm temp -0.05 0 0.05 0.1 0.15 0.2 -0.500.511.52 Voltage, (V)Current Density, (A/cm2 ) start finish start(D) finish(D) 7D @ rm temp -0.05 0 0.05 0.1 0.15 0.2 -0.500.511.52 Voltage, (V)Current Density, (A/cm2 ) 0 0(D) 2114(D) 2114
114 The Light J-V curve at room temperature for a representative light soaked device is shown in figure 77.Along with the decrease in Voc and FF, the elimination of cross-over for light and dark J-V is the most significant observation. Th e cross-over behavior is usually attributed to a barrier present at the front of the device ( CdTe/CdS or SnO2/CdS interface) . Lightsoaking has shown to reduce or eliminate this barrier due to reduction in photoconductivity of CdS by saturation with Cu related inters titial donors. Two key observations to be made from the light J-V curves are the absence of : 1) a kink in the fourth quadrant 2) roll-over of J-V in the first quadrant Both these phenomenon indicate degradation of th e back contact resulting in blocking contact formation. Thus, it is fair to conclude that no significant degradation in back contact was observed due to illumination stressing in CdTe devices fabricated at USF. 5.2.9 Capacitance-Voltage Measurements (C-V) By plotting NA vs bias voltage applied to measure capacitance for the control sample, changes in NA can be observed even without any stressing (figure 78). A reduction in NA can be observed even without stress possibly due to dopant diffusion along GBs and compensation of CdTe, junction and CdS. This results in increasing the width of the SCR.
115 Acceptor Conc. vs Bias 9-29A-7E 1E+13 1E+14 1E+15 1E+16 -2-1.5-1-0.500.5 Bias Voltage, VAcceptor conc., NA(/cm3) start Final Figure 78. NA-V in the Dark for a Witness Device Light soaking was found to increase the widt h of SCR possibly due to compensation. Significant decrease in capacitance is observed on al l devices after the start of light soaking. All devices show a drop in NA. The presence of a graded bulk in observed with the drop in carrier concentration towards the interface. A plot of the NA w.r.t bias voltage deduced from the C-V data of a representative device subjected to lightsoaking @ Voc (figure 79) clearly explains the observations. Much of the change in acceptor con centration at the junction occurs right at the beginning of the stressing period. As illuminati on reduces the barrier for diffusion of Cu ions from the back contact, significant diffusion occurs in to the junction and into CdS layers probably resulting in compensating effects. This can explain the reduction in junction capacitance. Under reverse bias the SCR extends further into CdTe. Thus, the profile in the reverse bias shows the doping in bulk CdTe. An increase in the grad ed doping profile for CdTe is observed due to possible compensation of CdTe near the juncti on. Cu diffusion does not significantly reduce the
116 amount of Cu in the back contact of HgTe:C u doped graphite paste used in USF devices as observed from the SIMS analysis shown later and reported by others . 9-29A-7D 1E+13 1E+14 1E+15 1E+16 -2-1.5-1-0.500.5 Bias Voltage, VAcceptor conc., NA(/cm3) initial 600 hrs 1000 hrs 1492 hrs 2000 hrs Figure 79. NA-V in the Dark for a LS Device @ Voc Significant changes are noted in the de vices when they were under load at Vm. Large increase in capacitance for cells 7F & 7C when being stressed at Vm was observed suggesting an increase in charged states at the junction interface. Thus higher interface states due to diffusion or possible field-assisted migration of Cu through grain boundaries or formation of Cu related metastable states towards the junction increasing th e capacitance. The drastic change in FF could be explained by these species acting as recombin ation centers. However, it was observed that these changes are reversible. The FF was completely recovered when the device was taken back to light soaking at Voc conditions. Voc degradation was observed to be permanent and no recovery was observed.
117 The acceptor concentration and depletion widt hs deduced from C-V curves are shown in table 16. NA does not significantly change in the bulk of CdTe. However, NA at zero bias shows the doping profile near the junction reduces by an order of magnitude. The widths of SCR can be deduced from the capacitance values and we see an increase in the zero bias depletion width due to reduction in capacitance. Table 16. NA and Depletion Width of Witness and Lightsoak Samples 5.3 SIMS Analysis of Thermal Stress Devices The elemental analysis of degraded devi ces by SIMS analysis helps understand the possible root cause of device degradation. Studi es have already identified two possible species most likely responsible for the parametric changes, Cu and Cl. The profile in figure 80 is the Cu and Cl profiles in devices which were stressed without any contacts for 1500 hours at 70oC and ConditionPart#Test time Acceptor Conc. (cm-3) from Slope Depletion Width, um @ 0V Acceptor Conc. (cm-3) @ 0V No StressWitnessStart3.38E+141.222.02E+14 Finish7.51E+131.763.55E+13 At Voc2100hrs 9-29A-7DStart2.22E+141.291.76E+14 2000 hrs2.14E+142.693.90E+13 At Voc2100hrs 9-29A-7BStart2.47E+141.411.52E+14 2000 hrs1.18E+142.491.85E+13 At Voc-850hrs, Vm-650hrs, Voc-600hrs 9-29A-7FStart2.23E+141.421.38E+14 2000 hrs2.22E+142.933.55E+13 At Voc-850hrs, Vm-400hrs, Voc-850hrs 9-29A-7CStart2.54E+141.311.81E+14 2000 hrs1.57E+143.352.17E+13
118 100oC. Minimal levels of Cu are found in the bulk Cd Te. However, high levels of Cu at the CdTe surface and CdS/SnO2 layers for devices with no intentional Cu doping of these substrates are to be noted. This means that a substantial amount of Cu in the device accumulates due to contamination from various starting materials and fa brication processes. It is not clear if the Cu levels at the top surface of CdTe are real or an ar tifact of SIMS analysis and needs to be verified. If it is real, it can be deduced that Cu contamination accumulates at the two regions of highest defectivity namely the oxidized CdTe top layer and CdS/CdTe interface. The profiles are similar to non-contacted substrates analyzed without an y thermal stressing. Samples contacted after thermal stressing for 1500 hours has shown simila r device parameters as a newly made device, which clearly shows that probably the root cause of degradation is Cu is initially present in the contact. Cl levels are relatively higher in th e bulk though accumulation occurs at the front and back similar to Cu due to CdCl2 treatment of the substrates. Substrate A 1 10 100 1000 10000 0246810 Depth, umCount, c/s Cu-70C Cu-100C Cl-70C Cl-100C Figure 80. SIMS Analysis of Non-contacted Substrates Thermally Stressed to 1500 Hours
119 Profiles of Cl distribution for both contacted & non-contacted devices are very similar in content and distribution in the device. Profiles of contacted devices before and after stress can be seen in figure 81. Concentration reduces an order of magnitude towards the back-contact but no significant changes were observed in the devices with thermal stress. Cl profile 1 10 100 1000 10000 01234567 Depth(um)Secondary Ion Counts control 70C_1539 hours 100C_1539 hours Figure 81. SIMS Comparison of Cl Content Before and After Thermal Stress The profile in figure 82 shows Cu distributio n in a contacted sample with no stressing and two uncontacted samples stressed at 70oC and 100oC. Cu levels are higher in the bulk and an order of magnitude higher at the junction for the contacted sample verifying that Cu from the back contact diffuses into the CdTe and r eaches the CdTe/CdS junction and the CdS.
120 Cu profile 1 10 100 1000 10000 0246810 Depth(um)Secondary Ion Counts contacted-control uncontacted-A(70C) uncontacted-A(100C) Figure 82. SIMS Comparison of Cu Content Before and After Contacting The effect of thermal stress can be seen in the Cu profile in figure 83. Comparison with an unstressed control sample shows higher levels of Cu in the bulk CdTe towards the junction and at the junction for both 70oC and 100oC stressed samples. Note that the Cu levels at the front of CdTe have not significantly redu ced which could explain why we see no roll-over effect on the stressed devices.
121 Cu profile 1 10 100 1000 10000 02468 Depth(um)Secondary Ion Counts control 70C_1539 hours 100C_1539 hours Figure 83. SIMS Comparison of Cu Content Before and After Thermal Stress Comparison of Cu distribution at the junction for a non-contacted (figure 84) vs contacted device (figure 85) shows a distinct difference. Cu contamination in the non-contacted sample accumulates at CdS/SnO2 interface and in the SnO2 and not the CdTe/CdS junction. This result is questionable and may actually be an artifact as Cu diffusion into SnO2 is unlikely. The high level of Cu in the front of CdTe surface also needs to be confirmed. The levels of Cu increase by an order of ma gnitude after contact application and anneal which redistributes the Cu into the junction.
122 Noncontacted Substrate 1 10 100 1000 10000 100000 1000000 0246810 Depth(um)Count(c/s) 32 S 35 Cl 63 Cu 111 Cd 119 Sn 125 Te Figure 84. SIMS Analysis of Non-contacted Sample 3-15A-3B(Control) 1 10 100 1000 10000 100000 1000000 012345678 Depth(um)Count(c/s) 32 S 35 Cl 63 Cu 111 Cd 119 Sn 125 Te Figure 85. SIMS Analysis of a Contacted Sample
123 5.4 Effect of Re-contacting Thermal Stress Samples A device thermally stressed at 700C for ~ 3000 hours was re-contacted after stripping the existing contact by sonication in acetone. This was a device on which thermal stressing studies were initiated. It was annealed at 700C in incremental steps of 1, 2, 4, 8 hours and so on. This resulted in the device being tested ~250 times during its 3000 hours anneal. The CdTe layer was re-contacted with graphite paste (Cu : HgTe dope d) after preparing the top surface of CdTe by etching in Br2/methanol solution to leave a Te rich surf ace. The changes to device parameters are tabulated in table 17. Table 17. Effect of Re-contacting on Device Parameters Jsc(A/cm2)Voc (V)FFEff.(%)Rsh @ Jsc(ohms) initial0.02110.85840.70312.74923 2990 hours0.02210.82180.4257.71522.3 recontacted0.02090.68600.5097.31513.6 A significant reduction in Voc was noted after re-contacting due to shunting and increased leakage losses in the junction, however the FF has shown improvement. A significant reduction in Jsc was also observed possibly due to increase in recombination losses. Increased shunting is clearly noted from the ln J-V curve (figure 86) in the dark after recontacting. The dark J-V curve shows an inter esting phenomenon of shifting of the knee to the left reducing the light and dark J-V cross-ove r. This is similar to the observations under illumination stressing. This could explain the elim ination of cross-over be havior for lightsoaked devices. Higher Cu diffusion during illumination or re-contact annealing into the junction and CdS could explain the elimination of cross-ove r behavior. High Cu content was found in lightstressed devices compared to thermally str essed devices most significantly in CdS . Reduction in cross-over was also observed. The light J-V curve of this device (figure 87) demonstrates two key changes. Thermal stressing ha d significantly reduced the FF of this device
124 as seen from the high Rs @ Voc along with an onset of a kink in the fourth quadrant usually attributed to back contact degradation. Figure 86. Ln(J)-V and Linear J-V in the Dark for Re-contacted Device Figure 87. Light J-V for Re-contacted Device 70oC(3-12A-4A) 1E-10 1E-09 1E-08 1E-07 1E-06 1E-05 0.0001 0.001 0.01 0.1 1 00.20.40.60.811.21.4 Voltage, (V)ln(dark J) start 3000 hrs recontact 70oC(3-12A-4A) 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 00.20.40.60.818.104.22.168.82 Voltage, (V)Current Density, (A/cm2 ) start 3000 hrs recontact 70oC(3-12A-4A) -0.04 -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 00.20.40.60.822.214.171.124.82 Voltage, (V)Current Density, (A/cm2 ) start 3000 hrs recontact
125 Significant physical deterioration of back contact due to probing ~250 times and electronic degradation (oxide barrier formation) due to exposure to atmosphere and humidity every time it was tested, was thought to be the root cause. Both Rs @ Voc and Rs @ high forward currents are improved on recontacting the back surface. Significant drop in Voc and Jsc are observed due to shunting and increase in leakage losses due to Cu accumulation. Recontacting of the device has not resulted in any improvement of device efficiency meaning junction losses are most likely non-reversible. 5.5 Comparison of Thermal Stress & Light Soak Results The comparison of various device parameters of representative samples after 2100 hrs of stressing under illumination and thermal stress in the dark at 70oC are tabulated in table 18. Positive values represent increas e in parametrics and negative values indicate a decrease. Table 18. Device Parameter Comparison Parameter Thermal Stress (9-29A-11A) LS (Rm) (9-29A-7D) LS (70oC) (9-29A-7D) Jsc (mA/cm2) -0.15 0.87 -1.15 Voc (mV) -14 -40 -31 FF (%) -4.5 -3.5 -3.8 (%) -1.0 -0.6 -1.5 The drop in Voc is higher when stressed under illuminati on. This is possibly the effect of increase in Cu levels at the junction as explained previously. The drop in Jsc under illumination at 70oC could not be verified by high temperature SR and could possibly be a result of aging of
126 the bulbs used for LS. The reduction of carrier mobility due to lattice scattering or collection losses due to active recombination centers at 70oC could also possibly result in the decrease in Jsc. The worst effects of degradation are obviously for device operation at 70oC with a net reduction of ~10-27% in efficiency after 2100 hours of illumination stressing. Comparing the dark & light J-V curves (figure 88), we do not see any significant change between the lightsoaked device and thermal stressed device except for a higher drop in Voc. Both devices show a small increase in Rs both at high current and at Voc. The dark J-V cross-over however is distinctly different for both with cr oss-over nearly eliminated after illumination stress and increasing for thermally stressed device. The dark to light J-V cross-over is more than 0.8V for a thermally stressed device as shown in figure 88. To understand this cross-over phenomenon better, J-V analysis under band pass filters of 460nm, 640nm, 800nm and light J-V were performe d. Illumination with various filters has reduced the cross-over, with 460nm filter reduci ng it most followed by 640nm and 800nm (figure 89). With SnO2 bandgap of 3.5eV(360nm) and CdS ba ndgap of 2.42eV(510nm), most of the 460nm blue light should be absorbed in the CdS with some light reaching CdTe if the CdS if very thin. This results in the reduction of the Rsh of this front contact leaky diode (photodoping of CdS). Thus the J-V under this filter shows reducti on in crossover as previously proposed by Dan Oman . Both red light filte rs 640nm and 800nm show higher cr ossover. This confirms the presence of a front contact barrier dependent cr ossover phenomenon. The parametric summary of band pass filter testing can only provi de qualitative information, as th e intensity of incident light for each filter was not constant. But since the irra diance of blue light is lower compared to red light for AM1.5 light spectrum, it means significantly lower levels of blue light photons could successfully reduce the front contact barrier compared to the higher levels of red light. This confirms that the cross-over effect is due to phot odoping of CdS. The general trend of low FF for higher wavelengths was observed (figure 90). The low FF of red light signifies collection losses
127 in the bulk CdTe due to thermal stressing with lif etime of the carriers generated in the CdTe bulk lost to recombination before reaching the depletion region. Figure 88. J-V Comparison of LS and TS Device at 70oC Illumination 70oC -0.05 0 0.05 0.1 0.15 0.2 -0.500.511.52 Voltage, (V)Current Density, (A/cm2 ) 0 0(D) 2114(D) 2114 Thermal 70oC -0.05 0 0.05 0.1 0.15 0.2 -0.500.511.52 Voltage, (V)Current Density, (A/cm2 ) 0 0(D) 2000(D) 2000
128 Figure 89. J-V Comparison of TS Device Under Band Pass Filters Figure 90. FF Variation of TS Devi ce Under Various Band Pass Filters J-V with filters (thermally stressed) -0.02 0.00 0.02 0.04 0.06 0.08 0.10 0.12 0.14 0.16 -0.500.511.52 Voltage, VoltsCurrent Density, (A/cm2 ) 460nm 640nm 800nm light dark Thermal Stressed Device 0.40 0.45 0.50 0.55 0.60 0.65 0.70 350nm460nm640nm800nmLight Wavelength, nmFF, % FF
129 The dark J-V response of a lightsoaked de vice under various filters shows no significant crossover from dark to light and by use of any filters (figure 91). Figure 91. J-V Comparison of LS Device Under Band Pass Filters Figure 92. FF Variation of LS De vice Under Various Band Pass Filters J-V with Filter (Light Soaked) -0.05 0.00 0.05 0.10 0.15 0.20 -0.500.511.5 Voltage, VCurrent Density, (A/cm2 ) 460nm 640nm dark 800nm light Illumination Stressed Device 0.60 0.62 0.64 0.66 0.68 0.70 0.72 0.74 350nm460nm520nm640nm800nmLight Wavelength, nmFF, % FF
130 The change in FF under the filters is show n in figure 92. No significant change is observed for all the filters. The small fluctuations observed are due to light intensity dependence of FF. The lowest FF measured was for observe d for light J-V under the solar simulator under AM1.5 conditions. 5.6 Acceleration Factor for Thermal Stress A reduction of Voc and FF with increasing temperature of thermal stressing was observed. An Arrhenius rate relationship can be used to determine the acceleration factor (a) for this degradation. We used the average drop in Voc and FF for 3 devices at each temperature of stressing. With the assumption that normal operating conditions for a device is 50oC, the above an acceleration factor of ~ 5 is deduced at 100oC. Table 19. Acceleration Factor for Degradation of Voc and FF Stress Tem p erature, oC a,Voc(mV) a,FF(%) 5011 601.41.4 701.91.8 802.52.4 903.23.2 1004.14.1 1206.66.5 The acceleration factors deduced above in table 19 are by no means statistically complete. Statistically significant sample sizes have to be evaluated in the future to generate accurate degradation factors. We could also po ssibly generate two acceleration factors one to represent the first 1000 hours of rapid degradati on and the second to represent the remaining 1600 hours of gradual degradation.
131 5.7 Simulation We have simulated the Voc and FF respon ses using the diode light I-V equation: J = Jo[e(V-JRs)/AkT 1] JL + (V-JRs)/Rsh The values of JL, Rs, Rsh deduced from the light J-V curves and A, Jo values deduced from the dark J-V curves before and after stressing de vices were used to simulate the response. Table 20. Comparison of Voc and FF Before and After Degradation It can be seen from the data in table 20 that a reasonable estimate of the Voc and FF can be deduced before stressing. Extraction of device parameters such as A, Jo, Rsh, and Rs for stressed devices is not accurate and therefore qua ntitative analysis becomes difficult. However, the results presented in this work, clearly dem onstrate that even the qualitative changes can be used to study degradation in CdTe cells. 5.8 Summary Both thermal and illumination stressing have resulted in degradation of devices. When comparing samples stressed at 70oC both thermally and under illumination, similar levels of Stress Hours Voc, V (meas) Voc,V (sim) Voc Change, V ( meas-sim ) FF, % (meas) FF, % (sim) FF Change, % (meassim ) Anneal-70oC 00.8460.8370.00973.175.3-2.2 36000.8310.8220.00967.972.3 -4.4 Anneal-100oC 00.8360.8140.02273.776.6-2.9 36000.8061.007-0.20153.955.2 -1.3 Anneal-120oC 00.8480.8280.0273.574.7-1.2 36000.7761.12-0.34444.332.9 11.4 Illumination 70oC 00.840.820.0272.476.7-4.3 21000.8010.7810.0268.970 -1.1 Note: "+" indicates "INCREASE", "-" indicates "DECREASE"
132 degradation in efficiency were observed from room temperature J-V measurements. The major difference in parametric changes between the tw o conditions has been that illumination stressing has higher reduction in Voc along with increase in Jsc (SR analysis) compared to thermal stressing. SIMS analysis has shown that higher accumulation of Cu occurs at the junction and CdS for illumination stress compared to thermal stress conditions . The key difference is how the Cu exists at the CdTe/CdS junction, bulk CdTe, bulk CdS and CdS/SnO2 interface. If Cu exists as an interstitial defect Cui +, it is a shallow donor state enhancing CdS doping and compensating CdTe. If Cu exists as a substitutional defect, CuCd is a deep-level acceptor e nhancing CdTe doping and compensating CdS. Cu diffusion from back contact into the bulk CdTe and accumulation at the junction and CdS has been well documented . It exists pr edominantly as an interstitial after fabrication diffusing via GBs during contact anneal . 1. Light soaking @ Voc enhances the diffusion of Cui + from the back contact into the junction and CdS via GB diffusion . GB diffusion being a fast process occurs within 100 hours of lightsoaking. This reduces the net NA in CdTe and increases the net ND in CdS. Increase in depletion width from CV analysis, improved collection from SR analysis and improved FF from J-V analys is in LS devices support this observation within 100 hours. This is also accompanie d by an increase in recombination current resulting in a rapid drop in Voc in the first 1000 hours. Deep level defect formation of Cui + and related complexes at the junction possibly form this fast component of degradation. 2. Thermal stressing @ Voc is believed to enhance Cu -related substitutional defect formation. However, the fast initial drop in performance within 500 hours is believed to be due to the formation of Cu-related deep le vel defects similar to LS at the junction and increases with stress temperature. The eviden ce of increase in recombination currents is
133 found in the dark J-V analysis. Collection losses were found to increase with stress temperature as shown in the SR analysis. The levels of Cu accumulation at the junction and CdS for thermal stress are lower than during LS . Thus, the doping concentration of CdS is not significantly altered to change the depletion width. A slower substitutional defect formation is propo sed to exist for both light soaking and thermal stress. Deep level Cu and Cl defect complexes or clusters possibly form at the junction and CdS. This will compensate CdS and increase its photoconductivity/resistivity. The continuous degradation of Voc and FF both for lightsoaking and thermal stressing over time is possibly a result of enhanced substitutional defect formation. This degradation appears to be permanent. Higher temperatures of thermal stressing increase these defects. The high recombination losses and shunting observed in devices stressed over 100oC along with reduction in depletion widths corroborate this theory. Saturation or overdoping of Cu in CdS can lead to: 1. Reduction of the front contact barrier due to higher ND of CdS. 2. Formation of shunt paths for carriers to tunnel through the CdS/SnO2 interface barrier. This explains the elimination or reduction of cr ossover observed during illumination stressing or recontacting thermal stressed devices. However, if Cu substitutes Cd in CdS, which means Cu has to enter the CdS grains and form a deep accepto r, it will compensate the net CdS doping resulting in photoconductive/resistive CdS. This occurs gradually during thermal degradation over time, increasing dark vs light J-V cross-over due to higher front contact barrier. Front-contact barrier changes observed at th e two stress conditions due to photodoping changes of CdS by Cu is proposed to have minimal impact on device degradation. This conclusion can be drawn based on: 1. The varying levels of cross-over observed in high efficiency CdTe devices fabricated at USF.
134 2. From the fact that elimination of cross-over has not stopped the light stressed devices from further degradation. The drop in FF accompanied by drop in Rsh @ Jsc for cells at Vm and increase in J-V cross-over suggests the diffusion or possible field assisted migration of charged Cu ions and their defect complexes at the junction and CdS. These defects can act as traps, deep states and form shunt paths along the GBs causing degradation of the junction. Increased capacitance during stress @ Vm supports the presence or creation of the interface states. These changes have been found to be reversible. Re-stressing the devices at Voc shows immediate recovery of FF and J-V cross-over. Thus, the front-contact barrier changes are suggestiv e of the diffusion and migration of Cu ions and its defect states. The absence of significant roll-over for bot h stress mechanisms signifies back contact integrity with no significant back contact barrier formation. Severe physical degradation and possible oxidation of back contact in the origina l thermal stressed device (figure 88) had shown the presence of back contact barrier. It can be concluded that degradation of CdTe/CdS devices fabricated at USF mainly occurs at the junction and not at the back cont act. DLTS analysis on USF samples had identified the presence of various deep level defects pe rtaining to Cu and its complexes  like Cui +, CuCd -, (Cui+ 2CuCd -)along with other defects associated with VCd complexes. Increase in these defect levels are the root cause of junction degradation. It is necessary to quantify these defect levels in stressed devices in the future using simulation tools and better characterization methods.
135CHAPTER 6 CONCLUSIONS Both thermal and illumination stressing have resulted in degradation of devices. Two components of degradation were observed. The f aster degradation component is seen both during thermal and illumination stressing. Cu interstitial diffusion from the backcontacts and their defect complexes contribute to the fast drop in Voc and FF. As the concentra tion of Cu interstitials are higher due to lightsoaking than thermal degradation , the performance drop is higher for lightsoaking than thermal stress. A slower component of degradation is also present that causes continual reduction in performance of the device. Substitutional defects and complexes of Cu in the junction and CdS are attributed to this de gradation and the resulting parametric loss was found to be irreversible. As both interstitial and substitutional defects exist in varying concentrations after stressing, different levels of degradation are observed for thermal stress and lightsoaking. It was concluded that degrad ation of CdTe/CdS devices fabricated at USF mainly occurs at the junction and not at the contact. DLTS an alysis on USF samples has identified the presence of various deep level defects pertaining to Cu and its complexes  like Cui +, CuCd -, (Cui + 2CuCd -)along with other defects associated with VCd complexes. Increase in these defect levels is possibly the root cause of junction degradation. It is necessary to quantify these defect levels in stressed devices in the future. Large statistically valid sample sizes have to be subjected to thermal and lightsoak stress to quantify the parametric losses a nd calculate acceleration factors. This will enable modeling of
136the performance degradation. Bias stressing studies are required to further understand the field enhanced migration of defects. DLTS studies of stressed samples are required to identify and quantify the deep-level defects. Techniques to reduce junction degradation have to be investigated. It may be possible to optimize the quantity of Cu penetrating the junction in high efficiency CdTe/CdS solar cells to prevent de gradation. Passivating th e junction defects could reduce rate of degradation and has to be investigated. Alternative stable Cu free back contacts can also be developed to prevent the junction degradation.
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ABOUT THE AUTHOR Bhaskar Reddy Tetali received his Bachelors Degree in Electronics and Communication Engineering from Andhra University, Visakhapatn am, A.P, India in 1994 and M.S. in Electrical Engineering in 1996 from the University of South Florida (USF). He has been associated with the Compound Semiconductor Laboratory (CSL) at USF since 1994 and his research has focused on development of CdTe/CdS thin film solar cel ls. His Masters work involved optimizing CdTe/CdS device performance on soda-lime substrates. He had successfully fabricated devices with >13% conversion efficiencies on low-cost s ubstrates (Highest efficiency of 13.6% achieved on a device tested at NREL A record efficiency at that time). The focus of his dissertation has been on studying and understanding the stability of CdTe/CdS solar cells and identifying the degradation mechanisms. This will help develop solutions to increase the lifetime of CdTe/CdS solar cells and make this thin film technology fina ncially viable for terrestrial applications as an alternative source of renewable energy. He has worked both as a Research Assistant (RA) with CSL and Teaching Assistant (TA) with the Electrical Engineering Department. His TA experience includes teaching Electronics Lab, Logic Lab, Microprocessor Lab, Electrical Circuits, Linear Systems Analysis, RF Microwave Circuits and Linear Control Systems. He was selected into the reputed Worldwi de Rotation Program as a Rotation Engineer at International Rectifier (IR) in 2001. He is cu rrently with the Advanced Technologies Division (FET R&D) of IR working as a Design Engi neer involved in designing power MOSFETs for Automotive and DC-DC applications.