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Implant annealing of al dopants in silicon carbide using silane overpressure

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Implant annealing of al dopants in silicon carbide using silane overpressure
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Rao, Shailaja. P
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Silicon carbide
Post-implantation annealing
Aluminum implant
Dissertations, Academic -- Electrical Engineering -- Doctoral -- USF   ( lcsh )
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theses   ( marcgt )
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Summary:
ABSTRACT: The goal of this research is to develop a post-implantation annealing process in silicon carbide (SiC). Due to the low diffusivities of dopants in SiC, even at temperatures in excess of 2000ʻC, diffusion is not a suitable process to achieve selective, planar doping. Ion implantation is therefore the most suitable means for achieving selective doping in SiC crystals. The strong covalent bonding in SiC requires that selective doping be performed via high-energy ion implantation. As a consequence of the high ion energy and flux, there is considerable lattice damage to the crystal surface. To repair the damage caused by the implantation, as well as to electrically activate the dopants, it is important to perform post-implantation thermal annealing at temperatures greater than 1600ʻC. However annealing at such high temperatures decomposes the SiC crystal surface due to the selective out-diffusion of Si causing surface morphology degradation.In this research two processes, both using a silane-based SiC CVD reactor, have been realized to minimize the evaporation of Si. This is accomplished by providing Si overpressure above the wafer surface during annealing thus suppressing the evaporation of Si from the lattice. Post-implantation anneals were performed in both hot-wall and cold-wall silane-based chemical vapor deposition (CVD) reactors. For each process temperature developed, silane was added to a stream of Ar in such a concentration such that the suppression of step-bunching, a well known phenomenon caused by the evaporation of Si at the surface, was achieved. The surfaces were studied after annealing via plan-view secondary electron microscopy (SEM) and atomic force microscopy (AFM). The resulting surface morphology was found to be both step-free and smooth.
Thesis:
Thesis (Ph.D.)--University of South Florida, 2005.
Bibliography:
Includes bibliographical references.
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by Shailaja P. Rao.
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Title from PDF of title page.
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Document formatted into pages; contains 136 pages.
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Includes vita.

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ABSTRACT: The goal of this research is to develop a post-implantation annealing process in silicon carbide (SiC). Due to the low diffusivities of dopants in SiC, even at temperatures in excess of 2000C, diffusion is not a suitable process to achieve selective, planar doping. Ion implantation is therefore the most suitable means for achieving selective doping in SiC crystals. The strong covalent bonding in SiC requires that selective doping be performed via high-energy ion implantation. As a consequence of the high ion energy and flux, there is considerable lattice damage to the crystal surface. To repair the damage caused by the implantation, as well as to electrically activate the dopants, it is important to perform post-implantation thermal annealing at temperatures greater than 1600C. However annealing at such high temperatures decomposes the SiC crystal surface due to the selective out-diffusion of Si causing surface morphology degradation.In this research two processes, both using a silane-based SiC CVD reactor, have been realized to minimize the evaporation of Si. This is accomplished by providing Si overpressure above the wafer surface during annealing thus suppressing the evaporation of Si from the lattice. Post-implantation anneals were performed in both hot-wall and cold-wall silane-based chemical vapor deposition (CVD) reactors. For each process temperature developed, silane was added to a stream of Ar in such a concentration such that the suppression of step-bunching, a well known phenomenon caused by the evaporation of Si at the surface, was achieved. The surfaces were studied after annealing via plan-view secondary electron microscopy (SEM) and atomic force microscopy (AFM). The resulting surface morphology was found to be both step-free and smooth.
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Implant Annealing of Al Dopants in S ilicon Carbide using Silane Overpressure by Shailaja P Rao A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Stephen E. Saddow, Ph.D. Andrew M. Hoff, Ph.D. Olle Kordina, Ph.D. John T. Wolan, Ph.D. Ryan Toomey, Ph.D. Date of Approval: July 8, 2005 Keywords: silicon carbide, post-implan tation annealing, Aluminum implant Copyright 2005, Shailaja P Rao

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ACKNOWLEGEMENTS I would like to express my gratitude to several people who have helped me throughout my research work, without whose a ssistance this work would not have been possible. First of all I wish to express my sincere gratitude and thankfulness to my advisor, Dr. Stephen E. Saddow, for his co nstant support and encouragement throughout the preparation of this work. He has always believed in me and provided me advice and resources necessary for me to accomplish my goals. He has also spent countless hours meeting with me and discussing various aspe cts of my work and guided me in every phase of my research. There is no doubt that I w ould not have come this far without his devotion. I would also like to offer my deep grateful ness to Dr. A. M. Hoff, Dr. O. Kordina and Dr. J. T. Wolan for their valuable advices, support and guidance and also for accepting to be on my dissertation committee. My next appreciations are due to Dr. R. Toomey who is also a member of my comm ittee for his critical suggestions in making this a better dissertation. I w ould like to take this opportuni ty to thank Dr. R. Nipoti and Dr. F. Bergamini from Bologna, Italy for the immense support especially for providing the ion implanted samples and conducting el ectrical characterization. Without their assistance and help this work would not have been possible. My sincere a ppreciations are due to Dr. E. Oborina for performing non-contact electrical measurements. I wish to acknowledge R. Myers, my fr iend and colleague, who has been very helpful and has provided me with her assist ance through out this wo rk. I would also like to thank T. Fawcett for helping me with a ll the thermodynamic calculations presented in

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this work. I would like to thank Dr. Y. Shis hkin for helping me write the dissertation by providing excellent sugges tions. Appreciation goes to the USF SiC group and in particular C. Frewin, I. Haselbarth, C. Co letti, J. Walker and B. Grayson for their continuous assistance. Many thanks go to Robe rt Tufts, Richard Everly and Jay Bieber and to NNRC for their support in the clean ro om facility. I extend my thanks to Dr. M. Wood of ARL, Adelphi, MD (USA) and Dr U. Starke of Max-Planck Institute, Stuttgart (Germany) for the SIMS measurements. Most of all, I would like to thank my parents and my brothers for their encouragement, persistence support and love, without which I would not have been able to be where I am today. I would like to th ank my friends, who ha ve also given me encouragement and have b een very understanding. This work was supported by the Defense University Resear ch Initiative on Nanotechnology (DURINT) program administer ed by the Office of Naval Research under Grant N00014-0110715 monitored by Dr. Colin Wood. Dr. Wood’s support is gratefully acknowledged.

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i TABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES iv ABSTRACT viii CHAPTER 1 INTRODUCTION 1 1.1 Properties of Silicon Carbide 1 1.2 Motivation of this Research 4 1.3 Background 5 1.4 Organization of Thesis 11 CHAPTER 2 ION IMPLANTATION AND IMPL ANT ANNEALING 12 2.1 Overview of Ion Implantation 13 2.1.1 Ion Implanter 13 2.1.2 Brief Theory on Ion Implantation 15 2.1.3 Ion Simulation Tools: SRIM and TRIM 19 2.2 Ion Implantation in SiC 21 2.2.1 Random Implants 22 2.2.2 Channeled (Aligned) Implants 24 2.3 Importance of Post-Implant Annealing 28 2.4 Silane Overpressure Model 29 2.5 Summary 35 CHAPTER 3 IMPLANT ANNEALING IN COLD-WALL CVD REACTOR 37 3.1 Chemical Vapor Deposition Reactor 37 3.2 USF Cold-wall CVD Reactor 40 3.3 Post Implant Annealing Experiments 45 3.3.1 Ion Implanted Samples 46 3.3.2 Post Implantation Annealing Process 49 3.4 Experimental Results 51 3.4.1 Surface Characterization 52 3.4.2 Comparison with Theory 57 3.5 Electrical Characterization 60 3.6 Summary 68

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ii CHAPTER 4 IMPLANT ANNEALING IN HOTWALL CVD REACTOR 70 4.1 Hot Wall CVD 70 4.2 USF Hot-Wall CVD Reactor 72 4.3 Post Implantation Annealing Experiments 77 4.3.1 Ion Implanted Samples 77 4.3.2 Post Implantation Annealing Process 81 4.4 Experimental Results 85 4.4.1 Surface Characterization 85 4.4.2 Comparison with Theory 92 4.5 Electrical Characterization 93 4.6 Summary 98 CHAPTER 5 SUMMARY AND FUTURE WORKS 99 5.1 Summary 99 5.2 Future Works 103 REFERENCES 106 APPENDIX 113 About the Author End Page

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iii LIST OF TABLES Table 1.1 Physical Properties of some of the Common Polytypes of SiC at Room Temperature Compared to Si. 4 Table 3.1 Summary of Measured Di ode Performance vs. Anode Size 63 Table 3.2 Statistics of the Measured Devices 66 Table 4.1 Summary of the Samples us ed for Both Surface and Electrical Characterization. 79

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iv LIST OF FIGURES Figure 2.1 Schematic of an ion implanter 13 Figure 2.2 (a): Plot of theoretical ion stopping power as a function of energy. (b): Theoretical Gaussian distribution of the implanted ions in the target sample. 16 Figure 2.3 A typical calculated impla ntation profile for a sequence of nitrogen implants in SiC. 19 Figure 2.4 Sketch of the wafer orientati on with respect to the ion beam in order to perform random implant. 23 Figure 2.5 SIMS profiles for random a nd <0001> channeled implant doping profiles in 6H-SiC for a low fluence values. 25 Figure 2.6 SIMS doping profile for <0001> channeled implant in 6H-SiC. 26 Figure 2.7 A cartoon of the proposed mechanisms. 30 Figure 2.8 Thermo-chemical predicted va por pressure vs. temperature of SiC annealed in argon. 33 Figure 2.9 Predicted silane flow rates as a function of anneal temperatures for both cold-wall and hot-wall CVD configurations. 35 Figure 3.1 Basic schematic of a horizon tal-cold-wall CVD reactor growth zone. 39 Figure 3.2 Photograph of the 75 mm hor izontal, cold-wall reactor. 40 Figure 3.3 Photograph of the SiC coated susceptor supported by ribs of a quartz boat. 42 Figure 3.4 Comparison of doping profile vs depth. 46 Figure 3.5 Predicted SRIM doping profile of samples used for electrical characterization. 48

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v Figure 3.6 Cross-sectional view of th e graphite susceptor placed on the quartz boat. 49 Figure 3.7 Implant annealing pro cess schedule for cold-wall CVD processing, 50 Figure 3.8 J.I.P.ELECTM furnace annealing performed at IMM in Bologna, at 1600C for 30 min in high purity Ar: (a) Plan view SEM micrograph of the surface morphology. (b) AFM data of the surface morphology of the annealed surface. 53 Figure 3.9 Surface morphology after sila ne overpressure annealing at 1600C for 30 min: 54 Figure 3.10 Illustration of the experi mental methodology used during this research work. 55 Figure 3.11 AFM data taken on postimplant annealed surfaces at temperatures of (a) 1650C, (b) 1675C, and (c) 1700C. 54 Figure 3.12 Plot of average RMS surface roughness as a function of temperature after annealing in the cold-wall CVD configuration 56 Figure 3.13 Plan view SEM micrograph of a SiC implanted layer annealed at 1650C in 15 sccm of silane flow. 57 Figure 3.14 Comparison of the theoretical silane flow rate vs. anneal temperature with experimental data for the cold-wall CVD reactor configuration. 58 Figure 3.15 (a) Photolithographic mask la yout of the device geometry used to form electrical characteri zation. (b) SEM micrograph of etched mesa on the W2 surface after annealing. 61 Figure 3.16 Electrical characte rization data taken on p+-n implanted diodes. 62 Figure 3.17 Electrical data taken on p+/n diodes annealed at 1600C in silane. 64 Figure 3.18 SIMS measurement of the Al profile on the full processed SiC wafer. 65 Figure 3.19 Typical p+/n diode forward bias (left) and reverse bias (right) characteristics. 67

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vi Figure 3.20 Comparison of set 1 and set 2 sheet resistance of the implanted layer versus post-implantation annealing temperature. 68 Figure 4.1 Schematic of the horizontal hot-wall CVD reactor with an angled top ceiling. 71 Figure 4.2 Photograph of the “100 mm” hor izontal hot-wall reactor during high-temperature operation. 73 Figure 4.3 Photograph of the (a) hot-wall susceptor: top susceptor is SiC coated and the bottom is TaC coated. (b) Front end of the graphite insulating foam after assembly. 74 Figure 4.4 Comparison of doping profile vs. depth 79 Figure 4.5 Predicted SRIM doping profile of the Al ion implantation performed on W2 samples. 80 Figure 4.6 SIMS measurement of the Al pr ofile of the as-implanted sample. 81 Figure 4.7 Implant annealing process schedule for T1 = 1700C hot-wall CVD processing. 85 Figure 4.8 Optical micrograph of (a): sample annealed at 1750C under a non-optimized silane flow rate. (b): crater formation on a sample annealed at 1600C. 86 Figure 4.9 Surface morphology analysis af ter annealing at 1650C in a hotwall system: 87 Figure 4.10 AFM data taken on postimplant annealed surfaces at temperatures of (a) 1600C and (b) 1650C. 88 Figure 4.11 AFM data taken on postimplant annealed surfaces at temperatures of (a) 1700C and (b) 1750C. 89 Figure 4.12 Plot of average RMS surface roughness as a function of temperature after annealing in the hot-wall CVD configuration 90 Figure 4.13 Plot of average RMS surface roughness as a function of function of silane flow rate at 1700C as the hot-wall CVD configuration 91 Figure 4.14 Comparison of the theoretical silane flow rate vs. anneal temperature with experimental data for the hot-wall CVD reactor configuration. 92

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vii Figure 4.15 Doping profile of the epitaxial film of the samples W2 before implantation, obtained by non-contact Q2-V measurement 94 Figure 4.16 Annealing process schedule for the (a) set 1 and (b) sets 2 and 3 sequential annealing experiments. 95 Figure 4.17 Measured contact potentia l difference (VCPD) during noncontact metrology of the samples annealed as per Fig. 4.13 96 Figure 4.18 Measured doping density vs annealing sequence measured using non contact electri cal measurements. 97 Figure 4.19 SIMS measurement of the Al profile on the samples annealed after 3 annealing steps (Set 1, 2, 3) at temperatures of (a) 1600C and (b) 1700C. 98 Figure 5.1 Predicted SRIMs profile of the Al+ implantation preformed through 400 of deposited oxide. 104

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viii Implant Annealing of Al Dopants in S ilicon Carbide using Silane Overpressure Shailaja P Rao ABSTRACT The goal of this research is to devel op a post-implantation annealing process in silicon carbide (SiC). Due to th e low diffusivities of dopants in SiC, even at temperatures in excess of 2000C, diffusion is not a suitab le process to achieve selective, planar doping. Ion implantation is therefore the most suitable means for achieving selective doping in SiC crystals. The strong covalent bon ding in SiC requires that selective doping be performed via high-energy ion implantati on. As a consequence of the high ion energy and flux, there is considerable lattice damage to the crystal surface. To repair the damage caused by the implantation, as well as to elect rically activate the dopa nts, it is important to perform post-implantation thermal anneal ing at temperatures greater th an 1600C. However annealing at such high temperatures decomposes the SiC crystal surface due to the selective out-diffusion of Si causing surf ace morphology degradation. In this research two processes, both using a silane-based SiC CVD reactor, have been realized to minimize the evaporation of Si. This is accomplished by providing Si overpressure above the wafer surface during annealing thus suppressi ng the evaporation of Si from the lattice. Post-implantation anneals were performe d in both hot-wall and cold-wall silanebased chemical vapor deposition (CVD) reactors. For each process temperature developed, silane was added to a stream of Ar in such a concentration such that the

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ix suppression of step-bunching, a well known phenomenon caused by the evaporation of Si at the surface, was achieved. The surfaces we re studied after annealing via plan-view secondary electron microscopy (SEM) and atomic force microscopy (AFM). The resulting surface morphology was found to be both step-free and smooth. Results of the annealing processes developed, the surface char acterization performed and electrical data relating to the dopant acti vation and implanted region conductivity are presented.

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2 CHAPTER 1 INTRODUCTION 1.1 Properties of Silicon Carbide Silicon Carbide (SiC) is evolving into a rea listic alternative to Si for use in high temperature and high power electronic and mech anical devices, due to its wide band gap and high thermal conductivity. Some of these pr operties of SiC indicate the potential for high density integration of SiC devices [1]. Other superior physical properties of SiC, when compared to narrow band-gap semiconducto rs such as Si, incl ude a lower intrinsic carrier concentration (by 10 or ders of magnitude), higher el ectric breakdown field (4-20 times greater), higher thermal conductivity (3 -13 times higher), and larger saturated electron drift velocity (2 -2.5 times faster) [2, 3], which are explained in detail in the next paragraph. In addition to this silicon dioxide (SiO2), which has the highest dielectric strength of all insulators and a key ingredient in th e making of the Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is the native oxide of SiC and can be thermally grown in dry oxygen or steam ambients [4]. Most of the other compound semiconductor materials such as GaN do not enjoy this particular advantage. SiC possesses unique physical and chemical properties which enable its use under severe conditions (i.e., harsh environments) hence making it a promising material for

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2 many electronic and optoelectronic device appli cations. Some of the unique properties of SiC are as follows: (a) Wide bandgap: SiC with its wide bandgap has a higher intrinsic temperature compared to Si [5]. Hence at high temperatur es the problem of devi ce failure due to the thermal generation of electron-hole pairs in ex cess of the number of dopant-provided free carriers is overcome because of its wide bandgap. (b) High thermal conductivity: As the temperature of a semiconductor increases the physical properties of the material change especially the carrier mobility, which decreases with increasing temperature [6]. SiC is an excellent thermal conductor enabling heat to flow more readily than in other se miconductor materials. As a point of reference the thermal conductivity of SiC at room temperature exceeds the thermal conductivity of any metal [7]. This property enables the us e of SiC for the manufacture of very highpower electronic devices, in which large am ount of heat is generated during device operation. [6]. (c) High electrical field: Due to its wide bandgap, the impact ionization energy is much higher in SiC compared to Si or GaAs. SiC can withsta nd voltage gradients as high as 2.2 MV/cm, which is ten times higher than th e value in Si [7]. This property allows the electric field to build up to a high valu e in the material without the avalanche multiplication of ionized carriers, which leads to the material electr ical breakdown effect [8]. For a device designed for the same br eakdown voltage using Si and SiC, the SiC device can have much thinner depletion regi on due to this parameter. Therefore the doping concentration in SiC can be much higher, which helps the series resistance of the active layers to be low due to the higher doping concentration.

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3 (d) High saturated electron drift velocity: SiC has a high saturated electron drift velocity of 2 x 107 cm/sec, which enables SiC devices to be operated at high frequencies [9]. At low the electric fields, drift velo city of the electron in a semiconductor is proportional to the electric field with a propo rtionality constant represented by the lowfield carrier mobility. However, at higher fields the direct proportionality fails and the velocity saturates and stays consta nt with increasing electric field. In addition to these advantageous prope rties, SiC exhibits two dimensional polymorphism called polytypism. Polytypes are alike in the two dimensions of a closepacked plane but differ in the stacking sequenc e in the dimension perpendicular to that plane. There are several hundred stacking or ders possible and hence many polytypes of SiC exist [10]. The individual bond lengths of the polytypes are identical but the crystal symmetry is determined by the stacking periodicity, which is the main cause for the different electrical and optical properties of the polytypes as listed in Table 1.1 [2]. The polytypes are divided into thre e basic crystallographic catego ries: cubic (C), hexagonal (H) and rhombohedral (R). However to fabricat e devices on single crystal substrates only a few of the polytypes are stable; these are 4H -, 6Hand 3C-SiC. 3C-S iC is not available in bulk form via seeded sublimation grow th but can be grown on Si or 6H-SiC. Unfortuately there has been limited success due to the large (> 20%) lattice mismatch between -SiC (i.e., 3C-SiC) and Si [11]. Theref ore 6H-SiC and 4H-S iC are the only SiC polytypes currently available in bulk wafer form, with 2” a nd 3” wafers in production and 4” wafers demonstrated by several wafer ve ndors. Among all the polytypes, 4H-SiC has become preferred due to the more isotropic na ture of many of its electrical properties.

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4 Table 1.1: Physical properties of some of the common polytypes of SiC at room temperature compared to Si [2, 3 ,6]. Properties 3C-SiC 6H -SiC 4H-SiC Si Band Gap (eV) 2.39 3.00 3.23 1.12 Critical Electric Field (MV/cm) 2.12 2.5 2.2 0.25 Thermal Conductivity (W/(cm-K)) 5.0 5.0 4.9 1.5 Saturated Electron Velocity (x 107 cm/s) 2.5 2.0 2.0 1.0 Electron Mobility n (cm2/(V-s)) 750 370 1000 1500 Hole Mobility p (cm2/(V-s)) 40 90 115 600 1.2 Motivation of this Research One of the most important process steps for any semiconductor is the ability to selectively dope various regions on a semic onductor die and/or wafer. In conventional semiconductors such as silicon (Si) or galliu m arsenide (GaAs), the process for selective doping is well established and is based on th e thermal diffusion of dopants, which is a well understood and characterized process. Th ese processes cannot be directly adapted into SiC technology because of the inherent mate rial properties of SiC, namely the very strong covalent bonding of the lattice whic h makes thermal diffusion impractical. One approach used to achieve selectively doped re gions on a SiC die is to dope various layers during epitaxial growth. One then etches back the areas that are not to be doped at this level, albeit at the expense of several add itional processing steps. While this is a valid approach, it does not result in a planar selectively-doped area, which is very important for making SiC integrated circuits economically attractive [12].

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5 Ion implantation and diffusion are the two pr ocesses that have been widely used in the Si community for selective doping. However, due to low diffusivities of the dopants in SiC even at temperatures in ex cess of 2000C, diffusion is not a suitable process in SiC [12, 13]. Ion implantation is therefore the only f easible technique for planar area selective doping of SiC. In this process, the substrate is bombarded with heavy ions, which not only cause damage to th e crystal lattice but also the implanted ions pre dominantly occupy interstitial lattice sites. In order to repair the damage as well as activate the dopants a high-te mperature thermal anneali ng step is required after implantation. This research focuses specifically on the anneal process and the basic concept employed will be discussed in section 1.3. Post ion implantation annealin g is not a completely mature process in SiC. There are several issues which incl ude selective evaporation of Si and C from the substrate surface during high-temperature anneali ng, which limits the maximum annealing temperature [14]. In addition this makes it diffi cult to restore the lattice quality back to the virgin (i.e., pre-implanted) level, especially if the degree of lattice damage is near the level where the material becomes amorphous. Many research works have been performed to overcome these critical problems and some of them are listed in the following section. This is intended to give a brief background for the work conducted during this doctoral research, namely the annealing of SiC ionimplanted layers in a silane ambient. 1.3 Background The most popular and conventional met hod of SiC post-implant annealing is thermal annealing performed in an argon ambien t at either atmospheric pressure or in

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6 vacuum [15 17]. A slightly modified versi on of this method is the use of a SiC wafer cap that provides a silicon overpressure a bove the wafer and was adapted by M. A. Capano, et al. [14]. They performed annealing on boron (B) implanted 4H-SiC and B and Al implanted 6H-SiC with a SiC cap, wh ich was another SiC wafer placed onto the surface of the wafer to be annealed. The implan ted samples were annealed in a resistively heated furnace at various temperatures be tween 1500C to 1800C. Two sets of anneals were performed during these experiments. In one set the samples were annealed for 40 min in an Ar ambient at 5 Torr. The second set of anneals were pe rformed with the cap separated from the implanted wafer by a distance of 250 m. In this technique a SiC wafer is clamped to the implanted wafer so that Si surface out-diffusion is suppressed by the cap wafer. The surface of the annealed samples was characterized via atomic force microscopy (AFM). Electrical characte rization was done by performing C-V measurements of schottky diodes formed by pa tterning Ni on to the implanted surface, and the contact resistance de termined using transfer leng th method (TLM) measurements. It was observed that temperatures in ex cess of 1650C were required to reach high activation levels for boron implants in 4H -SiC with complete activation achieved at 1750C. The sheet resistances of the Al-implanted 6H-SiC samp les that were annealed at 1800C were measured to be 32.2k / However there was an increase in the surface roughness after implant annealing of the samp les in the Ar ambient. According to a model that was proposed in that work to explain the observed surface roughness, SiC sublimation and highly mobile species enable the surface to reconfigure itself. Saddow et. al [28] proposed that anneals pe rformed in an ambient that prevents the evaporation of Si

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7 containing molecules would suppress the me chanism which leads to step bunching and hence surface morphology degradation of the post-implanted annealed surface. Similarly D. Kawase et al. investigated Si re-growt h from the amorphous phase caused by Al-implantation [18]. Implantations were performed both at room temperature and at 1000C. The samples were annealed in Ar for 30 min at temperatures between 800C to 1600C in order to re-crystallize th e amorphous layer. The damage induced by the implantation and the damage reductions by the subsequent annealing were determined by electron spin resonance (ESR) and transm ission electron microscopy (TEM). The ESR signal from the as implanted sample showed presence of dangling bonds which corresponds to amorphous SiC. The spin densit y of ESR increased with the fluence and decreased with the implantation temperature and annealing temperat ure indicating the recrystallization of amorphous regions. However, electric properties (carrier concentration and mobility) were independent of the implantation temperature and D. Kawase et al. observed that residual defects appeared in the implanted regions after annealing. K. A. Jones et al. used an AlN capping layer to prevent Si evaporation during activation of n-type dopants up to a temperat ure of 1600C [19]. Afte r annealing the AlN cap is stripped off. Of more concern was th at pinholes in the AlN cap were observed to form, especially at temperatures above 1600 C, thus limiting the utility of this approach. This is especially true in th e case of complete activation of p-type dopants, which require annealing temperatures above 1700C. L. B. Ruppalt et al proposed a dual BN/AlN capping layer for performing annealing on implan ted SiC up to a temperature of at least 1700C [20]. The AlN was used as a protective layer on SiC as it is chemically inert, while the BN layer on top of the AlN cap would prevent the AlN from evaporating at

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8 temperatures in excess of 1600C. Both the layers were deposited by pulsed laser deposition (PLD). After performing high te mperature annealing, the BN layer cap was removed by ion milling and the AlN was selec tively etched with a warm KOH etch. The surface structure after etching off the cap la yers was examined with scanning electron microscopy (SEM), X-Ray diffraction (XRD), atomic force microscopy (AFM) and High Resolution Transmission Electron Microscopy (HRTEM). It was observed that the surface of the film remained unchanged and there were no cracks or hexagonal thermal pits that had been observed when only AlN cap layer was used due to the exposed AlN. An Auger electron spectroscopy (AES) analysis of the surface showed no evidence of Al or N contamination. However, the processi ng steps involved using this method are daunting for production. First, large-area cap deposition using PLD is difficult as the deposition footprint is normally limited to a few centimeters in diameter. Second the twostep process to remove the dual-level ca p is both time consuming and can lead to processing errors, such as ion-milling through the BN cap into the AlN cap or, worse, through both caps and into the underlying SiC surface. K. V. Vassilevski, et al. developed a process similar to the one described in [19] and [20], but instead of AlN, graphite cappi ng layer was used to protect the surface during post-implantation annealing [21]. Phot oresist AZ-5214E, which is a special kind of resist that can be used as both positive and negative resist, was spun and baked in vacuum at temperatures ranging from 750 to 850 C. This helps in formation of a graphite layer. Complete conversion of the polymer in to a graphite layer was verified by Raman spectroscopy. After formation of the graph ite layer, post-implantation annealing was performed at atmospheric pressu re in an argon ambient for 30 mins at temperatures up to

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9 1650C. The capping layer was subsequently removed by dry oxidation followed by etching of the film in an HF:HNO3 (1:3) solution. Surf ace characterization was performed using AFM, which showed no st ep bunching with a surface roughness of ~0 4 nm. The schottky diodes fabricated on the capped epitaxial layer on the unimplanted regions showed ideal diode behavior. The el ectrical characterization of the implanted layer was not mentioned in the paper. Again this process, like th e BN/AlN cap,is very tedious and liable to several contamina tion issues because of the photoresist. C. Dutto et al performed laser annealing (LA) as an alternative to the classical thermal annealing processes for activati on of ion-implanted dopants in SiC [22] They used powerful pulsed-excimer laser beams of nanosecond temporal duration to deposit large amounts of energy in a short period of time into the near-surface region, while maintaining the substrate essentially at room temperature. They demonstrated the possibility of annealing Al implant-induced damage in 4H-SiC by single-shot laser processing in the solid phase using a XeCl excimer source of 200 ns pulse duration. The surface study revealed that this process kept the surface stoichiome try (Si:C) near unity and prevented any strong surface degradati on. The electrical activation of the Al dopant was confirmed by I-V measurements, which were performed on mesa pn junction diodes. Unfortunately they did not report on the dopant activation percentage so it is difficult to assess the usefulness of this technique. In addition, while laser ann ealing is an attractive research approach, for high-volume device produc tion the suitability of this approach is in doubt. Several other types of annealing proce sses have been used, such as furnace annealing and rapid thermal annealing (RTA). Furnace an nealing is reasonable for a

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10 temperature below 1800 C because of the Si sublimation and carbonization of the SiC surface [23]. In RTA processing, as the temperature uniformity across the wafer is excellent, there is a reduction in the thermal gradient that can warp wafers. However, for temperatures in excess of 1400 C using an RTA process has proven to be problematic due to the out diffusion of Si from the SiC su rface, which can cause step bunching [24]. It also was noticed that the surface roughness increased w ith the annealing time and temperature [25]. There was yet another tech nique in which a ther mally grown silicon dioxide was used as a capping layer [26, 27]. Ho wever this process is very sensitive to the thickness of the oxide and the annealing temperature is limited by the melting point or cracking of SiO2. Most of the annealing techniques mentioned in this section showed limited success and/or are very tedi ous to perform. Saddow et al. [28] and S. Rao [29] et al used silane over-pressure process to achieve this very goal. The concept of silane overpressure is similar to arsenic overpressure implemented in post-implantation annealing of implanted GaAs [30, 31]. In order to avoid preferential evapora tion of As from the surface, arsenic overpressure was provided in either a hot-wall furnace or using RTA with a proximity cap. In case of the hot-wall furnace, annealing was performed in a As gas containing ambient. In case of RTA, the sample was placed in close proximity with another GaAs wafer, which acted as a source of As. For both cases As vapor pressure was provided above the surface of the proces s wafer and thus suppressing further decomposition of the surface of the implanted sample. A similar technique was used for post-implantation annealing of GaN, where so me form on nitrogen overpressure was provided to minimize the loss of nitrogen from the semiconductor surface at high

PAGE 23

11 temperature [32]. Based on these processes, silane overpressure was implemented in order to suppresses the selectiv e evaporation of the Si from the SiC surface. This process, which will be discussed in more detail in following chapters, can be easily adapted by the SiC community since most SiC fabrication suites contain a hightemperature SiC CVD reactor which can be easily ad apted for this process. 1.4 Organization of this Document This dissertation will report on the im portance of ion implantation and post implantation annealing in SiC. The research wo rk done in this dissertation is divided into three main chapters. Chapter two will explai n briefly about the general theory behind implantation and then go on to explain the diffe rent methods of implantation in SiC. This chapter will also explain the theory along w ith a thermodynamic simulation of the silane overpressure process for post-implantation anne aling. Chapter three and four will discuss in detail the implant annealing processes deve loped here along with surface and electrical characterization of the samples annealed in cold-wall and hot-wall CVD configurations, respectively. Chapter five will summarize the work in this research and as well as discussing future work in this field.

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12 CHAPTER 2 ION IMPLANTATION AND IMPLANT ANNEALING As mentioned in Chapter 1, SiC is a promising wide bandgap semiconductor, whose properties are suitable for many a pplications, such as high power, high temperature and high frequency devices. Howeve r, there are several issues with the processing technology that need to be resolv ed to enable industrial-scale SiC device production. One of the most crucial processing steps is planar doping of SiC, especially for planar device fabrication. Controlled doping of bulk crystals and epitaxial layers can be performed in-situ during gr owth with help of chemical vapor deposition (CVD) [33]. However, to fabricate planar devices sele ctive area doping is requi red. In SiC, thermal diffusion is not a viable process because of the extremely high temperatures (> 2000C), normally required. Along with the thermal stab ility of SiC at such high temperatures there is also an issue regarding low atomic m obilities in SiC [1, 34]. To reach reasonable diffusivities ( 10-13 cm2/s) temperatures around or in excess of ~1800 C are needed for most elements [6]. Only light elements with a small atomic radius, like hydrogen, lithium, beryllium and boron, exhibit a signi ficant diffusion under equilibrium conditions at temperatures below 1800 C. Hence, ion implantation appears to be both attractive and the only practical method to realize a sele ctive, planar area doping technology for SiC [35].

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13 2.1 Overview on Ion Implantation Ion implantation is a process in which hi gh velocity ions of the element to be implanted are injected into the near-surface re gion of the target material [36]. The major advantage of implantation is that the surface concentration is not limited by the species solid solubility as ion-implantation is a non-equilibrium doping technique and all stable elements of the periodic table can be implan ted. It also gives precise control over the dopant concentration and depth profiles. A wide range of profiles can be obtained such as shallow junctions, buried doped regions, box pr ofiles, etc. Regions can be selectively doped by using implant masks that block the ions from penetrating into the surface. 2.1.1 Ion Implanter An ion implantation system typically consists of a highvoltage particle accelerator that produces a high velocity beam of ions which strike the surface of the target material which is to be implanted. Figure 2.1 shows the basic schematic of an ion implanter from reference [37]. Figure 2.1: Schematic of an ion implanter showing (1) ion source, (2) mass spectrometer, (3) ion electrost atic accelerator (4) beam scanning system and (5) end station, where the target is mounted [37]

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14 Most ion implanting systems are divi ded into five main components: a. Ion Source: A high voltage is used to prod uce plasma of the desired ion impurities from either a feed gas or solid ch arge, which are the sources of the implant species. In the case of solid charges, material is heated and the resultant vapor used as the ion source, flows past a filament. These vapors, or the feed gas, are broken down into a variety of atomic and molecular species with the help of a plasma glow discharge, where they are ionized [38]. Only de sired charged specie is sel ected, for example incase only the positive ions are required, beam of positiv e ion leaves the system through the exit, which is biased with a large negative pot ential with respect to the filament. b. Mass Spectrometer: The beam now consists of variety of species, most of which are ionized. With the help of an analyzer magnet the desired impurity is separated from other species based on its mass. An analyz er magnet bends the beam through a right angle (magnetic field perpendicular to the beam velocity exists) and the desired specie is passed through an aperture slit to the main accelerator column. c. Accelerator: The accelerator adds required energy based on the desired penetration depth, to the beam and accelerate s the ions to their final (i.e. desired) velocity. The required maximum energy or vo ltage depends on the desired penetration depth of the ions into the ta rget material. The accelerator column is typically several meters long and is maintained at high vac uum to avoid ion collisions during acceleration. d. Scanning System or Beam writing: The ion beam may be ra stered with the help of xand y-axis deflection plates. This ensu res uniform ion implantation across the target sample. In order to prevent neutral particle s, which may have formed during acceleration, from hitting the target the beam is bent slightly.

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15 e. End Station: Finally the target sample is mounted in a vacuum chamber, where the sample’s orientation and temperature are se t [39]. Also precise control of the ion dose is done at the end station by placing the sample in a Faraday cup. The cup captures all of the charges that enter it and the ion current is directly measured by connecting an amp meter between the cup and electrical ground. The dose is calculated by integrating the current over time and dividing the resulting va lue by the sample area. This measurement is usually done before an experiment, since Faraday’s cup absorbs all the energy. While a production-level ion implanter is very expensive; the flexibility and tight process control have overshadowed this disadvantage. As a consequence, ion implantation is currently the dominant t ool used to selectively dope SiC. 2.1.2 Brief Theory on Ion Implantation The theoretical background of ion im plantation is based upon Bohr’s and Rutherford’s early work [40]. Rutherford fi rst proposed that atoms consisted of a solid nucleus surrounded by a shell of orbiting elect rons and Bohr based on the collision between particles and bound elect rons, calculated the energy loss per path length for a heavy charged particle. This formed the basi s of ion implantation and led to the theory that several different effect s occur during the bombardment of solids with heavy charged particles that causes an energy loss [41]. As an ion enters the surface of a sample, it collides with atoms in the lattice and interacts with the electrons in the crystal. Inelastic collision with electrons (electronic stopping, Se) and elastic nuclear collisions (nuclear stopping, Sn) play a significant role in the stoppi ng of the particles. Each nuclear or electronic collision reduces the energy of the ion until it comes to rest within the target

PAGE 28

16 sample [37]. The total stopping power, Se,n (cross-section for electronic and nuclear stopping), is thus defined as the energy loss per unit path length and can be calculated using equation 2.1 en nuclearelectronicdEdE S dxdx (2.1) Where E is the beam energy at impact and x is the distance the ion travels into the sample. From Figure 2.2(a) it can be seen that at lower energi es nuclear stopping dominates, whereas at higher values the energy is transferred to the electrons of the target material [39]. (a) (b) Figure 2.2 (a): Plot of theoretical ion stoppi ng power as a function of energy [39]. (b): Theoretical Gaussian distribution of the implanted ions in the target sample. The profile shows that the impurity is completely implanted into the wafer below the surface [37]. The energy range of ion implantation, or th e ion interaction with the crystal is a statistical process that was fi rst investigated by Lindhard, Scharff and Schiott (LSS) in

PAGE 29

17 the early 60’s, called the LSS theory described in [42]. According to this theory, the ions have a Gaussian distribution function as shown in Figure 2.2(b) and mathematically described by equation (2.2): 2 2exp 2P P PxR NxN R (2.2) where NP is peak concentration, RP is projected range, and RP is straggle Due to the random nature of the collisions the total distance traveled, or range, and its projection on the direction parallel to the ion beam, called the projected range, RP, is the average distance an ion travels before it comes to stop. All of the parameters are random variables. The peak concentration NP lies at x = RP as shown in Figure 2.2 (b). The spread of the Gaussian distributi on is given by the standard deviation, RP, which is also called the straggle. For practical purposes one can indirectly control the energy and the dose, or fluence, of the implantation by varying the io n beam voltages and currents. The dose, is defined as the area under the Gaussi an distribution curve and is given by equation (2.3) 2PPNR (2.3) Implant doses typically range from 1010 cm-2 to 1018 cm-2 [37]. Due to ion bombardment of the crystal su rface, various defects can occur in the target material depending upon the energy, dos e and mass of the implanted ion. Some of these defect formations are: (a) Channeling effect: When implanting a single crystal material in which the atoms are regularly or symmetrically arranged, a sp ace in the crystal exists at particular orientation. The ions can pene trate deeper into the crystal when the ion velocity is

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18 parallel to these crystal orient ations [38]. This is called i on channeling where ions do not suffer any nuclear collisions and thus penetr ate deeper into the crystal [41]. Channeling can be avoided by tilting the target sample so that the ion entering the crystal lattice makes an angle less than a critical angle. The critical angle is the largest angle, whereby the “steering” action of the rows of atoms is lost. is given by equation (2.4) as 129.73 Z Z Ed (2.4) where E is the incident energy in keV, d is the distance between atoms and Z is the charge number for the incident and target ions The tilt angle of the sample with respect to the incident ion beam thus depends upon the lattice structure and crystal orientation. (b) Amorphous layer formation: In the case of a suffi ciently high ion dose, the damage due to displacement of target atom s by the implanted ion is very high [36]. The displaced atom can themselves displace other atoms, resulting in co llision cascade effect. This leads to the accumulation of vacancies and atomic clustering effects and hence the formation of an amorphous layer. Amorphous la yer formation can be reduced to a certain extent by heating the sample to a high temperature during im plantation. At high temperatures, the substrate surface thermally “s elf-anneals”, but not completely. In order to re-crystallize the target surface, a post im plantation anneal is performed at an even higher temperature, which is the basis of this research and is expl ained in the section 2.3. Often a thin passivation layer is deposited or grown on the sample surface to protect the bare surface from contamination as well as to reduce the damage caused by the high energy ions. In the case of a single i on implant, the passivation layer also helps in placing the peak of the implanted Ga ussian profile or to maximize the dopant

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19 concentration, at the sample surface. This is particularly important to minimize the contact resistance of metal contacts appl ied to the implanted region. In the case of shallow junctions, to reduce the sheet resistan ce and short channel e ffect, especially in MOSFETs, multiple implantations are performe d to obtain an implanted box-profile [43]. Figure 2.3 shows a typical box-sha ped profile for a sequence if nitrogen implants into a SiC surface to form source and drain wells in a MOSFET [4]. Figure 2.3: A typical calculated implantation pr ofile for a sequence of nitrogen implants in SiC to generate a box-shaped profile in order to form drain and source wells in a MOSFET [4]. 2.1.3 Ion Simulation Tools: SRIM and TRIM For a given ion energy and fluence it is possible to accurately model the distribution of the dopant ions in the substrate, which ma kes it convenient to determine the ion profile and concentration before hand. The most widely used software tool to predict the energy and depth of the implant pr ofile is the Stopping a nd Range of Ions in

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20 Solids (SRIM). SRIM is a group of programs which calculate the st opping and range of ions into matter using a full quantum mechanical treatment of ion-atom collisions [44]. During the collisions, the ion and atom ha ve a screened Coulomb collision, including exchange and correlation interactions between the overlapping electron shells. The ion has long range interactions cr eating electron excitations and plasmons within the target. These are described by including a descript ion of the target's collective electronic structure and interatomic bond structure when th e calculation is setup (tables of nominal values are supplied). The charge state of the ion within the target is described using the concept of effective charge, which includes a velocity dependent charge state and long range screening due to the collective electron se a of the target. A detailed explanation of the calculation and the mechanism used fo r making the simulation tool can be found elsewhere [45]. One of the comprehensive programs included in SRIM is a Monte Carlo statistical analysis program called TRIM (Transport of Ions in Matter). TRIM accepts complex targets made of compound materials with up to ei ght layers, each of different materials. It calculates both the final 3D distribution of the ions and also all kinetic phenomena associated with the ion's energy loss: ta rget damage, sputtering, ionization, and phonon production [44]. It was developed to determin e ion range and damage distributions as well as angular and energy distributions of th e backscattered and transmitted ions [41]. In this program the history of an individual ion or particle in the target is simulated. The particle is assumed to change directions as a result of binary nuclear collisions and move in straight free-flight paths between collisi ons. After a series of nuclear and electronic collisions the energy of the particle is re duced. The ion history is terminated if the

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21 particle looses its energy and comes to a comp lete stop in the target or if the ion misses the target sample completely. In this calc ulation, it is assumed that the target is amorphous and hence the directi onal properties of the crystal lattice are ignor ed. Also the nuclear and the electronic ener gy losses are assumed to be independent. As mentioned in the previous section at lo wer energy nuclear stopping domi nates, hence the program utilized this mechanism. SRIM was originally develope d by J. P. Biersack and now is owned by IBM. It can be run on a personal computer with eith er the DOS or Windows operating system. In this research work this tool was used to predict the doping profile of the implanted layer and also to compare these results with the i on implant profiles measured with Secondary Ion Mass Spectrometry (SIMS). 2.2 Ion Implantation in SiC Since SiC consists of the gr oup IV elements Si and C that have four electrons in the outer shell, SiC can be doped with the sa me elements that are used for Si. Group III elements, such as aluminum and boron, ar e most commonly used for p-type doping, while nitrogen and phosphorus are normally used for n-type doping [46]. Implantation and activation of p-type dopant species results in the highest level of damage to the crystal For this reasons and se veral others that are given in the next paragraph, the focus of this research work is on p-type dopant activation. Aluminum or boron are found to reside on silicon lattice sites and act as acceptors in SiC [47 49]. The ionization energies fo r aluminum and boron in 4H-SiC are 191 to 230 meV and 285 to 390 meV, respectively [6, 49] The ionization energies of aluminum

PAGE 34

22 and boron acceptors decrease with increasi ng acceptor concentration or increasing compensation [50]. This might be reason for the wide range of published data for the ionization energies. Due to the crystal symm etry of 4H-SiC, there are two equivalent lattice sites (cubic and hexagonal) which result in two dopant en ergy levels in the crystal. Boron is a lighter atom compared to al uminum thus the projected range of boron is a factor of 2 times deeper than aluminum, when implanted with the same energy [5]. In addition, boron causes less damage to the crysta l lattice due to its size and mass. This property is an advantage if deep implantations are required, e.g. to form edge termination of diodes. However the based on the smalle r value of ionization energies mentioned above, degree of ionization of aluminum is higher than that of boron and also the solubility of Al in SiC exceeds that of boron [49]. Therefore for high doping it is preferential to use aluminum. Also it has been observed that bor on implanted in SiC results in deep level defects called the D-cente r defect, which is speculated to be one of several intrinsic defect complexes consis ting of one boron atom [10]. During postimplant annealing at high temperatures, boron tends to diffuse easily and either out diffuses (i.e. leaves the crystal) or accumulate s at the surface [50]. In this research the surface of 4H-SiC, which was implan ted with aluminum, was studied. In SiC in order to avoid ion channe ling various implantation procedure are followed. Two of the most popular methods of implantation are listed here. 2.2.1 Random Implants The implantation process is said to be “random” when the direction of the ion beam with respect to the crystal is such that the high energy ions experience the same

PAGE 35

23 amount of energy loss and collisio ns as they would in a materi al with the same chemical composition but of amorphous structure [6]. In sp ite of this, there is always a probability that a few of these high energy ions scatter al ong major axial or planar directions, leading to channeled trajectories. In the case of SiC random implantation can be even more complicated because of the poor knowledge about ion channeling phenomena in the different SiC polytypes and also due to various different Si C crystal orientations with respect to the wafer primary flat. The primary flat is the longest length in the circumference of the wafer and has a specific crystallographic orientation relative to the wafer surface. The most general convention to identify the proper implantation geometry for random implants is to set tilt and twist angles with resp ect to the wafer normal and the wafer primary flat. The tilt angle corresponds to a rotation of the wafer normal with respect to the ion beam direction within the plane of the wafer flat as shown in Figure 2.4. The twist angle is the angle by which th e wafer is rotated around the wafer normal while remaining within its own plane. Beam TWOxTI C Axis Wafer Axis Wafer Flat Beam TWOxTI C Axis Wafer Axis Wafer Flat Figure 2.4: Sketch of the wafer orientation wi th respect to the ion beam in order to perform random implant. Tw is wafer twist, TI is the tilt angle and Ox is the off-axis of the wafer.

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24 It is very hard to achieve accurate random implantation in SiC. Since the wafers are misoriented with respect to the (0001) pl ane to improve epitaxial deposition. For 4HSiC the off-angle value is approximately 8, which again is not accurate. Because of all these issues of inaccuracy, the usual convention to fix tilt and twist angles w ith respect to the wafer normal and the wafer flat does not guarantee the desired control and reproducibility of the implantation geometry. The relative orientation between ion beam and SiC crystals often does not minimize th e probability of channeled implants. This explains the large spread of the published data regardi ng the shape and implant depth profile, particularly the tail of the implants. 2.2.2 Channeled (Aligned) Implants When performing channeled implants the i on beam is used in the single spot configuration, which leads to a non-homoge neous flux distribution within the beam cross-section. The channeled profile is deeper than the random implantation profile and has a trapezoidal shape while, ra ndom profile is more Gaussian as shown in Figure 2.5. In Figure 2.5, profiles corr espond to 1.5 MeV Al+ implants performed at room temperature with a low fluence of 1013 cm-2.

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25 Figure 2.5: SIMS profiles for random and < 0001> channeled implant doping profiles in 6H-SiC for a low fluence values. Note that for comparable implants the channeled implant in much deeper and wider [51]. The differences between random and channeled implants are because channeled ions experience lower electronic loss and less nuclear collisions than the random ions. Nuclear collisions are responsible for the at om displacements that produce build up of disorder in the crystal surface. As the da mage increases the material becomes more amorphous and/or contains more defects. Strong dechanneling occurs when the ions reach the buried damaged layer formed by a previous implant, since this layer contains more defects than the sub-surface regions. Thus the number of de-channeled ions in channeled implants increases and the doping profiles modify accordingly. The deepest edge of the channeled profile saturates with increasing ion fluence, and the profile shape starts resembling that of random implants or Gaussian profile as shown in Figure 2.6

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26 Figure 2.6: SIMS doping profile for <0001> channeled implant in 6H-SiC, showing the effect of the implantation dose on the depth profile. As multiple channeled implantations are performed, the intermediate peak grows, due to accumulation of defects between 1 and 4 m [52]. Another set of experiments were also pe rformed to study channeled implants in 4H-SiC at two different or ientations [53]. A 60 keV Al+ implantation was performed in (0001) with an off-axis miscut towards [1120] and (11-20) oriented 4H-SiC wafers. For the (0001) wafers, tilting the wafer during im plantation, along the (1 -100) plane did not result in significant channeli ng in contrast to tilting along th e (11-20) plane. But in case of (11-20) wafers, 10 tilt along various planes around the main crystallographic axis resulted in the largest degr ee of channeling along the ( 0001) plane with no channeling observed for the implant in the (1-100) plan e. Therefore depending upon the orientation and the direction of the implantat ion channeling can be minimized.

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27 There are however major technological difficulties with channeled implant method. The wafer has to be properly aligne d. Rutherford backscattering spectroscopy (RBS) has to be performed on the sample in order to find the proper orientation of the sample. RBS is an in situ process and is performed before the implantation. In RBS measurements the material has to be irradiated with helium i ons and the distribution if the backscattered helium ions are detected. The channeled orie ntation is found by minimizing the backscattering yield. RBS ha s to be carried out as fast as possible in order to minimize the damage created by the helium ion irradiation. Based on all the complication involved with the channel implantation, in this research random implants were performed on the samples used for annealing experiments Most of the aluminum implantation was performed by the group of Dr Nipoti at Consiglio Nazionale delle Rice rche (CNR, National research council), Istituto per la Microelettronica e Microsistemi (IMM Institut e for Microelectronics and Microsensors), Bologna, on Tandetron 4117 HC implanter. Th e 1.7 MV Tandetron accelerator system mainly consists of ion sources a, magneti c mass analyzer, a high voltage power supply, ion beam tubes, a switching magnet, an end station and a computer control system. The high-voltage power supply system is a Cockroft-Walton type (model 4117-HC). The terminal voltage range for this system is from 0.1 to 1.7 MV. The accelerator system is controlled by a computer which allows for unattended start-up and operation of the accelerator system. The data transmission betw een the accelerator and the computer is done by a fiber optic cable to reduce electr o-magnetic noise and potential sparking damage.

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28 The implantation performed was a random implant described in section 2.2.1. in which the ion beam impinges on the 4H-SiC crys tal at 15 with respect to the (0001) axis while remaining within a plane at 12 from the {11-20} crystal plane. In order to reduce the amount of damage accumulation or defects, the implantation were performed at a temperature higher than room temperature (typically ~ 4 00C). The details about the implantations performed are mentioned in ch apters 3 and 4 along with the post-implant anneals that were performed on implanted samples. 2.3 Importance of Post-Implant Annealing In addition to ion implantation perfor med at elevated temperatures, thermal annealing is normally performed after ion im plantation, which serves the dual purpose of repairing defects and activating dopants. Although a considerable part of the implantation-induced damage can be removed by annealing at 1200 C, to achieve reasonable electrical activation anneali ng at temperatures in excess of 1500 C should be performed because of the high bonding strengt h of the SiC lattice [ 54]. After bombarding the target surface with ions, the implanted io ns predominantly occ upy interstitial lattice sites [12]. These interstitial atoms do not aff ect the electrical properties and, in addition, these high energy ions damage the crystal lattice. The electrical activation of the implanted ions, via, the incorporation of dopants on to proper lattice sites known more formally as substitutional dopant incorporati on, is performed by thermal annealing of the wafer. It has been observed that at su ch elevated temperatures (>1500 C) the SiC surface degrades when annealed in inert gas (argon) as well as in vac uum. Silicon appears to

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29 preferentially evaporate and a carbon-rich layer is left behind on the surface [55]. Hence a technique needs to be implemented to permit high temperature annealing of SiC implants which would allow for dopant activat ion while suppressing the evaporation of Si from the surface. Low resistance ohmic contacts are dependent on highly doped surface layers and good carrier mobility, which in tu rn is dependent on the anneal temperature and anneal time. The higher the annealing te mperature the greater the degree of dopant activation. However, higher annealing temp eratures also cause extended defects, dislocation loops, etc to appear which are si milar to the end-of-ra nge defects seen in implanted and annealed Si. This imposes furt her limits on the annealing temperature/time window that can be used in processing of ion implanted SiC [6]. As discussed in Chapter 1, various ann ealing techniques have been performed by the SiC research groups, mostly with lim ited success. Some resu lts obtained showed promising results, but many of the processes are complicated and tedious to perform. In this research we have tried to implement a process we call the silane overpressure process, which is inherently simple and can be easily adapted by the SiC community. In the next section the theory behind this pr ocess is explained in detail and the process details implemented during actual implant anne aling experiments are described in chapter 2 and 3. 2.4 Silane Overpressure Model The most popular method of post-implant a nnealing of SiC is thermal annealing in an argon ambient [18]. As shown in Figure 2.7 (a) when a sample is heated to a high temperature, Si preferentially evaporates fr om the sample surface, leaving behind Si

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30 voids. This leads to the so called step-bunc hing phenomena of the su rface in addition to leaving a carbon-rich surface. In the case of silane over pressure method, the basic principle is described as follows. When the SiC wafer is a nnealed at high temperatures ( 1600 C), Si atoms on the surface of the SiC wafer may be exchange d with Si atoms provided by the cracking of the silane gas in the vapor phase. This model is based on the hypothesis that if the partial pressure of Si atoms above the SiC surface during annealing is greater than the vapor pressure of Si in the SiC matrix, then the evaporation of Si from the surface can be suppressed, as shown in Figure 2.7 (b). The silane is introduc ed via an argon carrier gas, since argon is an inert gas and does not etch or dope Si C. Initial work done by Saddow et. al. used hydrogen as the carrier gas, but th is lead to etching and was hence abandoned [28]. Silicon Argon Hydrogen ( a ) ( b ) Silicon Argon Hydrogen Silicon Argon Hydrogen Silicon Silicon Argon Argon Hydrogen Hydrogen ( a ) ( b ) Figure 2.7: A cartoon of the proposed mechanisms that can occur during postimplantation annealing of SiC in (a) an argon ambient. and (b) a silane/Ar ambient, which is the focus of this research. In this research work post-implantati on annealing process was developed for both cold-wall (Chapter 3) and hot -wall (Chapter 4) configurat ions, which are explained in

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31 detail in the following two chapters. Initial thermodynamic calculati ons for both hot-wall and cold-wall, were performed based on the e xperimental flow rates, especially for the carrier gas argon. Thermodynamic calculations were performed for silane flow rates as a function of temperature to study the silane over pressure mechanism in order to be able to predict the required silane flow as a function of process pres sure and temperature. These calculations were performed using the NAS A-Glenn Chemical Equilibrium Program CEA2 [56]. Details about this software can be found in NAS A publications [57, 58]. This software contains a graphical user interface (GUI) and can also be run using FORTRAN. With this software the chemical equilib rium compositions for assigned thermodynamic species can be predicted. Th ese states are specified by assigning two thermodynamic state functions which, in our case, are temperature and pr essure. The CEA program uses a minimization of free energy formulation, since each species can be treated independently without specifying a set of reactions. Gibbs free energies of formation is given by equation 2.5 000 f ffGHTS (2.5) where0 f G is the change in standard free energi es (free energy of a reaction at 25C and 1 atm pressure) when 1 mole of a substance is prepared from its constituent elements. 0 f H is the change in standard enthalpy and 0 f S is change in standard entropy of the closed system maintained at constant temper ature and pressure. In order to characterize the thermodynamic state of the system, which is at constant pressure and temperature the Gibbs energy is most easily minimized sinc e temperature and pressure are its natural variables. At equilibrium Gibbs free energy of a mixture of chemical species must be a

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32 minimum. At equilibrium the total free ener gy of the mixture is the sum of all the chemical potentials of each species, weighed by the number moles of each specie as given by equation 2.6. 10n ii idGdN (2.6) where i is chemical potential, Ni is number of moles of species anf n is the total number of species in system. In CEA program, equilibrium concentrations of species are calculated at specific temperatures and pressures. Once the thermodyn amic states are established one can input the reactants and number of reactant moles into the calculation. Based on the reactants the program generates all pos sible known complex solid, li quid and gaseous species. Depending on the probability of occurrence of certain specie we can select or omit that particular specie for iteration purposes and this is saved as the input file with .inp extension. Details of the CEA input and output file are shown as Appendix A. This input file is then executed and the mole fractions for all the species that were included in the input file is obtained as an ASCII file with either .out or .plt extension. The calculations were performed using typi cal process conditions such as process temperature and pressure, partial pressure of silane, an inert carrier gas (argon) and solid phase SiC (to take into consideration the s ubstrate). The temperature, pressure and the carrier gas flow rate for the calculations we re varied based on the reactor configuration and the experimental temperature values. Tw o set of calculations were performed for each anneal temperature. In the first calculation, solid phase SiC and gas phase argon were included as the reactants. This was done in order to obtain the theoretical value of

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33 silicon in the vapor phase when SiC is heated in both an argon ambient and when silane in argon cracks over the crystal surface. Fi gure 2.8(a) shows the calculated vapor pressure in the reactor during annealing. Of the 20 or more species that were simulated for condensed SiC in an argon ambien t, it was predicted that only Si2C, Si and SiC2 were present in the reactor during annealing. Thus the dominant species present in the gas phase over a solid SiC surface contains Si due to evaporation from the lattice. Figure 2.8: Thermo-chemical predicted vapor pr essure vs. temperature of SiC annealed in argon. All the dominant species out of ~ 30 predicted species by the simulation are shown. Note argon and condensed SiC are not shown in the plot si nce their values was much higher than the species shown. In the silane overpressure model silicon, delivered via silane gas during annealing, must be of sufficient partial pressu re to balance the partial pressure of silicon evaporating from the substrate. Therefore, in the next calculati on only silane and argon

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34 were incorporated into the calculations. A trial and error numerical iteration was performed with the help of Matlab to equate th e silicon due to the cracking of silane with the silicon due to evaporation from the SiC s ubstrate. A theoretical value of silane flow rate was thus obtained for both cold-wal l and hot-wall CVD configurations. This numerical simulation process was repeated for all annealing temperatures in both configurations. However the assu mption that the partial pressure of Si in the gas phase, (PP)Si, must be equal to the vapor pressure of Si evaporating from the SiC substrate, (VP)Si, is not correct. From the kinetic theory of ideal gases, the rate at which molecules hit surface of the substrate depends on the temperature, pressure, concentration of molecules and the thermal velocity and, hence, is a statistical process. Since the capture Si by the lattice to replace an evaporated Si atom is statistical in nature one can assume that more Si is needed to ensure this proce ss occurs in a reasonable period of time. If we assume that the probability of capture is 10%, then (PP)Si = 10*(VP)Si. The predicted silane flow, based on this order magnitude hi gher partial pressure assumption, was used in these calculations and is plotted as a func tion of temperature in Figure 2.9 for both the coldand hot-wall C VD configurations

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35 Figure 2.9: Predicted sila ne flow rates as a function of a nneal temperatures for both coldwall (circles) and hot-wall (triangles) CVD c onfigurations. An exponential fit has been applied to the data to indicat e the trend with temperature. It can also be observed from the figures that the predicted flow rate of silane increases exponentially as the anneal temperat ure is increased, which is expected due to the exponential increase in Si vapor pressure as a functi on of temperature. In the following chapters these theoretical curves ar e compared with experimentally determined silane flow rates. 2.5 Summary For selective doping of SiC in order to ma ke planar devices, ion-implantation is the most feasible process. Two different methods of implantation in SiC have been explained in this chapter. Even though there has been significant progress made in both implantation processes, several issues have yet to be tackled. In addition to implantation

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36 the importance of post-implant annealing is also mentioned. Implantation causes damage to the surface due to bombardment of ion. Th ermal annealing has to be performed to both repair the crystal damage and el ectrically activate dopants. In this research work a silaneover pressure process has been established for this purpose. Thermodynamic calculations performed to predict the silane flow rate wa s presented in this chapter. The following two chapters will explain the actual processes in cold-wall and hot-wall CVD configurations.

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37CHAPTER 3 IMPLANT ANNEALING IN A COLD-WALL CVD REACTOR Implant annealing normally is conducted in a high-temp erature furnace that is capable of reaching temperatures of greater than 1600C in the case of SiC. What is required for such a furnace is a high-purity hous ing, typically made from stainless steel or quartz, that limits the possi bility of introducing impuri ties into the annealing environment. In this work implant anneal ing was conducted in a high-purity chemical vapor deposition (CVD) reactor since (a) it is capable of reaching temperatures in excess of 1700C (cold-wall configura tion, this chapter and 1800 C hot-wall configuration, chapter 4) and (b) the reactor uses silane ga s as the silicon precursor for growth of SiC films. Indeed the second point is key to this re search which is to use an overpressure of Si to suppress the evaporation of Si from the SiC lattice during high te mperature annealing. 3.1 Chemical Vapor Deposition Chemical Vapor Deposition (CVD) is a sy nthesis process in which the chemical constituents react in the vapor phase near or on a heated substrate to form a solid deposit [61]. It is a common method of choice for epitaxial growth, si nce epitaxial layers are the building blocks for use in various device app lications. The basic idea of CVD is to flow precursors in a carrier gas through a heated re action zone where the precursor diffuses to

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38 the surface through a boundary layer and is adsorbed as reactants onto the substrate. At the substrate surface, after the deposition reaction takes place, gaseous by-products desorb and diffuse away from the surface through the boundary layer. The boundary layer is the region in which the flow is ideally laminar [61]. As shown in Figure 3.1, it starts almost at the front edge of the susceptor and increases in thickness until the flow is stabilized or the velocity gradient of the laminar flow decreases to zero. The deposition rate depends on the boundary la yer thickness, which in turn depends on the pressure in the system. In the case of low process pressu re the boundary layer is thin and the growth rate of the deposit is ideally controlled by surface-reaction kinetics [61]. (as a point of reference atmospheric pressure growth is id eally controlled by the diffusion of growth species through the boundary layer and is thus mass-transport limited [61]). There are different types of CVD reacto rs based on their or ientation, either horizontal or vertical, and based on the growth zone geometry, eith er cold-wall (where only the substrate is heated) or hot-wall (where both the subs trate and hot zone walls are heated). In addition there are numerous other va riations such as process pressure, the use of plasma chemistry to crack precursors, etc [62]. In this chapter the work related to implant annealing in a horizontal, cold-wall, low-pressure reactor is described starting with a description of the r eactor used for this work. Figure 3.1 shows the basic schematic of a growth zone for the horizontal-coldwall reactor used in this work. Details pert aining to this reactor can be found in the master’s thesis by M. Smith [63]. The sus ceptor is heated by a radio frequency (RF) generator which drives an i nduction coil that surrounds the re action chamber as shown. In this configuration only the substrate, whic h is placed on the SiC coated graphite

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39 susceptor, is heated. Therefore, ideally re actions take place on the substrate surface only although some deposit forms on the quartz cold-wall region. Gas Inlet Wafer Susceptor Gas Exhaust Reaction Chamber RF Coil Vacuum System Boundary Layer Cooling water jacket Gas Inlet Wafer Susceptor Gas Exhaust Reaction Chamber RF Coil Vacuum System Boundary Layer Cooling water jacketFigure 3.1: Basic schematic of a horizonta l-cold-wall CVD reactor growth zone. For reference a sketch of the bounda ry layer is shown. The sus ceptor sits on a quartz boat (not shown) to insulate it from the cold wall. The cooling water jacket is maintained at a temperature below the boiling point of water. As mentioned above, a CVD reactor is typi cally used to grow a single-crystal semiconductor epitaxial layer on a substrate. This is the most critical and important step for fabricating various types of devices, es pecially in SiC, where doping control along with poly-type control and def ect reduction must be obtained [5 ]. In general to epitaxially grow SiC, precursor gases such as silane and propane, which are th e sources of silicon and carbon, are mixed in a carr ier gas (typically hydr ogen) and then injected into the reaction chamber. This is a technique popularly employed in the SiC field [6] and hence most of the SiC community is equipped with silane-based CVD reactors. Thus one of the motivations for this implant annealing resear ch was the wide-spread applicability to the

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40 SiC community. The cold-wall CVD reactor used in the research was built in-house at USF and a detailed explanation is given in the following section. 3.2 USF Cold-wall CVD Reactor The reactor used for the implant annealing experiments during this research is shown in Figure 3.2. The cold-wall reactor was constructed us ing a 75mm inside diameter horizontal quartz tube, which could accommodate a susceptor that was designed to handle a maximum wafer size of two inch in diameter as shown in Figure 3.3. The overall length of the tube was 900 mm a nd was selected based upon practical heat transfer considerations and to ensure laminar flow in the growth zone [63]. Figure 3.2: Photograph of the 75 mm horizontal cold-wall reactor. Ga s inlet indicates the entrance of the gas into the reactor through a quarter-inch stainless steel gas line and exits out of the system through the 2-in ch exhaust, as shown [64].

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41 The front end of the quartz tube was clamped to the head plate via a quartz adapter and sealed with a Viton o-ring. The stainless-steel head plate was permanently clamped to the reactor housing. As shown in the picture above, the reactor was cooled with a water-cooled jacket. The graphite sus ceptor was supported by the ribs of a quartz boat, as shown, which was placed in the reac tor in the center of the RF induction coil. The susceptor was heated by the RF generato r via the induction coil, which was wrapped around the reaction tube. The graphite susc eptor was coated with SiC to prevent contaminants present in the bare graphite fr om contaminating the growth chamber [65]. The temperature of the susceptor was meas ured by focusing an IR pyrometer at a circular indent in the back of the sus ceptor. A standard me thod for calibrating the temperature of the susceptor was by performing a Si-melt test. In this test, a piece of silicon was placed in the “sweet spot” of th e hot zone (i.e., where the sample position during annealing and growth is) and the sus ceptor heated until the silicon melted, which is at 1410C under STP conditions. The pyromet er reading at the melt temperature was then recorded and the difference between the actual temperature (1410C) and the measured temperature, T, noted. As shown in Figure 3.2, a mirror above the reactor was used to observe the silicon melt with the naked eye. T was then used to determine the desired set point temperature used for all implant annealing experiments. The melt test was periodically repeated to ensure ma ximum temperature accuracy throughout this research.

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42 Figure 3.3: Photograph of the SiC coated susceptor supporte d by ribs of a quartz boat. The exhaust end of the tube was clamped to a quartz end cap, which also provided the transition from the reaction tube to the gas exhaust system. The exhaust system was connected to a dry pump via a pressure tran sducer and throttle valve. A programmable logic controller (PLC) and personal computer were designed and constructed to allow fail-safe safe operation of gases, reactor pur ging, gas metering, and temperature control [63]. Numerous sensors have been incorporated into the control system to ensure safe operation of the CVD reactor during processing. When the sensors are activated, the system shuts down all gases and the heating source, and Ar is pur ged through the reaction tube. The sensors for the c ontrol system include hydrogen and HCl gas sensors, a door sensor, and a cold water jacket flow sensor. The fault of any of these sensors results in immediate system shutdown as noted above. Th e details of the cont rol system can be found in MS thesis from T. Schattner’s [66]. There were two basic modes of operation for the reactor system mentioned above; ‘purge’ mode and ‘process monitor’ mode. Duri ng reactor start-up the system is in purge mode and an initial vacuum test is first performed to ensure that there were no leaks in the system. This was done by pumping down th e reactor to below 500 mTorr. The tube

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43 was then brought back to atmospheric pressure by trickling a small flow of hydrogen into the inlet (with the vent valve closed to prev ent outside air from entering the system from the exhaust port). Once the pressure reached near atmospheric pressure, the main hydrogen purge was initiated which opens th e vent valve and flows a high rate of hydrogen through the reactor. This ensures positive pressure in the system so no air can back fill the tube. After completion of the pump cycle, and to initiate the annealing process schedule, the system is switched over to ‘process monitor’ mode. In this mode the annealing process, which is explained in the following section, was performed. The process was manually controlled by the ope rator with the help of the Labview™ computer interface [63]. This program enable d the operator to set desired gas flows and the temperature set points required for the a nnealing process. Once the annealing process was finished the system was brought into purge mode. In this mode, hydrogen was purged through the reactor for 30 seconds, wh ich purged the process gases from the reactor. This was followed by a shut down of the RF generator under an Ar purge resulting in a cool down of the sa mple for approximately 30 minutes. The switches on the control panel open a nd close the valves for the various process gases and mass flow controllers (MFC ) regulate the gas flow. The flows were set by the Labview™ program which also controls the RF generator power level. To operate the system in low pressure; the pressure tr ansducer was activated by opening the poppet valve via a switch on the control panel. The transducer was connect ed to a pressure controller, where the signal was compared to the set point pressure. The error signal is received by the throttle valve, which then varies the angle of this butterfly valve to attain

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44 the desired pressure. Details of this portion of the reactor system can be found in the MS thesis of M. Smith [63]. The gas handling system mixes the proce ss gases in a gas manifold. A detailed layout of the overall sy stem is given in reference [63] The manifold allows for three basic functions: routing of pro cess gases to the reaction tube, injection of purge gases to the reaction tube, and establishm ent of process gases to the vent. The vent side allowed the gases to be vent ed without having to flow them through the reaction tube, which allows the operator to establish steady-state gas flow prior to grow th. In both purge and process monitor modes the venting of proces s gases is possible. But the routing of process gases to the reaction tube is enabled only when the system is in process monitor mode. This is done to avoid gas flow th rough the system when it was not properly configured. A separate welded stainless steel line was used to connect each gas source to the gas manifold. Only the silane gas a nd hydrogen feeds had additional features incorporated. The silane source was connected to a separate purge system where Ar was used to purge the line to ensure that there was not any unwanted air in the line before or after silane flow was established. Also utmo st care was taken to make sure proper start up and shut down procedures for handling silane gas. The silane line was purged with argon before the line was pressured with silane during the start up and vice-versa when the system was shutdown. In the case of the hydrogen source, hydroge n was fed through a palladium purifier, to purify the hydrogen above VLSI grade. Though this is of less relevance for implant annealing experiments, where argon is used as the carrier gas, nevertheless this again helps in the reduction of contaminants in the reactor prior to

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45 annealing. A detailed explanation of the a nnealing process is given in the following section. 3.3 Post Implant Annealing Experiments As mentioned in the previous chapter, high temperature annealing of ion implanted SiC samples must be performed to repair the crystal damage caused by the high intensity ion bombardment during implan tation. Thermal annealing is needed to electrically activate the dopant s by moving them from intersti tial to substitutional lattice sites. It is well known that during high-temperature annea ling of implanted SiC, Si atoms may evaporate from the wafer leading to a se vere degradation of the surface called step bunching [67]. The silane overpressure model, which was explained in the previous chapter, is that this can be suppressed by the exchange of evaporating Si atoms with vapor phase Si supplied by the cracking of s ilane gas over the surface to be annealed. Earlier work presented by Saddow et. al discusses an implant annealing process under atmospheric pressure conditions in a similar cold-wall CVD system [68]. However, the formation of silicon droplets on the annealed surface was an issue. Based on the approach in this prior work, implant anneals were pe rformed in a silane-based CVD reactor and carried out at low-pressure (around 150 Torr). This is because a shift in gas phase equilibrium occurs under low pressure, which helps to suppress Si cluster formation in the gas phase during sample annealing. Hen ce the probability of Si droplet formation should be reduced during implant annealing if the process is transferred to low-pressure process conditions.

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463.3.1 Ion Implanted Samples Two sets of wafers were used for this work. A 2”, high-purity, semi-insulating 4H-SiC wafer with an 8 miss-cut toward s [11-20], designated W1, was implanted at Cree, Inc. with 27Al+ at 650C in dual doses of 2 x 1013 cm-2 at 200 keV and 4 x 1013 cm-2 at 360 keV. Implantation was performed thr ough a thin 500 passivating film of SiO2. An SRIM simulation was performed to predic t and to ensure a box profile for the doping profile. Secondary Ion Mass Spectrometry (SIM S) was also performed to monitor the actual profile of the implanted sample. SIMS for this particular sample was performed at Max Planck Institute, Stuttgart, Germany on a Time of Flight SIMS (TOF-SIMS) instrument. Figure 3.4 shows the doping profile predicted by SRIM and SIMS analysis done on the as-implanted sample. 0.0E+00 5.0E+17 1.0E+18 1.5E+18 2.0E+18 2.5E+18 0200400600800 Depth (nm)Al Concentration (cm-3) SIMS SRIM Figure 3.4: Comparison of doping profile vs depth pred icted by SRIM and SIMS analysis done on the as-implanted sample.

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47 The wafer was then diced into 8mm x 8mm samples and the samples cleaned in acetone and isopropanol and then RCA cleaned. All surface characterization reported in this research was performed on these samples (including hot-wall processing described in the next chapter). Since the implants were formed directly in the surface of a semiinsulating substrate, these samples were suitable for morphology study only and not for electrical activat ion assessment. The second sets of samples implante d at CNR-IMM by Dr. Roberta Nipoti in Bologna, Italy, designated W2, were from a 4H-SiC (0001) Si-face Cree epitaxial wafer, with an 8 miss-cut towards the [11-20] direction. The doping concentration and thickness of the epilayer was ~3 1015 cm-3 and ~5 m, respectively. Aluminum was used as mask to protect the areas that we re not supposed to be implanted. A 1.7 MV Tandetron accelerator was used to implant Al+ into the unmasked regions. A thin oxide passivation layer was formed prior to implan tation in order to pl ace the peak of the implantation Gaussian profile at the surface of the sample. The implanted profile, as determined by SRIM, had a box shape with an ion concentration of 8 1019 cm-3 and an implant depth of 0.2 m from an integrated dose of 1.75 1015 cm-2 as shown in Figure 3.5.

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48 Figure 3.5: Predicted SRIM doping profile of the ion implantation performed on samples used for electrical characterization. In spite of the high fluence value, the crystal damage was reduced because the implantation was done at the elevated temper ature of 400C. The implantation performed was a random implant in which the ion beam impinges on the 4H-SiC crystal at 15 with respect to the <0001> axis while remaini ng within a plane at 12 from the {11-20} crystal plane. After the implantation pro cess the aluminum mask and passivating SiO2 film were etched off from the sample surface. The wafer was then diced into pieces so that various sections of the wafer coul d be processed under differing annealing conditions. All electrical char acterization for the cold-wall implant annealing process was performed on these samples.

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493.3.2 Post Implantation Annealing Process A silane based cold-wall CVD reactor desc ribed in the previous section was used for the work reported in this chapter. The samples were placed on a SiC-coated graphite susceptor as shown in Figure 3.6. 2”groove Ar + SiH4 By Products 2”groove Ar + SiH4 By Products Figure 3.6: Cross-sectional view of the gra phite susceptor placed on the quartz boat. The sample was placed in the center of the two in ch recessed groove as shown in the figure. The susceptor was heated up to the de sired anneal temperature via an RF induction coil. In order to verify the silane overpressure process, preliminary annealing experiments called set 1 were performed to compare silane overpre ssure process with argon annealing process. These anneals we re performed at 1600C and 1650C. After testing the process stab ility set 2 anneals at various te mperatures from 1600 to 1700C were performed at a process pressure of 150 Torr. The proces s schedule that was developed during this work is as shown in Figure 3.7.

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50 Ar FlowAnnealing T (C)T1 30 1 30 Ar Purge 10 6 0 10 0 Ar (slm) SiH4* (sccm) 760 150 t (min) Ar FlowAnnealing T (C)T1 30 1 30 Ar Purge 10 6 0 10 0 Ar (slm) SiH4* (sccm) 760 150 t (min) Figure 3.7: Implant annealing process schedu le for cold-wall CVD processing, indicating gas flow timing versus sample temperature. The silane flow indicated here is for the 1600C annealing process and corresponds to 3% silane in 97* UHP Ar. A 6 slm argon carrier gas flow was cons tantly flown in the reactor and the pressure maintained at 150 Torr until sample cool down. 3% silane premixed in ultra high purity (UHP) Ar was introduced into the reactor via an Ar carrier gas as shown in Figure 3.6, at a temperature of 1490C, which is ~80C above the Si me lting point of 1410C at standard temperature and pressu re (STP). This was used to prevent the formation of Si droplets on the surface during the heating cycle. Depending on the desired anneal temperature, it took 6 to 8 min to reach the anneal set point temperature after turning on the RF source. Once the set-point temper ature was reached a 30 min anneal was performed. To avoid Si droplet formation dur ing cool down, the silane was turned off after 30 min of annealing and the temperat ure reduced to a surf ace temperature of

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51 ~1490C. This was done to ensure that all sili con was purged from the reactor before cool down to temperatures below 1410C. After 1 min at this temperature the RF source was turned off and the sample cooled in 5 slm of Ar flow until room temperature was reached. The cool down time was approximately 45 min and determined by the annealing temperature and Ar flow rate. The samples were then removed from the reactor and surface characterization perfor med using SEM and AFM. 3.4 Experimental Results In this section details concerning ho w the post implant annealing process was characterized is given. The common problem with annealing SiC implants using other methods is a degradation of the surface caused by the selective evaporation of Si from the surface of the crystal. It was determined duri ng this work that the most useful means to characterize the annealing process was to first observe the surf ace under the optical microscope to see if large defects, caused by the annealing process, were evident. Once a sample appears to be smooth at this resolu tion, the sample was studied with Secondary Electron Microscopy (SEM) and atomic force microscopy (AFM). AFM proved to be the most useful technique sinc e it can provide a quantitati ve measure of the surface roughness. The experimental methodology used during this work was simply this – anneal implanted samples in a silane ambi ent and observe for which flow rates the resulting surface was smooth. Too little silane results in step-bunching, due to the high evaporation rate of Si from the surface, and too much silane results in Si condensation on the surface, which is easily observed as Si droplets. Details of this methodology are provided after a discussion of the surface characterization methods used is completed.

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523.4.1 Surface Characterization The surface morphology of all annealed samples was studied with the help of optical microscopy, SEM and AFM. Most of the SEM images in this work were taken on a Hitachi 800 field emission SEM at USF. For all the SEM data collected, the sample was tilted away from the detector and slightly ro tated. This was necessary because electronic scan lines from the SEM digital capture software made it hard to determine if step bunching was present on the surfac e, especially if the steps were aligned with the scan noise. More importantly the su rface morphology was best rev ealed by tilting the sample away from the detector since this helps to reveal three-dimensional features compared with 90 incident plan-view micrographs. The AFM scans were performed on a Digital Instruments Nanoscope Dimension model 3000 AFM. It was operated in tapping mode which causes less damage to the cantilever tip s. In the event that the cantilever scan direction completely coincides with the step bunching orientation, th e scan image will be incorrect. Hence to ensure that the correct data on step bunched surfaces was obtained, scans were performed with the cantilever oscillating at two di fferent angles (i.e., 0 and 90). For all samples studied the AFM scan s were performed on two-three different locations on the sample and an averag e RMS roughness noted to monitor any surface degradation caused by the hi gh-temperature anneals. As mentioned in section 3.3.2, for dire ct comparison between argon annealing and annealing with the silane overpressure proces s developed during this work, anneals were performed with both processes at 1600C and 1650C. Two samples with the same implantation profile were annealed in a J.I.P.ELECTM annealing furnace at 1600C and 1650C for 30 min at a pressure of 1,000 Torr in a high purity Ar ambient. The surface

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53 resulted in severe step-bunching as wa s evident from plan view SEM and AFM investigations. Figure 3.8 shows SEM and AFM data for the sample annealed in Ar at CNR-IMM at 1600C. The RMS roughness was found to be 13.76nm. (a) (b) Figure 3.8: J.I.P.ELECTM furnace annealing performed at IMM in Bologna, at 1600C for 30 min in high purity Ar: (a) Plan view SE M micrograph of the surface morphology. The step bunching on the sample surface is clearl y evident. (b) AFM data of the surface morphology of the annealed surface had an RMS roughness of ~ 13.76 nm. The AFM scan area was 10 m x 10 m. An identical implanted sample was ann ealed at 1600C using the cold-wall CVD silane overpressure CVD process described here. No step bunching or any kind of surface morphology degradation was observed after ann ealing at this temperature. Figure 3.9 shows the SEM and AFM data after these sila ne overpressure anneals were performed. The RMS roughness of the surface obtained from AFM was 0.38 nm, compared to 13.76 nm in Ar.

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54 (a) (b) Figure 3.9: Surface analysis after silane ove rpressure annealing at 1600C for 30 min: (a) Plan view SEM micrograph of surface mo rphology at 5000x. (b) AFM data of the surface morphology. RMS roughness ~ 0.38 nm. The AFM scan area is 10 m x 10 m. For the 1600C process to produce a smooth surface, it was found empirically that 10 sccm of silane flow was required. The correct silane flow was determined by monitoring the surface with the SEM by ensu ring that no step bunching or any surface morphology degradation was present after ann ealing at each temperature. Figure 3.10 illustrates the experimental methodology that was used for all of the research work reported in this dissertation. The surface morphology of samples annealed at 1650C for various flow rates of silane are shown in th is figure. SEM images of samples annealed with insufficient silane flow (10 sccm) had step bunching as shown in Figure 3.10 (a). When excessive silane flow was used (20 sccm) Si droplets were observed on the surface when viewed under the optical microscope (Figure 3.10 (c)). A smooth surface was obtained for an optimum flow of silane (15 sccm) as shown in Figure 3.10 (b). For each anneal conducted a similar set of data was taken and the annealing process for the smooth surface recorded along with its corresponding surface roughness as monitored via AFM.

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55 (a) (b) (c) Figure 3.10: Illustration of th e experimental methodology used during this research work. Observed surface morphology of samples anneal ed at 1650C for increasing silane flow values of (a) 10 sccm (step bunching) (b) 15 sccm (smooth, specular surface) and (c) 20 sccm (Si droplets). Data reported from th is point forward corre sponds to the process shown in image (b). AFM analysis was then performed on the post-implant annealed samples to gather quantitative data and to make sure the SEM re sults were correct. A set of AFM data taken for each process temperature under optimized silane flow are shown in Figure 3.11 (minus the 1600C data already shown in Fig. 3.9). (a) (b) (c) Figure 3.11: Post-implant annealed AFM da ta at (a) 1650C, (b) 1675C, and (c) 1700C. The AFM scan area was 10 m x 10 m. RMS values shown in Fig. 3.12.

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56 The average RMS roughness obtained from the AFM scans was computed based on 3 surface scans per sample. The annealed surface showed an average RMS roughness of less than 0.69 nm (at 1700C) indicating th at the surface did not suffer any postimplantation annealing degradation. Figure 3.12 shows a plot of average RMS roughness vs. annealing temperature. Figure 3.12: Plot of average RMS surface r oughness vs. temperature after annealing in the cold-wall CVD configurati on as measured with AFM. 10 m x 10 m scan size used for all data points. As mentioned above, any further increase in the silane flow would normally result in Si droplet formation due to excess Si in the vapor phase. Occasionally these droplets were seen on the edges of the samples, most likely due to temperature gradients across the sample due to radiative cooling of th e sample edge. Figure 3.13 shows an extreme example of such a situation. The SEM image shows that the droplet formation was mainly at the edges of the sample. A highe r magnification image of a droplet is also shown for reference.

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57 (a) (b) Figure 3.13: Plan view SEM micrograph of a SiC sample annealed at 1650C in 15 sccm of silane flow. (a) low magnification image show ing Si droplets at the edge of the sample and (b) a higher magnification image of one of the Si droplets. The magnification is indicated on each micrograph. Si droplet formation, while reduced in occurrence under low pressure conditions, is one of the draw backs of the cold-wall system. Also si nce it is believed that for maximum activation of Al dopants, it is bett er to anneal at temperatures up to 1800C [67, 69] the maximum available power on the RF generator limited our cold-wall experiments to 1700C. This limitation is due to the use of cold-wall reactor geometry and, hence, further implant annealing studies were conducted in a hot-wall CVD reactor, which is explained in detail in the next chapter. 3.4.2 Comparison with Theory A plot of the experimentally determined si lane flow rate, determined for different temperatures for the cold-wall CVD process, is shown in Figure 3. 14. A comparison with

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58 the theoretically computed silane flow rates (assuming (PP)Si = 10* (VP)Si), as discussed in Chapter 2, is shown for comparison. Figure 3.14: Comparison of experimental and th eoretical silane flow rates for the coldwall CVD reactor configuration. An exponential curve fit was applied to the data and is also shown (lines in figure). Note the trend is exponential with increasing temperature. Based on the data points shown in Figure 3.14, a exponential curve fit was applied to the data. The silane flow rate, expressed as an exponen tial function of the form bx y ae for both the theoretical and e xperimental data is given as 214(1.910*)4.510*T the (3.1) 36(9.510*) exp2.510*Te (3.2) where th is theoretical flow rate of silane and exp is experimental flow rate of silane. As seen from the plot and equations, the assumption that the partial pressure of Si in the gas phase is an order magnitude higher than the Si vapor pressure is clearly not correct. There are several explanations for this large discrepanc y, all of which will result in a larger flow

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59 of silane being required to ach ieve the proper balance betwee n Si partial pressure and Si vapor pressure. These are as follows: a. Reaction rate limitations: The residence time of silane over the wafer is less than the time required for the reaction to occur, therefore incomplete cracking of Silane occurs. b. Mass transport limitations: Si from cracked silane has to diffuse through the boundary layer in order to replace the evap orated Si. The time required for this to occur may be longer than the residence ti me of the silane over the wafer, thus resulting in less Si present at the wafer surface. c. Temperature gradients: In cold-wall there is a large temperature gradient above the wafer surface, therefore only a small fr action of silane gas passing near the sample surface is cracked. d. The calculations assume thermodynamic equilibrium: In order to compute the theoretical silane flow th ermodynamic equilibrium was assumed. However, CVD is not an equilibrium process hence gross errors between experiment and theory are expected. In order to explain the difference in the ex perimental and theoretical data and take into account all of the above possible mechanisms, a generic term called the cracking efficiency, was defined and is calculated as exp th (3.3)

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60 It was seen that cracking efficiency vari ed with temperature, with the cracking efficiency increasing with temperature, as ex pected. Further analysis and experiments are required to determine precisely what m echanisms are responsible for the observed discrepancy which is beyond the scope of this current research. 3.5 Electrical Characterization Electrical device processing and characteri zation of the annealed samples were conducted at CNR-IMM under the directio n of Dr. Roberta Ni poti by Dr. Fabio Bergamini [72]. As mentioned in the previ ous section electrical characterization was performed on the samples designated as W2. Before implantation, an Al mask was put down on top of a passivating oxide layer. Photolithography was used to pattern the Al mask to mask the region that was not to be implanted. The mask layout used for this process is shown in Figure 3.15 (a). After implantation and removal of the Al/SiO2 mask, the samples were cleaned and then annealed with the silane overpressure process described already. Figure 3.15 (b) shows an SEM image of one of the patterned surfaces after annealing. Before the formation of the metal contacts on the W2 samples was performed, reactive ion etch ing (RIE) was used to remove ~40 nm from the wafer surface. The purpose of this etching step wa s to prepare the surface for better ohmic contact and to set the peak of the implantation profile at the surface. Contacts to form circular 150 m and 350 m diameter diodes, 400 m square Van der Pauw (VdP) devices and Transmission Line Measurements (TLM) structures were defined by wet etching of a 420 nm thick sputtered Titanium /Aluminum (Ti/Al) film. A backside contact

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61 was formed by evaporating 300 nm of Ni Thermal annealing of both contacts was carried out during the same process at 1000C for 2 min in vacuum. Schottky Diode p+/n Diode Implanted Region TLM Contacts Schottky Diode p+/n Diode Implanted Region TLM Contacts (a) (b) Figure 3.15: (a) Photolithographic mask layou t of the device geometry used to form electrical devices for charac terization of the annealing pr ocess. (b) SEM micrograph of etched mesa on the W2 surface after an nealing and prior to metallization. Current-voltage (I-V) measurements were performed at IMM Bologna on p+/n diodes and Van der Paw (VdP) devices at 28 C using a computer controlled parametric characterization system. The characterization unit was equipped with a Micromanipulator MM6620 semiautomatic probe station, a Te mptronic TP315B hot chuck, a Keithley K707 switching matrix (equipped with 7072 and 7174 semiconductor cards) and a Keithley K90 I-V measuring system, comp osed of a Keithley K2361 synchronism controller and four Keithle y K238 source measure units. Two sets of electrical characterization were performed. First pr eliminary characterizat ion was performed on samples annealed at 1600C and 1650C (Set 1). For both of these anneals the silane flow was held constant at 10 sccm. As mentioned in section 3.2.2 this was done to test the

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62 process stability over a small (50C) temper ature range and it was expected that slight step bunching would be observed at the higher annealing temperature due to the increased vapor pressure of Si in the SiC lattice. However, the second set (Set 2) of electrical characteri zation was performed for a temper ature range of 1600C – 1700C, where the silane flow was increased with incr easing temperature so as to eliminate stepbunching as described earlier. The measured devices were homogene ously distributed on the sample surface. Typical forward bias J-V characteristic curves for 350 m diameter diodes on set 1 sample, annealed at 1600 C are as shown in Figure 3.16. Figure 3.16: Electrical charac terization data taken on p+-n implanted diodes. Forward IV data shown from typical F1 (no excess current bump) and F2 (excess current bump) 350 m diodes. F1 devices displaye d a turn-on voltage of 1.75V with an ideality factor of less than 1.2. Two significantly different trends on the forward J-V characteristics were observed. One trend, labeled F1, corresponds to a fam ily of diodes with very weak generation-

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63 recombination current and an almost exponen tial trend between curr ent and voltage with an ideality factor of up to 1.2. The second trend, labeled F2, corresponds to diodes that showed an “excess current component” which is often observed in the case of ion implanted SiC diodes [70]. The excess current component is generally attributed to the presence of defects due to the ion implanta tion process in the junction depletion region [71]. The fact that at 1600C a majority of the diodes did not show an excess current component, as shown in Table 3.1, is a promis ing result from the point of view of being able to reduce the formation of ion beam damage induced defects using the silane overpressure process. The trends F1 and F2 were observed for 97% of the 136 measured diodes. The percentage distribu tion of diodes that followed F1 and F2 is also given in Table. 3.1. Table 3.1: Summary of measured diode pe rformance vs. anode size [72] 56 diodes = 150 m 80 diodes = 350 m Anneal Temp. (C) F1 F2 F1 F2 Rsh ( ) ( -cm) 1600 93 % 5% 60% 35% 1 106 11 It was also observed that the turn-on volta ge for the F1 diodes was about 1.75 V, which is a typical value for a good ion implan ted diode [70]. Below this turn-on voltage both F1 and F2 diodes have a generationrecombination current a few orders of magnitude lower than the corresponding values published in the literature [70, 71]. This again was a promising result from the point of view of the energy dissipation when the

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64 junction is in the off-state. For a forward bi as voltage above 2.5 V the F1 and F2 curves overlapped and followed an exponential trend with an ideality factor up to 1.2. The reverse bias trend for the F1 and F2 diodes did not, however, show any noticeable difference as shown in Figure 3.17 (a). The histogram of the grouped reverse bias characteristics for 350 m diameter diodes at –100 V is as shown in Figure 3.17 (b). The spread of the values is very low and the average leakage current density was (9.7 0.4) x 10-9 A/cm2. A majority of the diodes disp layed a leakage current of ~ 10 nA/cm2. (a) (b) Figure 3.17: Electrical data taken on p+/n diodes annealed at 1600C in silane. (a) Typical J-V reverse characteristics at -100V. (b) Histogram of the reverse current density values at –100 V fo r 75 diodes of 350 m diameter. Average leakage current density was (9.7 0.4)10-9 A/cm2, and the spread of the values was very low. Table 3.1 also shows the sheet resistance and resistivity values of the implanted layer. An average sheet re sistance on the order of 106 / at room temperature was measured on the 400 m x 400 m VdP devices. A Cameca IM S-4f spectrometer SIMS

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65 tool was used to measure the Al doping profile within the VdP area in the fully processed SiC wafer. An 8 keV O2 + primary beam having 150 nA total current was swept over a 125 125 m2 sputtering area. The secondary ion signal was collected from a central circular spot having 50 m diameter as shown in Figure 3.18. From SIMS analysis using the half maximum width (HMW) the thickness of the implanted layer was found to be 110 nm with Al doping concentration of 5 1919 cm-3. Using these values, the resistivity was calculated to be 11 -cm, which is an order of magn itude higher than expected with respect to the best electrical activation results published in the literature [73]. The onstate forward voltage drop at 100 A/cm2 was about 4.2 V, and the on resistance at the same current density was 12 m -cm2 diode which includes resi stance contributions from the bulk, the epilayer, the implanted layer, and both front and back contacts. Figure 3.18: SIMS measurement of the Al profile on the full processed SiC wafer. Measurement was done inside the post-implant annealed sample inside the active area of a VdP device as shown in the inset.

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66 Forward and reverse characteri stics, as well the breakdow n voltage values, of these Al+ implanted p+/n diodes annealed in silane ambient were comparable with the best values obtained for similar implanted diodes but annealed in an Ar ambient [74, 75]. Moreover, the spread of the diode performan ces was very small, indicating a stable and robust process had been achieved. On the downside the high resistivity value of the implanted layer suggested the need to perform more studies to improve the electrical efficiency of the annealing process in silane ambient. Electrical characterization was repeated on samples a nnealed using the cold-wall process at temperatures of 1600C, 1650C 1675C and 1700C (Set 2). Results obtained were similar to the Set 1 samples. The measur ement statistics and process yield for this set of experiments are listed in Table 3.2 A ll electrical characteri zation was performed at room temperature and the experimental set-up has an instrumental current floor ranging from 10-13 to 10-12 A, depending on the measurement configuration. Table 3.2: Statistics of the measured devices p+/n diodes p+ = 61019 cm-3 n = 31015 cm-3 = 150 m Annealing temperature (C) Measured diodes diode yield Measured VdP device 1600 8 78% 2 1650 100 80% 10 1675 9 75% 8 1700 20 65% 2 Typical forward and reverse bias characteri stics taken on the di odes are as shown in Figure 3.19(a) and (b), respectively. For temperatures > 1675C and a bias < 1.65 V

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67 the diode forward current is below the instrument limitation (i.e. 10-13 A), while for a bias > 1.6 V the diode conduction could be modeled as an abrupt p+/n junction with a very low-level injection current and an ideality factor of < 2. For annealing temperatures < 1650C the forward current was generally hi gher than the instrument current floor at any bias value and could be modeled as that of an abrupt junction only for a bias of > 2.1 V, with an ideality factor of < 2. Figure 3.19 (a) also shows that the diode series resistance was more prominent for samples annealed at lower temperatures (i.e. < 1650C). The diode reverse conduction (Figur e. 3.19 (b)) was on the order of the instrumental current floor (i.e. 10-12 A) for the samples annealed at temperatures > 1675C and increased for decreasing post -implantation annealing temperature. In summary these results indicated that as the annealing temperatures were increased, there was higher electr ical activation of the implanted Al+ ions, which corresponds to better electrical conduction of the p+/n junction. Figure 3.19: Typical p+/n diode forward bias (left) and re verse bias (right) characteristics, measured for various post-implantation anne aling temperatures in silane for Set 2 samples.

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68 Figure 3.20 shows the trend of the sheet re sistance values with respect to the postimplantation annealing temperature. As seen in the figure the sheet resistance value for samples annealed in non-optimized silane flow (Set 1) was slightly higher than the set 2 samples which correspond to optimized flow. Also the data shows that for increasing annealing temperature, the sheet resistan ce decreased to a minimum value of 70 k Figure 3.20: Comparison of set 1 and set 2 sh eet resistance of the implanted layer versus post-implantation annealing temperature. Set 2 data corresponds to optimized silane flow conditions. As can be seen from Figure 3.20, high sheet resistance values remains an issue for the silane overpressure annealing process developed here. SIMS analysis of samples annealed in silane showed that there was so me removal of the material from the surface. This could have occurred due to the pres ence of hydrogen, which results from the cracking of silane. This is just a prelimin ary hypothesis and more study on this was done during the hot-wall process development which is explained in detail in the next chapter.

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693.4 Summary Post-implantation anneals in an optim ized silane ambient performed on Al+ implanted 4H-SiC samples in a cold-wall CVD reactor revealed no step bunching or surface morphology degradation up to 1700C. Electrical characteri zation conducted on the annealed samples showed highly reproducible p+/n diode performance and yield. Unfortunately the formation of silicon droplets was still an issue, especially at the edges of the sample, during some of the anneals. Th is could be due to th e non-uniformity of the temperature profile across the sample in th e cold-wall reactor because of higher cooling rates at the die edge due to radiation. This problem may be reduced by the development of a hot-wall CVD annealing process. Also there was an issue concerning the diodes studied having a higher than expected sheet resistance value of the implanted layer. Since this problem became evident at the end of th e cold-wall research portion of this work, special attention was paid to this issue during hot-wall implanta tion annealing process development which is discussed in the next chapter.

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70CHAPTER 4 IMPLANT ANNEALING IN HOT-WALL CVD REACTOR There are different types of CVD reactors ba sed on their design and, in particular, orientation and hot zone environment. Chapter 3 focused on annealing research conducted in a cold-wall, low-pressure SiC CVD reactor. One of the major drawbacks of the cold-wall system is the difficulty in maintaining a uniform temperature across the entire wafer surface due to the high cooling rates at the susceptor edges compared with the central region. This was the main reason for the formation of Si droplets on the periphery of the many of the samples that we re annealed in the cold-wall CVD reactor (Chapter 3). This temperature uniformity issue can be eliminated if the entire hot zone is maintained at a uniform temperature, which is possible in a hot-wall CVD configuration. 4.1 Hot Wall CVD In the hot-wall CVD system, the susceptor completely surrounds the substrate to be annealed, thus eliminating any temperature gradients in the hot zone (or, at least, reducing them as much as possible to a minimum value). This is accomplished by supporting the susceptor by a carbon foam insulation material which encases the susceptor and provides adequate thermal in sulation between the hot zone and the quartz tube wall. The insulation severely reduces radiation losses from the heated susceptor and

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71 also providing an environment that decreases the particle nucleation in the gas phase [76]. Thus a hot-wall CVD system not only offers good uniform heating efficiency, but also a high cracking efficiency of the reactant gases [77]. Figure 4.1 shows a basic schematic of a horizontal-hot-wall CVD reactor. In this configuration, the ceiling, walls and the bottom of the susceptor, all of which are made of graphite, are heated with a radio frequenc y (RF) induction coil. The susceptor used consists of two pieces – a top part and a botto m part. The top part is SiC coated while the bottom part is TaC coated. The coating serves the purpose of preventing the leakage of C or other impurities from en tering the growth system. Afte r assembling the susceptor and placing it in the foam insulation, the compone nts are slid into the quartz tube and the sample is placed on the bottom susceptor. The top susceptor is shown to have an angled ceiling, which will be explained in detail in section 4.2. RF Coil SiC coated Susceptor Graphite foam insulation Inert cooling gas inlet Reactant gas inlet Quartz tube By product gas outlet to pump SiC Poly plate TacCoated Susceptor Substrate RF Coil SiC coated Susceptor Graphite foam insulation Inert cooling gas inlet Reactant gas inlet Quartz tube By product gas outlet to pump SiC Poly plate TacCoated Susceptor Substrate RF Coil SiC coated Susceptor Graphite foam insulation Inert cooling gas inlet Reactant gas inlet Quartz tube By product gas outlet to pump SiC Poly plate TacCoated Susceptor Substrate Figure 4.1: Schematic drawing of the horizo ntal hot-wall CVD reactor used in this research with an angled top ceiling.

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72 A major advantage of the hot-wall CVD co nfiguration is that the isothermal design of the susceptor assembly helps to reduce the RF power requirement For example in the hot wall system an RF power of 17 kW power was required to achieve an annealing temperature of 1700 C versus 29 kW to obtain the same temperature in the cold-wall system, a 42% decrea se in RF power. In addition to the advantages of an isothermal hot zone, where a reduction in Si-droplets at the periphery of the sample is expected, most SiC researchers have access to a silane-based hot-wall CVD reactor. Therefore research into the post-implantation annealing of SiC in hot-wall systems was undertaken and is reported in this chapter. Th e hot-wall CVD reactor used in the research was built in-house and a detailed explanatio n is given in the following section. 4.2 USF Hot-Wall CVD Reactor The first hot-wall reactor used, designated as the “20 mm” reactor (based on the die size that can be processed) had the same tube design as the cold-wall CVD reactor. As explained in the last section a graphite foam insert containing the hot-wall susceptor was used as the hot zone instead of the susceptor sitting on the quartz boat as explained in the previous chapter. Initia l implant annealing work at temperatures up to 1600C was performed in this 20 mm hot-wall reactor. Ho wever, since the reactor was not designed for hot-wall operation but, rather, adapted to it, the quartz tube with the cooling water jacket cracked due to the thermal gradient at the high temperatures needed for implant annealing (indeed this was mostly due to a lo ss of insulation quality after excessive wear and tear on the system). In addition th e “20 mm” reactor design was limited to a maximum die size of 2 cm, which is not suita ble for a 2-inch or higher diameter wafer

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73 processing. Considering all th ese criteria, a new-large scal e, 100 mm hot-wall reactor with an improved design (suc h as the elimination of the c ooling water jacket, glass to glass seals, etc.) was built. Figure 4.2 sh ows a photograph of the “100 mm” hot-wall CVD reactor during high-temperature operation. Figure 4.2: Photograph of the “100 mm ” horizontal hot-wall reactor during hightemperature operation. The graphite foam/sus ceptor insert shown here can hold up to a 2-inch wafer while use of a different in sert can accommodate a 4 -inch wafer. The front end of the quartz tube was clam ped to a stainless-steel S. S. mounting hardware head plate via a stee l ring and sealed with a Vito n O-ring. The head plate was cooled with circulating chilled water. The ba ck end of the quartz tube was clamped to a stainless-steel drum via an identical stainles s-steel ring and also sealed with a Viton Oring. The drum also comprises the exhaus t port through which r eactor by-products are

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74 evacuated out of the system via a poppet valu e and dry pump where they are sent to a scrubber. A stainless-steel door was attached to the drum via hinges and was sealed with Viton O-rings and a C-clamp. A photograph of the hot-wall susceptor is shown in Figure 4.3 (a). The SiC polyplate with recess sits on the bottom Tantalum Carbide (TaC) susceptor. Both susceptors were enclosed by insulating grap hite foam as shown in Figure 4.3 (b). (a) (b) Figure 4.3: Photograph of the (a) hot-wall su sceptor: top susceptor is SiC coated and the bottom is TaC coated. (b) Front end of the graphite insulating foam after assembly (susceptor is inside) showing the hole used to sight the pyrometer for measurement of the susceptor temperature. Note that the samples are loaded on a polycrystalline plate with machined recesses as shown in (a). The top susceptor, which was SiC coated, has an angled ceiling as was schematically shown in Figure 4.1. the angl ed ceiling was implemented because during epitaxial growth with the initia l flat ceiling susceptor design r eactants depleted at the inlet

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75 of the susceptor due to the high cracking effi ciency of the design. Since this is a wellknown phenomenon in CVD growth a tilt in th e ceiling was then incorporated as shown in the Figure 4.1 (in most CVD systems the floor is tilted but a titled ceiling will allow for wafer rotation, etc. which has advantag es) [78]. The result was a reduction in the depletion of the reactants at the front of the susceptor hot zone inlet with more uniform deposition on the sample. The bottom susceptor was TaC coated graphite. It has been indicated that the lifetime of the susceptors and quality of the epitaxy has been improved by using TaC coated graphite since this coa ting is more durable than the conventional SiC coating [63]. The susceptor was enclosed in the graphite foam and inserted into a quartz liner as shown in Figure 4.2. The quart z liner not only held th e insulating foam and graphite susceptor assembly together but also protected the outer t ube from damage since hot graphite foam in contact with quartz generates COX which slowly degrades the quartz making it rough and difficult to clean. The liner was placed inside the horizontal quartz tube in such a way th at the susceptor sat in the center of the RF induction coil, which heats the susceptor. Initially there was a problem with the gr aphite foam which increased the coil inductance to such a high value that the RF generator source impedance could not be matched to the coil and, hence, the RF genera tor could not turn on. In order to overcome this issue the circular insulating foam was cu t into the shape as shown in Figure 4.3, to reduce the RF load impedance so that the RF generator could turn on. Once this problem was solved the reactor was ready for initia l growth process development. The samples were loaded on top of the TaC susceptor bottom part via a polycrystalline plate, which has machined recesses. The recesses were used to prevent sample movement during

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76 growth and, in this case, post-implant an nealing. In this way a repeatable sample temperature could be achieved thus allowing a more stable process to be developed. The stainless-steel door was designed with a view port for the IR pyrometer and, after some difficulties with the window clouding during annealing, an Ar purge was implemented to keep the window clean. The temperature of the susceptor was measured by focusing the pyrometer at a circular indent on the back of the top susceptor which is SiC coated. The argon purge assembly was to minimize the coating of the view port with reactor byproducts during annealing, which wo uld cause inaccurate reading of the actual temperature by the pyrometer. Also the view port was used to perfor m the Si melt test for calibrating the temperature of the susceptor. The idea and the method behind this test was the same as explained in Chapter 3, with the only difference that instead of the mirror the view port was used to monitor the peak of the solidified Si (which had been melted and solidified before). The temperature at which the peak disappeared is the Si melt temperature (melt SiT) which is 1410C under STP conditi ons. The corresponding reading on the pyrometer was then recorded (melt readingT) and T meltmelt readingSiTT computed. T was then used to determine the desired set point te mperature used for all implant annealing experiments. The melt test was periodically repeated to ensure maximum temperature accuracy throughout this research. The gas handling system, the PLC and the pr essure controlling unit was all similar to one used for cold-wall system, as explaine d in Chapter 3. A few changes were made to the control panel and the gas handling system. One improvement that directly impacted this research was the installation of a hydr ogen purge stick on the main gas manifold. This was done to purge the gas manifold with purified hydrogen before and after the

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77 introduction of process gases. In addition to the new hydrogen purge stick, since the cross-section of the hot-zone increased new mass flow controllers (MFC’s) capable of increased flow were installed for the carrier gases (H2 and Ar) as well as the reactant gases (SiH4 and C3H8).. The basic system operating modes, namely ‘purge’ mode and ‘process monitor’ mode, were identical to those explained in Chapter 3 for the cold-wall system. Several pump and purge cycles were performed before starting the anneali ng process. This was done to ensure reduction of contamination in the reactor prior to high-temperature annealing. The details of the annealing pro cess are explained in the following section. 4.3 Post-Implant Annealing Experiments In Chapter 2 the motivation for post-impla ntation annealing of SiC was explained while the cold-wall CVD process was desc ribed in Chapter 3. Although processes developed in a cold-wall CVD apparatus pr oduced step-bunch free surfaces, there was still an occasional problem of silicon droplet formation, mostly at the edges of the sample. The reason behind this is the nonuniform temperature distribution across the samples. As explained in section 4.1, this problem can, in principle, be overcome in a hot-wall system which was the focus of the next phase of this research which is now described in detail. 4.3.1 Ion Implanted Samples Similar to the cold-wall research described in Chapter 2, two sets of wafers were used for this work. A 2-inch, high-purity, se mi-insulating 4H-SiC wafer with an 8 miss-

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78 cut towards [11-20], designated W1, was implanted at Cree Inc. with 27Al+ at 650C in dual doses of 2 x 1013 cm-2 at 200 keV and 4 x 1013 cm-2 at 360 keV. Implantation was performed through a thin 500 passivating film of SiO2. SRIM simulation was performed to predict and to ensure a box profile for the doping profile. Secondary Ion Mass Spectroscopy (SIMS) was also performe d to monitor the actual profile of the implanted sample. SIMS for this particular sa mple was performed by the surface analysis group of Prof. U. Starke at the Max-Planck Institute in Stuttgart, Germany using a Time of Flight SIMS (TOF-SIMS) instrument. Fi gure 4.4 shows the doping profile predicted by SRIM and the corresponding SIMS analysis performed on the as-implanted sample. From the figure it can be s een that the predicted and th e measured peak Al doping concentration was ~ 2.0e18 cm-3. Table 4.1 gives summary of the sample that was used for surface characterization. The wafer was then diced into 8mm x 8 mm and the samples cleaned in acetone and isopropanol and then RCA cleaned. Al l surface characterization reported in this research was performed on these samples. Since the implants were formed directly in the surface of a semi-insulating substrate, thes e samples were suitable for morphology study only and not for electrical activation assessment.

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79 0.0E+00 5.0E+17 1.0E+18 1.5E+18 2.0E+18 2.5E+18 0200400600800 Depth (nm)Al Concentration (cm-3) SIMS SRIM Figure 4.4: Comparison of doping prof ile vs. depth predicted by SRIM and the corresponding SIMS profile performed on the as-implanted W1 sample by the group of Prof. U. Starke of Max-Planck Institute, Stuttgart, Germany. The second sets of samples were impl anted at CNR-IMM by the group of Dr. Nipoti in Bologna, Italy, and are designat ed W3. These samples were from a 4H-SiC (0001) Si-face Cree epitaxial wafer, with an 8 miss-cut towards the [11-20] direction. The doping concentration and thickness of the epilayer was ~1 1016 cm-3 and ~6 m, respectively. Table 4.1 gives the implantation summary along with description of the sample W3. Table 4.1: Summary of the samples used for both surface and electrical characterization. Sample ID Description Implantation parameter Purpose W1 4H-SiC semi-insulating 2e13 cm-2, 200 keV 4e13 cm-2, 360 keV Surface Characterization W3 4H-SiC, n-type, ~1e18 cm-3 nepi, ~1 1016 cm-3 & 6 m 1.72e14, 250keV 1.5e15, 360keV Electrical Characterization

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80 The samples were diced into 1 cm x 1.2 cm pieces prior to implantation. A 1.7 MV Tandetron accelerator was used to perform blanket implantation of Al+ ions into the SiC surface. A 4300 thick oxide passivating layer was deposited prior to implantation in order to place the peak of the implantati on Gaussian profile at the surface of the sample. The implanted profile, as determined by SRIM, had a box shape with an Al ion concentration of 8 1019 cm-3 and an implant depth of 0.2 m from an integrated dose of 1.75 1015 cm-2 as shown in Figure 4.5. 0.0E+00 1.0E+19 2.0E+19 3.0E+19 4.0E+19 5.0E+19 6.0E+19 7.0E+19 8.0E+19 0.000.100.200.300.400.500.600.700.800.901.00De p th ( m ) Al concentration (cm-3) 250keV 360keV SUM SiO2 0.0E+00 2.0E+19 4.0E+19 6.0E+19 8.0E+19 0.000.100.200.30 Figure 4.5: Predicted SRIM doping profile of the Al ion implantation performed on W3 samples via 400 deposited oxid e and the inset shows the de pth profile in the sample after etching the oxide. Implants performed by the group of Dr. R. Nipoti, CNR-IMM, Bologna, Italy.

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81 In order to reduce the crystal damage during implantation, ion implantation was done at the elevated temperature of 400C The implantation performed was a random implant in which the ion beam impinges on the 4H-SiC crystal at 15 with respect to the <0001> axis while remaining within a plane at 12 from the {11-20} crystal plane. Figure 4.6 shows the measured Al doping profile ta ken by a Cameca IMS-6f spectrometer SIMS tool, on one of these as-implanted samples at the Army Research Laboratory (ARL), MD USA by Dr. M. Wood. All non-contact electrical characterization (which is explained in section 4.5) for the hot-wall implant annealin g process was performed on these samples. Figure 4.6: SIMS measurement of the Al prof ile of the as-implanted sample. SIMS data taken by Dr. M. Wood of the Army Research Laboratory, Adelphi, MD. 4.3.2 Post Implant Annealing Process After the samples were implanted and cleaned using the RCA process, the samples were loaded with the help of a poly crystalline plate with machined recess as

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82 mentioned in section 4.2 and the plate loaded into the hot-zone of the CVD reactor. For initial implant annealing runs, the argon carri er gas flow was based on the carrier gas flow used for the baseline process for epitaxial growth. In the case of epitaxial growth in the cold-wall system 10 slm of hydrogen car rier gas was flown to obtain the baseline growth process for 4H-SiC [63]. This was rais ed to 40 slm [78] for the standard baseline process in the upgraded hot-wall system, whic h was four times the in itial gas flow (this change makes sense since the hot-zone cross-sectio n also increased by a factor of 4). Hence for initial implant annealing experiments 25 slm of argon was constantly flown in the reactor and the pressure maintained at 150 Torr until cool down. 100% silane was introduced into the reactor vi a the Ar carrier gas at a temp erature of 1490C, which is ~80C above the Si melting point of 1410C at standard temperature and pressure (STP). This was used to prevent the formation of Si droplets on the surface during the heating cycle. Due to limitations in the silane MFC, the minimum silane that could have been flown for the 1600C process was 3 sccm (the MFC full-scale flow was 50 sccm and MFC’s are normally only accurate to within 10% of full-rated flow). The thermal ramp rate is also an important parameter to track during process de velopment. It took approximately 15-16 minutes to reach te mperature 1490C after turning on the RF source. It took approximately another 3 mi nutes to reach the final anneal set point temperature of 1600C. A total of 10 minutes of annealing in silane was performed from the time silane was turned on until the reactor was purged of silane prior to cool down. After 10 minutes the RF was turned off and, si nce the heat dissipation is much slower in the hot-wall system due to the insulating foam the silane continued to flow until the temperature fell to 1490C. This took approx imately 2-3 minutes based on the annealing

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83 set-point temperature. This was determined to be a necessary step in order to avoid any evaporation of silicon from the sample surf ace during this short cool down time. To ensure that all silicon was purged fr om the reactor before cool down to temperatures below 1410C, 35 slm of argon at the process pressu re of 200 Torr was flown for 1 min after the silane was turned off. After 1 min of argon purging, the sample was cooled in 5 slm of Ar flow in atmospheric pressure until room temperature was reached. The cool down time was approximately 45 minutes. The sample was then removed and inspected under the optical microscope. For a silane flow of 3 sccm in 25 sl m of argon surface defects (craters), presumably made by silicon droplets, were observed on the samples when they were inspected under the optical microscope. Since this was the minimum stable flow possible from the silane MFC, the argon flow was in creased by 10 slm to 35 slm. At 35 slm of argon flow, the lowest pressure that could be controlled by the pressure control system was 200 Torr. Annealing processes were repeat ed as mentioned above, but with 35 slm of argon and at 200 Torr with a silane flow of 3 sccm. The surface of th e sample annealed at 1600C did not contain any crat ers or step bunching and process development to higher temperatures was then conducted. However at temperatures greater than 17 00C, a slight variation in the process had to be made in order to achieve a sm ooth surface morphology. When the same process as employed for temperatures less than 16 50C was implemented, the formation of Sidroplets was, even though the surface arou nd the droplets was smooth. In the hot-wall system, the thermal ramp rate was much slower than in a cold-wall system and it took at least 3-5 minutes to reach the anneal temp erature set point from 1490C. The required

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84 flow rate of silane for that particular a nneal temperature could not be set at 1490C as was the case for the cold-wall system. The silane flow was ramped along with the temperature in order to avoid the formation of Si droplets at temperatures above 1490C but below the set point anneal temperature as shown in Figure 4.7. The thermodynamic simulations presented in Chapter 2 make this clear – one needs to flow ever increasing silane amounts as the process temperature in creases. The need for va riable silane flow during thermal ramping in the cold-wall system is not necessary due to the short ramp rates involved. After several experiments conducted at temperatures greater than 1700C, it was observed that trickling a very small amount of hydrogen (1 slm) into the reactor resulted in improved morphology than without hydrogen. The hydrogen was turned on only for the short duration after the anneal set point temperature had been attained. The most plausible reason for this process improvement was that the hydrogen prevented Si cluster formations while also performing a light etch on the surface of the implanted crystal. The later hypothesis was confirmed when SIMS was performed on these samples after noncontact electrical characteri zation and a slight removal of the implanted layer was detected. These results are presented in section 4.5. Similarly during sample cool down, the silane flow rate was ramped down and turned off when the temperature of 1490C was reached. As an illustration of the hot-wall implant annealing process developed during this research, the process schedule for the 1700C run is shown in Figure 4.7.

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85 Ar FlowAnnealing T (C)T1 Ar Purge 35 10 0 4.7 0 Ar (slm) SiH4* (sccm) 760 200 t (min) Pressure (Torr) 1490 ~3 -5 10 130 Ar FlowAnnealing T (C)T1 Ar Purge 35 10 0 4.7 0 Ar (slm) SiH4* (sccm) 760 200 t (min) Pressure (Torr) 1490 ~3 -5 10 130Figure 4.7: Implant annealing process schedule for T1 = 1700C hot-wall CVD processing, indicating gas flow timing versus sa mple temperature. Note the silane flow is ramped along with the temperature. This was found to be necessary to achieve specular surface morphology for all temperatures above 1700C. After post-implantation annealing, the samples were removed from the reactor and surface characterization performed using th e SEM and AFM, as described in section 4.4 4.4 Experimental Results 4.4.1 Surface Characterization The surface of all annealed samples was st udied by optical microscopy and AFM. Optical microscopy is the fastest and the easiest method for obtaining a rough idea about

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86 the surface morphology. Samples can be analy zed in air and the images display their natural color. For the Leitz Ergolux optical microscope in the NNRC cleanroom, the highest power objective was 100X. For e.g. Figure 4.8 (a) shows an optical micrograph of a sample annealed at 1750C under non-optimized silane flow. The surface morphology is clearly observed to be poor and it would therefore be a wa ste of resources to do further extensive surface characterization on such a sa mple. Figure 4.8 (b) shows a different type of defect observable under the optical micros cope. This sample contains surface craters that most probably were formed by the evap oration of Si-droplets which formed on the surface early in the 1600C annealing process development. (a) (b) Figure 4.8: Optical micrograph of (a) samp le annealed at 1750C under a non-optimized silane flow rate which is highly damaged. (b ) Crater formation on a sample annealed at 1600C, probably due to the formation of Si-droplets followed by etch removal. The magnification for both images is 50X. In the case of optical microscopy (and, for that matter, electron microscopy), the depth of focus is the distance above and below the image plane over which the image

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87 appears in focus. Thus, as the magnification increases the depth of focus decreases. In such a situation the SEM is a better choice of microscope because of its shallow depth of focus and higher resolution capability. However SEM analysis is qualitative and can be at times misleading, because of the detector posi tioning with respect to the sample as shown in Figure 4.9 (a) and (b). In this figure, the SEM and AFM images were taken on the same sample. Note that the SEM image shows a very smooth morphology, where as the RMS roughness determined by the AFM scan is 4.6 nm. (a) (b) Figure 4.9: Surface morphology after annealing at 1650C in a hot-wall system: (a) Plan view SEM micrograph of surface morphology at 10,000X. (b) AFM data of the surface morphology. RMS roughness ~ 4.6 nm The AFM scan area is 10 m x 10 m. Note the SEM did not reveal surface step-bunching whereas the ARM clearly shows the steps. Considering this factor, only AFM scans were performed on the post-implant annealed samples, after a quick initial ex amination under the optical microscope. As explained in Chapter 3, the AFM was operated in tapping mode a nd scans performed in

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88 two scan directions, at 0 and at 90 angles. This would avoid incorrect scan data in case the cantilever scan direction completely coinci des with the step bunchi ng orientation. For all samples studied the RMS roughness was noted to monitor any surface degradation caused by the high-temperature anneals. For the 1600C and 1650C processes to result in smooth surfaces it was found empirically that 3 sccm and 3.75 sccm of 10 0% silane was required, respectively. The AFM scans were performed on the samples annealed at 1600C and 1650C and are as shown in Figure 4.10. (a) (b) Figure 4.10: AFM data taken on post-implant annealed surfaces at temperatures of (a) 1600C and (b) 1650C. The AFM scan area was 10 m x 10 m. RMS roughness vs. process temperature is plotted in Fig. 4.12. As per the thermodynamic calculations di scussed in Chapter 2 as the annealing temperature is increased the silane flow rate should also be increased. Thus the silane flow was varied for each process temperature until step bunching was eliminated. It was also noticed that further increase in silane flow caused the formation of Si-droplets as seen in the cold-wall process.

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89 As mentioned in the section 4.3.2, a slight variation in the process had to be made for samples annealed at temperatures grea ter than 1700C in orde r to obtain a smooth morphology. Figure 4.11 (a) and (b) shows th e AFM scan data taken on samples annealed at 1700C and 1750C, respectively. The RM S roughness was found to be 0.56 nm and 0.65 nm for 1700C and 1750C, respectively. (a) (b) Figure 4.11: AFM data taken on post-implant annealed surfaces at temperatures of (a) 1700C and (b) 1750C. The AFM scan area was 10 m x 10 m. RMS roughness vs. process temperature is plotted in Fig. 4.12. The average RMS roughness was obtained from the AFM scanned data. Figure 4.13 shows the plot of average RMS roughness vs. temperature.

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90 Figure 4.12: Plot of average RMS surface roughness as a function of temperature after annealing in the hot-wall CVD config uration as measured with AFM. 10 m x 10 m scan size used for all data points. The data of Figure 4.12 shows the su rface roughness vs. temperature for the optimized processes. The optimized process flow was selected based on the observed surface roughness at each temperature. An example of this selection criterion is illustrated in Figure 4.13 for a single process te mperature. For silane flows of 3.8 and 4.2 sccm severe step bunching was observed w ith a surface roughness of ~6 nm RMS. For silane flow of 4.5 sccm the step bunching was greatly reduced but still present with a roughness of ~ 2 nm. The step bunching was comp letely eliminated for silane flow of 4.7 sccm, which was confirmed by AFM where a roughness of less than 0.6 nm RMS. Thus using AFM as a quantitative measure of the surface roughness is valid.

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91 Figure 4.13: Plot of average RMS surface roug hness as a function of function of silane flow rate at 1700C as th e hot-wall CVD configuration as measured with AFM. 10 m x 10 m scan size used for all data points. Severe step bunching was observed for silane flows less than 4.2 sccm, slight step bunching for 4.5 sccm and no step bunching was observed for 4.7 sccm. Several preliminary experiments were conducted to obtain an optimized 1800C process, since it is believed to be necessary to anneal Al implants at temperatures up to 1800C [14]. Unfortunately due to the lack of sufficient resources and a non-availability of samples during the period of this research, this process temperature could not be established and will be a part of the future work. Due to the same reason extensive electrical characterization co uld not be performed on the samples annealed in hot-wall system. Preliminary non-contact electrical measurements was performed for this work is presented in the following section.

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924.4.2 Comparison with Theory The process silane flow determined experimentally vs. temperature for the hotwall CVD process is shown in Figure 4.14 alon g with the comparison with the theoretical silane flow rates. Figure 4.14: Comparison of the theoretical sila ne flow rate vs. anne al temperature with experimental data for the hot-wall CVD react or configuration. Exponential curve fits have been applied to the data and are as shown. Note the trend is exponential with increasing temperature. Based on the data points shown in Figur e 4.14, a exponential curve fit was applied to the data. The silane flow rate, expressed as an exponential function of the form bx y ae for both the theoretical and experimental data is given as 214(1.910*)2.0210*T the (4.1) 36(8.610*) exp2.610*Te (4.2)

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93 From the figure and the equations it can be seen that there is difference between the experimental and theoretical flow rates. In addition to the possible mechanisms explained in Chapter 3, section 3.4, another probable reason could be because of depletion of Si near the graphite adapters before the silane reaches the hot zone. This is based on the observation of Si deposition on these graphi te parts: clearly Si is being consumed upstream of the hot zone and, therefore, more s ilane is needed to compensate for this loss. 4.5 Electrical Characterization Non-contact Electrical measurem ents were conducted on the n-/n+ 4H-SiC epi samples designated as W3, by Dr. E. Oborin a and Dr. A. M. Hoff based on their prior work performed on non-contact doping profil ing on epitaxial SiC [79]. The purpose of this was to develop an in-process metrol ogy technique for SiC processing, whereby characterization of annealed layers coul d be conducted during processing without the need for destructive test structure fabrication. This technique is based on Q2-V method, an earlier wo rk done on doping profile extraction from dielectrics [80]. The basic idea is that a surface depletion layer is created by placing corona charge QC of opposite polarity (compared to semiconductor surface) on the semiconductor surface. The doping ND (or NA) of the depletion layer of width W is then obtained from equations 4.3 and 4.4. CDQqAWN (4.3) where A is the area of the device area a nd q is the elemental (electron) charge 22cosDDokT QqNVV q (4.4)

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94 where o and s are permittivity of free space and of the semiconductor, respectively, VD is the voltage drop, V0 is the potential of the semiconductor Fermi level with respect to the conduction band and kT is the thermal energy This is similar to extraction of doping by C-V measurement of a Schottky barrier diode The detailed explanation of the process and the parameters extracted is given by A. Savtchouk et. al. [79]. The main advantage of this technique is that it is non-contact, non-destructive an d preparation-free; hence we were able to perform electrical measurements efficiently and effectively on the same sample after sequential annealing processing steps. The doping profile of the nepitaxial layer (ND) (sample W3) on an n+ 4H-SiC substrate that were diced into 1cm x 1.2cm, was determined using this method before implantation and is shown in Figure 4.15. The doping concentration of the nepitaxial layer was found to be in the upper 1016 cm-3 range. Figure 4.15: Doping profile of W3 epitaxial film before implantati on, obtained by noncontact Q2-V measurement. Nd1, Nd2 and Nd3 are doping profiles of three different 1cm x 1.2 cm W3 samples. Data provided by Dr.’s E. Oborina and A. Hoff.

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95 After Al implantation, non-contact C-V measurement was again performed to check if there was any difference in the dopi ng profile. A very slight change was noticed in the corona discharge, which indicated a very small shift in the net doping concentration of the as-implanted surface. Po st-implantation annealing was performed on samples for two different annealing temperat ures at 1600C and 1700C. For each sample three sets of anneals were performed at the same temperature. In set 1 sample A and B were ramped up to anneal temperature of 1600C and 1700C, respectively. Once the set point temperature was reached the RF was turned off and the samples were cooled down as shown in Figure 4.16 (a). After non-cont act electrical measurements of the sample were performed and doping profiles were extracted the samples were cleaned and annealing was performed on the same samples at same temperatures but for longer duration. In set 2 and set 3 the samples were annealed at the desired temperatures for 5 minutes each as shown in the schematic in Figu re 4.16 (b). For set 3 the total annealing time at the desired anneal temperature was 10 minutes, excluding the ramp up and ramp down time for these temperatures. T (C) DT t (min)T (C) DT t (min) DT t (min)(a) 5 min DT t (min)T (C) 5 min DT t (min)T (C)(b) Figure 4.16: Annealing process schedule for the (a) set 1 and (b) sets 2 and 3 sequential annealing experiments. Two annealing temperatures were studied and the samples A and B, were annealed at temperature (DT) of 1600C and 1700C, respectively.

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96 The non-contact measurement provided fast feedback of the de gree of electrical activation achieved after each proce ss step. The net doping concentration NA ND was extracted from the measured contact potenti al difference shown in Figure 4.17 and a histogram of the doping concentration data was plotted as shown in Figure 4.18. It can be seen that, in the case of sample A that was annealed at 1600C, the net doping profile increased after each anneal process. Also as expected, electrical activation of the Al dopants increased with the temperature (sample B, which was annealed at 1700C). Figure 4.17: Measured contact potenti al difference (VCPD) during non-contact metrology of the samples annealed as per Fig. 4.16. Note that a qualitative difference in doping type, from n-type to p-type, was observ ed after the initial annealing step (Set 1).

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97 1 2 3 4 5 6 7 8 1-1700oC 3-1600oC 2-1600oC 1-1600oC( NAND ) x 1018, cm-3Anneal Sequence Temperature Figure 4.18: Measured doping density vs annealing sequence measured using non contact electrical measurements developed by Ho ff et al [79]. Note that the Set 1 anneal at 1700C (sample B) yielde d a higher degree of dopant activation than 3 successive anneals conducted at 1600C (sample A). This outcome indicates that rapid annealing may be preferable to long thermal soak anneals. One of the clearest outcomes of this first set of non-contact measurements was that the single process step at 1700C appears to result in superior activation compared to 3 successive anneals at 1600C. This seems to indicate that a more rapid thermal process is preferable over longer thermal soaking. This data is preliminary and is the subject of future work that is described in Chapter 5. An additional point was the processing trend seen on sample A. For this sample a gradua l increase in electrical activation with the anneal time was observed, as expected. However this was not seen for sample B, which was annealed at the higher temperature of 1700C. As the anneal time was increased further for 1700C process, raw data obtain ed from non-contact measurement showed no

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98 presence of Al dopants in the sample. The sample behaved more n-type than p-type, which led this conclusion to be drawn. In order to further investigate this issue, SIMS measurement was performed on both the samples (A and B) by Dr. M. Wood at the ARL. From the SIMS data it was confirmed that the surface of the sample was being etched during the annealing as shown in Figure 4.19 (a) and (b) for 1600C and 1700C, respectively. (a) (b) Figure 4.19: SIMS measurement of the Al profile on the samples annealed after 3 annealing steps (Set 1, 2, 3) at temperatur es of (a) 1600C and (b ) 1700C. Note that the sample annealed successively at 1700C appears to no longer contain an Al implanted layer, most likely due to mate rial removal during processing. Both the samples were annealed for the same time duration, i.e. sets 1, 2 and 3. Since the etch rate of SiC in hydrogen increas es with temperature [81] the most likely

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99 explanation is that the small amount of hydr ogen introduced to ‘clean up the surface’ may be etching the implanted layer, but this is only speculation as this time. Clearly for the hot-wall silane overpressure im plant annealing process to be of value to the community this issue must be resolved. Hence additional experiments and a few alternative solutions have been proposed and will be described in the next chapter. 4.6 Summary Post-implantation anneals were performed on Al+ implanted 4H-SiC samples in a hot-wall CVD reactor using the silane over pressure method for temperatures up to 1750C. Surface characterization of the impl ant annealed samples revealed no step bunching or surface morphology degradation. Preliminary electrical measurements done by non-contact technique showed successful elec trical activation of the dopants. However from these preliminary results, it was also observed that there was slight etching of the surface material and hence removal of the implanted layer for long process runs at higher temperatures (i.e., 1700C). SIMS analysis done on the samples co nfirmed the removal of the material. This could explain the higher sheet resistance of the implanted layer seen in the samples annealed in cold-wall CVD react or (Chapter 3). To study this further and to solve this issue a few ideas have been developed and will be explained in the future work section of Chapter 5.

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100CHAPTER 5 SUMMARY AND FUTURE WORK 5.1 Summary Post-implantation annealing process deve lopment of 4H-SiC implanted with Al ions was completed during this research work in both cold-w all and hot-wall CVD reactors. The primary goal of this research was to establish a silane over pressure annealing process so that the crystal dama ge caused during implantation, as well as dopant activation, could be performed while returning the surface morphology to the preimplanted state. Therefore the process development conducted was focused on the improvement of the surface morphology during th is research work, w ith full-activation of the dopants taking on a secondary role. As a consequence detailed surface characterizations of annealed films were performed using plan-view SEM and AFM. These characterization techniques showed that samples annealed with the silane over pressure process had a better surface morpho logy than the samples annealed with the conventional argon anneal process. Empirical thermodynamic gas-phase chemistry models for the silane over pressure annealing process, both for cold and hot-wall reactors, were also developed during the course of this work. The ther modynamic calculations were performed to obtain theoretical silane flow rates as a func tion of annealing temperature. The basis for

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101 this modeling was to ensure that the partial pressure of Si, derived from the cracking of silane in the gas phase, was greater than the va por pressure of Si in the SiC substrate. If this condition is met then the principle behi nd the silane overpressure process would be valid, i.e. the suppression of preferential evaporation of Si from the SiC lattice is reduced and, hopefully, eliminated. Based on the earlier work done in an atmospheric-pressure cold-wall CVD reactor, the new processes developed during this research were for low pressure operation. In the APCVD process the forma tion of Si droplets was an issue, hence shifting this process to low-pressure was desi rable to reduce homogenous nucleation of Si in the gas phase. The annealing temperature was varied between 1600C to 1700C and the 3% silane premixed in UHP argon was intr oduced into the reactor via an argon carrier gas in such a concentration that step bunc hing of the surface, which is known to be caused by the selective evaporation of Si from the SiC lattice, was eliminated. Electrical characterization of cold-wall CVD an nealed samples showed reproducible p+/n diode performance and yield. However the sheet resistance was found to be an order of magnitude higher than what was expected base d on the ion dose and implant profile. In addition there was occasional issue of the Si dr oplets at the edges of the sample due to the non-uniform temperature distribution across the die. This is mainly to be expected in a cold-wall reactor due to the fact that only the substrate is heated and not the annealing zone around the sample. In addition, due to th is high cooling rate of the sample in cold wall, the RF generator power required to do higher temperature anneals (above 1700C) was more than our system could provide. Therefore cold-wall annealing has both a temperature uniformity problem and a limitation in annealing temperature that results in

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102 annealed layers that are not fu lly activated (it is widely beli eved that Al implants require thermal anneals to be performed at temperatures approaching 1800C !) To overcome these limitations, research in to post-implantation annealing in a hotwall CVD reactor for anneal temperatures between 1600C to 1750C was conducted and a process developed. The process was similar to the process developed in the cold-wall reactor, except that 100% silane was us ed. The resulting surf ace after annealing was again found to be step-bunch free and sm ooth if the proper process procedure was followed. The issue of Si-droplet was comp letely eliminated. Preliminary electrical measurements taken by non-contact measurement methods showed an increase in electrical activation of the dop ants with anneal temperatur e, as expected. However the electrical and SIMS measurements showed th at there was slight etching of the surface material during annealing for longer duration anneals at the higher temperatures. Hence the process needs additional research and refinement, which will be the subject of the future work section of this chapter. Due to the lack of resources, such as implanted samples, fresh graphite susceptors, adequate electrical characterization tools, and an in-house SIMS measurement capability no further research was possible to research solutions for these important issues. However further work based on some of the ideas developed for the improvement of the process are mentioned in the following sections. Indeed some of this work has already been started and is explained in detail in the following section.

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1035.2 Future Work The goal of future research in the area of post-implant ion annealing of SiC layers should be to look into the issue regarding the partial removal of the implanted layer which resulted in a higher than expected sh eet resistance. Etching could be occurring because of the presence of hydrogen due to cracking of silane. In order to confirm this hypothesis, high temperature anneals should be performed in Ar only (where there is no hydrogen present) and electrical charac terization followed by SIMS measurements performed on the samples. This is perh aps the only experimental approach to understanding the etching mechanism in play here. A theoretical study, based on known hydrogen etch rates of SiC and using the pa rtial pressure of hydrogen during silane overpressure processing should also be perf ormed. This would be based on the model developed during this work whereby the Si and H partial pressures in the gas phased are calculated based on thermodynamics. While this approach cannot stand on its own merits, simulations coupled with the Ar annealing experiments described above should provide sufficient insight into the material removal issue. While the slight removal of material is a concern it has been seen that the developed silane overpressure processes yield smooth, step-bunch free surfaces which is something that annealing in Ar simply can not do. Therefore one approach to overcome the issue of material removal is to perform ion implantation through very thin passivating oxide layers. This would shift the peak of the implant Gaussian profile deeper inside the sample surface, thus ensuring that an adeq uate volume of the implanted layer remains after annealing. From the SIMS measuremen t it was estimated that approximately 300nm of the material was etched away after post-implantation annealing with silane

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104 overpressure method at 1700C and for 15 min. In order to test this idea out, a 400 of oxide was deposited on a 4H-SiC sample with a 6 m epilayer of doping density in mid 1016 cm-3. The samples were shipped to Dr Nipo ti at Bologna, Italy for implantation. Figure 5.1 shows the predicted SRIM implantation profile. Figure 5.1: Predicted SRIMs profile of the Al+ implantation preformed through 400 of deposited oxide. The position of the sample surface after annealing is shown by a vertical line. Note that this would result in a peak of the implant profile residing on the sample surface after annealing at 1700C for 15 min. Non-contact electrical measurements, fo llowed by SIMS analysis, should be performed on each of these samples. Once the process has been established, p+/n diodes

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105 should be fabricated and sheet resistance, as well as the doping pr ofile of the annealed samples, extracted. Dr Nipoti’s group at CNR-IMM in Bologna, Italy, has kindly offered to perform the necessary electr ical measurements and the samples should be shipped to her when they are ready. Prior to shipping th e samples to Bologna, a thermal oxide could also be grown on the post-implanted anne aled samples to realize metal oxide semiconductor capacitors (MOSCAP’s). This is to check the oxide-semiconductor interface for any kind of defects, which is ve ry vital step in fabr ication of metal oxide field effect transistor (MOSFET). The latter step of fabrication of MOSCAP’s can be performed at USF and the electrical meas urements conducted by Dr. Hoff’s group using the non-contact measurement method desc ribed earlier in this dissertation. Other than the conventional argon annea ling process, which leads to severe surface degradation, samples annealed in si lane overpressure process should also be compared with the samples annealed using a graphite cap. As explained in chapter 1, a graphite capping layer is form ed by hard baking the photores ist [21]. This process could lead to contamination of th e surface unlike silane overpre ssure process. The samples annealed by the graphite cap method, along with as-implanted SiC, will be supplied by Dr. Karl Hobart of Naval Research Laborato ry (NRL), USA. The testing and comparison of both surface and electrical characterization can then be done at both USF and NRL.

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106References [1]. R. F. Davis, G. Kelner, M. Shur, J. W. Palmour and J. A. Edmond, “Thin film deposition and microelectronic and opt oelectronic device fabrication and characterization in monocrystalline alpha and beta SiC”, IEEE, Vol 79, No 5, 677 (1991). [2]. J. B. Casady and R. W. Johnson, “Statu s of silicon carbid e (sic) as a wldebandgap semiconductor for high-temp erature applicati ons: a review”, Solid State Electronics, Vol 39. No 10, 1409 (1996). [3]. Committee on Materials for High-Tempera ture Semiconductor Devices, National Research Council 1995. [4]. D. M. Brown, E. Downey, M. Ghezzo, J. Kretchmer, V. Krishnamurthy, W. Hennessy and G. Michon, “Silicon Carbide MOSFET technology”, Solid State Electronics, Vol 39, No 11, 1531 (1996). [5]. Carl-Mikael Zetterling, Process Technology for Si licon Carbide Devices, EMIS processing series; no. 2, INSP EC, London, United Kingdom, 2002 [6]. S. E. Saddow and A. Agarwal, Advances in Silicon Carbide Processing and Applications, Semiconductor materials and devi ces series, Artech house, inc., 2004. [7]. Pierre Masri, “Silicon Carbid e and silicon carbide-based structures The physics of epitaxy”, Surf. Sci. Reports, Vol 48, 1 (2002). [8]. T. P. Chow, V. Khemka, J. Fedison, et .al, “SiC & GaN bipolar power devices,” Solid-State Electronics, 277 (2000) [9]. Z. C. Feng and J. H. Zhao, Optoelectronic propertie s of semiconductors and superlatices: Silicon Carbide ma terials, processing and devices, Vol 20, Taylor & Francis Books, Inc., (2004). [10]. G. Pensl and W. J. Choyke, “Electrical and optical characterization of SiC Phys. B, Vol 185, 264 (1993).

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109 [33]. D. J. Larkin, “SiC dopant incorporation using site-competition CVD”, Phys. Stat. Sol.(B) 202, 305 (1997). [34]. S. Soloviev, Y. Gao, I. I. Khlebnikov, and T. S. Sudarshan, Mater. Sci. Forum, Vol. 338, 945 (2000). [35]. M. V. Rao, “Maturing ion-implantation t echnology and its devi ce applications in SiC”, Solid-State Electronics 47, 213. (2003). [36]. J. K. Hirvonen, Treatise on Materials Sc ience and Technology – Ion Implantation, Vol. 18, Academic Press, 1980. [37]. R. C. Jaeger, Modular Series on Solid State: Introduction to microelectronic fabrication, Prentice-Hall, Inc. 2nd Edition, 2002. [38]. Stephen A. Campbell, The Science and Engineering of Microelectronic Fabrication Engineering, Oxford University Press, 1999. [39]. H. Ryssel and I. Ruge, Ion Implantation, Wiley-Interscience publications, 1986. [40]. J. W. Mayer, L. Eriksson and J. A. Davies, Ion Implantation in Semiconductors, New York, 1970. [41]. J. F. Ziegler, Ion Implantation: Science and Technology, Boston : Academic Press, 2nd Edition, 1988. [42]. S. Wolf and R. N. Tauber, Silicon Processing for the VLSI Era Volume 1 Process Technology Lattice Press, second edition, 2000. [43]. J. D. Plummer and P. B. Griffin, “Material and process limits in silicon VLSI technology”, Proc IEEE Vol. 89(3), 240 (2001). [44]. SRIM download at the web page: http://www.srim.org/SRIM [45]. J. F. Ziegler, J. P. Biersack and U. Littmark, The Stopping and Range of Ions in Solid, Pergamon Press, New York, Vol. 1, 1985. [46]. M.S. Janson, M. K. Linnarsson, A. Halle n, and B. G. Svensson, “Ion Implantation range distributions in silicon carbide” J. Appl. Phys, Vol. 93 No. 11, 8903 (2003). [47]. W. J. Choyke and L. Patrick, “Lumin escence of Donor-Acceptor Pairs in Cubic SiC”, Phys. Rev. B2, Issue 12, 4959 (1970).

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110 [48]. D. J. Larkin, P. G. Neudeck, J. A. Powell, and L. G. Matus “Site-competition epitaxy for superior sili con carbide electronics”, Appl. Phys. Lett. Vol. 65 1659 (1994) [49]. T. Troffer, M. Schadt, T. Frank, H. Itoh, G. Pensl, J. Heindl, H. P. Strunk and M. Maier, „Doping of SiC by implantation of boron and aluminum”, Phys. Stat. Sol (A), Vol. 162, 277 (1997) [50]. A Schoner, N. Nordell, K. Rottner, R. Helbig and G. Pensl, Inst. Phys. Conf. Ser. No. 142, 493 (1996) [51]. Jiang, W., et al., “Displacement energy m easurements for ion-irradiated 6H-SiC,” Nucl. Instr. and Meth. in Phys. Res. B, Vol. 148, 557 (1999). [52]. E. Morvan, P. Godignon, M. Vellvehi, A. Halln, M. Linnarsson, and A. Yu. Kuznetsov, “Channeling implantations of Al+ into 6H silicon carbide,” Appl. Phys. Lett., Vol. 74, 3990 (1999). [53]. J. Wong-Leung,, M.S. Janson, and B. G. Svensson “Effect of crystal orientation on the implanted profile of 60 keV Al into 4H-SiC crystals,” J. Appl. Phys., Vol. 93, 8914 (2003). [54]. Morvan, E., et al., “Lateral spread of implantation ion distribution in 6H-SiC: simulation,” Mater. Sci. Ing., Vol. B61-62, 373 (1999) [55]. L. Muehlhoff, W. J. Choyke, M. J. Bo zack, and J. T. Yates, Jr., “Comparative electron spectroscopic studies of surf ace segregation on SiC(0001) and SiC(0001)”, J. Appl. Phys., Vol. 60, 2842 (1986). [56]. B. McBride and S. Gordon, NASA-Glenn Chemical Equilibrium Program CEA2 (1994). [57]. B. J. McBride and S. Gordon, “Computer program for calculation of complex chemical equilibrium composition and applicationsI. Analysis”, NASA reference publication 1311, (1994) [58]. B. J. McBride and S. Gordon, “Computer program for calculation of complex chemical equilibrium composition and applicationsII. Users manual and program description”, NASA reference publication 1311, (1996) [59]. M. Tao and L. P. Hunt, “The thermodynami c behaviour of the Si-H system and its role in Si-CVD from SiH4”, J. Electrochem. Soc., Vol 139, No. 3, 806 (1992).

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111 [60]. E. Janzen, J. P. Bergman, O. Danielsson, U. Forsnerg, C. Hallin, J. Ul Hassan. A. Henry and P. Persson ,“ Si C and III-nitride growth in a hot-wall CVD reactor”, Mater. Sci. Forum, Vol. 483-485, 61 (2005). [61]. H. O. Pierson, Handbook of Chemical Vapor Deposition, 2nd Edition, Noyes publications, William Andrew p ublishing, LLC, New York, 1999. [62]. M.R. Leys, The Chimney Reactor, A Comp ilation of Results, Philips Research Laboratories, Eindoven, Netherlands, 1985. [63]. Matt Smith, Design and Development of a Silicon Carbide Chemical Vapor Deposition Reactor, Master’s Thesis, University of South Florida, Tampa, FL, Dec 2003. [64]. Rachael L Myers, CVD Growth of SiC on Novel Si Substrates, Master’s Thesis, University of South Florida, Tampa, FL, Dec 2003. [65]. Yoon Soo Park, et. al., SiC Materials and Devices, Semiconductors and Semimetals Vol 52, Academic Press, 1998. [66]. Thomas Schattner, Homoepitaxial Growth of 4H and 6H-SiC in a 75mm Reactor, Master’s Thesis, Mississippi State University, Starkville, MS, May 2000. [67]. M. Capano, S. Ryu, M. R. Melloch, J. A. Cooper, K. Rottner, S. Karlsson, N. Nordell, A. Powell and D. E. Walker, “S urface roughening in ion implanted 4HSilicon Carbide,” J. of Electron. Mater. Vol. 28, 214, (1999). [68]. S. E. Saddow, M. Capano, J.A. Cooper, M. S. Mazzola, J. Williams and J. B. Casady, Mater. Sci. Forum, Vol. 338, (2000). [69]. M. Capano, S. Ryu, M. R. Melloch, J. A. Cooper, and M. R. Buss, “Dopant activation and surface morphology of ion implanted 4Hand 6H-Silicon Carbide,” J. Electron. Mater. Vol. 27, 370, (1998). [70]. T. Ohyanagi, T. Ohno, K. Amemiya, A. Watanabe, “Characterisation of the Forward-Conduction of 4H-SiC Planar Junction Diode,” Material Science Forum Vols. 433-436, 835 (2003). [71]. N. Keskar, K. Shenai, and P. Neudeck, “Defect Modeling and Simulation of 4H SiC P-N Diode,” Material Science Forum Vols. 338-342, 1351 (2000). [72]. F. Bergamin, Optimization of the ion implantati on process for the realization of p+/n junction in Silicon Carbide, Ph.D Dissertation, Department of Applied Chemistry and Material Science, Univer sity of Bologna, Bologna, Italy, May 2005.

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113 APPENDIX

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114Appendix A: CEA: Chemical Equilibrium with Application software code The NASA CEA program can calculate ch emical equilibrium compositions for assigned thermodynamic states, which in the ca se of this research work is temperature and pressure. Chemical equilibrium can be expressed either in terms of equilibrium constants or minimization of the system free en ergy. The equilibrium constant relates to a chemical reaction which occurs under equilibrium conditions and free energy is a measure of the amount of work that can be extracted from the system. From the second law of thermodynamics the minimization of free energy is a requirement for any system to reach equilibrium. These methods can be generalized. However, in the case of the equilibrium constant approach, it is not suita ble for a large chemical system since each species cannot be treated independently, unle ss a set of known reactions is specified a priori. Taking into consideration this fact or, NASA implemented the minimization of free energy approach when they developed the CEA program. The equilibrium condition can be stated in terms of several thermodynamic functions, such as the minimization of the Gibbs or Helmholtz energy. In order to characterize the thermodynamic state of the system, which is at constant pressure and temperature, the Gibbs energy is most easily minimized. Minimization of the Gibbs free energy can be obtained from both the first and second laws of thermodynamics. The first law of thermodynamics is the application of conservation of energy. It states that energy cannot be created or destroyed, but can be changed from one form to another. The second law of thermodynamics states that in all ener gy exchanges, if no energy enters or leaves

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115 the system, the potential energy of the state will always be less than that of the initial state. A detailed derivation of minimization of Gibbs energy can be found in ref [57]. Initially the CEA program was written in ANSI standard FORTRAN 77. With the original NASA Lewis code running on a PC platform, a user friendly, graphical user interface, or GUI, “front end” was develope d by Zeleznik and Gordon in 1961. Various versions of the equilibrium program or modifications of the program have been incorporated since then. The CEA library of thermodynamic data contains data for both reaction products and reactants. Thermodynamic data are provided with the program on a separate file, called thermo.inp (which is an input file) and the processed data are stored in thermo.lib for subsequent use by the CEA pr ogram. Another type of input is prepared by the user, which contains the specific problem to be solved and is stored as the “userdefined-filename”.inp file. A particular pr oblem is specified initially by assigning a thermodynamic state such as temperature and pressure, as shown in Figure A.1 Figure A.1: Graphical screen capture from the CEA program. A problem is initiated in the CEA program by first assigning a thermodynamic state of the system.

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116 To assign particular values for temp erature and pressure, one needs to double click on the Assigning Temperature and Pressu re – tab in Figure A.1. A window, as shown in Figure A.2, then comes up where a user can choose up to 16 temperature and pressure values via a GUI. Both temperatur e and pressure can be defined with four different systems of units system, as show n. The inputted values are saved and the window is closed by clicking on the save button Figure A.2: Graphical screen capture fr om the CEA program. Window for inputting temperature and pressure values for a specific problem. Note four different options for units are provided for both temperature and pressure After assigning the temperature and pressure values, the next tab, “Reactant,” is chosen. In this window the reactants for whic h the thermodynamic calc ulations are to be performed are entered, as shown in Figure A.3. For e.g. in Figure A.3 the reactants used for a 1600C cold-wall implant annealing proc ess are shown. Flow rates of argon, and silane were input as number of moles. The SiC substrate was also taken into

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117 consideration in moles by adding SiC (b) to th e reactants. A value much higher than the number of moles of argon and silane was a ssigned to SiC(b), to take into account the large amount of SiC present in the form o the solid substrate. Only the reactant that was available in the thermodynamic library could be chosen and beta-SiC was the only available polytype available to the user in the condensed form. However, from a thermodynamic point of view it does not matter which polytype of SiC is chosen so this does not lead to any errors in the calculation. Figure A.3: Graphical screen capture from the CEA program. A snapshot of the window which shows reactants and corresponding va lues in number of moles is input. Based on the reactants entered in th e window shown in Figure A.3, CEA generates all possible complex solid, liquid an d gaseous species. Figu re A.4 shows all of the possible species for the reactants entered in the window shown in Figure A.3. The tabs that follow the reactant tabs “Only,” “O mit,” and “Insert,” allow the user to either

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118 list only those species from the thermodynamic da ta file that are to be considered for the current problem, if not all, or omit certain species or must include certain species, respectively. If none of these three tabs are specified, CEA performs calculations on all the available species for the reactants ente red in Figure A.3. Calculations of the condensed species are usually optional and CEA includes these species occasionally if they are required to obtain convergence. On the “insert” tab, condensed species to be included can be specified as possible pro duct from the start of the calculations. Figure A.4: Graphical screen capture fr om the CEA program. Gaseous and condensed species generated by CEA for the reactants show n in Figure A.3. Note in “only” tab one can choose whatever specie that is most probable can be chos en if not all.

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119 The last tab is the “output” tab and is shown in Figure A.5. As shown in the figure, after the iteration is performed, th ere is an option to omit species with mole fractions lesser than user defined valu es (which in this case is 1e-10). Figure A.5: Graphical screen capture from the CEA program The window for the output tab. The thermodynamic state of the system al ong with the mole fractions of the species that are to be plotted are specified in this window.

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120 The input file “user-defin ed-filename”.inp is saved and upon execution generates an output file with filename “user-defined-filename”.out and a plot file with filename “user-defined-filename”.plt. A plot file for specified thermodynamic states (temperature and pressure) and mole fractions of the species obtained after performing iterations on the reactant species is generated by choosing th e thermodynamic state a nd list of species on the output tab shown in Figure A.5. All thes e files .inp, .out and .plt are in the ASCII format and can be opened in a notepad or word pad. The plot file is the most convenient file to access the processed data. A sample of the both output file followed by the plot file for a problem with reactants shown in Figure A.3 at temperatur e of 1600C and pressure of 150 Torr and 760 Torr is shown below Output file: ************************************************************************ NASA-GLENN CHEMICAL EQUILIBRI UM PROGRAM CEA2, MAY 21, 2004 BY BONNIE MCBRIDE AND SANFORD GORDON REFS: NASA RP-1311, PART I, 1994 AND NASA RP-1311, PART II, 1996 ************************************************************************ problem tp t,c=1600, p,mmhg=150,760, react name=Ar moles=6000 name=SiC(b) moles=10000 name=SiH4 moles=0.32 only Ar C CH CH2 CH3 CH4 C2 C2H H H2 Si SiC SiC2 SiH SiH2 SiH3 SiH4 Si2 Si2C Si3 Si(cr) Si(L) SiC(b) output trace=1e-10 plot p t Ar H H2 Si SiC2 SiH SiH2 Si2 Si2C Si3 Si(L) SiC(b) end OPTIONS: TP=T HP=F SP=F TV=F UV=F SV=F DETN=F SHOCK=F REFL=F INCD=F RKT=F FROZ=F EQL=F IONS=F SIUNIT=T DEBUGF=F SHKDBG=F DETDBG=F TRNSPT=F

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121 T,K = 1873.1500 P,BAR = 0.199984 1.013250 TRACE= 1.00E-10 S/R= 0.000000E+00 H/R= 0.000000E+00 U/R= 0.000000E+00 REACTANT MOLES (ENERGY/R),K TEMP,K DENSITY EXPLODED FORMULA N: Ar ********** 0.000000E+00 0.00 0.0000 AR 1.00000 N: SiC(b) ********** 0.000000E+00 0.00 0.0000 SI 1.00000 C 1.00000 N: SiH4 0.320000 0.000000E+00 0.00 0.0000 SI 1.00000 H 4.00000 SPECIES BEING CONSIDERED IN THIS SYSTEM (CONDENSED PHASE MAY HAVE NAME LISTED SEVERAL TIMES) LAST thermo.inp UPDATE: 9/09/04 g 3/98 *Ar g 7/97 *C tpis79 *CH g 4/02 CH2 g 4/02 CH3 g 8/99 CH4 tpis91 *C2 g 6/01 C2H g 6/97 *H tpis78 *H2 g 8/97 *Si tpis91 SiC tpis91 SiC2 tpis91 SiH g 3/01 SiH2 g 3/99 SiH3 tpis91 SiH4 tpis91 Si2 tpis91 Si2C g 7/95 Si3 tpis91 Si(cr) tpis91 Si(cr) tpis91 Si(L) tpis91 SiC(b) tpis91 SiC(b) O/F = 0.000000 EFFECTIVE FUEL EFFECTIVE OXIDANT MIXTURE ENTHALPY h(2)/R h(1)/R h0/R (KG-MOL)(K)/KG 0.00000000E+00 0.00000000E+00 0.00000000E+00 KG-FORM.WT./KG bi(2) bi(1) b0i *Ar 0.93653379E-02 0.00000000E+00 0.93653379E-02 *Si 0.15609396E-01 0.00000000E+00 0.15609396E-01 *C 0.15608897E-01 0.00000000E+00 0.15608897E-01 *H 0.19979388E-05 0.00000000E+00 0.19979388E-05 POINT ITN T AR SI C H 1 19 1873.150 -23.473 -3.722 2.372 -15.448 ADD SiC(b) 1 10 1873.150 -22.726 -5.449 -6.040 -15.049 ADD Si(L) 1 2 1873.150 -22.726 -5.507 -5.982 -15.049 2 4 1873.150 -21.103 -5.507 -5.982 -14.218 THERMODYNAMIC EQUILIBRIUM PROPERTIES AT ASSIGNED TEMPERATURE AND PRESSURE CASE = REACTANT MOLES ENERGY TEMP KJ/KG-MOL K NAME Ar 6000.0000000 0.000 0.000

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122 NAME SiC(b) ************ 0.000 0.000 NAME SiH4 0.3200000 0.000 0.000 O/F= 0.00000 %FUEL= 0.000000 R,EQ.RATIO= 0.000000 PHI,EQ.RATIO= 0.000000 THERMODYNAMIC PROPERTIES P, BAR 0.19998 1.0132 T, K 1873.15 1873.15 RHO, KG/CU M 1.3709-1 6.9460-1 H, KJ/KG 306.96 306.80 U, KJ/KG 161.07 160.92 G, KJ/KG -6108.25 -5871.53 S, KJ/(KG)(K) 3.4248 3.2984 M, (1/n) 106.759 106.764 MW, MOL WT 40.039 40.039 (dLV/dLP)t -1.00005 -1.00001 (dLV/dLT)p 1.0013 1.0003 Cp, KJ/(KG)(K) 1.0115 1.0094 GAMMAs 1.0836 1.0836 SON VEL,M/SEC 397.6 397.6 MOLE FRACTIONS *Ar 3.7498-1 3.7498-1 *H 5.4079-6 2.4507-6 *H2 3.7235-5 3.8746-5 *Si 1.6566-5 3.2694-6 SiC2 9.178-10 1.811-10 SiH 1.1590-7 5.2522-8 SiH2 1.796-10 1.869-10 Si2 4.8460-7 9.5641-8 Si2C 6.5241-7 1.2876-7 Si3 1.4964-7 2.9533-8 Si(L) 1.2473-6 1.6268-5 SiC(b) 6.2496-1 6.2496-1 THERMODYNAMIC PROPER TIES FITTED TO 20000.K PRODUCTS WHICH WERE CONSIDERED BUT WHOSE MOLE FRACTIONS WERE LESS THAN 1.000000E10 FOR ALL ASSIGNED CONDITIONS *C *CH CH2 CH3 CH4 *C2 C2H SiC SiH3 SiH4 Si(cr)

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123Plot File: p t H H2 Si SiC2 SiH 2.00E-01 1.87E+03 5.41E-06 3.72E-05 1.66E-05 9.18E-10 1.16E-07 1.01E+00 1.87E+03 2.45E-06 3.87E-05 3.27E-06 1.81E-10 5.25E-08 p t H H2 Si SiC2 SiH SiH2 Si2 Si2C Si3 Si(L) SiC(b) 1.80E-10 4.85E-07 6.52E-07 1.50E-07 1.25E-06 6.25E-01 1.87E-10 9.56E-08 1.29E-07 2.95E-08 1.63E-05 6.25E-01 SiH2 Si2 Si2C Si3 Si(L) SiC(b) The plot file is used to analyze the comp uted data and as mentioned in Chapter 2, section 2.4 further computation was performed to obtain the final plots shown in Figure 2.8 and 2.9.

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About the Author Shailaja Rao received the Master of Science degree in Electrical Engineering from the University of South Florid a in 2002 where she completed research on SiC based transistors. Prior to her Maste r’s studies, she completed the Bachelors degree in Electrical Engineering from the Mangalore University, Mangalore, India. She has been pursuing her PhD in Electrical Engineering since that time and has been active in all aspects of the research work being conducted in the USF SiC Group, in which she is the first student to earn the PhD degree. Her research has focuse d on novel SiC device processing, including the work reported here, and she has actively supported industry and federal government sponsors through her work. Dr. Rao plans to continue working for the USF SiC Group after graduation as a post-doctoral researcher focusing in the area of SiC epitaxy and bulk crystal growth.