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Development and implementation of a DSP based air detector system to prevent embolism during hemodialysis therapy

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Development and implementation of a DSP based air detector system to prevent embolism during hemodialysis therapy
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English
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Nguyen, Nhat
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University of South Florida
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CodeWarrior
Timer
Interrupt
Ultrasound
Piezoelectric effect
Dissertations, Academic -- Electrical Engineering -- Masters -- USF
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bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

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Abstract:
ABSTRACT: This thesis describes the design of a DSP based air detector system to prevent air embolism during Hemodialysis, which is a treatment option for kidney failure disease. Hemodialysis consists of removing blood from the body, filtering and treating the blood to remove toxic substances such as wastes and fluids, reestablishing proper chemical levels in the blood and returning the processed blood to the body. The functions of hemodialysis are performed through the use of a dialyzer, which is also known as an artificial kidney. During hemodialysis small air bubbles may infiltrate the tubing used during the therapy and combine to form larger air bubbles that are harmful to the patient. If an air bubble is large enough and enters the patient's circulatory system, the blood flow can be blocked and the patient can die by embolism. Most of the hemodialysis instruments in use today are equipped with air detection systems, which are based on analog design and digital microcontroll ers. This thesis presents a design method based strictly on DSP technology. The Motorola DSP 56824EVM was considered suitable for this biomedical application since its performance parameters include high-speed, multi-signal control capability, reliability and stability. These performance parameters are considered to be the most important when designing biomedical instruments dealing with human beings' life and safety. The objective of this research was the development and implementation of a DSP algorithm for the detection and measurement of the sizes of air bubbles in a fluid. In addition the algorithm had to possess the capability, when appropriate, to initiate protective and awareness measures such as triggering a tube clamp as well as activating visual and audio alarms. The air detection was accomplished by means of a commercial air detector module, which was based on piezo ceramic and ultrasound sensing. The function of the tubing clamp was to stop the fluid flow in the tub ing and prevent an air bubble from entering the patient's circulatory system. A secondary goal of this research was to exploit the capability of the DSP 56824EVM and demonstrate its suitability for biomedical applications.
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Thesis (M.S.)--University of South Florida, 2005.
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Includes bibliographical references.
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by Nhat Nguyen.
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Development and Implementation of a DSP Based Air Detector System to Prevent Embolism During Hemodialysis Therapy by Nhat Nguyen A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Wilfrido Moreno, Ph.D. James T. Leffew, Ph.D. Paris Wiley, Ph.D. Date of Approval November 4th, 2005 Keywords: CodeWarrior, Timer, Interrupt, Ultrasound, Piezoelectric Effect Copyright 2005, Nhat Nguyen

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DEDICATION I dedicate this thesis to my father, Nguyen Chi, and my mother, Nguyen Thi Kinh.

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ACKNOWLEDGEMENTS I would like to take the o pportunity to thank my major professor Dr. Wilfrido Moreno for supporting me throughout my undergraduate and graduate studies. I would like to thank the enti re faculty and staff of the Department of Electrical Engineering at the University of South Florid a. Particular menti on goes to Dr. Wiley, Dr. Leffew and Prof. Ezurek for th eir teachings and education. I would like to thank Angel Lasso, Director of Engineering at Baxter Tampa Bay for giving me the opportunity to intern at Baxter and for supporting the development of my thesis. I would like to thank all the engineers and employees at Baxter Tampa Bay. Particular mention goes to Dr. Alex Yu, East Lee, Joel Tejedor, Hector Caro and Derrick Benton for improving my engineering skills and making my internship such an incredible learning experience. Last but not least, I would like to thank Yohan Prevot for his continuous support and friendship.

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i TABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES v LIST OF CODES viii ABSTRACT ix CHAPTER 1 INTRODUCTION 1 1.1 Problem Statement 1 1.2 Research Objective 2 1.3 Thesis Organization 3 CHAPTER 2 BIO-MEDICAL OVERVIEW 5 2.1 Kidney Function and Kidney Failure 6 2.2 Medical Treatments 8 2.3 Hemodialysis 11 2.4 Air Embolism 14 CHAPTER 3 SYSTEM OVERVIEW 15 3.1 Air Detector Module 15 3.1.1 Piezo Electric Ceramic and Piezo Electric Effect 16 3.1.2 Ultrasonic Transmitter and Receiver 19 3.1.3 Acoustic Impedance and Impedance Mismatch between Air and a Fluid 20 3.2 Blood Line Clamp 24 3.3 By Pass Loop for Air Bubble Injection 25 3.4 Visual and Audio Alarms 27 CHAPTER 4 HARDWARE OVERVIEW 28 4.1 Interface Circuit Board 28 4.1.1 DC-DC Converter 30

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ii 4.1.2 556 Timer Circuit Driving the Audio Buzzer Alarm 32 4.1.3 3.3V Voltage Regulator 36 4.1.4 Diode Clamp Circuit 37 4.1.5 LEDs 38 4.2 Motorola DSP 56824EVM 39 4.2.1 Port B: General Purpose Input/ Outp ut, (GPIO), Port 41 4.2.2 Clock Synthesis 46 4.2.3 Timers 49 4.2.4 Generation of Interrupts 52 CHAPTER 5 SOFTWARE OVERVIEW 58 5.1 Metrowerks CodeWarrior Developmen t Environments 58 5.2 Air Detection Algorithm 59 5.2.1 Registers Settings 64 5.2.2 GPIO Interrupt Service Routine 66 5.2.3 Air Detector Input Signal Detection 68 CHAPTER 6 EXPERIMENTAL RESULTS 74 6.1 System Validation Test 75 6.2 System Performance Test 76 CHAPTER 7: CONCLUSIONS AND FUTURE WORK 83 7.1 Conclusions 83 7.2 Future Work 84 REFERENCES 85 APPENDICES 87 Appendix A Air Detector DSP Code 88 Appendix B Register.h Code 92 Appendix C System Performance Test Data 93

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iii LIST OF TABLES Table 3.1: Typical Piezo Electri c Materials and their d and K Values 19 Table 3.2: Impact of Temp erature on Acoustic Impedance 21 Table 3.3: Acoustic Impedance in Diffe rent Media 22 Table 4.1: Truth Table for the 74ACQ 244 Chip 31 Table 4.2: Limiting Resistances 39 Table 4.3: Port B: GPIO and PBDDR Re gister Formats 43 Table 4.4: PBDR Register When No Air wa s Detected in the Blood 44 Table 4.5: PBDR Register When Air was De tected in the Blood 44 Table 4.6: PBINT Register for Detection of Rising Edge Transition on PB0 45 Table 4.7: PBINT Register for Detection of Fa lling Edge Transition on PB0 46 Table 4.8: PCR0 Register for the 70MHz Clock Signal 47 Table 4.9: PCR1 Register for the 70MHz Clock Signal 48 Table 4.10: Clock Source/Eve nt Select Bits Association 51 Table 4.11: TCR01 Register Format 51 Table 4.12: TCR2 Register Format 51 Table 4.13: TCR01 Register for Activation of the Timer1 & Timer0 Timing Modules 52 Table 4.14: Interrupt Prio rity Structure; Level 1 54 Table 4.15: Interrupt Prio rity Structure; Level 0 54

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iv Table 4.16: Main Interrupt Sources a nd their Interrupt Vectors 55 Table 4.17: Bit Configuration of the ISR Register 56 Table 4.18: IPR Register for Port B GPIO Interrupt Generation 57 Table 4.19: IPR Register for IRQB Push-Bu tton Interrupt Generation 57 Table 4.20: SR Register to Enable IPLO Interrupts 57 Table 5.1: On-Chip Periphera l Registers and their Memory Addresses 64 Table 5.2: State 1 Inputs and Next States 69 Table 6.1: System Validation Test Results 76 Table C.1: 10 to 50 L Air Bubble Injections 93 Table C.2: 60 to 100 L Air Bubble Injections 93

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v LIST OF FIGURES Figure 1.1: DSP Based Air Detector System 4 Figure 2.1: ESRD Worldwide Patient P opulation 6 Figure 2.2: Front View of Urinary Tract 7 Figure 2.3: Right Kidney Sectioned 8 Figure 2.4: Kidneys Vasculatur e 8 Figure 2.5: PD Process 10 Figure 2.6: Hemodialysis Process 12 Figure 2.7: Central Venous Ca theter Assess 12 Figure 2.8: Fistula Access 13 Figure 2.9: Graft Access 13 Figure 3.1: Air Detector Module 15 Figure 3.2: Induced Polarization Due to an Applied Mechanical Strain 16 Figure 3.3: Induced Polarization Resulting in an Electric Field 17 Figure 3.4: Mechanical Strain Due to an Applied Electric Field 18 Figure 3.5: Ultrasonic Transmitter a nd Receiver System 20 Figure 3.6: Sound Pressure in Di fferent Media 23 Figure 3.7: Blood Line Clamp 24 Figure 3.8: Blood Line Tubing 25 Figure 3.9: Peristaltic Pump 26

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vi Figure 3.10: Visual and Audio Alarms 27 Figure 4.1: Interface Circuit Board 29 Figure 4.2: Schematic Diagram of the Interface Circuit Board 29 Figure 4.3: IC Connection Diagram for the 74ACQ244 Chip 31 Figure 4.4: Schematic Diagram of the DC-DC Converter 32 Figure 4.5: Schematic Diagram of the 556 Astable Timer 33 Figure 4.6: The 556 Astable Timer and Ca pacitor Output Plots 34 Figure 4.7: Block Diagram of the 556 Timer 34 Figure 4.8: Schematic Diagram of the LM317 Voltage Regulator 36 Figure 4.9: Schematic Diagram of th e Diode Clamp Circuit 37 Figure 4.10: Output of Diode Clamp Circuit 38 Figure 4.11: Schematic Diagram of the Power LEDs 39 Figure 4.12: DSP56824 Chip Architecture 40 Figure 4.13: Connection Diagram for the DSP GPIO Board 43 Figure 4.14: Block Diagram of On-Chip Cl ock Synthesis Module 47 Figure 4.15: Block Diagram of the Timer Module 50 Figure 4.16: Interrupt Service Routine Diagram 53 Figure 5.1: CodeWarrior IDE Debugging Window 59 Figure 5.2: Main Program Flow Chart 60 Figure 5.3: Port B Interrupt Servic e Routine Flow Chart 62 Figure 5.4: IRQB Push-bu tton Interrupt Service Routine Flow Chart 63 Figure 5.5: State Diagram fo r Air Detector Input Signal Detection Method 68 Figure 6.1: Bovine Blood Used During Testing 75

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vii Figure 6.2: XY-Scatter Plot of Sy stem Performance 78 Figure 6.3: 3D Column Plot of System Performance 79 Figure 6.4: Average and Sta ndard Deviation Plots of System Performance 80 Figure 6.5: Line Plot of System Performance 81 Figure 6.6: Detection Per centage Plot of System Performance 82

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viii LIST OF CODES Code 5.1: Simplified Version of Main Program 65 Code 5.2: Setup Interrupt Service Routine 67 Code 5.3: Output of State 2 70 Code 5.4: Output of State 3 71 Code 5.5: Behavior of State 4 72 Code 5.6: Behavior of State 5 73

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ix DEVELOPMENT AND IMPLEMENTATION OF A DSP BASED AIR DETECTOR SYSTEM TO PREVENT EM BOLISM DURING HEMODIALYSIS THERAPY Nhat Nguyen ABSTRACT This thesis describes the design of a DSP based air detector system to prevent air embolism during Hemodialysis, which is a trea tment option for kidney failure disease. Hemodialysis consists of removing blood fr om the body, filtering and treating the blood to remove toxic substances such as wastes and fluids, reestabl ishing proper chemical levels in the blood and returning the proce ssed blood to the body. The functions of hemodialysis are performed through the use of a dialyzer, which is also known as an artificial kidney. During hemodialysis sm all air bubbles may infilt rate the tubing used during the therapy and combine to form larger air bubbles that are harmful to the patient. If an air bubble is la rge enough and enters the patients circulatory system, the blood flow can be blocked and the patient can die by embolism. Most of the hemodialysis instruments in use today are equipped with air detection systems, which are based on analog design and digital microcontrollers. This thesis presents a design method based strictly on DSP technology. The Motorola DSP 56824EVM was considered suitable for this bi omedical application since its performance

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x parameters include high-speed, multi-signal c ontrol capability, reliability and stability. These performance parameters are considered to be the most important when designing biomedical instruments dealing with human beings life and safety. The objective of this research was the development and implement ation of a DSP algorith m for the detection and measurement of the sizes of air bubbles in a fluid. In addition the algorithm had to possess the capability, when appr opriate, to initiate protecti ve and awareness measures such as triggering a tube clamp as well as activating visual and audio alarms. The air detection was accomplished by means of a co mmercial air detector module, which was based on piezo ceramic and ultrasound sensing. The function of the tubing clamp was to stop the fluid flow in the tubing and preven t an air bubble from en tering the patients circulatory system. A secondary goal of this re search was to exploit the capability of the DSP 56824EVM and demonstrate its suitabi lity for biomedical applications.

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1 CHAPTER 1 INTRODUCTION 1.1 Problem Statement The kidneys have the physiological f unction of cleaning the blood by removing wastes, excess fluids and minerals. Additiona lly, the kidneys regulate the level of certain chemicals such as sodium, phosphorus and potassium in order to maintain an adequate chemical balance in the body. When the kidne ys’ functionality is gr eatly reduced or the kidneys completely cease to work, kidney failure occurs. A person suffering renal disfunction usually undergoes medical treatme nts to sustain life. A common medical treatment for kidney failure is Hemodialysis, wh ich uses an artificial kidney to clean the blood. A rare but possible problem associated with hemodialysis is the infiltration of small air bubbles inside the tubing used duri ng the therapy. The in filtrated air gases, inside the blood, can combine together and fo rm large air bubbles, which are called air emboli. These air bubbles are very dangerous and harmful to the patient. If an air bubble enters the patient’s circulatory syst em the blood flow can be blocked and the patient can die as a result of the air embo lism. Depending on the size of the air bubble and the location where the blood stream is obstructed, air embolism can cause strokes, brain damage and cardiovascular arrest.

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2 1.2 Research Objective This research focused on the development and implementation of an air detector system to prevent air embolism during he modialysis therapy. Most of the new hemodialysis instruments in use today are eq uipped with air detection systems based on analog designs and the use of digital microcontro llers. This research was directed toward the development and implementation of an air detection system based on Digital Signal Processing, (DSP), technology. Any DSP, whic h is adequate for such a biomedical application, must possess performance char acteristics that include high-speed, multisignal control capability, reliability and stab ility. Such performance parameters are considered to be the most important require ments in designing biomedical instruments, which deal with human beings’ life and safety. The Motorola DSP56824EVM was considered to be suitable for this biomedical application. The detection of the entrapped air was accomplished through the use of a commer cial air detector module, which utilized piezo ceramic and ultrasound sensing. A DSP algorithm was developed and implemented to recognize the signal generated by the air detector module. Measurement of the sizes of the air bubbles was accomp lished by examining the pulse width of the electrical signals received from the air detector module. Additionally, the DSP algorithm was used to trigger a tubing clamp as well as a visual and audio alarm when the presence of 60L air bubbles was detected. The functi on of the tubing clamp was to stop the blood flow in the tubing and prevent the air bubbles from re-entering the patient’s circulatory system. The DSP algorithm was also structur ed so that if air bubbles smaller than 60L were detected neither the tubing clamp nor any of the alarms triggered. The ultimate goal

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3 of this research was to exploit the capabi lity of the DSP56824EVM and demonstrate its suitability for biomedical applications. 1.3 Thesis Organization This thesis consists of 7 chapters. Ch apter 2 provides a biomedical overview, which presents the physiology of kidneys and general medical information about kidney failure, hemodialysis therapy and problems associated with air embolism. Chapter 3 provides an overview of the DSP based Air De tector System from the system level point of view. Chapter 3 illustrate s the physics behind the detec tion of air and describes the various components in the system, their charac teristics and their func tional properties. The discussion continues in Chapter 4, which il lustrates the electric al hardware employed by the system. Chapter 4 emphasizes the de sign of the Interface Circuit Board and the hardware characteristics of the Motorola DSP56824EVM board. Chapter 5 describes the software algorithm and the codes that we re developed and implemented on the DSP board in order to detect and measure the pulse width of the signal generated by the Ultrasonic Air Detector module. A System Validation Test and the System Performance Data are presented in Chapter 6. The Syst em Validation Test was conducted to ensure that the Dsp based Air Detector System consis tently, reliably and accurately detected air bubbles in the blood. The System Performan ce Data were collected using bovine blood to analyze the system performance with different sizes of air bubbles and to verify that air bubbles larger than 60L were successf ully stopped via th e blood line clamp. Conclusions and future work recommendations are discussed in Chapter 7. Figure 1.1 provides a picture of the system developed during this research.

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4 Figure 1.1: Dsp Based Air Detector System

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5 CHAPTER 2 BIO-MEDICAL OVERVIEW Throughout the United States in exce ss of 450,000 people are undergoing medical treatment for end-stage renal disease, (ESR D), which is irreversible and lethal if untreated. Based on data published by the Ce nters for Medicare and Medicaid Services, (CMS), the approximate number of ESDR patients under Medicare or Medicaid that require medical treatments has grown fr om 66,000 in 1982 to 260,000 at the end of 2000. This population is estimated to be growing at an annual rate of 8%. The most recent and complete data for the total ESRD populati on in the United States come from the 2004 Annual Data Report of the United States Rena l Data System, (USRDS). The USRDS is a national data system that collects, analyzes and distributes information about ESRD in the United States in conjunction with the CM S. According to this annual report the number of patients receiving ESRD therapy at the end of 2002 was 431,284. This implies that approximately one of every 3500 people in the United States is undergoing treatment for ESRD. However, this problem is not isolated to the United States. In 1984 the number of ESDR patients worldwide was estimated to be 300,000. Today there are approximately 1,500,000 people with renal failur e. Figure 2.1 illustrates the worldwide ESRD patient population.

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6 Figure 2.1: ESRD Worldw ide Patient Population ESRD is not only a serious medical problem for the United States. ESRD is a public health concern throughout the world. Th erefore, an understa nding of the problem from the medical prospective is essential fo r optimizing treatment and medical devices, which sustain life for those affected by ESRD. 2.1 Kidney Function and Kidney Failure The kidneys are organs located just be low the rib cage near the middle of the lower back. The physiological function of healthy kidneys is to clean the blood by removing excess fluid, minerals and wastes. Ea ch day a pair of kidneys processes about 200 quarts of blood. Approximately 2 quarts of waste products and extra water, which become urine, are filtered from the blood by the kidneys. Urine is collected in the bladder after it flows through t ubes, called ureters. Wastes in the blood originate from the normal breakdown of active tissues and fr om the digestive process of food. The body uses the nutritious elements from food for ener gy and self-repairs, while the waste is sent to the blood. Figure 2.2 illustrates the front view of the urinary tract.

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7 Figure 2.2: Front View of Urinary Tract The filtering process in the kidneys takes place in tiny elements called nephrons. A healthy kidney has about a million nephrons. In a nephron, chemical exchange occurs in small blood vessels called glomerulus, wh ich are connected to tiny urine collecting tubes or tubule. During the chemical exch ange waste materials and excess water leave the blood and enter the urinary system. Simulta neously, the kidneys regulate the level of chemicals such as sodium, phosphorus and pot assium in order to maintain the proper chemical balance necessary for life. If the body has insufficient amounts of these substances, the kidneys release them back to the blood. On the contrary, if these chemicals are excessive they are purged fr om the blood via the urinary system. In addition to removing wastes and balancing chemicals in the body, the kidneys produce hormones that keep bones strong and mainta in healthy blood. Figure 2.3 and 2.4 picture respectively the internal com ponents of a healthy kidney and the typical appearance of kidney’s blood vessels, (vasculature).

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8 Figure 2.3: Right Kidney Sectioned Figur e Figure 2.4: Kidney’s Vasculature When the kidneys stop operating at their full potential or lose completely their physiological functions ESRD occurs. Harm ful wastes build up in the body causing blood pressure to rise and excess fluid to be retained in the blood. These conditions adversely affect the synthesis of red blood cells, which leads to anemia and medical conditions that affect bones, (Renal Osteodystrophy), nerves and skin (Pruritus due to uremic toxins). 2.2 Medical Treatments Two options are available to an individua l that has been diagnosed with ESRD. In the United States a person can choose to undergo medical treatment s to sustain life or refuse and/or withdraw from medical treatment if that individual feel s that such treatment is a burden that will only pr olong suffering. This second, extreme, choice leads to death within weeks due to the fata l nature of the disease. Individuals who choose life sustaining treatments have a choice of th ree medical treatment options, which are:

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9 Hemodialysis, Peritoneal Dialysis, Kidney Transplantation. Hemodialysis, (HD), is a therapy that cl eans and filters blood by using a machine to temporarily remove harmful wastes, extra salt and extra water. During HD blood is pumped out of the body and is run through an ar tificial kidney called a dialyzer. Wastes and extra water are removed while chemical s such as potassium, sodium, calcium and bicarbonate are brought to physiological levels. Hemodialysis is usually required three times a week. Each treatment lasts from 3 to 5 or more hours. Usually, HD is performed in specialized clinics. However, a new ge neration of hemodialysis machines allows hemodialysis to be performed comfortably at home. Peritoneal dialysis, (PD), us es the lining of the abdomen to remove wastes. This lining is called the peritoneal membrane and acts as the ar tificial kidney. During PD the peritoneal cavity is filled, through a soft tube, with a dial ysis solution that contains a mixture of minerals and sugar. The sugar, called dextrose, draws wastes, chemicals and extra water from the tiny blood vessels inside the peritoneal membrane into the dialysis solution. The filtering process takes severa l hours. Once it is completed, the used solution is drained from the peritoneal cavity and collected in a disposable bag. There are two types of Peritoneal Dialysis. Conti nuous Cycler-Assisted Peritoneal Dialysis, (CCPD), uses a machine called a cycler to fill and empty the periton eal cavity with the dialysis solution three to five times at night, while the individual is sleeping. In the morning the patient is required to perform only one exchange th at lasts the entire day. A

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10 drain is performed at bedtime when the cycler is reconnected. The s econd type of PD is called Continuous Ambulatory Peritoneal Di alysis, (CAPD), which does not require the use of a cycler machine. CAPD requires the dialysis solution to always be present in the abdomen. The dialysis solution is excha nged 4 to 5 times a day by manually draining and refilling the abdomen. At night the patien t fills the peritoneal cavity with the solution and drains it in the morning. Both PF therapie s require strict asepti c techniques. Figure 2.6 illustrates the PD process. Figure 2.5: PD Process Hemodialysis and peritoneal dialysis are medical treatments that replace the kidney functions. These treatments help patients to feel better and live longer. However, they do not cure kidney failure Surgical kidney transplantat ion is considered to be the only definitive cure for ESRD. Kidney transp lantation consists of surgically placing a healthy kidney from a donor into the patient’s body. The replacement kidney can be donated by a family member of the patient, (living related donor), by a person who has recently died, (deceased donor), or from a spouse or a very close friend of the patient, (living unrelated donor). If an ESRD individual does not ha ve a living donor the patient is placed on a waiting list for a deceased donor kidney. The wait for a deceased donor kidney can be several years. Therefore, patients awaiting a replacement kidney, from a

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11 deceased donor, will be required to receive di alysis treatments. There are three main factors in matching available kidneys with pot ential recipients. These factors help to predict whether the patient’s immune system will accept or reject the new kidney. The three factors are: Blood type, Human leukocyte antigens, (HLAs), Cross-matching antigens. Blood type is the most important matchi ng factor. The blood type of the donor has to match the blood type of the recipient. In addition the HLAs of the donor and the recipient have to be compatible. Since HLAs are inherited antigens, family members are most likely to possess a complete match. The la st factor is cross-matching. This is the last step before implanting the organ. A sm all sample of the blood of the donor is mixed with the blood of the recipient to see if there is a side-eff ect reaction. When these three factors are successfully matched the tr ansplant operation can take place. 2.3 Hemodialysis As described in section 2.2, hemodialysis is a therapy that rem oves organic wastes and extra water by filtering blood. During hemodialysis a machine pumps blood out of the patient’s body via a system of tubings. The blood is run through an artificial kidney called a dialyzer and then returned to the patient. Waste in th e blood is removed by a diffusion process while extra fluids are elim inated by an ultrafiltration method. Heparin is infused in the blood, during the therapy, to prevent the blood from coagulating and clotting. A system of multiple arterial and venous pressure m onitors are engaged in order

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12 to ensure the blood pressure is kept within a safe margin. An air trap and air detector are used to prevent air embolism. Figure 2.7 illustrates the hemodialysis process. Figure 2.6: Hemodialysis Process Before starting hemodialysis, a vascular access to the bloods tream has to be created in order to provide a means of ex tracting and returning blood rapidly from the body to the hemodialysis machine. Typicall y, there are three main types of accesses. The first type is the Central Venous Catheter which is a long slende r tube placed in a vein either in the chest, neck or le g. Figure 2.7 illustrate s a venous catheter. Figure 2.7: Central Venous Catheter Assess

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13 The second access is via a fistula. The fistul a is a direct surgi cal connection of an artery to a vein, which is usually located in the forearm. The increased blood flow makes the vein grow larger and stronger, which facili tates its use for repeated needle insertions. Figure 2.9 illustrates a fistula for hemodialysis. Figure 2.8: Fistula Access The last type of vascular access uses a graft, which conn ects an artery to a vein through the use of a synthetic t ube. Hemodialysis needles are inserted into the synthetic tube instead of the vein. Figure 2.10 illustrates a graft vascular access. Figure 2.9: Graft Vascular Access Vascular accesses dangerously expose bl ood and the circulatory system to the environment. If not cleaned regularly a nd disinfected appropriately, vascular accesses can be subjected to infection. Additionall y, if hemodialysis needles are accidentally disconnected, air may infiltrate and travel inside the blood causing air embolism.

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14 2.4 Air Embolism Embolism occurs when a solid, semi-solid or gaseous substance traveling in the bloodstream obstructs the blood flow. The s ubstance is called an embolus. Common types of embolus are blood clots, crystal or chol esterol, clumps of infected cells, bits of bone marrow and a mix of air gases. If the blood obstruction is caused by air bubbles circulating in the blood an air embolism arises When an air embolus is present in an artery, it will travel through a system of cap illaries that gradually becomes smaller. The embolus will eventually reach a point where it completely blocks a blood vessel and cuts off the blood supply to some area. Absence of blood to an area cau ses the corresponding tissues and cells to die due to the absence of oxygen. If the embolus blocks an artery that supplies the brain a stroke will ensue and perm anent brain damage will occur. However, if the air embolus occurs in a vein it does not cause harm until it reaches the heart since the vein system widens along the direction of the blood flow. In addition, if the air embolus is large enough to block a cardiac artery a cardiovascular collapse may take place. Air embolism during hemodialysis thera py is a rare but potentially lethal complication. Air can infiltrate inside the hemodialysis circuit from malfunctioning tubing fittings, vascular assess’ needles and loose dialyzer port s. The dialyzer itself may be a source of air if refrigerated dialysate co ntaining dissolved air is used. In fact, due to the pressure developed in the tubing and the blood flow rate, dissolv ed air may aggregate and form larger air bubbles. Due to the danger of air embolism, new hemodialysis machines are equipped with the double safety fe atures of an air trap chamber and an air detector module.

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15 CHAPTER 3 SYSTEM OVERVIEW In order to understand how the DSP based Air Detector functi ons, it is important to comprehend the physics behind the air dete ction and to learn the various components in the system. This chapter introduces each module and explains their characteristics and functional properties. 3.1 Air Detector Module The Air Detector Module is a commercia l, non-invasive, ultr asonic transducer that is used to detect the pr esence of air bubbles in fluid flowing through flexible plastic tubing. Two precision piezo electric ceramic plates are secure d within a molded protective housing. The plates are positioned so that they face one another. The tubing is placed between the two ceramic plates. Figure 3.1 provides a picture of the Air Detector Module. Figure 3.1: Air Detector Module

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16 3.1.1 Piezo Electric Ceramic and Piezo Electric Effect Piezo electric ceramics are materials that have the unique property of producing electrical charges when compressed, twisted or distorted and exhibit mechanical strain or distortion when an electric field is applied. If a piezo electric cer amic is mechanically stressed, charge separation occurs on the su rfaces of the ceramic. As a result, one surface of the ceramic becomes positively ch arged while the other side is negatively charged, which causes a potential difference to develop. Changing the direction of deformation reverses the polarity of the ge nerated voltage as ill ustrated in Figure 3.2. Figure 3.2: Induced Polarization Due to an Applied Mechanical Strain (a) Piezo Electric Ceramic in the absence of an applied force. (b) Piezo Electric Ceramic under a compressional force. (c) Piezo Electric Ceramic under a tensional force. Generally, an applied stress in one dir ection produces an induced electrical potential in other di rections. Suppose a mechanical force, Tj, along the j-direction is

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17 applied to a piezo ceramic. An induced polarization, Pi, will result, which is linearly related to Tj by: Pi = dij Tj, (3.1) where dij is the Piezo Electric Coefficient For most materials, the resulting electric field and the polarization are related by: P= 0 e E (3.2) where e is the Electric Susceptibility and 0 is the Permittivity of Free Space. Figure 3.3 illustrates how the induced polarization of charge produces an electric field. Figure 3.3: Induced Polarization Resulting in an Electric Field On the contrary, the same piezo electric ceramic shows signs of mechanical strain and distortion when the ceramic is placed into an electric field. The direction of mechanical deformation depends on the directio n of the applied field and the intensity is proportional to the strength of the field. The induced strain, Sj, along the j-direction is proportional to the applied electric field, Ei, along the i-direction. The induced strain and the applied electric field are related by: Si = dij Ej. (3.3) Figure 3.4 illustrates the relati onship of induced strain due to the applied electric field.

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18 Figure 3.4: Mechanical Strain Du e to an Applied Electric Field (a) Piezo Electric Ceramic in the abse nce of an applied electric field. (b) Piezo Electric Ceramic under an applied electric field, V. (c) Piezo Electric Ceramic under an applied electric field, -V. These two effects are paired t ogether and define the Piezo Electric Effect, which can be a Direct Effect or a Converse Effect. Piezo electric ceramics are electromechan ical transducers that convert an electrical signal into a mechanical signal and vice versa. They are widely used in many engineering applications such as crystal osc illators, ultrasonic transducers, accelerometers and microphones. The relationship between elec trical and mechanical energies is given by the Electromechanical Coupling factor, K, which is defined in terms of K2 by: 2Electrical Energy converte d to Mechanical Energy K= Input of Electrical Energy (3.4) and 2Mechanical Energy converted to Electrical Energy K= Input of Mechanical Energy (3.5) Table 3.1 lists some typical piezo electric materials and the values for their d and K coefficients.

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19 Table 3.1: Typical Piezo Electric Ma terials and their d and K Values Piezo Electric Material Piezo Electric Coefficient d (m V -1) Electromechanical Coupling Factor K Quartz (crystal SiO2) 2.3 X 10-12 0.1 Barium Titanate (BaTiO3) 190 X 10-12 0.49 Lead Zirconate Titanate (PbTi1xZrxO3) 480 X 10-12 0.72 Polyvinylidene Fluoride (PVDF) 18 X 10-12 3.1.2 Ultrasonic Transmitter and Receiver Piezo electric ceramics are widely used to generate ultrasonic waves, (ultrasonic transmitter), and to detect such waves, (ultrasonic receiver). Piezo electric ceramics possess two modes of operati on. The first mode is known as the Generator Mode In the Generator Mode an applied voltage causes the piezo electric ceramic to distort, which causes mechanical strain as described in sec tion 3.1.1 and is known as a Converse Effect. If a sine wave voltage at an ultrasonic frequency is applied to the ceramic, (transmitter), and the ceramic is in contact with a medi um it will create a compressional wave that travels through the medium. The generated compressional wave can be longitudinal or transverse according to the ceramic’s cut and shape. The vibration is largest when the electric field stimulates a natural frequenc y of the piezo electric ceramic. Such a frequency is known as a Resonant Frequency. Generally, the ceramic is cut into a slice

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20 with a thickness equal to one-half of the wave length of the desired ultrasonic frequency. This construction ensures that most of the ener gy is emitted at the fundamental frequency. The second mode of operation is called the Motor Mode When a mechanical wave strikes a ceramic it distorts and creates a volta ge, which is viewed as a Direct Effect. Taking advantage of these two modes of operation makes it possible to build an ultrasonic transmitter and receiver system by placing two ceramic plates that face each other and are coupled together. Figure 3.5 illustrates the ultrasoni c transceiver system. Figure 3.5: Ultrasonic Transmitter and Receiver System 3.1.3 Acoustic Impedance and Impedan ce Mismatch between Air and a Fluid Ultrasound is defined as hi gh frequency sound waves, wh ich are above the range of human hearing. Normally the ultrasoni c frequency range starts at 20 kHz and go up into the megahertz range. As sound wave s, ultrasonic waves are simply organized mechanical vibrations trav eling through a medium at a specific speed and with a predictable direction of propa gation. When the waves encounter a boundary, with a different medium, a portion of their energy will be reflected and a portion will be

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21 transmitted. The amount of reflected energy is related to the acoustic impedances of the two media. Given any two medi a, the reflection coefficient, as a percentage of incident energy is calculated as: 21 21Z-Z = Z+Z (3.6) where Z1 and Z2 are the acoustic impedance of medium 1 and medium 2 respectively. The acoustic impedance is defined as the ratio of the sound pressure, p, to particle velocity, v. The acoustic impedance is also the product of the density, of the medium and the speed of sound, c, in the medium. The acoustic impedance is measured in Pa s/m and is given by: 2 2pJp Z==== c vvJ (3.7) where J is the sound intensity measured in W/m2. Temperature also has an impact on acoustic impedance. In most cases higher te mperatures yield lower acoustic impedances. Table 3.2 presents the impact of temperature on acoustic impedance. Table 3.2: Impact of Temp erature on Acoustic Impedance Temperature (C) Speed of Sound in Air C(m/s) Density of Air (kg/m3) Acoustic Impedance (Pa s/m) -10 325.4 1.341 436.5 -5 328.5 1.316 432.4 0 331.5 1.293 428.3 5 334.5 1.269 424.5

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22 Table 3.2: Continued 10 337.5 1.247 420.7 15 340.5 1.225 417.0 20 343.4 1.204 413.5 25 346.3 1.184 410.0 30 349.2 1.164 406.6 Air and blood have very different acoustic impedances. A beam of ultrasonic waves, going from blood to air, is almost entirely reflected and only a small portion is transmitted. This effect is due to the fact that the acousti c impedance of blood is several orders of magnitude larger than the acoustic impedance of air, which causes the mismatch between air and blood, as well as the reflection coefficient, to be very high. Table 3.3 lists different medium and the relative acousti c impedance. The acoustic impedances of air and blood are given sp ecifically in Table 3.3. Table 3.3: Acoustic Impe dance in Different Media Medium Acoustic Impedance (Pa s/m) Air 429 Water 1500000 Blood 1590000 Fat 1380000 Muscle 1700000 Bone 6500000

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23 The enormous acoustic impedance mismatch between air and blood is the key to the ability to detect air bubbles in blood. When the ultrasonic transmitter is excited by a sine wave voltage of a given frequency comp ressional waves are created. In the present of only blood, the sound pressure amplitude re ceived by the ultrasonic receiver matches closely the amplitude of the transmitted wave The piezo ceramic on the receiver side gets excited, becomes polarized and creates an electrical signal as illustrated in Figure 3.6. (a) (b) Figure 3.6: Sound Pressu re in Different Media (a) Sound Pressure in the presence of only blood (b) Sound Pressure in presence of air bubble in blood When an air bubble passes through the tubing, the compressional waves are greatly reduced in intensity by the reflection phenomenon. The piezo ceramic on the receiver side returns to a neut ral electrical state an d no electrical signal is produced. The electrical signal is not presen t for the entire time the air bubb le passes through the tubing.

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24 It is possible, with proper electrical signal cond itioning, to generate an electric pulse that is logic high when blood is flowing in the tu bing and logic low when air is passing. In addition, the width of the pulse can be made proportional to the size of the air bubble. It is this pulsed signal that alerts the DSP board of the presence and the size of an air bubble in the blood. 3.2 Blood Line Clamp The function of the blood line clamp is to pinch the tubing as soon as the system detects a harmful air bubble in the blood line. By clamping the tubing, the blood flow is stopped and the air bubble cannot enter the patien t’s circulatory system A brushless DC motor was used to accomplish this task. The motor features high energy neodymium magnets for high torque, high speed and extr emely smooth and precise motion. It required a +24V input voltage and turned on when +5V was applied to its Clamped Signal. The output torque generated by the mo tor, when it turned on, was 90oz-in. The current drawn by an active motor was 1.15A. Figure 3.7 presents a picture of the blood line clamp assembly. Figure 3.7: Bl ood Line Clamp

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253.3 By Pass Loop for Air Bubble Injection For testing purposes, a By Pass Loop was requi red in order to inje ct air bubbles. Due to the flow and the pressure developed inside the tubing an air bubble was likely to break into smaller bubbles if it was injected directly inside the tubing. In the By Pass loop, a Y connector was used to divide the blood flow into two lines. The main line constantly allowed the blood to flow. The second one was manually clamped through the action of a brushless DC mo tor/clamp, which was identical to the Blood Line Clamp. When the line was clamped, the blood flow was stopped. However, the blood continued to stream into the main line. Since the by pass line was pinched a bubble could be manually injected without being broken by the combined action of pressure and flow. Figure 3.8 presents a diagram of the blood line tubing setup. (a) (b) Figure 3.8: Blood Line Tubing (a) Blood flows in both lines (b) Blood flows only into the By Pass Loop

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26 The air bubble injection wa s performed using a L-calibrated syringe via the injection port. Once the ai r bubble was entered in the tubing, the By Pass Loop clamp was manually turned off, which allowed th e blood to flow in both lines and then recombined together though a second Y c onnector. The air bubble was then pushed by the blood flow and traveled through the tubi ng eventually reaching the air detector module. The flow speed was controlled by a peristaltic blood pump that sucked the blood from a blood container, ran it through th e system’s tubing and returned it to the same container in a continuous cycle. Figur e 3.9 presents a picture of the Peristaltic Pump. Figure 3.9: Peristaltic Pump

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273.4 Visual and Audio Alarms The system developed in this research was provided with both a visual and an audio alarm. When the blood was free of ai r a bi-color LED, with a green color, was illuminated and the audio alarm was set to mute. When a harmful air bubble was detected the bi-color LED turned red and the audio alarm emitted a pulsed sound. Figure 3.9 presents a picture of the vi sual and audio alarm mechanism. Figure 3.10: Visual and Audio Alarms

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28 CHAPTER 4 HARDWARE OVERVIEW The main hardware components utilized in this research were the Interface Circuit Board and the Motorola DSP56824. The following sections provide an overview of these two components. 4.1 Interface Circuit Board The interface circuit board was designed to allow the system components to efficiently interact with each ot her and to be electrically comp atible in terms of input and output voltages. In addition, the interface ci rcuit was required in order to accommodate, on board, all the analog signals utilized by th e DSP based Air Detector System. Figure 4.1 provides a picture of the Interface Circuit Board while Figure 4.2 presents the circuit schematic of the Inte rface Circuit Board.

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29 Figure 4.1: Interface Circuit Board R6 240 0 D3 +3.3V 555 Timer Astable C3 20u By Pass Clamp On/Off Switch 3.3V R12 35k 5Vdc DSP Board U6 0 1 2 R8 1200 R3 .1Meg R11 3.5k D2 +5V 3.3V_Logic_High_1 R9 D6 RED Clamped Signal of By Pass Clamp R1 1460 J1 CON18A 1 3 5 7 9 11 13 15 17 2 4 6 8 10 12 14 16 18 0 0 R7 323 5V_Square_Wave U2 74ACQ244 10 1 20 2 4 6 8 19 17 15 13 11 18 16 14 12 3 5 7 9 GND OE1 VCC I0 I1 I2 I3 OE2 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7 Air Detected2.6V 5V_Logic_High_2 0 03.3V_Logic_High_2 24Vdc 5V Audio Alarm Buzzer5V R2 193 GPIO3.3V_Square_wave R10 .1Meg D4 D1N914 R17 10k 3.3 V Voltage Regulator Clamped Signal of Blood Line Clamp C2 0.1u R15 .1Meg U5A LM556 3 6 2 4 7 5 1 14CON TRG THRES RSTGNDOUT DISVCC D1 +24V R4 80 5V R16 .1Meg DC-DC Converter 5V_Logic_High_1 R5 394 R14 80 D5 GREEN Visual Alarm LEDs U1 LM317K 2 3 1INOUTADJ Diode Clamp Power LEDs 0 R13 80 0 C1 1u Figure 4.2: Schematic Diagram of the Interface Circuit Board

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30 The operational characteristics for each sub-ci rcuit of the Interface Circuit Board will be described in detail in the following sections. 4.1.1 DC-DC Converter When the Motorola DSP board detects a large bubble, in the blood, three output pins on the General Purpose Inputs/Outputs are activated. The th ree pins produce 3.3V logic high outputs that trigge r the blood line clamp, the a udio alarms and the visual alarm. Both the blood line clamp and the audio buzzer required a 5V control signal. Therefore, a DC-DC converter was required to convert the 3.3V out put signals generated by the DSP board to 5V levels. A 74ACQ244 integrated circuit was used to accomplish the change in potential level. The 74ACQ244 is a Quiet Series Octal Buffer/Line Driver with 3-STATE outputs. The 74ACQ244 was designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver. During this research the IC was used to simply convert an output voltage of 3.3V to 5V. The 74ACQ244 integrated circuit has ei ght buffers, which are grouped in two sets. Each set has 3-STATE Output Enable Inputs called OE1 and OE2. When the enable input is set low, the outputs of the buffers follow the state of the corresponding input. That is, if the input of the bu ffer is low, the output is low as well and if the input is high, the output follows the input a nd becomes high. When the enab le input is set to high, the outputs of the buffers become high-impedan ce outputs regardless of the inputs. Figure 4.3 presents the connection diagram for the 74ACQ244 chip and Table 4.1 presents the truth table related to the functional capabilities of the 74ACQ244 chip.

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31 Figure 4.3: IC Connection Di agram for the 74ACQ244 Chip Table 4.1: Truth Tabl e for the 74ACQ244 Chip Since a DC-DC converter circuit was required, the enable input OE1 was tied to ground in order to force the outputs of the buffers to follow the state of their corresponding input. Also, the VCC pin was connected to the 5V line to guarantee the presence of a 5V potential at the buffer output stage when the inputs were high. In addition, two pull down resistors were added to the outputs of the buffers to prevent them from floating when the buffers’ inputs were low. When the input is low, the buffer output is pulled down to ground, which prevents the output from floating. However, if

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32 the input is high, the output is 5V and very little curre nt flows through the pull down resistor due to its high resi stance. Figure 4.4 presents the schematic for the DC-DC converter sub-circuit. PB10 from DSP board 5V_Logic_High_1 R10 .1Meg 5V_Logic_High_2 556 Timer Astable's Vcc Clamped Signal of Blood Line Clamp PB12 from DSP board U2 74ACQ244 10 1 20 2 4 6 8 19 17 15 13 11 18 16 14 12 3 5 7 9 GND OE1 VCC I0 I1 I2 I3 OE2 I4 I5 I6 I7 O0 O1 O2 O3 O4 O5 O6 O7 DC-DC Converter R3 .1Meg 5Vdc 0 Figure 4.4: Schematic Diagra m of the DC-DC Converter 4.1.2 The 556 Timer Circuit for Driving the Audio Buzzer Alarm A 556 timer operating in an astable mode was used to drive the Audio Buzzer Alarm. The function of the circuit was to turn the buzzer on for approximately half a second and to turn it off for approximately half a second. Therefore, a 556 timer was employed to provide a 5V square wave with a duty cycle of 50% and a period of 1 second. The schematic for the 556 astable timer sub-circuit is presented in Figure 4.5.

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33 C2 0.1u R12 35k R11 3.5k 0 Audio Alarm Buzzer 556 Timer Astable C3 20u U5A LM556 3 6 2 4 7 5 1 14CON TRG THRES RSTGNDOUT DISVCC 5V_Logic_High_1 R3 .1Meg Figure 4.5: Schematic Diagram of the 556 Astable Timer The 556 astable circuit uses a capacitor, C, which is connected between the Trigger pin and the Ground pin in order to fo rce the output to switch repeatedly between logic high and logic low levels. As soon as the 556 timer is powered by a 5V Vcc potential capacitor C starts charging. The Threshold and Trigger inputs monitor the capacitors’ voltage level. When th e capacitors’ voltage level reaches of Vcc, also known as the Threshold Voltage, the output b ecomes logic low and the Discharge pin is connected to ground. With the Discha rge pin connected to ground, capacitor C discharges and current flows through a resist or placed between the Discharge pin and the Threshold/Trigger pin. When th e voltage across C decreases to of Vcc, also known as Trigger voltage, the output becomes high ag ain and the discharge pin is disconnected, which allows the capacitor to start charging again. The waveforms for the 556 astable timer and capacitor output are illustrated in the Figure 4.6.

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34 Figure 4.6: The 556 Astable Time r and Capacitor Output Plots Figure 4.7 presents the pin layout an d block diagram of the 556 timer. Figure 4.7: Block Diagram of the 556 Timer The period and frequency of the square wave were calculated using the relationships given by: 11122T=0.7(R+2R)C (4.1) 111221.44 f= (R+R)C (4.2) The time period is the sum of the output high Mark Time, Tm, and the output low Space Time, Ts, which are defined as:

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35m11122T=0.7(R+R)C, (4.3) s122T=0.7RC. (4.4) In order to produce a timer wavefo rm with a duty cycle of 50% Tm was set to 1 second and Ts was set to 0.5 second. In addi tion, choosing a value of 20F for C2, in equations (4.3) and (4.4) yields simultaneous relations for R11 and R12 as: -6 1112 -6 121=0.7(R+2R)2010 .5=0.7R2010 (4.5) Solution of the simultaneous relations pres ented in equation (4.5) yielded the design values for the parameters pr esented in equation (4.6): 2 11 12C=20F R=3500 R=35000 (4.6) Additionally, a 0.1F capacitor, C3, was connected between the control pin and ground in order to reduce electrical noise.

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364.1.3 3.3V Voltage Regulator The air detector module’s output is a 5V DC signal that goes low when an air bubble is detected. Since the Motorola DSP board’s General Purpose Inputs/Outputs are electrically rated so that a Logic High Voltage, (VH), on both inputs and outputs is 3.3V. A DC voltage regulator was required in order to provide a 3.3V regulated voltage for the system. The 3.3V voltage was required as a re ference voltage for the diode clamp circuit, which will be described in the next section. The schematic for the 3.3V Voltage Regulator circuit is presented in Figure 4.8. Vout C1 1u R5 394 U1 LM317K 2 3 1INOUTADJ R6 240 Vin3.3 V Voltage Regulator Figure 4.8: Schematic Diagram of the LM317 Voltage Regulator An LM317 integrated circuit was used in the design of the voltage regulator. The LM317 is a regulator with no ground terminal. The LM317 adjusts the output voltage to maintain a constant 1.25V potential between the output terminal and the adjustment terminal. A small resistor, R6, was used between these two terminals so that the voltage remained constant at 1.25V. The current through R6 was chosen to be 5.2mA. Therefore, the value for R6 was required to be 240 The output voltage is given by: out56V=1.25(1+R/R), (4.7)

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37 where R5 is the resistor that controls the output voltage. The value for R5 was found to be equal to 394 for an output voltage of 3.3V. In addition, a loop compensation capacitor was used as for the regulator. The loop compensation capacitor was connected between the output voltage pin and the ground pin. 4.1.4 Diode Clamp Circuit The diode clamp circuit was designe d to prevent the voltage of the Air Detected signal, produced by the Air Detector Module, from exceeding 3.3V. Figure 4.9 presents the schematic diagram for th e Diode Clamp sub-circuit. D4 D1N914 02.6V R7 323 1k Diode Clamp Air Detected 3.3 V from Voltage Regulator 5V_Square_Wave R8 1200 Diode Clamp CKT Output R9 3.3V_Square_wave 3.3V Figure 4.9: Schematic Diagra m of the Diode Clamp Circuit A voltage divider with an input voltage of 3.3V was used to obtain a bias voltage of 2.6V across R8. The diode becomes forward biased as soon as the anode voltage exceeds the sum of the bias volta ge and the 0.7V diode voltage drop. When the diode is forward biased, the anode voltage cannot assu me a value larger than the bias voltage +0.7V. Therefore, any voltages that would ex ceed 3.3V are clamped at the 3.3V level. When the diodes’ anode voltage is lower than 3.3V the diode is reversed biased. A

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38 reverse biased diode appears as an open ci rcuit, which forces the anode voltage to maintain a constant voltage level. A 1 K resistor was added between the input signal and the anode of the diode to limit the sink current. Figure 4.10 illustrates how a 5V signal, generated by the Air Detect or Module, was clamped to 3.3V. Figure 4.10: Output of the Diode Clamp Circuit 4.1.5 LEDs For troubleshooting purposes a set of LEDs was used to monitor the presence of 3.3V, 5V and 24V potentials in the interf ace circuit. Each LED required a limiting resistor whose value was determined from the equation: supplyLED limiting desiredV-V R= I (4.8) where VLED is the voltage drop across the LED and Idesired is the desired current through the LED. VLED was 2.2V and Idesired was 15mA. The limiting resistances are listed in Table 4.2.

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39 Table 4.2: Limiting Resistances V supplied (V) Limiting Resistance ( ) 3.3 80 5 193 24 1460 The schematic diagram for the power LED’s is presented in Figure 4.11. R2 193 R1 1460 D2 +5V D3 +3.3V 3.3V Voltage Regulator Output D1 +24V Power LEDs V2 5Vdc V1 24Vdc 0 R4 80 Figure 4.11: Schematic Diagram of the Power LEDs 4.2 Motorola DSP 56824EVM Board The Motorola DSP56824EVM is a Digital Si gnal Processor board that provides a hardware tool for the development of app lications that use the DSP56824 chip. The configuration flexibility and processing power of this gene ral purpose DSP makes it ideal for signal processing and control functions. The CPU permits as many as six operations per instruction cycle via the pa rallel operations of three exec ution units. This capability translates into 35 million instructions per second, (MIPS), with a 70 MHz clock. The DSP56824 consists of the DSP56800 core, pr ogram and data memory and peripherals useful for embedded control applications. Fi gure 4.12 presents the architecture of the DSP core chip.

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40 Figure 4.12: DSP56824 Chip Architecture The main features of the DSP56824EVM board include: On-Chip memory 1. 32K, 16-bit program ROM 2. 128K, 16-bit program RAM 3. 3.5K, 16-bit RAM for data and applications 4. 2K, 16-bit Data RAM Off-Chip memory 1. As much as 64 K, 16-bit data memory 2. As much as 64 K, 16-bit program memory 3. External memory expansion; port programmable

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41 Peripheral Circuits 1. External Memory Interface 2. Sixteen dedicated GPIO pins, (eight pins programmable as interrupts) 3. Programmable Input/Output Port 4. Serial Peripheral Interface, (SPI) 5. Synchronous Serial Interface, (SSI) 6. Three programmable 16-bit timers 7. Two external interrupt/mode control push-buttons 8. One external reset pin for hardware reset 9. JTAG/On-Chip Emulation, (OnCE™) 10. Phase Lock Loop-based, (PLLbased), frequency and clock synthesizer for the DSP core clock 11. Debugging LEDs 4.2.1 Port B: General Purpose Input/Output, (GPIO), Port The DSP56824EVM offers several Genera l Purpose Input/Output, (GPIO), ports. Port B is a dedicated GPIO that provides 16 programmable I/O pins. Port B can be configured to generate an interrupt on its lo wer eight pins, (PB7 through PB0), if they are configured as inputs. The upper eight pi ns, (PB15 through PB8), do not offer such a feature. Port B is controlled by three read/w rite registers, which are located in the X memory of the processor. The three read/write register s are designated as:

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42 Port B Data Directi on Register, (PBDDR), Port B Data Re gister, (PBDR), Port B Interrupt Register, (PBINT). The Port B Data Direction Re gister allows each pin to be programmed as an input pin or an output pin. The direction of each pin is controlled by a corresponding control bit in the PBDDR. A pin is configured as an input pin if the corre sponding control bit is set to “0”. When a pin is used as an output pin the corresponding c ontrol bit must be set to “1”. The PBDDR register is cleared during processor rese t, which configures all pins as input pins. During this research, one input and four outputs were required from the Port B GPIO. The input received the Air Detected signal generated by th e air detector module and conditioned it through the di ode clamp circuit. The input pin associated with the Air Detected signal was pin 1 and the related co ntrol bit in the PBDDR register was PB0. The first output was connected to the visual alarm circuit, which turned on the green LED when air was not present in the blood. This output was associated with GPIO pin 9 and its control bit was PB8. The other three outputs were connect ed respectively to the audio alarm, (GPIO pin 10), the red LED of the vi sual alarm circuit, (GPIO pin 11), and the blood line clamp, (GPIO pin 12). The correspon ding control bits in the PBDDR register were PB9, PB10 and PB11. These outputs were active when air was detected. Figure 4.13 presents the DSP GPIO pin layout.

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43 Red LED Visual Alarm Audio Alarm J1 CON18A 1 3 5 7 9 11 13 15 17 2 4 6 8 10 12 14 16 18 Air Detected Signal DSP Board Green LED Visual Alarm GPIO Clamped Signal of Blood Line Clamp 0 Figure 4.13: Connection Diagram for the DSP GPIO Board Pin 17 and Pin 18 of the GPIO are re ference ground signals and are not programmable. Pins 2 through 8 and 13 thr ough 16 were not used. For convenience, unused pins were cleared, even though they could be set with no effects on system performance. Table 4.3 catalogs each pin, the as sociated control bit in the register and its assigned value. Table 4.3: Port B: GPIO and PBDDR Register Formats GPIO PIN 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PBDDR Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 The second register used for controlling the Port B GPIO was the PBDR. This register determined the logic level of the pins in use. When a value of “0” was assigned to a PBDR control bit the corr esponding pins output logic leve l was set to “0”. However, if a PBDR control bit was set to “1” the associ ated pin generated a logic level of “1”. A potential of 3.3V defined a logi c level of “1”. This behavior was only true for pins that were configured as outputs. If a pin was c onfigured as an input pin the corresponding bit value reflected the potential valu e applied to the pin when the register was read. It was

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44 possible to overwrite the PBDR control bit of an input pin. However, the value was only transferred to the PBDR regist er and not to the input pin. During this research, the PBDR register wa s used to control the outputs associated with the green LED visual alarm, the red LED visual alarm, the audio alarm and the blood line clamp. When air was not present in the blood, the only active output was the green LED of the visual alarm. Therefor e, only output pin 9 was set to “1” and the PBDR register was assigned bit vector “ 100000000”. This condition is presented in the register formats presented in Table 4.4. Table 4.4: PBDR Register When No Air was Detected in the Blood GPIO PIN 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PBDR Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 When air was detected in the blood the three remaining output pins became active, pin 9 was deactivated and the PBDR register received bit vector “111000000000”. Table 4.5 the register format for the PBDR register when air was detected. Table 4.5: PBDR Register When Air was Detected in the Blood GPIO PIN 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PBDR Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 The third register associated with Port B is the Interrupt Register. PBINT is a 16 bit control register used to set the capabil ity of the lower 8 GPIO pins, (PB7 though PB0), in order to trigger an interrupt. An in terrupt is a technique used in real-time

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45 programming, which consists of interrupting the normal activity of the processor when a certain event occurs. An interrupt signal for ces the processor to execute a specific set of instructions and return, when complete, to the state where it left. The PBINT register configures the lower GPIO inputs in such a way that a rising or fa lling transition on the pins can trigger an interrupt routine. PBINT control bits are divided into Interrupt Mask bits (PBINT bit 15 th rough bit 8), and Interrupt Invert bits, (PBINT bit 7 through bit 0). Each interrupt mask bit is a ssociated with a lower GPIO input pin and can enable or disable the pin to generate an interrupt. A va lue of “0” assigned to an interrupt mask bit disables the corresponding pin fo r interrupt generation. A valu e of “1” enables the pin to generate an interrupt. The interrupt invert bits are used to individually program whether a rising or falling transition is to be detected on each pin. A value of “0” assigned to an interrupt invert bit allows the associated GPIO input pin to generate an interrupt when a rising edge transition, (from l ogic level 0 to logic level 1), is detected on that pin. Similarly, a value of “1” permits the genera tion of an interrupt when the corresponding GPIO input during a falling edge transition, (from logic level 1 to logic level 0). This process is crucial for the air detection algor ithm and it will be described in detail in Chapter 5. During this research, PB0 was pr ogrammed to generate an interrupt for both rising and falling edge transitions of the Air Detected input signal. Tables 4.6 and 4.7 present the values assigned to the PBINT in both cases. Table 4.6: PBINT Register for Detec tion of the Rising Edge Transition on PB0 GPIO INPUT PIN 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Interrupt Mask Bits Interrupt Invert Bits PBINT Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

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46 Table 4.7: PBINT Register for Detecti on of the Falling Edge Transition on PB0 GPIO INPUT PIN 8 7 6 5 4 3 2 1 8 7 6 5 4 3 2 1 Interrupt Mask Bits Interrupt Invert Bits PBINT Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 Tables 4.6 and 4.7 indicate that, in orde r to generate an interrupt on the rising edge transition of the PB0 input signal, the PBINT has to receive the bit vector “100000000”. Similarly, assignment of the bit vector “100000001” to the PBINT allows the GPIO input pin PB0 to trigge r an interrupt on th e falling edge transition of its input signal. 4.2.2 Clock Synthesis Two main clocks are used by the DSP 56824EVM board to drive the DSP core and the peripheral circuits. The main clocks are the Oscillator Clock and the Phi Clock. The oscillator clock derives its clock signal from an exte rnal crystal and runs at 3.6864MHz. The phi clock generates its clock si gnal from the oscillator clock. The phi clock can actually produce a hi gher frequency than the Osci llator Clock due to an on board Phase Locked Loop, (PLL). The maximum frequency supported by the DSP56824 board is 70MHz, which is obtained by forcing the PLL to generate a clock signal with a frequency 19 times higher than the oscill ator clock’s freque ncy, (19*3.6864MHz=70 MHz). Generally, a higher clock signal transl ates into higher time resolution, which is a very important feature when dealing with algorithms invol ving timing such as the one

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47 developed during this research. Figure 4.14 presents the block diagram of the On Chip Clock Synthesis Module. Figure 4.14: Block Diagram of th e On-Chip Clock Synthesis Module The Clock synthesis is controlled by PLL control registers PCR0 and PCR1. The first register is a 16 bit-wide register that hol ds the binary value of the PLL multiplier + 1. Only 10 bits, PCR0 bit 14 through bit 5, of the register are programmable. The remaining bits are reserved bits for future compatibility and are automatically written with 0s. Since the 70MHz clock signal was re quired the PLL multiplier was chosen to be 19. Therefore, PCR0 received the binary value of 20, (101002), in bits 14 through 5. Table 4.8 presents the PCRO format for this situation. Table 4.8: PCR0 Register for the 70MHz Clock Signal PCR0 Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 *Reserved Bits for future compatibility. Theoretically, the PCR0 register b its 14 through 5 can be set to “1111111111”, which yields a PLL multiplier factor of 1023. However, this is not recommended since the DSP processor cannot physically run fast er than 70MHz. A PLL multiplier of 1023

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48 would force the DSP board to attempt to run at 3.771GHz, (1023*3.6864 MHz=3771MHz). The second register, PCR1, enables or disa bles the PLL. To enable the PLL bit 14, (PLL Enable), and bit 13, (PLL Power Down), of the PRC1 register must be set to “1” and “0” respectively. Bits 10 through 8, (PS bits), contro l the prescaler clock, which is another clock signal that can be generated from the DSP board. For convenience, these three bits were set to “010” even though the prescaler clock was not used. Bit 3, (VCS), allows the Voltage Controlled Oscillator, (VCO), to be optimized for 40 to 70MHz operation when the bit is set to “0”. If bit 3 is set to “1” the VCO is optimized for 10 to 40MHz operation. Since the operating fre quency was 70MHz, bit 3 was cleared. The remaining bits were not critical or reserved and were set as depicted in the format presented in Table 4.9. Table 4.9: PCR1 Register for the 70 MHz Clock Signal PCR1 Control Bit 15 14 PL LE 13 PL LD 12 11 10 PS 9 PS 8 PS 7 6 5 4 3 VC S 2 1 0 Value 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 *Reserved Bits for future compatibility. During this research the DSP Board was programmed to synthesize a 70MHz clock signal that provided a time base for the DSP board timers. In reality, the timers received a clock signal whose frequency was of the phi clock. The following section explains in detail the functionality of the ti mers used during this research. The topic of timing will be discussed in Chapter 5.

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494.2.3 Timers In order to measure the pulse width of the Air Detected signal it was necessary to keep track of time using the DSP board timer module. The DSP56824 provides three independently programmable 16-bit timer/eve nt counters, which are termed Timer0, Timer1 and Timer2. All three timers can be clocked with the Phi-Clock/4, a Prescaler Clock or external signals from Timer I/O pi ns, (TIO01 and TIO2). Timer1 and Timer2 can also be clocked respectiv ely by overflow events of Timer0 and Timer1. However, the overflow of Timer2 cannot be cascaded to another register. However, Timer2 can trigger an interrupt. The input stage of each timer has an exclusive-OR gate followed by a 4-to-1 multiplexer that permits the selec tion of the clock signal. The timer module contains eight read/write registers, which are located in the X memory. Each register has two sets of 16-bit registers. One set of bits is for the prel oad register, (TPR[x]), and the other set is for the count regi ster, (TCT[x]). Timer0 and Ti mer1 share one 16-bit register, TCR01, with 8 bits assigned to each timer. Time r2 uses only 8 bits of the 16 bit register TCR2. Figure 4.15 presents the block diagram of the Timer Module.

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50 Figure 4.15: Block Diagram of the Timer Module Every time the output signal from a multiplexer transitions from low to high, the corresponding count register decrements the va lue loaded by the preload register. When the count registers reach zero an overflow signal is genera ted, which can trigger an interrupt or enable another timer. Afterwards the count register reloads the value stored by the preload register and resumes its c ountdown. The reload and countdown sequence events are repeated until either the preload valu e is clear or the timer is disabled through bit 15 and bit 7 in TCR01 and bit 7 in the TCR2, which are called Timer Enable bits, (TE). TE bits must be set to “1” to enab le the corresponding timer Bits 9 and 8 of TCR01 determine the MUX input, which is to be applied to Timer1. Similarly, bits 1 and 0 for both TCR01 and TCR2 control the clock signal for Timer0 and Timer2. These two

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51 bits are called Event Select bits, (ES). Tabl e 4.10 catalogs the clock source/Event Select bits association. Table 4.10: Clock Source/Eve nt Select Bits Association Event Select Bits Clock Source 00 Internal Phi Clock/4 01 Internal Prescaler Clock 10 Previous Timer Overflow from Timer1 or 2 11 External Event from TIO pin The remaining bits were not of concern since they were not used during this research. Table 4.11 and Table 4.12 presen t the TCR01 and TCR2 register formats and their control bits. Table 4.11: TCR01 Register Format Timer1 Timer0 TCR01 Control Bit 15 TE 14 13 12 11 10 9 ES 8 ES 7 TE 6 5 4 3 2 1 ES 0 ES *Reserved Bits for future compatibility. Table 4.12: TCR2 Register Format Reserved Timer2 TCR2Control Bit * * * * 7 TE 6 5 4 3 2 1 ES 0 ES *Reserved Bits for future compatibility. This arrangement enables the programming of each register to cycle through a fixed interval, which is determined by the size of the preload value. The frequency of the clock signal determines the c ount register decrement rate. The timers can run independently or they can be cascaded to increase time resolution that can range from nanoseconds to seconds. During this research Timer1 and Timer0 were used in a cascaded configura tion. Timer2 was not utilized during this

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52 research. Since Timer0 was clocked by the Phi Clock/4, the count register started decrementing when bit 7 of TCR01 was set to “1”. Every time the count register reached 0 an overflow signal was genera ted and the count register, TCT0, was reloaded with the value set in the preload register, TPR0. Sin ce Timer1’s Event Select bits were set to “10”, Timer1’s count register started decr ementing every time there was a low to high transition from Timer0’s overflow signal and bi t 15 on TCR01 was set to “1”. Therefore, the “Timer1&Timer0 Timing module” c ould be activated if bit vector “1000001010000000” was assigned to TCR01. Table 4.13 illustrates how to activate the Timer1&Timer0 Timing module. Table 4.13: TCR01 Register for Activati on of the Timer1 & Timer0 Timing Modules TCR01 Control Bit 15 TE 14 13 12 11 10 9 ES 8 ES 7 TE 6 5 4 3 2 1 ES 0 ES Value 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 *Reserved Bits for future compatibility. The deactivation of the Timing module was accomplished by simply assigning bit vector “0000000000000000” to the TCR01 regi ster, which stopped the decrementing process in both TCT1 and TCT0. 4.2.4 Generation of Interrupts To Motorola DSP5824 uses a programming technique called Interrupt Generation in order to handle events async hronously. This method allows an event to interrupt the normal operation of the DSP processor and to force it to execute a different set of instructions called an Interrupt Service R outine, (ISR). Once the task, called by the interrupt, has been completed the processor resumes operation at the point where it was

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53 interrupted. Interrupts can be either intern ally generated, such as the overflow signal from a timer, or externally triggered. The IRQA and IRQB push-buttons are examples of ways to produce externally ge nerated interrupts. Figure 4. 16 presents a diagram of the activity that ensues when an interrupt occurs. Figure 4.16: Interrupt Service Routine Diagram The processor initially executes the main pr ogram. At any time in the program an interrupt can be triggered by in ternal or external events. When the processor recognizes an interrupt, it completes the current instruc tion in the main program while it performs a check of the priority of the interrupt. The priority level of an interrupt allows the DSP processor to arbitrate pending in terrupt requests and select the one to handle first in case two or more interrupts are ge nerated at the same time. The processor recognizes two interrupt priority levels, whic h are designated as level 1, (IPL1), and level 0, (IPL0). Level 1 interrupts have the hi ghest priority and are always executed before any level 0

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54 interrupts. Both IPL1 and IPL0 are enabled or disabled via a register called the Interrupt Priority Register, (IPR). The Interrupt Prior ity Structure is presented in Tables 4.14 and 4.15. Table 4.14: Interrupt Prio rity Structure; Level 1 Priority Level 1, (Non-maskable) Interrupt Source Priority Hardware Reset Highest COP watchdog Timer Reset Illegal Installation Trap Hardware Stack Overflow OnCE Module Instruction Trap Software Interrupt (SWI) Lowest Table 4.15: Interrupt Prio rity Structure; Level 0 Priority Level 0, (Maskable) Interrupt Source Priority IRQA Push-Button Highest IRQB Push-Button Synchronous Serial Interface Reserved Timer Module Serial Peripheral Interface 1 Serial Peripheral Interface 0 Real Time Timer Port B GPIO Lowest When an interrupt is to be processed the processor freezes the Program Counter, (PC), which determines the address of the next instruction to be ex ecuted. The PC and Status register, (SR), which de scribe the status of the proc essor, are pushed onto the stack in order to provide a return address and the processor condition at the moment of interruption. When the proce ssor finishes executing the ISR the return address will be

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55 used to return to the point in the main program where it left off. In order to process the interrupt the processor maps the appropriate interrupt vector, which is located in the lower area of the program memory, P, of the DSP56824. The interrupt vector points to a set of memory locations. Each pair of th e set of memory locations corresponds to a particular interrupt. The first word of th e interrupt vector corresponds to a Jump to Subroutine, (JSR), instructi on. The second word contains the memory address of the interrupt handler. The PC only fetches th e handler’s address while the interrupt controller supplies the JSR instruction. Table 4.16 presents the association of the main interrupts and their corres ponding interrupt vectors. Table 4.16: Main Interrupt Sour ces and their Interrupt Vectors Interrupt Source Interrupt Starting Address Hardware RESET $0000 IRQA $0010 IRQB $0012 Port B GPIO interrupt $0014 Real-time interrupt $0016 Timer0 overflow $0018 Timer1overflow $001A Timer2 overflow $001C After resolving the interrupt priority arbitration, the pr ocessor places the JSR into the instruction stream so that it is fetched next and releases the PC. Arbitration among any other pending interrupts is pe rmitted at this stage. This continuing arbitration allows an executing interrupt routine to be interrupted by a higher priority interrupt. When the

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56 processor completes all the ISR instructions it uses the PC and SR to return to the main program. The Interrupt Priority Register, (IPR), is responsible for the determination of which DSP peripherals can genera te interrupts. The SR regist er enables these interrupts. The IPR is a 16-bit register whose format is presented in Table 4.17. Table 4.17: Bit Configura tion of the ISR Register Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit name P B GPIO Real Time Timer SPI0 SPI1 Timer Module Reserved SSI * IBL1 IBL0 IB INV IAL1 IAL0 IA INV *Reserved Bits for future compatibility. Two interrupt sources were used during this research. The first was Port B GPIO and the second was the IRQB push-button. Th e GPIO was used to trigger interrupts on every low to high or high to low transition of the Air Detected signal from the air detector module. The IRQB push-button was used to reset Timer1 and Timer0 registers and to clear all the outputs generated by the GPIO after an air detection occurred. This reset process stopped the audio alarm, unclamped the blood line clamp and allowed the visual alarm to turn green. Therefore, only bit 15 and bits 5 through bit 3 of the ISR register were of concern. If bit 15 was asserted, th e Port B GPIO lower inputs were allowed to generated interrupts. Bits 5 through bit 3 we re reserved for the IR QB push-button. In order to trigger an interrupt when the IRQB button was pushed required bit 5 through bit 3 to receive bit vector “110”. The IBL0 bit enabled the IRQB push-button while IBL1 and the IB-INV bits made the interrupt falli ng edge sensitive. Tables 4.18 and 4.19

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57 present respectively the IPR register format required to enable Port B GPIO interrupt generation and IRQB push-bu tton interrupt generation. Table 4.18: IPR Register for Po rt B GPIO Interrupt Generation IPR Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 *Reserved Bits for future compatibility. Table 4.19: IPR Register for IRQB Push-Button Interrupt Generation IPR Control Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Value 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 *Reserved Bits for future compatibility. The status register enabled both non-ma skable, (IPL1), and maskable, (IPL0), interrupts. Bit 9 and bit 8, which are termed Interrupt Mask bits, enabled or disabled respectively IPL1 and IPL0 interrupts. Si nce both Port B GPIO and IRQB were IPL0 interrupts, the only bit to be a sserted was bit 8. Table 4.20 presents the format for the SR register and its control bits. Table 4.20: SR Register to Enable IPLO Interrupts Mode Register Condition Code Register SR Control Bit 15 # 14 13 12 11 10 9 8 7 # 6 # 5 # 4 # 3 # 2 # 1 # 0 # Value X 0 0 0 0 0 0 1 X X X X X X X X *Reserved Bits for future compatibility. #Bits of not concern for the purpose of Interrupt Generation.

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58 CHAPTER 5 SOFTWARE OVERVIEW 5.1 Metrowerks CodeWarrior Development Environments The Metrowerks CodeWarrior IDE is software used to program the DSP56824EVM board. This software is us ed in combination with the Motorola Embedded Software Development Kit, (SDK), to develop, test and debug DSP applications. The SDK library provides a multitude of useful DSP functions to simplify the development process. The CodeWarri or software and the DSP56824 hardware communicate via a parallel cable that connect s the evaluation board to the host PC. The program is written in a mixed language that comprises C and Assembly language. The CodeWarrior IDE has an extensible architecture that uses plug-in compilers and linkers to specifically target the DSP56824 board. Afte r the code is compiled the linker links together all the files required by a project. The Linking process insures that each sub program communicates properly with the other el ements in the project. After successful compilation and linkage of the code the progr am can be downloaded to the DSP program memory via the parallel port for code debugging CodeWarrior offers many features that facilitate debugging. One of the mo st important features is the breakpoint which allows the programmer to halt code execution and manua lly step in or out of the code. This

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59 capability results in an easier and more effective debugging process. Figure 5.1 presents a picture of the CodeWarrior IDE Debugging Window. Figure 5.1: CodeWarrior IDE Debugging Window 5.2 Air Detection Algorithm The objective of the Air Detection algorith m, developed during this research, was to measure the pulsewidth of the Air Detected signal, which was generated by the Air Detector Module. The value of the pulsew idth was used to cont rol activation of the blood line clamp and trigger the alarms. Sec tion 5.3 presents a general overview of the algorithm and the processes perf ormed by the DSP processor. Initially the program sets Port B GPIO to support interrupt generation on input pin 1 and activates the green LED of the visual alarm. Ne xt, a 70 MHz clock signal is synthesized and applied to D SP’s internal timers. After the timers are activated all preload and count registers of Timer1 and Timer0 are initialized and enabled for falling edge transition interrupts on Port B GPIO input pin1. When these in itialization activities

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60 are completed, the program places the processor in a while loop to wait until an external interrupt occurs. Figure 5.2 flowchar ts the main program processes. Figure 5.2: Main Program Flow Chart

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61 When a falling edge transition causes an interrupt to be generated the program jumps to the Interrupt Service Routine, (ISR), associated with the GPIO. The ISR causes the processor to check whether the global variable FLAG is cleared or asserted. Since FLAG is initially loaded with “0”, the progr am starts the Timer Module. The PBINT register is modified to allo w the detection of a rising edge transition on GPIO pin1 while the status of FLAG is changed from “0” to “1”. The program exits the ISR and waits. In the meanwhile, the timer module keeps counting until a rising edge transition interrupt on pin 1 occurs. When the interrupt is generate d the program jumps again to the ISR. This time, the timer module is stopped since variable FLAG is asserted. The program uses the values stored in Timer1 and Timer0’s count registers and the clock frequency to calculate the time resolution and the time duration of each timer. This information is utilized to calculate the Total Elapsed Time which is equivalent to the pulsewidth of the Air Detected signal. All preload and count re gisters are reset, PBINT is modified to recognize falling edge transition inte rrupts on GPIO pin 1 and variable FLAG is cleared. The processor compares the Total Elapsed Time with a fixed value of 0.003 seconds, which represents the pulse width threshold. If the Total Elapsed Time is greater than the fixed value, the DSP processor activates thr ee logic-high outputs of the GPIO. The three logic-high outputs trigger the red LED of the visual alarm, the audio alarm and the blood line clamp. Simultaneously, GPIO interrupt ge neration is deactivated, which leaves only the IRQB push button interrupt enabled. If Total Elapsed Time is less than the fixed value the program exits the ISR and waits fo r a new falling edge transition interrupt. Figure 5.3 flowcharts the Port B In terrupt Service Routine operations.

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62 Figure 5.3: Port B Interrupt Service Routine Flow Chart The IRQB interrupt was used to release the Air Detector system from the alarm status. When the IRQB push button is presse d the three GPIO output s, which are applied to the visual alarm, audio alarm and the blood line clamp are deactivated. The green LED of the visual alarm is activated. All pr eload and count registers are reset, PBINT is modified to recognize falling edge transiti on interrupts on GPIO pin 1 and variable FLAG

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63 is cleared. The processor exits the Interrupt Service Routine and waits for a new falling edge transition interrupt to be generated. Figure 5.4 flow charts the IRQB Push-button Interrupt Service Routine operations. Figure 5.4: IRQB Push-button Inte rrupt Service Routine Flow Chart

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64 5.2.1 Registers Settings The DSP56824 has 128 words of on-chip program ram that are reserved for on chip peripheral registers. The hexadecimal a ddresses for this ram span $FFC0 to $FFFF. Table 5.1 catalogs the regist ers used during this res earch and the corresponding hexadecimal memory addresses. Table 5.1: On-Chip Peripheral Regi sters and their Memory Addresses Register Memory Address: Interrupt priority register, (IPR) $FFFB Bus control register, (BCR) $FFF9 PLL control register 1, (PCR1) $FFF3 PLL control register 0, (PCR0) $FFF2 Port B data register, (PBDR) $FFEC Port B data direction register, (PBDDR) $FFEB Port B Interrupt register, (PBINT) $FFEA Timer control reg. 1 & register 0, (TCR01) $FFDF Preload register for timer 1 $FFDC Preload register for timer 0 $FFDE Count register for timer 1 $FFDB Count register for timer 0 $FFDD The program used a # include instruction to call a subroutine that defined each register and its corresponding me mory address. This allowe d the processor to match the register name, which can be defined by the pr ogrammer, to the physical register location and to create predefined pointers to the regist ers for read/write purposes. To set a value in a register, the pointer to th at particular register must be called and set equal to the desired value. Since all the registers were 16-bit wide, hexadecimal notation was used. For example, if pin 1 of the GPIO was to be set for output, the Po rt B Data Direction Register must be written with bit ve ctor “0000000000000001”, which is equivalent to

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65 $0001. Since the #include subroutine defines the Port B Data Direction Register to be at location $FFEB as “PBDDR”, a pointer to the re gister called “*PBDDR” was created. In order to write $0001 into the Port B Data Direction Register the instruction *PBDDR=0X0001 was used. As mentioned in Chapter 4, several register s had to be configured initially. The main program performed the initialization f unction. A simplified version of the main program is presented as Code 5.1. Code 5.1: Simplified Version of the Main Program int main(void) { int i; *PBDDR = 0x0F00; *PBDR = 0x0400; *PBINT = 0x0101; *IPR = 0x8000; *PCR0 = 0x280; *PCR1 = 0x4208; //Enable all levels of interrupts asm(bfset #$0100,sr); asm(bfclr #$0200,sr); *TCR01 = 0; *TPR0 = 0xFFFF; *TPR1 = 0xFFFF; *TCTR0 = 0xFFFF; *TCTR1 = 0xFFFF; while(i) { asm(nop); asm(nop); } return 0; } //end main()

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66 The PBDDR register is set to 0x0F00 to enable four outputs on the Port B GPIO. The PBDR register is loaded with $0400 in or der to activate the green LED of the visual alarm while the PBINT and IPR registers are c onfigured so that GPIO pin 1 can trigger on a falling edge transition interrupt. PCR0 and PCR1 are set in such a way that a 70 MHz clock signal for the timers’ registers is synthesized. The preload and count registers for both Timer1 and Timer0 are loaded with an initial value of $FFFF. The Timing module is initially turned off via TCR01. Using Assembly Language bit manipulation, the Status Register is acce ssed and modified to enable all level interrupts. After execution of these preliminary register setup procedures, the proce ssor enters a “while loop” and waits for an interrupt event to o ccur. The complete version of the main program is presented in Appendix A. 5.2.2 GPIO Interrupt Service Routine In order to initialize the GP IO Interrupt Service Routine, the program is required to write the ISR interrupt vector into the inte rrupt vector table. To accomplish this step an assembly language routine labeled pmemwrite() was written. The prototype for pmemwrite() is: void pmemwrite( WORD value_V, WORD address_ADD ) The pmemwrite() function writes the 16 bit “ value_V ” at memory location “ address_ADD ” This function is called four times. The first two times the function is called to write the JSR instruction, (0xE9C 8), at 0x0012 and the name of the ISR at 0x0013 for the IRQB Interrupt. Th e last two times the function is called to write the JSR instruction, (0xE9C8), at 0x0014 and the name of the ISR at 0x0015 for the Port B GPIO

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67 interrupt. The need of this function was dict ated by the fact that Program memory could not be accessed via pointers. The code pres ented as Code 5.2 the operation of the Setup ISR using the pmenwrite() function. Code 5.2: Setup Interrupt Service Routine //setup Interrupt Service Routines (ISRs) pmemwrite((WORD)0xE9C8,(WORD)0x0012 ); //IRQB Interrupt pmemwrite((WORD)Irqb_ISR,(WORD)0x0013); pmemwrite((WORD)0xE9C8,( WORD)0x0014); //Port B GPIO Interrupt pmemwrite((WORD)ISR,(WORD)0x0015)

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68 5.2.3 Air Detector Input Signal Detection The Air Detector Input signal Detect ion method was developed in accordance with the state diagram presented in Figure 5.5. 1 Processor waits for GPIO Interrupt Event 2 Processor waits for GPIO Falling Edge Transition Detection 3 Processor waits for GPIO Rising Edge Transition Detection 4 Total Time Elapsed > 0.003 ? Falling Trans. =TRUE Z1 Falling Trans. =FALSE No Output Rising Trans=FALSE No Output 5 Processor waits for IRQB Interrupt Event IRQB =FALSE No Output IRQB =TRUE Z4 Interrupt Event =TRUE and FLAG=1 No Output Rising Trans=TRUE Z2 TRUE Z3 Interrupt Event =TRUE and FLAG=0 No Output Interrupt Event=FALSE and FLAG=X No Output FALSE Z5 Figure 5.5: State Diagram for the Air Detector Input Signal Detection Method The state diagram of Figure 5.5 shows that th ere are five distinct states, which the processor might enter. In state 1, the pro cessor enters an infinite loop and does not

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69 perform any operation. While in state 1 the processor waits for an interrupt event to occur. This state is governed by the detection of an interrupt event from the Port B GPIO input and the status of variable FLAG Since there are two i nputs four possible events can occur. Table 5.2 details the inpu t combinations and the corresponding Next States Table 5.2: State 1 I nputs and Next States Interrupt Event Detection Flag Status Next State FALSE 0 State 1 FALSE 1 State 1 TRUE 0 State 2 TRUE 1 State 3 Regardless the status of FLAG if an interrupt event on the GPIO is not detected the processor stays in the same state and waits for an external event. If an interrupt is generated and FLAG is set to“0” the processor goes to State 2. However, the next state will be State 3 if FLAG is set to “1”. All four input co mbinations simply affect the next state and no outputs are produced. In State 2 the processor expects a Falling Edge Transition on GPIO pin 1. If this condition is true the next stat e will be State 3 and output Z1 is generated. Z1 is a set of instructions for the purpose of: Resetting preload and count timers, Starting the timer module, Turning off the green LED of the visual alarm, Modifying PBINT register to allo w rising edge transition interrupt generation on GPIO pin 1, Asserting variable FLAG

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70 The code presented as Code 5.3 reflects the output of State 2. Code 5.3: Output of State 2 case 0: for(j = 0; j < 150;j++) //Short Delay in nanoseconds range {asm(nop);} *TPR0 = 0xFFFF; //Timer0 Preload Register Reset *TPR1 = 0xFFFF; //Timer1 Preload Register Reset *TCTR0 = 0xFFFF; //Timer0 Count Register Reset *TCTR1 = 0xFFFF; //Timer1 Count Register Reset *TCR01 = 0x8280; //Start Timer Module *PBINT = 0x0100; //Rising Edge Transition Enable *PBDR = 0; //Green LED Disable FLAG = 1; break; If a falling edge transition interrupt is not generated the processor returns to State 1 and no output is generated. In State 3 the DSP processor expects th e reception of a ri sing edge transition interrupt. If a rising edge tr ansition interrupt is generated State 4 becomes the next state and Z2 is produced. The following operati ons are executed in response to Z2: Timer Module is stopped, Total Time Elapsed is calculated and printed on the console, Preload and Count registers are reset, Falling Edge Transition interrupt ge neration is enabled via PBINT. The code presented as Code 5.4 reflects the output of State 3.

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71 Code 5.4: Output of State 3 case 1: *TCR01 = 0x0000; //Stop Timing Module low_count = (WORD)*TCTR0; //Calculate Total Time Elapsed high_count = (WORD)*TCTR1; clock = (3.6864 19) / 4; timer0_resolution = 1/clock 0.000001; timer0_duration = 0xFFFF timer0_resolution; time_elapsed = (float)(65535high_count) timer0_duration + (float)(65535 low_count)* timer0_resolution; printf("Time = %e%s\n", time_elapsed, "sec"); *TPR0 = 0xFFFF; //Timer0 Preload Register Reset *TPR1 = 0xFFFF; //Timer1 Preload Register Reset *TCTR0 = 0xFFFF; //Timer0 Count Register Reset *TCTR1 = 0xFFFF; //Timer1 Count Register Reset *PBINT = 0x0101; //Falling Edge Transition Enable *PBDR = 0; //Disable any signals on GPIO As described in Chapter 4, the Phi Clock/4 is synthesized in order to provide the timer module with a time base. Since the Ph i Clock runs at 70 MHz, the Phi Clock/4’s frequency is 17.5 MHz. Since Timer0 is cl ocked by the Phi Clock/4 signal, the timer decrements every 57.143 ns, (T = 1/f = 1/17.5 MHz). This value is stored in Timer0_resolution If the Timer0 Count Timer is loaded with $FFFF, it requires 65535 clock transitions before reset ting and generating an overflow si gnal. In terms of time, the time elapsed for a complete Timer0’s cycle is 3.7448 ms, (65535*57.143 ns), which corresponds to Timer0_duration Therefore, Timer1 decrements by one every 3.7448 ms since Timer0 is cascaded to Timer 1. Multiplying TCTR0’s counts, ( low_count ), by Timer0_Resolution and TCTR1’s value, ( high_count ), by Timer0_Duration yields Time_Elapsed which is given by: Time_Elapsed=(65535high_count)* timer0_duration + (65535low_count)* timer0_resolution. (5.1)

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72 If a falling edge transition occurs when the current state is State 3 the processor returns to State 1. However, due to the natu re of the Air Detect Signal, it is not possible to obtain two consecutive falling edge transition interrupts. If such a situation occurs the processor can be taken to an Error State or simply forced to return to State 1, which restarts the entire sequence. State 4 performs a comparison between the Total Time Elapsed variable and a fixed value equal to 0.003. If Total Time Elapsed is greater than the fixed value, the processor enters St ate 5 and outputs Z3, which performs the actions: Activate Blood Line Clamp, Activate Audio and RED LED Visual alarms, Modify IPR register to disable Po rt B GPIO interrupt and enable IRQB interrupt, Set variable FLAG to “0”. If Total Time Elapsed is less than 0.003 the processor returns to State 1 and only the green LED of the visual alarm is activated. The code presented as Code 5.5 describes the behavior of the processor in State 4. Code 5.5: Behavior of State 4 if (time_elapsed > 0.003s) { printf("Alarm\n"); *PBDR = 0x0B00; //Activate alarms outputs *IPR=0x0012; // Disable GPIO interrupt and enable IRQB } //Interrupt else { *PBDR = 0x0400; //Activate Green LED } FLAG=0; break;

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73 In State5, the DSP processor stops and wa its for the operator to stop the alarms by pressing the IRQB pushbutton. Activation of the IRQB pushb utton initiates execution of the operations: Preload and Count Timers are reset, The IPR register is modified to enable Port B GPIO interrupts and disable the IRQB interrupt, Falling Edge Transition interrupt ge neration is enabled via PBINT, The Blood Line Clamp is deactivated, The Audio and red LED Visual Alarm are deactivated, The green LED of the Visual Alarm is activated. If IRQB is not pressed no fu rther operations are executed. The code presented as Code 5.6 describe s the operations executed in State 5. Code 5.6: Behavior of State 5 for(I = 0; I < 0x40000; i++) //Add delay to debounce the switch { asm(nop); } *TPR0 = 0xFFFF; //Timer0 Preload Register Reset *TPR1 = 0xFFFF; //Timer1 Preload Register Reset *TCTR0 = 0xFFFF; //Timer0 Count Register Reset *TCTR1 = 0xFFFF; //Timer1 Count Register Reset *PBINT = 0x0101; //Falling Edge Transition Enable *IPR = 0x8000; //Enable GPIO interrupt and disable IRQB *PBDR = 0x0400; //Activate Green LED Notice that a short delay is added to de bounce the IRQB switch. This concludes the discussion of the Software. The complete program code is presented in Appendix A.

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74 CHAPTER 6 EXPERIMENTAL RESULTS A system validation test and a system pe rformance test were conducted to verify the functionality of the system developed duri ng this research. Bovine blood was used as a replacement for human blood, during testing. The choice of bovine blood was dictated by the fact that the viscosity and density of bovine blood are similar to those in human blood. Additionally, bovine blood and human blood have comparable hematocrit levels, which are defined as the measure of the proportion of blood volume occupied by red blood cells. Bovine blood was slowly raised to body temperature, (37 1)C, using a warm water bath that was heated by a comm on laboratory heater. A peristaltic pump was employed to produce a blood flow of 300mL/m in. Figure 6.1 provides a picture of the bovine blood test setup.

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Figure 6.1: Bovine Blood Used During Testing 6.1 System Validation Test The purpose of the system validation test was to ensure that the DSP based Air Detector System consistently, reliably and accurately detected air bubbles in the blood. The system was tested using 40, 60, 80 and 100L air bubbles. For each air bubble size, three air bubbles were injected. The objective of the test was to compare the percent error between the pulsewidth of the analog signal generated by the Air Detector Module and the pulsewidth calculated by the DSP board. The success criteria for this test stated that the percent error, for each air detection, had to be less than 1%. An unsuccessful comparison for any of the 12 test runs would automatically deem the entire system validation test to be a failure. For these tests an oscilloscope, set in Trigger Mode, was connected to measure the Air Detector Modules output signal. The DSP algorithm was programmed to output, on the console, the value of the time_elapsed variable. Therefore, each air bubble injection event yielded two comparable values. The values compared were the oscilloscope measurement and the system pulsewidth. 75

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76 The system validation test, using bovine blood, was performed without anomalies. Data were recorded and percen t errors were calculated. Ta ble 6.1 presents the data and results of the system validation test. The percen t errors for each of the 12 test trials were within 1%. Therefore, the DSP based Ai r Detector System successfully passed the validation test. Table 6.1: System Validation Test Results Oscilloscope Pulse (ms) System Pulse (ms) Percent error % Pass/Fail 40 L air bubble RUN 1 2.44 2.454 0.57377049 PASS RUN 2 3.1 3.123 0.74193548 PASS RUN 3 2.54 2.563 0.90551181 PASS 60 L air bubble RUN 1 4.3 4.324 0.55813953 PASS RUN 2 4.28 4.298 0.42056075 PASS RUN 3 4.86 4.893 0.67901235 PASS 80 L air bubble RUN 1 5.9 5.934 0.57627119 PASS RUN 2 6.26 6.292 0.51118211 PASS RUN 3 6.4 6.383 0.265625 PASS 100 L air bubble RUN 1 7.16 7.152 0.11173184 PASS RUN 2 7.22 7.235 0.20775623 PASS RUN 3 7.34 7.325 0.20435967 PASS 6.2 System Performance Test The system performance test was executed in order to collect data to study the performance of the system with different sizes of air bubbles. The analysis was required in order to verify that the system would successfully stop, via the blood line clamp, air bubbles larger than 60L. The test was pe rformed with bovine blood at body temperature and a blood flow rate of 300mL/min. A seri es of air bubbles, ranging from 10 to 100Ls,

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77 were injected inside the blood tubing and the pulsewidths measured by the DSP algorithm were recorded. For each air bubble size, ten air bubble injections were performed and the corresponding pulsewidth m easurements were recorded. The complete data are presented in Appendix C. The data collected allow the generation of several plots, which were used to analyze system performance. The first plot was an XY-Scatter plot. In this plot, each measurement is represented by a data point whose X-value represents the air bubble size and the Y-value is the measured pulsewidth. Since ten injections were performed for each air bubble size, the plot displayed a series of sequences of 10 points, which were plotted vertically. This type of graph indi cates the consistency and reliability of the measurements. For example, if ten measurements are collected by injecting ten 50L air bubbles and the plot shows a sequence of point s scattered vertically, the measurements will be inconsistent. Such a plot could arise due to a system failure. Analysis of the scatter plot of system performance revealed that each air bubble size yielded sequences of data points, whic h were uniformly distributed around a center point, with no scattered points. Therefore, the system developed during this research was considered to be consistent and reliable. Figure 6.2 presents the XY-Scatter plot of system performance.

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XY-Scatter Plot of System Performance0123456789020406080100Air bubble size (uL)Pulse Width (ms) 120 10 uL 20 uL 30 uL 40 uL 50 uL 60 uL 70 uL 80 uL 90 uL 100 uL Figure 6.2: XY-Scatter Plot of System Performance In order to display the data distribution as a function of air bubble size, pulsewidth and test run, a three dimensional column plot was generated. The column plot provides an intuitive view of the data distribution. The column plot generated from the system performance test data demonstrated that the system was not capable of detecting 10 and 20L air bubbles. However, the system detected 30L air bubbles six out of ten times. This behavior was considered acceptable since the air detector modules piezo ceramic was calibrated to reliably detect air bubbles larger than 40L. In addition, the plot shows that the pulsewidth becomes gradually larger as the air bubble size increases. These phenomena are illustrated by the column plot of system performance presented in Figure 6.3. 78

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12345678910 10 uL30 uL50 uL70 uL90 uL 012345678Pulse Width (ms)RunAir Bubble Size (uL)3 D Column Plot of System Performance 10 uL 20 uL 30 uL 40 uL 50 uL 60 uL 70 uL 80 uL 90 uL 100 uL Figure 6.3: 3D Column Plot of System Performance A bar graph was generated, from the system performance data, which displayed the average of the ten test runs for each air bubble size. The bar at the top of each column, in Figure 6.4, indicates the standard deviation of the group. The bar graph display of system performance clearly indicates a linear relationship between air bubble size and pulsewidth. Since 30L air bubbles were detected six out of ten times, the standard deviation for this data set was visibly higher. Figure 6.4 presents the Average and Standard Deviation Plots of system performance. 79

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Average and Standard Deviation Plots of System Performance 012345678102030405060708090100Air Bubble Size (uL)Pulse Width (ms) Figure 6.4: Average and Standard Deviation Plots of System Performance The strong correlation between air bubble size and pulsewidth was also observed in the Line plots of the average of the ten test runs for each air bubble size, which were generated from the system performance data. By intersecting the data curve with a horizontal straight line, which represents the 3ms threshold, it is possible to predict the theoretical air bubble size associated with the 3ms threshold. During these tests the threshold air bubble size was 45L. This means that 45L air bubbles are likely to produce pulsewidths of 3ms. The Line plots of system performance are presented in Figure 6.5. 80

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Line Plot of System Performance012345678102030405060708090100Air Bubble Size (uL)Pulse Width (ms) Data Curve 3 ms Threshold Figure 6.5: Line Plot of System Performance Data associated with the frequency of activation of the blood line clamp and the triggered alarms was gathered for each air bubble size. A percentage value was calculated, as the ratio of the number of times the measured pulsewidth was larger than 3ms to the sample size of 10 test runs, for each air bubble size. The calculations indicated that the system could not halt air bubbles smaller than 30L. The chances of stopping 40 and 50L air bubbles were 40% and 70% respectively. The uncertainty was due to the fact that 40 and 50L air bubbles produce pulsewidths that are very close to the 3ms threshold. However, the system successfully stopped all air bubbles greater than or equal to 60L. The data demonstrates that the system performed in accordance with the specifications. Figure 6.6 presents the plots of system performance with respect to detection percentages related to air bubble sizes. 81

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Detection Percentage Plot of System Performance0%20%40%60%80%100%120%102030405060708090100Air Bubble Size (uL)% of Detection 10 20 30 40 50 60 70 80 90 100 Figure 6.6: Detection Percentage Plot of System Performance 82

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83 CHAPTER 7 CONCLUSIONS AND FUTURE WORK 7.1 Conclusions This research addressed the design of a D SP based air detector system to prevent air embolism during hemodialysis therapy. Th e research successfully demonstrated that the air detector system developed was capable of reliably detecti ng 60L or larger air bubbles in blood. The experimental results de monstrated that the system was reliable, fast and accurate for detecting air bubbles. With respect to the software perspective, implementation of the DSP algorithm to detect air bubbles was demons trated to be highly effective as shown by the system validation test data. The average percent error was found to be less than 1%. With respect to the hardware viewpoint, the DSP56824 was found to be very suitable for accurately meas uring the pulsewidth of the signal generated by the Ultrasound Air Detector. Even though th e system was feasible from the design point of view, the DSP based Air Detector System develope d in this research was not cost-effective due to the high cost of a DSP board and the CodeWarrior IDE software. Therefore, the manufacturability of the system in large scale on hemodialysis machines is not suggested. However, the system can be us ed as a test fixture to test air detector modules before their installati on in a hemodialysis machine.

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84 7.2 Future Work Future investigations should incorporat e the development and implementation of a test fixture to simultaneously test multiple air detector modules. The fixture designed during this research could be used to test the reliability and the performance of air detector modules before they are instal led in hemodialysis machines. Future investigations should also consider the idea of developing a mechanical sub-system for breaking down and/or dissolvi ng a large bubble into smaller one s when air is detected in blood and the blood line clamp is activate d. Mechanical vibration could be an appropriate approach for breaking up large air bubbles. The vibr ation should be strong enough to break the air bubble but, at the same time, not strong enough to damage biological structures in the blood such as red and white blood cells.

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85 REFERENCES [1] John T. Daugirdas and Todd S. Ing, “Handbook of Dialysis”, 2nd Edition, A Little Brown Handbook, 1994 [2] Gerard J. Tortora, Bryan H. Derricks on, “Principles of Anatomy and Physiology”, 11th Edition, 2005 [3] Sherri Bresn, “Overview of Hemodialysis”, http://www.ikidney.com/iKidney/Community /Pro2Pro/Nurses/Printer/Overviewof Hemodialysis.htm [4] Hendrick Health System, “Overview of Dialysis”, http://www.ehendrick.org/healthy/003421.htm [5] National Kidney and Urologic Diseases Information Clearinghouse, “Treatment Methods for Kidney Failure: Hemodi alysis”, NIH Publication No. 03–4666, September 2003 http://kidney.niddk.nih.gov/kudi seases/pubs/hemodialysis/ [6] United States Renal Data Sy stem, “2004 Annual Data Report”, 2005 http://www.usrds.org/adr.htm [7] Sanford T. Reikes, “Trends in End-Stag e Renal Disease”, Post graduate Medicine Journal, Volume 108; NO 1, July 2000 [8] Walter G. Belleza, “End Stage Renal Disease” http://www.hypertension-consult.com/ Secure/Articles/RenalDisease.htm [9] Aksys LTD, “Treating End-Stage Renal Disease” http://www.aksys.com/therapy/renal.asp [10] S.O.Kasap, “Principles of Electrical Engineering Mate rials and Devices”, Revised Edition, McGraw-Hill, 2000 [11] Paul Horowitz and Winfield Hill, “The Art of Electronics”, 2nd Edition, Cambridge University Press, 1989 [12] National Semiconductor IC Datash eet, “LM556 Dual Timer”, March 2000

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86 [13] Motorola Analog IC Device Datasheet “Three-Terminals Adjustable Output Positive Voltage Regulator”, 1996 [14] Fairchild Semiconductor Datasheet, “74ACQ244/74ACTQ244 Quiet Series Octal Buffer/Line Driver with 3-STATE Outputs”, 1989 [15] Motorola Inc., “DSP56824 Evaluation Module Hardware Reference Manual”, 1999 [16] Motorola Inc., “DSP56824 16 bit Digita l Signal Processor: Technical Data”, 2000 [17] Motorola Inc., “DSP56824 Evaluation Module User Manual”, 2000 [18] Motorola Inc.; Metrowerks, “Programming Motorola's DSP”, 2003 [19] Motorola Inc.; Metrowerks, “CodeWa rrior for Motorola DSP56824 Tutorials”, 2000 [20] William H. Ford and William R. Top p, “Introduction to Computing Using C++ and Object Technology”, Prentice Hall, 1999

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87 APPENDICES

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88 Appendix A Air Detector DSP Code #include #include "56824Registers.h" /*Global variables*/ int flag = 0; /*Prototypes for our interrupt handlers*/ void ISR(void); //IRQA interrupt handler void Irqb_ISR(void); int main(void) { int i; //setup Interrupt Service Routines (ISRs) pmemwrite((WORD)0xE9C8,(WORD)0x0014); //Write JSR instruction pmemwrite((WORD)ISR,(WORD)0x0015); //ISR address pmemwrite((WORD)0xE9C8,(WORD)0x0012); //Write JSR pmemwrite((WORD)Irqb_ISR,(WORD)0x0013); //IRQB's ISR address *PBDDR = 0x0F00; //Set PBDDR register. pin1: input; pin9 thru 12: outputs *PBDR = 0x0400; //Enable Gr een LED of visual alarm *IPR = 0x8000; //Enable GPIO interrupt by setting the INTERRUP PRIORITY REGISTER: //binary 1000000000000000 = hex 8000*/ /* ** Set PBINT to trigger interrupts: ** FALLING EDGE INTERRUPT on pin1 ==> PB INT = 0x0101 ** FALLING EDGE INTERRUPT on pin1 ==> PBINT = 0x100 */ *PBINT = 0x0101; //Falling edge interrupt enabled *BCR = 0; //Initialize BCR for zero wait states *PCR0 = 0x0280; //3.6864 MHz 19 = 70 MHz //Enable PLL using the oscillator clock *PCR1 = 0x4208; //Enable PLL printf("Clock running at %3f MHz\n", 19* 3.6864); //Print Phi clock's frequency for(iI = 0;i < 0x1fff;i++) //Delay to meet lock spec

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89 Appendix A: (Continued) { asm(nop); asm(nop); asm(nop); } for(i = 0;i < 0x1fff;i++) //Delay to meet lock spec { asm(nop); asm(nop); asm(nop); } //Enable all levels of interrupts asm(bfset #$0100,sr); asm(bfclr #$0200,sr); //Preload and Count Timers initialization printf("Initializing timers\n"); *TCR01 = 0; //Turn off Timing module *TPR0 = 0xFFFF; //Timer0 Preload Register Reset *TPR1 = 0xFFFF; //Timer1 Preload Register Reset *TCTR0 = 0xFFFF; //Timer0 Count Register Reset *TCTR1 = 0xFFFF; //Timer1 Count Register Reset //Processor sits in an infinite loop waiting for an Interrupt event to occur while(i) { asm(nop); asm(nop); } return 0; } //end main() void ISR(void) #pragma interrupt { //Variable Declarations WORD low_count; WORD high_count; float time_elapsed; float clock; float timer0_resolution; float timer0_duration; int j;

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90 Appendix A: (Continued) switch(flag) //check variable flag status { case 0: for(j = 0; j < 150;j++) //nanoseconds delay { asm(nop); } *TPR0 = 0xFFFF; //Timer0 Preload Register Reset *TPR1 = 0xFFFF; //Timer1 Preload Register Reset *TCTR0 = 0xFFFF; //Timer0 Count Register Reset *TCTR1 = 0xFFFF; //Timer1 Count Register Reset *TCR01 = 0x8280; //Start Timing module *PBINT = 0x0100; //Rising Edge Transition Enable *PBDR = 0; //Green LED Disable printf("Timer on\n"); break; case 1: *TCR01 = 0x0000; //Stop Timing module //Read Timer0 and Timer1 count value. low_count = (WORD)*TCTR0; high_count = (WORD)*TCTR1; clock = (3.6864 *19)/4; //Calculate Phi Clock/4 frequency timer0_resolution = 1/clock 0.000001; //Calculate Timer0 Resolution timer0_duration = 0xFFFF timer0_resolution; //Calculate Timer Duration time_elapsed = (float)(65535-high_count)* timer0_duration + (float)(65535-low_count)* timer0_resolution; //calculate time_elapsed printf("Timer off\n"); printf("Time = %e%s\n",time_elapsed, "sec"); //Reset Preload and Count Timers *TPR0 = 0xFFFF; *TPR1 = 0xFFFF; *TCTR0 = 0xFFFF; *TCTR1 = 0xFFFF; *PBINT = 0x0101; *PBDR = 0;

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91 Appendix A: (Continued) if (time_elapsed>0.003) //Compare to Air Detected Threshold { printf("Alarm\n"); *PBDR = 0x0B00; //Activate alarms outputs *IPR = 0x0012; //Disable GPIO interrupt and enable IRQB } else *PBDR = 0x0400; //Activate Green LED break; } //end swith structure flag = (flag == 0) ? 1: 0; //Toggle Flag for (j = 0;j < 1000;j++) //Short delay { asm(nop); } } //end ISR() void Irqb_ISR(void) { #pragma interrupt long i; //Add delay to debounce the switch for(i = 0;i < 0x40000;i++) { asm(nop); } //Reset Preload and Count Timers *TPR0 = 0xFFFF; *TPR1 = 0xFFFF; *TCTR0 = 0xFFFF; *TCTR1 = 0xFFFF; *PBINT = 0x0101; //Falling Edge Transition Enable *IPR = 0x8000; //Enable GPIO interrupt and disable IRQB *PBDR = 0x0400; //Activate Green LED } //end Irqb_ISR()

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92 Appendix B “56824Register.h” Code #define IPR (WORD*)0xFFFB //I nterrupt priority register #define BCR (WORD*)0xFFF9 //Bus control register #define PCR1 (WORD*)0xFFF3 //PLL control register 1 #define PCR0 (WORD*)0xFFF2 //PLL control register 0 #define PCD (WORD*)0xFFEF //Port C data register #define PCDDR (WORD*)0xFFEE //Por t C data direction register #define PCC (WORD*)0xFFED //Port C control register #define PBDR (WORD*)0xFFEC //Port B data register #define PBDDR (WORD*)0xFFEB //P ort B data direction register #define PBINT (WORD*)0xFFEA //Port B Interrupt register //Timer defines #define TCR1 (WORD*)0xFFDF //Timer control register 1 #define TCR2 (WORD*)0xFFDA //Timer control register 2 #define TPR0 (WORD*)0xFFDE //P reload register for timer 0 #define TPR1 (WORD*)0xFFDC //P reload register for timer 1 #define TPR2 (WORD*)0xFFD9 //P reload register for timer 2 #define TCTR0 (WORD*)0xFFDD //Count register for timer 0 #define TCTR1 (WORD*)0xFFDB //Count register for timer 1 #define TCTR2 (WORD*)0xFFD8 //Count register for timer 2

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93 Appendix C System Performance Test Data Table C.1: 10 to 50 L Air Bubble Injections Temp Flow Rate Temp 37 C 300 mL/min 37.1 C 10 20 30 40 50 RUN 1 0 0 0 2.454 3.942 RUN 2 0 0 2.112 3.123 3.421 RUN 3 0 0 1.823 2.563 3.84 RUN 4 0 0 0 2.343 2.927 RUN 5 0 0 1.995 2.866 3.529 RUN 6 0 0 0 3.555 3.234 RUN 7 0 0 2.002 2.123 3.123 RUN 8 0 0 2.393 2.982 2.993 RUN 9 0 0 0 3.453 3.523 RUN 10 0 0 1.732 3.342 2.534 AVERAGE 0 0 1.2057 2.8804 3.3066 STAND. DEV. 0.0000 0.0000 1.0520 0.4956 0.4315 % Detection 0% 0% 0% 40% 70% Table C.2: 60 to 100 L Air Bubble Injections Temp Flow Rate Temp 37 C 300 mL/min 37.1 C 60 70 80 90 100 RUN 1 4.324 5.234 5.934 6.793 7.152 RUN 2 4.298 5.4534 6.292 6.421 7.235 RUN 3 4.893 6.324 6.383 6.902 7.325 RUN 4 3.793 6.001 6.021 6.829 6.834 RUN 5 3.932 5.766 6.091 6.552 6.992 RUN 6 4.29 5.231 5.713 5.991 7.532 RUN 7 4.217 5.372 5.923 6.199 7.239 RUN 8 3.823 4.945 6.493 6.773 7.002 RUN 9 3.937 4.992 6.012 6.625 7.592 RUN 10 4.124 5.783 6.241 6.462 7.623 AVERAGE 4.1631 5.51014 6.1103 6.5547 7.2526 STAND. DEV. 0.3257 0.4482 0.2387 0.2936 0.2692 % Detection 100% 100% 100% 100% 100%


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Development and implementation of a DSP based air detector system to prevent embolism during hemodialysis therapy
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ABSTRACT: This thesis describes the design of a DSP based air detector system to prevent air embolism during Hemodialysis, which is a treatment option for kidney failure disease. Hemodialysis consists of removing blood from the body, filtering and treating the blood to remove toxic substances such as wastes and fluids, reestablishing proper chemical levels in the blood and returning the processed blood to the body. The functions of hemodialysis are performed through the use of a dialyzer, which is also known as an artificial kidney. During hemodialysis small air bubbles may infiltrate the tubing used during the therapy and combine to form larger air bubbles that are harmful to the patient. If an air bubble is large enough and enters the patient's circulatory system, the blood flow can be blocked and the patient can die by embolism. Most of the hemodialysis instruments in use today are equipped with air detection systems, which are based on analog design and digital microcontroll ers. This thesis presents a design method based strictly on DSP technology. The Motorola DSP 56824EVM was considered suitable for this biomedical application since its performance parameters include high-speed, multi-signal control capability, reliability and stability. These performance parameters are considered to be the most important when designing biomedical instruments dealing with human beings' life and safety. The objective of this research was the development and implementation of a DSP algorithm for the detection and measurement of the sizes of air bubbles in a fluid. In addition the algorithm had to possess the capability, when appropriate, to initiate protective and awareness measures such as triggering a tube clamp as well as activating visual and audio alarms. The air detection was accomplished by means of a commercial air detector module, which was based on piezo ceramic and ultrasound sensing. The function of the tubing clamp was to stop the fluid flow in the tub ing and prevent an air bubble from entering the patient's circulatory system. A secondary goal of this research was to exploit the capability of the DSP 56824EVM and demonstrate its suitability for biomedical applications.
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