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Low-power flip-flop using internal clock gating and adaptive body bias

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Title:
Low-power flip-flop using internal clock gating and adaptive body bias
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Language:
English
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Galvis, Jorge Alberto
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University of South Florida
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Subjects / Keywords:
Clocked Storage Elements
Logical effort
Spice simulations
Power consumption
Clocked logical units
Dissertations, Academic -- Electrical Engineering -- Doctoral -- USF
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bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

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Abstract:
ABSTRACT: This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency.A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice.The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison.Simulations demonstrated that the new flip-flop is appropriate for applications that require low switching activity. In such a situation the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increase as the length of the period with no switching activity increases, especially when the input data is all zeros. The trade-off is an increase in the D-to-Q delays and in the flip-flop area. The LPFF presented D-to-Q delays of 60% to 69% longer than the delays of the TGFF and 9% to 11% longer than the delays of the TGCGFF. The LPFF cells require an area that is 15% to 34% larger than the TGFF cells and 6% to 17% larger than the TGCGFF cells.
Thesis:
Dissertation (Ph.D.)--University of South Florida, 2006.
Bibliography:
Includes bibliographical references.
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Statement of Responsibility:
by Jorge Alberto Galvis.
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Title from PDF of title page.
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Document formatted into pages; contains 149 pages.
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Includes vita.

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aleph - 001789669
oclc - 138471654
usfldc doi - E14-SFE0001465
usfldc handle - e14.1465
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Low-Power Flip-Flop Using Internal Clock Gating And Adaptive Body Bias by Jorge Alberto Galvis A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Wilfrido Moreno, Ph.D. Fernando Falquez, Ph.D. James Leffew, Ph.D. Srinivas Katkoori, Ph.D. Hua Cao, Ph.D. Date of Approval: March 28, 2006 Keywords: Clocked Storage Elements, L ogical Effort, Spice Simulations, Power Consumption, Clocked Logical Units. Copyright 2006, Jorge Alberto Galvis

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ACKNOWLEDGEMENTS I wish to thank Dr. Wilfrido Moreno, my major professor, for his friendship, encouragement and support. Without Dr. Morenos support this Ph.D. process would truly not have been completed. I wish to thank Dr. James T. Leffew for his arduous work in the revision and correction of the dissertation document. I wish to thank Dr. Fernando Falquez for his guidance and counseling throughout the process of this dissertation. I wish to thank Dr. Srinivas Katkoori for his guidance and teachings during my years as a graduate student and throughout the process of this dissertation. I wish to thank Dr. Hua Cao for his gentle help in this dissertation. I wish to thank Dr. A. N. V. Rao for his friendly help in this dissertation. I wish to thank my family for their sincere and valuable support.

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TABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES iv ABSTRACT vii CHAPTER 1 BACKGROUND 1 1.1 Power Consumption 1 1.2 Leakage Current 2 1.2.1 pn Junction Reverse-Bias Current 3 1.2.2 Subthreshold Leakage 4 1.2.2.1 Drain-Induced Barrier Lowering, (DIBL) 6 1.2.2.2 Body Effect 7 1.2.2.3 Narrow-Width Effect 8 1.2.2.4 Effect of Channel Length and Rolloff 8 THV 1.2.3 Tunneling Into and Through Gate Oxide 9 1.2.3.1 Fowler-Nordheim (FN) Tunneling 9 1.2.3.2 Direct Tunneling 9 1.2.4 Injection of Hot Carriers from Substrate to Gate Oxide 10 1.2.5 Gate-Induced Drain Leakage 10 1.2.6 Punchthrough 10 1.2.7 Leakage Reduction Techniques 11 1.2.8 Process-Level Leakage Reduction Techniques 11 1.2.8.1 Retrograde Doping 12 1.2.8.2 Halo Doping 12 1.2.9 Circuit-Level Leakage Reduction Techniques 12 1.2.9.1 Transistor Stacking, (Self-Reverse Bias) 13 1.2.9.2 Multiple Designs 13 THV 1.2.9.3 Multiple Channel Doping 14 1.2.9.4 Multiple Oxide CMOS 14 1.2.9.5 Multiple Body-Biases 14 1.2.9.6 Supply Voltage Scaling 18 1.3 Logical Effort 19 1.4 Clocked Storage Elements 22 1.4.1 Latch-Based Clocked Storage Elements, (CSE) 22 1.4.2 Transmission-Gate Flip-Flop, (TGFF) 24 1.4.3 True-Single-Phase-Clock Latch 26 i

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1.4.4 Transmission-Gate Flip-Flop with Input Gate Isolation 26 1.4.5 C2MOS Flip-Flop 27 1.4.6 Pulse-Triggered Latches 28 1.4.7 Pulse Register Single Latch 29 1.4.8 Purely Digital Flip-Flop 30 1.4.9 Time Window-Based Flip-Flops 31 1.4.9.1 Semi-Dynamic Flip-Flop, (SDFF) 31 1.4.9.2 Hybrid-Latch Flip-Flop, (HLFF) 32 1.4.10 Differential-Input Differential-Output Flip-Flops 33 1.4.10.1 Sense Amplifier Based Flip-Flop, (SAFF) 33 1.4.10.2 Modified Sense Amplifier Flip-Flop, (modSAFF) 34 1.4.11 Flip-Flops with Internal Clock Gating 36 1.4.11.1 Data-Transition Look-Ahead D Flip-Flop, (DL-DFF) 37 1.4.11.2 Clock-on-Demand Flip-Flop, (COD-FF) 38 1.4.11.3 Conditional-Capture Flip-Flop, (CCFF) 39 1.4.11.4 Gated TGFF, (TGCGFF) 39 1.5 Proposed Desig 41 1.6 Environment Setup 43 CHAPTER 2 METHODS 47 CHAPTER 3 RESULTS 55 CHAPTER 4 CONCLUSIONS 78 REFERENCES 80 APPENDICES 83 Appendix A Simulation Results 84 Appendix B Interface Programs 140 ABOUT THE AUTHOR End Page ii

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LIST OF TABLES Table 2.1: Fan-out for Each Cell Size 50 Table 2.2: Transistor Sizing for Each Cell 52 Table 3.1: Delay Measurements 56 Table 3.2: Power Consumption Measurements 58 Table 3.3: Total Transistor Area and Area Overhead 60 iii

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LIST OF FIGURES Figure 1.1: Using the Body Effect through Body-Bias Control 15 Figure 1.2: Global RBB Scheme 16 Figure 1.3: n-well Body-Bias Scheme 16 Figure 1.4: Adaptive Body-Bias Control Structure 17 Figure 1.5: Simple Latch 23 Figure 1.6: Clocked D Latch 23 Figure 1.7: Earls Latch 24 Figure 1.8: Conventional Transmission Gate Flip-Flop 25 Figure 1.9: Transmission-Gate Master Slave Latch, Used in the PowerPC 603 Microprocessor 25 Figure 1.10: True Single Phase Clock, (TSPC), Master Slave Latch 26 Figure 1.11: 6-stage Transmission Gate Flip-Flop 27 Figure 1.12: C2MOS Flip-Flop 28 Figure 1.13: Intel Pulsed Latch 29 Figure 1.14: Texas Instruments SN7474 D-type Flip-Flop 30 Figure 1.15: Semi-Dynamic Flip-Flop 32 Figure 1.16: Hybrid-Latch Flip-Flop 32 Figure 1.17: Sense Amplifier Flip-Flop 34 Figure 1.18: Modified Sense Amplifier Flip-flop, (modSAFF) 36 iv

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Figure 1.19: Data-Transition Look-Ahead D Flip-Flop 37 Figure 1.20: Clock-on-Demand Flip-Flop, (COD-FF) 38 Figure 1.21: Conditional-Capture Flip-Flop, (CCFF) 39 Figure 1.22: Gated TGFF 40 Figure 1.23: Proposed Design 41 Figure 1.24: Test Bench Used for the Simulations 46 Figure 2.1: Flip-Flop Time Measurements 48 Figure 2.2: Procedure Followed in the Comparison of the Flip-flops 49 Figure 2.3: Active Circuit Limiting Clock-Q Delay 50 Figure 3.1: Clock-to-Q delay with D Rising, (cqR) 62 Figure 3.2: Clock-to-Q Delay with D Falling, (cqF) 63 Figure 3.3: D-to-Q Delay with D Rising, (dqR) 64 Figure 3.4: D-to-Q Delay with D Falling, (dqF) 65 Figure 3.5: Power Consumption with 1111 as Input Pattern 66 Figure 3.6: Power Consumption with 0101 as Input Pattern 67 Figure 3.7: Power Consumption with 1001 as Input Pattern 68 Figure 3.8: Power Consumption with 0000 as Input Pattern 69 Figure 3.9: Power Consumption with the Input Pattern Comprised of 20 Ones 70 Figure 3.10: Power Consumption with the Input Pattern Comprised of 50 Ones 71 Figure 3.11: Power Consumption with the Input Pattern Comprised of 100 Ones 72 Figure 3.12: Power Consumption with the Input Pattern Comprised of 20 Zeros 73 Figure 3.13: Power Consumption with the Input Pattern Comprised of 50 Zeros 74 Figure 3.14: Power Consumption with the Input Pattern Comprised of 100 Zeros 75 v

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Figure 3.15: Power Consumed by the FF During the Total Simulation Period, (FFp) 76 Figure 3.16: Power Consumed by the Test Bench Circuit During the Total Simulation Period, (tbP) 77 vi

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LOW-POWER FLIP-FLOP USING INTERNAL CLOCK GATING AND ADAPTIVE BODY-BIAS Jorge Alberto Galvis ABSTRACT This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency. A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice. The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison. vii

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Simulations demonstrated that the new flip-flop is appropriate for applications that require low switching activity. In such a situation the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increase as the length of the period with no switching activity increases, especially when the input data is all zeros. The trade-off is an increase in the D-to-Q delays and in the flip-flop area. The LPFF presented D-to-Q delays of 60% to 69% longer than the delays of the TGFF and 9% to 11% longer than the delays of the TGCGFF. The LPFF cells require an area that is 15% to 34% larger than the TGFF cells and 6% to 17% larger than the TGCGFF cells. viii

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CHAPTER 1 BACKGROUND 1.1 Power Consumption Power consumption has become a very important issue for VLSI designers. For battery-operated systems, such as laptops, calculators, cell phones and MP3 players power dissipation is critical since it determines the battery life and has a direct impact on the consumer valuation of the product. Low power consumption is generally achieved only by careful handcrafted design. Power consumption in CMOS circuits can be divided in two components: Static dissipation, which is due to leakage current. Leakage current is a small current that flows through the transistor even when the transistor is off and there is no switching activity. Dynamic dissipation, which is due to charging and discharging of load capacitances and short circuit currents while both pMOs and nMOS networks are partially on. Dynamic Power can be expressed as, [32]: 221dddynCfVP (1.1) where is the switching activity, 1

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f is the frequency, C is the capacitance. The subthreshold leakage power is: TTHddssubddleaknVVVLWIIVPexp (1.2) where subI is the subthreshold current, THV is the threshold voltage, TV is the thermal voltage, W is the channel width, L is the channel length. 1.2 Leakage Current The major mechanisms responsible for leakage current in short-channel transistors are: reverse-bias pn junction leakage, subthreshold leakage, oxide tunneling current, gate current due to hot-carrier injection, gate-induced drain leakage, (GIDL), channel punchthrough current. 2

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1.2.1 pn Junction Reverse-Bias Current In the normal operation of an MOS transistor the drain and source to well junctions are reverse biased. This bias condition generates a small pn junction leakage current. This current has two components: a current due to minority carrier diffusion near the edge of the depletion region, a current due to electron-hole pair generation in the depletion region. The reverse-bias leakage from a pn junction is a function of junction area and doping concentration, [26]. As MOS technology scales down beyond the 180 nm technology, the n and p regions of the transistors are more heavily doped and the dominant component of the leakage current is due to band-to-band tunneling, (BTBT), [26]. The tunneling current density is given by, [26]: EEBEEVAJggrbbbb3exp (1.3) 23*2hqmA (1.4) qhmB228* (1.5) where *m is the effective mass of electron, gE is the energy-band gap, rbbV is the applied reverse bias, 3

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E is the electric field at the junction, q is the electric charge of the electron, h is Planck's constant. Assuming a step junction, the electric field at the junction is, [61]: dasibirbbdaNNVVNqNE2 (1.6) where aN is the doping in the p side, dN is the doping in the n side, si is the permittivity of silicon, biV is the built-in voltage across the junction. 1.2.2 Subthreshold Leakage A small current flows between the source and drain when THGSVV This small current is called the subthreshold or low inversion leakage current. The subthreshold current is essentially a diffusion current. The subthreshold current is given by, [61]: TDSTTHgToxdsVvmVVVVmLWCIexp1exp120 (1.7) where, dmoxoxdmoxsioxdmWtWtCCm3111 (1.8) 4

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qkTVT (1.9) and THV is the threshold voltage, TV is the thermal voltage, k is the Boltzmann's constant, T is the temperature, oxC is the gate oxide capacitance, 0 is the zero bias mobility, m is the subthreshold swing coefficient, which is also called the body effect coefficient, dmW is the maximum depletion layer width, oxt is the gate oxide thickness, dmC is the capacitance of the depletion layer,. The inverse of the slope of the dsI10log versus characteristic is called the subthreshold slope, which is expressed as, [61]: GSV oxdmdsgstCCqkTqmkTIdVdS13.23.2log110 (1.10) The subthreshold slope indicates how effectively the transistor can be turned off. This phenomenon is observed as the rate of decrease of when is decreased below The parameter is measured in millivolts per decade of the drain current. For the limiting case of room temperature and OFFI GSV THV tS 5

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0oxt tS = 60 mV/decade, [26]. 1.2.2.1 Drain-Induced Barrier Lowering, (DIBL) In the case of long-channel devices, the source and drain are separated enough that their depletion regions have no effect on the potential or field pattern in most part of the device. In this case, the threshold voltage is virtually independent of channel length and drain bias. As the distance from source to drain decreases, the electrical potential barrier between the source and drain diminishes in height, the threshold voltage decreases and the dependence of the threshold voltage on the drain voltage increases. This set of phenomena is termed short channel effects, (SCE), [1]. In the case of short-channel devices, the source and drain depletion width in the vertical direction and the source drain potential have a strong effect on band bending over a significant portion of the device. Therefore, the threshold voltage and the subthreshold current of short-channel devices vary with the drain bias. This effect is termed Drain-Induced Barrier Lowering, (DIBL), [26]. In the case of a long-channel device the barrier height is mainly controlled by the gate voltage and is not sensitive to However, in the case of a short-channel device, an increase in the drain voltage diminishes the energy barrier and lowers the threshold voltage. Therefore, the subthreshold current increases. The DIBL effect is more pronounced with high drain voltages and shorter channel lengths. Higher surface and channel doping along with shallow source/drain junction depths reduce the DIBL effect DSV 6

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on the subthreshold leakage current. DIBL lowers but has no effect on the subthreshold slope (), [26]. THV tS 1.2.2.2 Body Effect When the well-source junction of a MOSFET is reverse biased, the bulk depletion region is widened and increases. can be expressed as, [26]: THV THV oxbsBsiBfbTHCVqNVV222 (1.11) iaBnNqkTln (1.12) where fbV is the flat-band voltage, aN is the doping density in the substrate, B is the difference between the Fermi potential and the intrinsic potential of the substrate. The subthreshold leakage of an MOS device including weak inversion, DIBL and body effect can be modeled as, [10], [26]: TDSTDSSTHSGsubVvmVVVVVVAIexp1'exp0 (1.13) TTHTeffoxVVeVLWCAexp8.12'0 (1.14) where 0THV is the zero bias threshold voltage. 7

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The body effect for small values of source to bulk voltages is linear and is represented by the term SV where is the linearized body effect coefficient, is the DIBL coefficient, 0 is the zero bias mobility, m is the subthreshold swing coefficient of the transistor, THV is a term introduced to account for transistor-to-transistor leakage variations. 1.2.2.3 Narrow-Width Effect The decrease in gate width modulates the threshold voltage, which modulates the subthreshold leakage. 1.2.2.4 Effect of Channel Length and Rolloff THV The decrease in threshold voltage as the channel length is reduced in the different chip generations is called rolloff. In short-channel devices, the distance from source to drain is comparable to the depletion width in the vertical direction. Currently, the source and drain depletion regions extend deeper into the channel, which depletes part of the channel. Hence, has to invert less bulk charge in order to turn on a transistor. Therefore, the threshold voltage is lower for a short-channel device. The same THV GSV GSV 8

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produces more band bending in the Si-SiO interface in a short-channel device than in a long-channel device, [26]. 2 1.2.3 Tunneling Into and Through the Gate Oxide As the CMOS technology scales down the gate oxide thickness is reduced, which increases the electric field across the gate oxide. As a consequence, the tunneling current across the gate oxide increases. Tunneling between the polysilicon of the gate and the substrate can be classified in two components: Fowler-Nordheim, (FN), tunneling direct tunneling, [26]. 1.2.3.1 Fowler-Nordheim, (FN), Tunneling Electrons tunnel into the conduction band of the oxide layer as a result of FN tunneling. However, normal device operation produces negligible FN tunneling current. 1.2.3.2 Direct Tunneling In very thin oxide layers, which measure less than 30-40 Angstroms, electrons from the inverted silicon surface tunnel directly to the gate through the forbidden energy gap of the SiO layer. The current density of direct tunneling can be expressed as, [26]: 2 oxoxoxoxDTEVBAEJ2/3211exp (1.15) 9

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oxhqA83 (1.16) hqmBox3282/3* (1.17) As the gate oxide becomes thinner the direct tunneling current becomes a more significant part of the leakage current. 1.2.4 Injection of Hot Carriers from Substrate to Gate Oxide In a short channel device, holes or electrons can gain enough energy from the electric field to cross the Si-SiO2 interface potential barrier and enter the oxide layer. This phenomenon is called hot-carrier injection and is more likely for electrons than holes since the electron barrier height is 3.1 eV while the hole barrier height is 4.5 eV, [61]. 1.2.5 Gate-Induced Drain Leakage A high electric field in the drain junction produces Gate Induced Drain Leakage, (GIDL), [61]. Thinner gate oxides and higher s increase the electric field in the drain junction, which increases the Gate Induced Drain Leakage. DDV 1.2.6 Punchthrough As the channel length is scaled down and the doping is kept constant, a point where the depletion regions of drain and source merge can be reached as is increased. This situation is called punchtrhough, [26]. DDV 10

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1.2.7 Leakage Reduction Techniques As the channel length scales down in new chip generations, also decreases. Therefore, power consumption due to leakage current becomes a significant component of the total power consumption in both active and idle modes. A reduction in leakage power can be achieved through the use of both process and circuit-level techniques. At the process level, the techniques for decreasing leakage power involve controlling transistor dimensions such as junction depth, channel length and width, oxide thickness and doping profiles. At the circuit level, the techniques include transistor sizing and controlling the voltages of the body, drain, source and gate terminals. THV 1.2.8 Process-Level Leakage Reduction Techniques The principle of constant field scaling requires device voltages and device horizontal and vertical dimensions to be scaled by the same factor in order to keep the electric field constant. This principle ensures that the scaled device retains the same behavior in terms of hot-carrier injection. One technique for leakage control involves scaling down the vertical dimensions, such as junction depth and oxide thickness, as the horizontal dimensions and the applied voltages are decreased, [26]. Another set of techniques involves changing the doping profile in the channel in order to modify the distribution of the electric field and potential contours. Careful optimization of the doping profile allows the OFF-state leakage to be minimized while the linear and saturated drive currents are maximized. This set of techniques includes halo implants and superstep retrograde wells, [26]. 11

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1.2.8.1 Retrograde Doping Retrograde doping involves a vertically, non-uniform, low-high channel doping. Low surface channel concentration and highly doped sub-surface regions are created. The low surface concentration minimizes channel impurity scattering, which increases surface channel mobility. The highly doped sub-surface region serves as a barrier against punchtrough, [26]. 1.2.8.2 Halo Doping Halo doping involves a nonuniform channel profile in a lateral direction. In the case of nMOSFETs, more highly p-type doped regions are formed near the two ends of the channel by injecting point defects during sidewall oxidation that gather doping impurities from the substrate. The effect of the halo doped regions is to reduce the width of the depletion region in the drain-substrate and source-substrate areas. The effective channel length is reduced and the off-current becomes less sensitive to channel length variation. The distance between the source and drain depletion regions becomes larger since the junction depletion widths are smaller and the channel edges are more heavily doped. As a result, the probability of a punchthrough decreases, [26]. 1.2.9 Circuit-Level Leakage Reduction Techniques There are four major circuit design techniques for leakage reduction in digital circuits. The circuit design leakage reduction techniques are: Transistor stacking, Multiple THV 12

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Dynamic THV Supply voltage scaling, which includes multiple and dynamic DDV 1.2.9.1 Transistor Stacking, (Self-Reverse Bias) In a stack of series-connected transistors the subthreshold leakage current decreases substantially when one or more transistors in the stack are turned off. This effect is known as the stacking effect, [26]. As a consequence of the stacking effect, the subthreshold leakage current through a logic gate depends on the applied input vector. Several methods have been proposed for obtaining the best input vectors for decreasing the leakage current in a given circuit. The methods proposed include random search, simulated annealing and genetic algorithms. Another technique based on the stack effect inserts a leakage control transistor in series for gates, which are not in the critical path. The control transistor is turned off in the idle mode. 1.2.9.2 Multiple Designs THV This method uses lowtransistors in the critical paths for maintaining high performance and hightransistors are used in non critical paths for reducing leakage power consumption. THV THV 13

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1.2.9.3 Multiple Channel Doping Low and high threshold voltages can be obtained by adjusting the channel-doping densities, [26]. Multiple channel doping requires two additional process masks. However, if the difference between the threshold voltages is very small, variations in the doping density distributions make the task very difficult. 1.2.9.4 Multiple Oxide CMOS The threshold voltage can also be controlled by changing the gate oxide thickness. This technique requires that two different oxide thicknesses be deposited. Thicker oxide transistors have higher threshold voltage and are used in non-critical paths while transistors with smaller oxide thickness have lower threshold voltage and are used in the critical paths. In submicron devices the channel length must be increased when the oxide thickness is increased, in order to avoid Short Channel Effects, [26]. The use of higher oxide thicknesses has several benefits. Higher oxide thickness reduces the subthreshold leakage, the gate oxide tunneling and the gate capacitance. Therefore, the use of higher oxide thicknesses reduces both the static power consumption and the dynamic power consumption. 1.2.9.5 Multiple Body-Biases Body voltage can be modified in order to control the threshold voltage in bulk silicon devices. If different body bias voltages are applied to different nMOS transistors, a triple well is required since the transistors cannot share the same well. One method to control drain-to-source leakage is through the use of the body effect by variation of the 14

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body voltage. When lowtransistors are used, a reverse body bias, (RBB), is applied during the idle mode in order to reduce leakage. When hightransistors are used, a forward body bias, (FBB), is applied during the active mode in order to reach high performance. Figure 1.1 illustrates how the body effect is used through body-bias control. THV THV p+n+n+p+p+n+substr tapwell tapp substrateVbbnGNDVddVbbpn well Figure 1.1: Using the Body Effect through Body-Bias Control The body-bias should be kept to less than 0.5 V. Excessive RBB produces greater leakage through band-to-band tunneling while excessive FBB increases the current through the body to source diodes, [32]. A global RBB procedure for a 1.8V n-well process biases the p-type substrate at bbnV = -0.4V and the n-well at bbpV = 2.2V. The structure for this procedure is presented in Figure 1.2 15

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Vdd Gnd VbbnVbbp AY Figure 1.2: Global RBB Structure In an n-well process all nMOS transistors share the p substrate and must use the same The disadvantage of this situation is that additional power supply rails are required for distributing and An alternative procedure provides bias to the n-well and keeps the p substrate connected to ground. The structure for this procedure is presented in Figure 1.3. bbnV bbnV bbpV Vdd GndVbbp AY Figure 1.3: n-well Body-Bias Structure In comparison to the global RBB procedure n-well body-bias requires only one additional rail for distributing bbnV 16

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Gregg and Chen proposed an alternative scheme, which is termed Individual-Well Adaptive Body-Biasing, (IWABB), [11], [5]. IWABB uses small voltage control structures for biasing the n-well of selected small groups of pMOS transistors. Figure 1.4 presents the Adaptive Body-Bias control structure proposed by Gregg and Chen. bcbody contactVbbpVdd pull-cntlvdiv-cntl Figure 1.4: Adaptive Body Bias Control Structure Using adaptive body-bias, each n-well bias voltage can be chosen to be or a locally-generated bias. The choice is controlled by the complementary signals pull-cntl and vdiv-cnt, which can be derived from fuse-latches, scan-latches or an externally generated source. The selection is performed during post-fabrication testing and modifies the body bias permanently. Therefore, IWABB can be classified as a static body bias control procedure. IWABB is used to improve delay and leakage under the presence of process variation, [4]. The Adaptive Body-Bias technique can also be used in Silicon on Insulator, (SOI), pass-transistor logic, which was demonstrated by Cho and Chen, [6]. DDV In a triple-well process groups of transistors can use different p-wells, which are isolated from the substrate. Therefore, different body-biases can be used in a triple-well process. The disadvantage of this procedure is the high cost of the triple-well process due 17

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to additional and more complex processing steps. Additionally, the triple-well process requires several power supply rails. 1.2.9.6 Supply Voltage Scaling Scaling down the supply voltage significantly decreases subthreshold leakage and gate leakage. The two ways of lowering supply voltage are: static supply scaling, dynamic supply scaling. Static Supply Scaling uses two different supply voltages. A high supply voltage is applied to the elements in the critical paths while the elements in the non-critical paths receive a low supply voltage. Whenever an output from an element with a low supply drives an input of an element with a high voltage supply, a voltage level conversion is required at the interface, [26]. Dynamic Supply Scaling uses a single supply voltage. The supply voltage is kept high when high performance and a fast duty cycle are required. The supply voltage is lowered when high performance is not required. Dynamic supply scaling is a global procedure applied to several chips and requires an Operating System capable of software control of a regulation loop that generates the required supply voltage, [33]. All chips operate at the same clock frequency and same supply voltage when dynamic supply scaling is employed, [26]. A Dynamic Supply Scaling procedure exists that raises the source voltage in the idle mode. This action reduces and increases through decreased DIBL. In addition, this procedure increases which increases through the body effect. The DSV THV sbV THV 18

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disadvantage of this procedure is the difficulty of generating a stable and adjustable source voltage rail, [32]. Another procedure exists for reducing the drain to source leakage, in standby mode, by decreasing to a level just high enough to maintain the state of the system, [32]. DDV 1.3 Logical Effort Sutherland et al., have designed a method for gate-sizing that is well-adapted for fast hand calculations, [30]. The Sutherland procedure is called the Logical Effort method. This method is useful for obtaining a good approximation for the initial design point and provides good insight about the performance of different circuit topologies. The logical effort method has been used in the design of a range of digital circuits, which includes such devices as flip-flops, counters, adders and arithmetic blocks, [8], [9], [34]. The logical effort method was used in this dissertation for obtaining a first approximation of the transistor sizing of the different flip-flop cells. The logical-effort method is based on an equivalent RC circuit model. Delays are caused by the capacitive load that the logic gate drives and by the topology of the logic gate. Inverters are the simplest logic gates and are used as the basic units in this model. By definition, a static inverter possesses a logical effort of one. The logical effort of other gates measures their ability to drive current for the same input capacitance when compared to a static inverter. The delay, d, of a logic gate has two components, [30]: parasitic delay, p, which is a fixed component, stage effort, f, which is a component that is proportional to the gate's output load. 19

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The delay of a logic gate is given by: pfd (1.18) The stage effort is the product of logical and electrical efforts. The stage effort, f, is given by: hgf (1.19) The logical effort, g, is the effect of the logic gate's topology on its ability to produce output current. It is independent of the size of the transistors in the circuit. The electrical effort, h, refers to the effect of the load and the size of the transistors in a gate on its driving capability. The electrical effort is given as: inoutCCh (1.20) where outC is the total output load capacitance, inC is the input capacitance. The logical effort method can be generalized to cover multistage logic networks. A logical effort and an electrical effort are defined for a given path in the logic network. The logical effort of the path is G, which is defined as the product of the logical efforts of all the logic gates along the path. The electrical effort of the path is H, which is defined as the ratio of the load capacitance of the last logic gate in the path to the input capacitance of the first logic gate in the path. The branching effort, b, takes into account the fan-out within the network and is defined as, [30]: usefultotalonpathoffpathonpathCCCCCb (1.21) 20

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where onpathC is the load capacitance along the given path, offpathC is the capacitance of the connections branching off the path. If there is no branching, the branching effort is equal to one. The branching effort along the given path is B, which is defined as the product of the branching efforts of all the gates along the path. The path effort is F, which is equal to the product of the logical, electrical and branching efforts, [30]: HBGF (1.22) In order to obtain Minimum Delay along an N-stage logic network, each stage in the path must possess the same stable effort. In such a situation the stage effort is given by, [30]: NiiFhgf/1 (1.23) The subscript i refers to the ith stage in the path. The minimum path delay is, [30]: PFNDN/1 (1.24) where P is the total parasitic delay. Once the stage effort is determined, the transistors in each stage are sized accordingly. The transistor sizing procedure begins at the end of the path and works backwards. The input capacitance of each stage is calculated as, [30]: fCgCioutiiin,, (1.25) This input capacitance is then distributed among the transistors in the gate connected to the input. The distribution of capacitance takes into account several factors, 21

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which include the difference in carrier mobility between the nMOS and pMOS transistors. Logical effort can be viewed as the ratio of the gate to inverter input capacitance when both the gate and the inverter are sized to drive the same current, [30]. The logical effort method provides an approximate solution of the transistor sizing problem. However, some modifications are required in order to be able to apply the method to real submicron circuits. In reality, the logical effort of stacked devices is lower than the one predicted by the simple logical effort method based on a long-channel MOSFET model. A more accurate measurement of the logical effort of stacked devices is usually extracted from Spice simulations, [23]. 1.4 Clocked Storage Elements Clocked storage elements, (CSE), are digital circuit elements that capture the information at a particular moment in time and maintain it for as long as it is needed by the digital system, [23]. Clocked Storage Elements include latches and flip-flops. 1.4.1 Latch-Based Clocked Storage Elements, (CSE) The simplest CSE consists of 2 inverters connected in such a way that the second inverter provides positive feedback to the first inverter. The CSE concept is presented figuratively in Figure 1.5. 22

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DQ Figure 1.5: Simple Latch The data input is maintained due to the positive feedback loop and it can only be modified by forcing the output of the feedback inverter to change its logic state. This configuration is also known as the keeper since its function is to maintain the information on a particular node in the circuit. The major advantage of the keeper structure is its simplicity. But its major disadvantage is the high power consumption required in order to force a change to the logical state. The simple S-R, (Set-Reset), latch can modify its output, Q, at any time. In order to adapt the latch to synchronous design, the time when Q can be changed must be limited by introducing the clock signal that determines when the latch is transparent and when it is opaque. Normally, the latch will be transparent in the half cycle when the clock signal is at logic level 1 and will be opaque in the half cycle when the clock signal is at logic level 0. If the S input is connected to the R input through an inverter, a D-latch results. The resulting D-latch is presented in Figure 1.6. D QQbClk Figure 1.6: Clocked D Latch 23

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Earl's Latch was introduced during the design of the IBM S360/91 machine in mid-60's. Earl's Latch is a Sum-of-Products, (SOP), topology implementation. Earls Latch is presented in Figure 1.7. D Q ClkClk Clkb Figure 1.7: Earls Latch In order to avoid the transparency of the simple latch, two latches are connected back-to-back and clocked with two non-overlapping clock signals in an arrangement known as a Master-Slave Latch, (MSL). The first latch serves as a Master by receiving the value from the data input, D, and passes it to the Slave latch, which simply follows the Master. 1.4.2 Transmission-Gate Flip-Flop, (TGFF) The transmission gate flip-flop is built from two transmission gate latches connected in cascade. Several latch circuits can be used for implementing the TGFF. The simplest implementation is presented in Figure 1.8 and is called a conventional TGFF. The conventional TGFF is a positive-edge triggered flip-flop. 24

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CP CPICNQm SmCPI CPISmCN DQ Figure 1.8: Conventional Transmission Gate Flip-Flop An improved version, called the 4-stage TGFF, consumes less power by removing the wire connecting the drains of the top PMOS and bottom NMOS transistors, as depicted in Figure 1.9. Clk ClkbQmSm ClkbSsClk DQ Figure 1.9: Transmission-Gate Master Slave Latch, Used in the Power-PC 603 Microprocessor An extra inverter that drives the output is used for preventing loading of the feedback loop by the output capacitance. The TGFF was used in the design of the PowerPC-603 microprocessor in the mid-90's. 25

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1.4.3 True-Single-Phase-Clock Latch In the early 90's, a fast and simple structure that used a single-phase clock was designed. It was called true-single-phase-clock, (TSPC), latch, which is presented in Figure 1.10. This latch was created by combining a Master NORA logic stage and a Slave Domino logic stage. This topology results in a non-transparent MSL that only requires a single clock signal. The transfer from the master latch to the slave latch occurs during the rising edge of the clock signal and resembles the behavior of a rising-edge triggered flip-flop. DClkQ Figure 1.10: True Single Phase Clock, (TSPC), Master Slave Latch The advantages of the TSPC MSL are simplicity and speed. Its disadvantages are high power consumption and sensitivity to glitches created by the clock edges, [23]. 1.4.4 Transmission-Gate Flip-Flop with Input Gate Isolation The master latch of the 4-stage TGFF is susceptible to input noise. In order to solve the problem a 6-stage TGFF was developed. The 6-stage TGFF includes an 26

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additional inverter at the D input. Additionally, inverters were added at the Q and Qb outputs to improve the FF driving capability. Power consumption in the 6-stage TGFF is higher than in the 4-stage TGFF due to the additional stages and the increase in the total clocked capacitance. However, the 6-stage TGFF is less susceptible to input noise and has better internal race immunity, [17]. These characteristics allow the 6-stage TGFF to tolerate relatively large clock skew. The 6-stage TGFF is presented in Figure 1.11. DDbCPiCNSmQmCPiCNSsQsbQ ClkCNCPi Figure 1.11: 6-stage Transmission Gate Flip-Flop 1.4.5 C2MOS Flip-Flop The C2MOS is a pseudo-static FF, which is obtained by the addition of a weak C2MOS feedback at the outputs of the master and the slave latches in a dynamic C2MOS flip-flop. The C2MOS flip-flop is presented in Figure 1.12. 27

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DQ CPICN CPICN CPICN CPICN CPCPICN QM Figure 1.12: C2MOS Flip-Flop When selecting a flip-flop architecture, the most important aspects to take into account are flip-flop delay, internal race immunity, power consumption and noise robustness, [17]. A comparison between the 4-stage TGFF, the 6-stage TGFF and the C2MOS FF with respect to power consumption demonstrates that the 6-stage TGFF is the best and the 4-stage TGFF is the worst. The 4-stage TGFF also shows poor input noise immunity. The 6-stage TGFF has better internal race immunity and less power consumption than the C2MOS at a cost of increased delay, [16]. 1.4.6 Pulse-Triggered Latches Pulsed triggered latches have very high performance at a cost of higher power consumption. They are commonly used in the high performance microprocessors. A recent design proposed by Cheng and Lin claims to keep high performance while decreasing power dissipation, [3]. 28

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1.4.7 Pulse Register Single Latch In order to decrease the power consumption and the possibility of signal-race hazards during the transparent phase of the latch the clock pulse is made very short which minimizes the time window when the latch is transparent. The resulting latch is termed a Pulsed Latch. The short clock pulse cannot be distributed globally in the chip since it would be lost in the clock distribution network. The clock pulse is generated locally and usually drives a set of single latches that comprise a register and that are physically located very close to each other. The clock pulse is shared between several latches, which reduces the power consumption and the complexity of the register. A trade-off has to be made between opposite requirements that make this design difficult to implement. The clock pulse must be wide enough to allow the latch to capture its input data and short enough to minimize the possibility of a critical race. Intel's implementation of the pulsed latch is presented in Figure 1.13. DQbClk Figure 1.13: Intel Pulsed Latch The pulsed latch uses 3 inverters connected in series at the input of a NAND2 gate to produce a small delay in that input. The clock signal is applied to both inputs and 29

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the result is a train of very narrow pulses synchronized with the clock signal. This pulse generating mechanism is based on the principle of reconvergent fan-out with nonequal parity of inversion, [23]. 1.4.8 Purely Digital Flip-Flop A purely digital implementation of a flip-flop uses basic digital gates as units. An example of a purely digital implementation of a flip-flop is theTexas Instruments SN7474 D-type flip-flop. This flip-flop depends on the races, in time, inside the first stage in order to operate properly. The Texas Instruments flip-flop is presented in Figure 1.14 ClkDQQb Figure 1.14: Texas Instruments SN7474 D-type Flip-Flop The equations: SDRClkSn (1.26) RDSClkRn (1.27) 30

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establish the relationship between the Set, (S), and Reset, (R), signals of the S-R output latch and the Data, (D), and Clock, (Clk), input signals. The next state, (), of this flip-flop will be set to 1 only at the time the rising edge of the clock becomes 1, the data at the input is 1 and the flip-flop is in the steady state with both S and R at logic level 0. As soon as the flip-flop is set, (S = 1, R = 0), any change in data input will not affect the flip-flop state since the data input will be locked to = 1 since S = 1 makes D + S = 1 regardless of the value of D and would be disabled. nS nS nR 1.4.9 Time Window-Based Flip-Flops A discrete time event with reference to the clock or one or more inverter or gate delay units following the transition of the clock determines when the flip-flop is shut off. Flip-flops that are shut off using a reference different from the clock are called Time window-based flip-flops. 1.4.9.1 Semi-Dynamic Flip-Flop, (SDFF) The semi-dynamic flip-flop is a single-input single-output positive edge triggered inverting flip-flop, [13]. The SDFF is composed of a dynamic front-end and a static back-end. The SDFF is presented in Figure 1.15. 31

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D CP CPi CP Q CP XSQb Figure 1.15: Semi-Dynamic Flip-Flop 1.4.9.2 Hybrid-Latch Flip-Flop, (HLFF) Partovi et al. developed the Hybrid-Latch flip-flop, which was one of the first Time-window-based flip-flops. The HLFF is a single-input single-output positive edge triggered inverting flip-flop, [2] [24], [18]. The structure of the HLFF is presented in Figure 1.16. ClkDQQb X Figure 1.16: Hybrid-Latch Flip-Flop The clock edge, in the HLFF, exists during a time interval, which is required for the Clk signal to travel through 3 inverters. During the time the signal travels through the 32

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inverters the flip-flop may be transparent. Outside this time interval the flip-flop is non transparent. The time reference is produced by creating a short pulse using the clock signal and three inverters connected in series with both paths reconverging as inputs of a NAND gate. The falling edge of this pulse is used as a time reference for shutting off the flip-flop. The HLFF is similar to the SDFF since it consumes more power in the transition 1-1 than in the transition 0-0 due to the precharge/discharge operation on an internal node X, [17]. 1.4.10 Differential-Input Differential-Output Flip-Flops 1.4.10.1 Sense Amplifier Based Flip-Flop, (SAFF) The flip-flop used in the third generation of Digital Equipment Corporations 600-MHz Alpha processor was based on a static memory cell design. This particular flip-flop is known as a sense-amplifier flip-flop, (SAFF). The SAFF is also a time window-based flip-flop. The SAFF is a differential-input differential-output positive edge triggered flip-flop. The structure of the SAFF is presented in Figure 1.17. 33

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DClkDbQQb Vdd Figure 1.17: Sense Amplifier Flip-Flop In the SAFF flip-flop a 1-0 transition on D takes longer to propagate to Q than a 0-1 transition due to an additional delay through the NAND circuit. The SAFF consists of a pulse generator, (PG), and a pulse Capturing Latch, (CL). The CL can be a simple cross-coupled NAND or NOR set-reset, (S-R), latch. Like the SDFF and the HLFF, the SAFF possesses a relatively small delay. However, the SAFF also possesses a small race margin. 1.4.10.2 Modified Sense Amplifier Flip-Flop, (modSAFF) Nikolic et al., designed an improved PG stage based on the sense amplifier and combined it with the second-stage CL created by Stojanovic, [21], [23], [29]. The result 34

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was a superior flip-flop that it is considered to be one of the best high-performance flip-flops. This flip-flop is referred to as the Modified SAFF, (modSAFF). The modSAFF implements its output stage with a pass-transistor circuit in order to solve the mismatch between the rising and falling Clk-Q delays of the SAFF and uses two additional inverters for creating the S and R signals. The modSAFF has balanced timing and energy parameters due to its fully differential structure and fully balanced output stage, [17]. The modSAFF is presented in Figure 1.18. All of the pulse-triggered flip-flops, (SDFF, HLFF, SAFF and modSAFF), display a very small race margin. Therefore, pulse-triggered flip-flops are only able to tolerate minimal clock skew. This fact makes the clock distribution more difficult to design and increases the need for de-skewing circuits, which leads to an augment in the energy consumed in the clock distribution network. In addition, pulse-triggered flip-flops consume more power than the master-slave flip-flops. Master-slave flip-flops have better internal race immunity and consume less power than the pulse-triggered latches. However, the pulse-triggered latches have less delay and higher performance than master-slave flip-flops. 35

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Figure 1.18: Modified Sense Amplifier Flip-Flop, (modSAFF) 1.4.11 Flip-Flops with Internal Clock Gating This flip-flop family uses an internal predictive circuit for turning off the internal clock when the input and the stored data are equal. The internal clock gating technique is 36

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appropriate for flip-flops with low switching rate in the input data. However, its advantage decreases as the switching rate increases because of the associated overhead. 1.4.11.1 Data-Transition Look-Ahead D Flip-Flop, (DL-DFF) The Data-Transition Look-Ahead D Flip-Flop is a positive edge triggered, non-inverting flip-flop, [22]. The output of the data-transition look-ahead, (DL), circuit is an XNOR function of D and Q. When D = Q, the DL circuit output is 0 and the internal clock is deactivated. When D and Q are different the DL circuit output is 1 and the clock control circuit activates the internal clock signals. The DL-DFF is presented in Figure 1.19. DQ CKCKCKbCKbQmCP CKbCK P1 CKI CKCKb Data-TransitionLook-AheadClockControlPulseGenerator Figure 1.19: Data-Transition Look-Ahead D Flip-Flop 37

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In order to decrease the power consumption, the pulse generator is shared among several flip-flops. Simulations presented by Markovic show that the DL-DFF has less power consumption than the 6-stage TGFF when the input data transition probability is less than 0.25 and the number of flip-flops driven by a single Pulse Generator is more than 2, [17]. 1.4.11.2 Clock-on-Demand Flip-Flop, (COD-FF) The COD-FF is a positive edge triggered non-inverting flip-flop. The COD-FF possesses a local pulse generator and the control function is integrated in the internal pulse generator. The COD-FF is presented in Figure 1.20, [12]. DQ CKICKbCP XNORCKbCKI CKb PulseGeneratorData-TransitionLook-AheadDb Figure 1.20: Clock-on-Demand Flip-Flop, (COD-FF) The COD-FF possesses a small race margin since it is a pulse-triggered FF. The internal clock gating produces better power consumption when the sizes of the clocked transistors are relatively large and for low data activity rates, [17]. 38

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1.4.11.3 Conditional-Capture Flip-Flop, (CCFF) The Conditional-Capture Flip-Flop, (CCFF), is a positive edge triggered differential input differential output flip-flop, [14]. The CCFF is similar to the modified SAFF with some differences in the output stage and the presence of the internal clock gating, [19]. The CCFF has longer delay and smaller internal margin than the modSAFF. For small transistor sizes, the CCFF consumes more power than the modSAFF. Only for large transistor sizes is the CCFF more power efficient than the modSAFF, [17]. The CCFF is presented in Figure 1.21. D CP Db QbQ SbS RbR CP QbQNbN RbSSbR CPD Figure 1.21: Conditional-Capture Flip-Flop, (CCFF) 1.4.11.4 Gated TGFF, (TGCGFF) The gated TGFF is derived from the 6-stage TGFF by inserting a clock gating circuit. The comparator is implemented with complementary pass-transistor logic, (CPL), and uses available true and complementary signals. The function of the 39

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comparator is to determine if D and Q are equal. The output of the comparator is 0 when D is different from Q and activates the generation of the internal clock signals CN and CPI. The gated TGFF is presented in Figure 1.22. DDbQsbSsDbDcmpCPiCNCPiCNSmQmCPiCNSsQsbQ Clk Figure 1.22: Gated TGFF Pulse-triggered latches have higher performance than master-slave flip-flops but the cost is greater power consumption. Therefore, is not appropriate to compare pulse-triggered latches and master-slave flip-flops only in terms of energy efficiency. A more appropriate comparison is made using an energy delay product, (EDP). Markovic compared the DL-FF, COD-FF, 6-stage TGFF, gated TGFF and CCFF using an EDP and transition probabilities as the measurement parameters, [17]. His simulations 40

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demonstrated that the 6-stage TGFF presents the best energy-delay product with good race immunity for > 0.12 while the gated TGFF demonstrated the best energy-delay product for < 0.12. 1.5 Proposed Design The new flip-flop architecture proposed for this research is termed the Low-power Flip-Flop, (LPFF), and is derived from the TGFF by incorporating Adaptive Body-Bias control and Internal Clock Gating. The structure of the LPFF is presented in Figure 1.23. DDbQsbSsDbDcmpCPiCNCPiCNSmQmCPiCNSsQsbQbc bc bc bc bc bc bc bc bc bc bc bc bc bc Clk bc bc bc bc bc VddVbbpVddVdd Figure 1.23: The LPFF Proposed Design 41

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Internal Clock Gating is a suitable technique for decreasing dynamic power consumption. Adaptive Body-Bias is a technique aimed at decreasing subthreshold leakage current, which comprises the main component of static power consumption. The two techniques can be combined in a flip-flop architecture that targets both dynamic and static power consumption. Several advantages make the TGFF the best candidate for the base of the design. The TGFF has good race immunity, low power consumption and a good energy-delay product for low transition probabilities and large transistor sizes. The Adaptive Body-Bias and the Internal Clock Gating schemes can be easily incorporated in the TGFF. The body-bias control circuit used in the LPFF can modify the body-bias voltage dynamically by decreasing it when there is high data transition and increasing it when the input data does not change. In contrast, the body-bias control circuit proposed by Gregg and Chen permanently sets the body-bias voltage to a given value during the post-fabrication testing and it is aimed at optimizing the power consumption in the presence of process variations, [11]. In the design proposed for this research, the Body-Bias control circuit can use the available signal coming from the comparator in the Clock Gating circuit as the control signal that switches the Body-Bias Voltage in order to change Therefore, both circuits share the comparator, which saves transistor area and consumed power. THV The resulting flip-flop architecture is able to suspend the clock signal to the internal latches and increase the threshold voltage when the input datum is equal to the stored datum. When both data are different, the generation of the internal clock signals will be reactivated and will be lowered. This procedure allows the flip-flop to THV 42

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decrease dynamic and static power consumption during periods of low transition probability. 1.6 Environment Setup Establishing the simulation environment is a critical element of any performance comparison study. The simulation environment has to provide the conditions for a fair comparison of the different structures analyzed. However, the simulation environment must also fulfill the requirements of the intended application. Different simulation environments have been proposed in recent studies. Stojanovic and Oklobdzija implemented an environment setup for comparing the clocked storage elements, (CSEs), that used a single-sized load resembling a reasonably a loaded critical path in a processor with extensive parallelism, [29], [27], [28]. The CSEs were sized to attain optimum data-to-output delay for the given output load. In the most common case, the creation of a cell library, CSEs are designed in a discrete set of sizes with each optimized for a given load. Nikolic and Oklobdzija initially sized several CSEs to drive a fixed load and then varied the load. In this setup, the delay of a CSE presents a linear function of the size of the load, [21], [20]. The slope of the delay curve is the logical effort of the driving stage of the CSE and the zero-load intercept corresponds to the parasitic delay of the driving stage plus the delay of the inner stages of the CSE. If speed is the main design criterion, the CSE should be optimized for the elements in the critical path since they determine the clock rate of the whole system. The simulation method should try to imitate the actual data-path environment. The number of 43

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logic stages in a CSE and their complexity depend on the particular circuit implementation in which the CSE is used. A compromise has to be reached between the CSE delay and the size of the clocked transistors since some of the clocked transistors are always in the critical path of the CSE. Depending on the CSE topology, some structures can trade delay for clocked transistor size more efficiently than others. One issue of debate has always been how to compare differential and single-ended structures. Some authors are against such a comparison because of the cost that single-ended structures incur in producing the complementary output. The other approach is not to require that single-ended structures generate both true and complementary values at the output, [23]. In this research, this last approach was used because all the compared flip-flops were single-ended structures. The simulation load usually consists of several inverters in a chain, which is designed to avoid the error in delay due to Miller capacitance effects from the fast switching load back to the driver stage. Some studies have compared the performance of different CSEs using a single load that is representative of the critical path load. Other studies, especially the ones involved in the design of cell libraries, use a set of loads, which correspond to the different cell sizes in the library. In this case the CSEs are resized for each load setting. In this research, the cell library approach was used and the load was sized according to the cell size. Some CSE structures with a small number of stages and high logical effort require the testbench to provide additional buffering before the load stage. In this case and for each CSE, the calculation of the optimal effort per stage and the number of stages 44

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required to drive the load capacitance, is needed. The optimal effort per stage is given by: outC inoutCCH (1.28) where outC is the load capacitance, inC is the CSE's first stage input capacitance. The optimal number of stages, N, is given by: HGroundN 4log (1.29) The new stage effort, f, is obtained using the optimal number of stages as: NHGf/1 (1.30) The CSE internal stages and the external inverters, if there are any, must be resized after calculating the stage effort. Figure 1.24 presents the test bench used for all the simulations. FF is the flip-flop, (TGFF, TGCGFF or LPFF), under test. D is the data input and Clk is the clock signal input. Vdd is the power supply for the flip-flop. Vbbp is the power supply for the Adaptive Body-Bias circuit, which was used only with the LPFF. With respect to the LPFF: bbpV = + 0.5V. (1.31) ddV For the TGFF and the TGCGFF flip-flops, Vbbp was not required and was not present. 45

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FFVbbpVddVdd2Vdd2DClkQQaaQbbnw= 8pw= 16m= fanoutnw= 8pw= 16m= 4 fanoutxQxQdum Figure 1.24: Test Bench Used for the Simulations Vdd2 is the power supply for the test bench. It had the same voltage value as Vdd but was kept independent from the Vdd supply in order to allow independent power consumption measurements for the flip-flop and the test bench circuit. The load is represented by xQ. It was a basic CMOS inverter with a channel width of 8 for the nMOS transistor and 16 for the pMOS transistor, [31], [10]. Parameter m, (multiplier), was used to simulate the fanout. The load xQ had a load, which was designated by xQdum. The xQdum parameter was four times bigger than xQ parameter as specified by the m parameter. The purpose of xQdum was to create a more realistic xQ. Transistor models used for all the simulations were BSIM3v3 for TSMC 180 nm technology and were obtained from MOSIS. Currently, the BSIM3v3 is the most used model in industry and academy, [31]. The BSIM3v3 is a physics-based single-equation model that is continuous and smooth over all regions of operation. The BSIM3v3 offers a thorough, accurate and functional mathematical representation of MOS device physics, [15]. MOSIS uses the BSIM3v3 as the standard model. The BSIM3V3 requires approximately 180 parameters and provides reasonable accuracy for subthreshold and strong inversion operation, [25]. 46

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CHAPTER 2 METHODS The new flip-flop architecture, called the Low-Power Flip-Flop, (LPFF), was compared to the 6-stage Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate Clock-Gated Flip-Flop, (TGCGFF), using a comprehensive set of Hspice simulations with BSIM3v3 transistor models for TSMC 180 nm technology. The TGCGFF was derived from the TGFF by inserting a clock gating circuit. The LPFF was derived from the TGFF by adding a clock gating circuit and an Adaptive Body-Bias circuit. The purpose of the comparisons was to establish the effectiveness of introducing Internal Clock Gating and Adaptive Body-Bias on the power consumption and to determine the effect of these techniques on the delay and performance of the flip-flop. Several delay measurements were taken during the simulations and are explained graphically in Figure 2.1. The D input is rising when it is making a 0-1 transition. The D input is falling when it is making a 1-0 transition. Setup time, (SU), is the time interval, prior to the transition of the active clock edge, during which data input, D, must be stable in order for the flip-flop to operate properly. Two setup times, designated dRc and dFc, were considered. The dRc parameter is the setup time when D is rising and the dFc parameter is the setup time when D is falling. See Figure 2.1. 47

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dRcdFccqRcqFdqRdqFclkDQ Figure 2.1: Flip-Flop Time Measurements Hold time, (HO), is the minimum time interval, after the arrival of the active clock edge, during which data input, D, must be stable, in order for the flip-flop to operate properly. Clock-to-Output delay is the time interval from the arrival of the active clock edge to the activation of the Output. Two Clock-to-Output delays, cqR and cqF, were considered. The cqR parameter tracked the Clock-to-Output delay when D was rising. The cqF parameter tracked the Clock-to-Output delay when D was falling. See Figure 2.1. In order for the flip-flop to operate properly, Hold time must be smaller than the Clock-to-Output delays. Normally, hold time is totally overlapped by the Clock-to-Output delay. Therefore, it is not taken into account when calculating the total delay of the flip-flop. Data-to-Output delay is the time interval from a transition in the D input to the same transition in the Output. Data-to-Output delay is also called the total delay of the flip-flop. Two Data-to-Output delays, dqR and dqF, were considered. The dqR 48

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parameter tracked the Data-to-Output delay with the D input rising. The dqF parameter tracked the Data-to-Output delay with the D input falling. See Figure 2.1. The following equations establish the relationships between the different flip-flop delays: cqRdRcdqR (2.1) cqFdFcdqF (2.2) The procedure followed in making the comparisons is presented schematically in Figure 2.2. During the first step, schematic diagrams were drawn for each flip-flop using the Cadence Schematic Tool. These schematics became the initial flip-flop designs. InitialFlip-FlopDesignsTransistorSizing usingLogical EffortFF Library with cells sized fordifferent Fanouts Transistor Level Schematicsin CadenceTransistor LevelSpice NetlistsHiead.exeFlatad.exeHspice Netlists SetupTunningFineTransistorResizingHspice simulationsvarying Temperature,FO, and Vdd GraphicalPresentationof Results 1122DesignInterfaceAssessment Figure 2.2: Procedure Followed during the Comparison of the Flip-Flops Five cells were designed for each of the three flip-flops. Each cell was designed and tested for a specific range of fan-out, as indicated in Table 2.1. The transistors in each cell were sized according to the Logical Effort method and used the central Fan-out 49

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value in the corresponding range. For example, Cell 1 was sized for FO 6 and Cell 2 was sized for FO 19. The fanout for each cell is presented in Table 2.1. Table 2.1: Fan-out for Each Cell Size Cell Fanout 1 2 4 6 8 10 2 13 16 19 22 25 3 29 33 37 41 45 4 50 55 60 65 70 5 76 82 88 94 100 The limiting active circuit clock-Q delay in the three designs was the same and is presented in Figure 2.3. QmCPiCNSsQsbQ bc bc bc n1p1n2p2n3p3 Coff-path Figure 2.3: Active Circuit Limiting Clock-Q Delay Using the Logical Effort Method, cells were sized in accordance with the procedure: The off-path capacitance driven by the second stage is the capacitance of two minimum width feedback transistors where: minCCpathoff (2.3) If the size of the inverter in the third stage is x times larger than a minimum sized inverter then the total branching effort can be expressed as: 50

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xxbB12 (2.4) The logical effort, G, is: G = 1. (2.5) The electrical effort, H, is: inoutCCH (2.6) The remaining parameters can now be calculated as: HBGF (2.7) 3/13/11xxHFf (2.8) min3/133,1CxxxHHfCgCoutin (2.9) xHxxH3/11 (2.10) 331HxxxH (2.11) min2,22,1CfxfCgCoutin (2.12) Following this procedure, the transistor sizing data presented in Table 2.2 was obtained. 51

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Table 2.2: Transistor Sizing for Each Cell Cell Fanout H 3,inC f 2,inC n1 p1 n2 p2 n3 p3 1 2-10 6 3 2 2 2 4 4 8 6 12 2 13-25 19 6.8 2.8 2.79 2 4 6 11 14 27 3 29-45 37 10.78 3.43 3.43 3 6 7 14 21 43 4 50-70 60 15 4 4 4 8 8 16 30 60 5 76-100 88 19.47 4.52 4.53 4 8 9 18 39 78 Fanout is given in basic inverter units. Capacitances are expressed using as the basic unit. Transistor sizes are expressed in minC units. These transistor sizes were used to create a flip-flop library with 5 cells for each flip-flop. During the fourth step the transistor level schematics for each cell of each flip-flop were drawn using the Cadence schematic tool. Spice netlists were extracted from the Schematic diagrams, which became the inputs to Hspice simulations. Extracted netlists can be flat or hierarchical. Netlists require several parameter insertions and adaptations in order to make them suitable for Hspice simulations. Two programs were written in C++ as an aid to adapt netlists extracted from Cadence schematics to Hspice. A program, designated Flatad.exe, was designed for adapting flat netlists to Hspice and a program, designated hiead.exe, was designed for adapting hierarchical netlists. Appendix B presents an example of a flat netlist and the corresponding resulting netlist after processing by flatad.exe. Appendix B also presents an example of a hierarchical netlist and the corresponding resulting netlist after processing by hiead.exe. Comprehensive Hspice simulations were conducted on the netlists. Parameters such as Set-up time delay, temperature, fanout and supply voltage for each flip-flop were 52

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varied systematically. Temperature values used in the simulations were 0, 25, 50, 75, 100 and 125 degrees Celsius. Fanout values depended on the cell size as presented in Table 2.1. Supply voltage values used in the simulations were 1.68V, 1.8V and 1.98V, which corresponded to 90%, 100% and 110% of the nominal supply voltage appropriate for TMSC 180 nm technology. The operation frequency was kept constant at 500 MHz during all the simulations. Pilot simulations were used for fine tuning the setup time delay and to refine the resizing of the transistors in each library cell of each flip-flop. The purpose of these pilot simulations was to optimize each cell for power consumption while fulfilling the requirements of proper functioning at a minimum operation frequency of 500 MHz and to maintain the size and area as minimal as possible. The input pattern: 01111010110010000(100-1)(100-0) was used for all the simulations. The (100-1) element of the input pattern represents a sequence of 100 1's and the (100-0) element stands for a sequence of 100 zeros. The average power consumption measurements taken during all the simulations were: p1111: Flip-flop power consumption with an input pattern of 1111. It was measured from the beginning of cycle 2 to the end of cycle 5. p0101: Flip-flop power consumption with an input pattern of 0101. It was measured from the beginning of cycle 6 to the end of cycle 9. p1001: Flip-flop power consumption with an input pattern of 1001. It was measured from the beginning of cycle 10 to the end of cycle 13. p0000: Flip-flop power consumption with an input pattern of 0000. It was measured from the beginning of cycle 14 to the end of cycle 17. 53

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p20-1: Flip-flop power consumption with an input pattern of 20 1's. It was measured from the beginning of cycle 18 to the end of cycle 37. p50-1: Flip-flop power consumption with an input pattern of 50 1's. It was measured from the beginning of cycle 18 to the end of cycle 67. p100-1: Flip-flop power consumption with an input pattern of 100 1's. It was measured from the beginning of cycle 18 to the end of cycle 117. p20-0: Flip-flop power consumption with an input pattern of 20 0's. It was measured from the beginning of cycle 118 to the end of cycle 137. p50-0: Flip-flop power consumption with an input pattern of 20 0's. It was measured from the beginning of cycle 118 to the end of cycle 167. p100-0: Flip-flop power consumption with an input pattern of 20 0's. It was measured from the beginning of cycle 118 to the end of cycle 217. FFp: Flip-flop power consumption for all the simulation intervals. It was measured from the beginning of cycle 1 to the end of cycle 217. tbP: Test Bench power consumption for all the simulation interval. It was measured from the beginning of cycle 1 to the end of cycle 217. In order to automate the parameter variations, control the simulation execution and collection of the resulting data a program was written in perl. This program, designated Ch.pl, filled a pattern form with the parameter values for all iterations, ran Hspice and saved the results of all iterations in a text file. In the final step, the results obtained were presented graphically using a Matlab program that generated 3D graphics from the Hspice simulation results. 54

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CHAPTER 3 RESULTS The actual results obtained from the Hspice simulations are presented in Appendix A. Each cell of each flip-flop was simulated separately and produced its own result file. All result files were organized and assembled in three files. Each file was designated for one of the flip-flops involved in the simulations. The TGFF, TGCGFF and LPFF flip-flops were each simulated. Mean values were calculated for each measurement in each flip-flop file. These mean values are presented in Tables 3.1 and 3.2. The three data files contained the input data for the matlab program, which was used to generate and display the results as 3D graphs. The graphics generated included a detailed exhibit of the different delay and power consumption measurements produced by the simulations and are presented in Figures 3.1 to 3.16. Table 3.1 presents delay measurements for each flip-flop and compares the delay performance of the flip-flops. 55

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Table 3.1: Delay Measurements Delay Measurement TGFF (ps) TGCGFF (ps) LPFF (ps) TGCGFF/TGFF (%) LPFF/TGFF (%) LPFF/TGCGFF (%) mcqR 546.02 574.62 644.81 5.24 18.09 12.21 mcqF 510.08 488.66 533.59 -4.20 4.61 9.19 mdqR 631.02 959.62 1064.81 52.08 68.74 10.96 mdqF 595.08 873.66 953.59 46.81 60.25 9.15 The mean value of the clock-Q delay with the D input rising is designated mcqR. The mean value of the clock-Q delay with the D input falling is designated mcqF. The mean value of the D-Q delay with the D input rising is designated mdqR. The mean value of the D-Q delay with the D input falling is designated mdqF. The first three columns in Table 3.1 are the mean delay values for the three flip-flops. These values are expressed in picoseconds. The remaining columns present comparisons between the flip-flops with respect to the delay measurements. All the comparisons are expressed as percentages. Positive percentages mean an increment, expressed in percentage, in the measured delay with respect to the delay that was used as a reference. Negative percentages mean a decrement, expressed in percentage, in the measured delay respect to the reference delay. The TGCGFF/TGFF column in Table 3.1 compares the delay measurements obtained for the TGCGFF with the delay measurements of the TGFF as reference. The TGCGFF displayed a small increment in the cqR delay of 5.24% but a small decrement in the cqF delay of 4.2% when compared with the corresponding TGFF delays. The dqR and dqF parameters take into account the setup time. Therefore, when the dqR and dqF delays of the TGCGFF were compared with TGFF delays, the TGCGFF displayed 56

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greater increments of 52.08% and 46.81 respectively. TGCGFF requires a longer setup time than the TGFF. The LPFF/TGFF column in Table 3.1 compares the LPFF to the TGFF. The LPFF displayed increments in dqR delay of 68.74% and in dqF delay of 60.25%. The increments are primarily due to the longer setup time required by the LPFF. The LPFF/TGCGFF column in Table 3.1 compares the LPFF to the TGCGFF. The LPFF displayed increments of 9% to 12% in its delays when compared to the same TGCGFF delays. The data in Table 3.1 demonstrate that the introduction of the clock gating circuit in the TGCGFF increased the flip-flop delays from 60% to 68%. Additionally the introduction of the body bias circuit in the LPFF increased the flip-flop delays from 9% to 12%. Therefore, the introduction of the clock gating circuit had a greater impact in increasing delays than the introduction of the body bias circuit. Table 3.2 presents the average power consumption measurements for each flip-flop and compares the power consumption of the flip-flops. The mean value of the average power consumption when the input pattern is 1111 is designated m1111. The mean value of the average power consumption when the input pattern is 0101 is designated m0101. The mean value of the average power consumption when the input pattern is 20 ones is designated m20-1. The mean value of the average power consumption when the input pattern is 100 zeros is designated m100-0. The mean value of the average power consumption of the flip-flop when it was isolated from the test bench circuit during the total simulation period is designated mFFp. The mean value 57

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of the average power consumption of the test bench circuit when it was isolated from the flip-flop during the total simulation period is designated mtbP. Table 3.2: Power Consumption Measurements Power Consumption Measurement TGFF (uW) TGCGFF (uW) LPFF (uW) TGCGFF/TGFF (%) LPFF/TGFF (%) LPFF/TGCGFF (%) m1111 154.59 131.76 132.83 -14.77 -14.08 0.81 m0101 303.17 304.11 305.37 0.31 0.73 0.41 m1001 168.06 153.17 154.99 -8.86 -7.78 1.19 m0000 46.35 23.27 26.38 -49.80 -43.09 13.37 m20-1 57.04 27.43 27.20 -51.91 -52.33 -0.86 m50-1 42.41 11.68 11.29 -72.47 -73.37 -3.27 m100-1 37.53 6.40 5.99 -82.95 -84.05 -6.46 m20-0 35.34 5.22 5.09 -85.22 -85.60 -2.58 m50-0 33.71 2.69 2.34 -92.03 -93.05 -12.83 m100-0 33.16 1.84 1.40 -94.46 -95.77 -23.68 mFFp 45.18 15.15 14.89 -66.46 -67.03 -1.71 mtbP 106.46 106.90 108.94 0.41 2.32 1.91 The first three columns in Table 3.2 present values for the average power consumption of the three flip-flops under test. All average power consumption values are expressed in microwatts. The TGCGFF/TGFF column in Table 3.2 compares the average power consumption measurements of the TGCGFF to those of the TGFF. There is only one measurement, m0101, that shows and increment in the power consumption of the TGCGFF when compared with the power consumption of the TGFF. The increase was a 58

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small one of 0.31%. This case happened when the input pattern was 0101, which is the maximum transition rate in the input. All the other comparisons exhibit decrements in the power consumption of the TGCGFF that vary from 8.86% when the input pattern was 1001 to 94.46% when the input pattern was 100 zeros. Of particular interest is the situation where the input pattern is comprised of either all zeros or all ones. In such a situation, as the pattern length increased, the power consumption decreased in the TGCGFF faster than the decrease in power consumption of the TGFF. The decrement in the power consumption was more pronounced when the input pattern was all zeros than when the input pattern was all ones. The LPFF/TGFF column in Table 3.2 compares the average power consumption measurements of the LPFF to those of the TGFF. The data in this column displays the effect of the introduction of the clock gating circuit on power consumption. There is only one measurement, m0101, where the LPFF shows an increase in power consumption when compared to the TGFF. The LPFF exhibited the same behavior as the TGCGFF when compared to the TGFF. When there was no data transition and the pattern length increased, the power consumption decreased faster in the LPFF than the decrease in power consumption of the TGFF. Additionally, the diminution in the power consumption was more pronounced when the input pattern was all zeros than when the input pattern was all ones. The LPFF/TGCGFF column in Table 3.2 compares the average power consumption measurements of the LPFF to those of the TGCGFF. This column displays the effect of the introduction of the body-bias circuit on power consumption. With short and fast-varying input patterns such as 1111, 0101, 1001 and 0000 the LPFF consumed 59

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more average power than the TGCGFF. The increase in power consumption for the first three patterns was less than 1.2%, which is very small. The difference in power consumption between the LPFF and the TGCGFF was appreciable only for the 0000 input pattern, which yielded an increment of 13.37 %. With long slow-varying input patterns such as 20 ones, 50 ones, 100 ones, 20 zeros, 50 zeros and 100 zeros the LPFF consumed less average power than the TGCGFF. As the input pattern length increased the LPFF power savings increased when compared to the TGCGFF, especially when the input pattern was all zeros. With the input pattern was comprised of 20 zeros the LPFF consumed 2.58% less average power than the TGCGFF. With the input pattern was comprised of 50 zeros the LPFF saved 12.83% more average power than the TGCGFF. Remarkably, when the input pattern was comprised of 100 zeros the LPFF consumed 23.68% less average power than the TGCGFF. Table 3.3 presents the effect of the introduction of clock-gating and adaptive body-bias on transistor area. Table 3.3: Total Transistor Area and Area Overhead Cell TGFF () 2m TGCGFF () 2m LPFF () 2m TGCGFF/TGFF (%) LPFF/TGFF (%) LPFF/TGCGFF (%) 1 10.9 11.8 13.8 8.3 27.1 17.3 2 14.1 16.9 18.9 20.2 34.7 12.1 3 18.5 20.6 22.7 11.7 22.7 9.9 4 25.9 28.0 30.1 8.3 16.2 7.3 5 29.3 31.6 33.7 8.1 15.1 6.4 60

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The first three columns in Table 3.3 give the total transistor area, expressed in square microns, for each cell of the three flip-flops. The last three columns in Table 3.3 compare the total transistor area of the flip-flops and express the area overhead as a percentage. The column labeled TGCGFF/TGFF shows that the area overhead, due to the introduction of the clock-gating circuit, in the TGCGFF varied between 8.1% and 20.2%. The column labeled LPFF/TGFF shows that when the adaptive-body-bias circuit was introduced in the LPFF the additional area overhead varied between 6.4% and 17.3%. The overhead percentage tended to decrease as the size of the cell increased. Figures 3.1 to 3.16 present the simulation results in detail. In these figures the value of the dependent variable, which is either time delay or average power consumption, is the mean of the corresponding values obtained for the three Power Supply values of 1.68V, 1.8V, and 1.98V, which were analyzed in the simulations. 61

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Figure 3.1 presents the Clock-to-Q delay with the D input rising, (cqR). The TGFF exhibited the smallest delay and the LPFF exhibited the longest delay. The cqR delay increased, on average, by 5.24% for the TGCGFF and by 18.09% for the LPFF when compared to the cqR delay of the TGFF. See Table 3.1. Figure 3.1: Clock-to-Q delay with the D Input Rising, (cqR) Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 62

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Figure 3.2 presents the Clock-to-Q delay with the D input falling, (cqF). The TGCGFF exhibited the smallest delay and the LPFF exhibited the longest delay. The cqF delay decreased, on average, by 4.2% for the TGCGFF and increased by 4.61% for LPFF when compared to the cqF delay of the TGFF. See Table 3.1. Figure 3.2: Clock-to-Q Delay with the D Input Falling, (cqF) Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 63

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Figure 3.3 presents D-to-Q delay with the D input rising, (dqR). The TGFF exhibited the smallest delay and the LPFF exhibited the longest delay. The dqR delay increased, on average, by 52.08% for the TGCGFF and by 68.74% for the LPFF when compared to the TGFF dqR delay. See Table 3.1. These increments are due mostly to the longer setup time required by the TGCGFF and the LPFF. Figure 3.3: D-to-Q Delay with the D Input Rising, (dqR) Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 64

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Figure 3.4 presents the D-to-Q delay with the D input falling, (dqF). The TGFF exhibited the smallest delay and the LPFF exhibited the longest delay. The dqF delay increased, on average, by 46.81% for the TGCGFF and by 60.25% for the LPFF when compared to the dqR delay of the TGFF. See Table 3.1. These increments are due mostly to the longer setup time required by the TGCGFF and the LPFF. Figure 3.4: D-to-Q Delay with the D Input Falling, (dqF) Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 65

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Figure 3.5 presents the power consumption with 1111 as the input pattern. Power consumption decreased, on average, by 14.77% for the TGCGFF and by 14.08% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.5: Power Consumption with 1111 as Input Pattern Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 66

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Figure 3.6 presents the power consumption with 0101 as input pattern. The input transition rate is the highest for this input pattern. Power consumption increased, on average, by 0.31% for the TGCGFF and by 0.73% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Remarkably, these are modest increments. Figure 3.6: Power Consumption with 0101 as Input Pattern Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 67

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Figure 3.7 presents the power consumption with 1001 as the input pattern. Power consumption decreased, on average, by 8.86% for the TGCGFF and by 7.78% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.7: Power Consumption with 1001 as Input Pattern Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 68

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Figure 3.8 presents the power consumption when the input pattern was comprised of 0000. Power consumption decreased, on average, by 49.08% for the TGCGFF and by 43.09% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.8: Power Consumption with 0000 as the Input Pattern Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 69

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Figure 3.9 presents the power consumption when the input pattern is 20 ones. In average, power consumption decreases 51.91% for TGCGFF and 52.33% for LPFF in comparison to TGFF power consumption. See Table 3.2. Notice that for this and for the next input patterns LPFF consumes less power than TGCGFF. Figure 3.9: Power Consumption with the Input Pattern Comprised of 20 Ones Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 70

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Figure 3.10 presents the power consumption when the input pattern was comprised of 50 ones. Power consumption decreased, on average, by 72.47% for the TGCGFF and by 73.37% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.10: Power Consumption with the Input Pattern Comprised of 50 Ones Temperature is expressed in degrees Celsius. The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 71

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Figure 3.11 presents the power consumption with the input pattern comprised of 100 ones. Power consumption decreased, on average, by 82.95% for the TGCGFF and by 84.05% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.11: Power Consumption with the Input Pattern Comprised of 100 Ones Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 72

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Figures 3.9 to 3.11 demonstrate conclusively that as the length of the input pattern, comprised of all ones, increases the average consumed power for both the TGCGFF and the LPFF decreases. Figure 3.12 presents the power consumption when the input pattern was comprised of 20 zeros. Power consumption decreased, on average, by 85.22% for the TGCGFF and by 85.60% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.12: Power Consumption with the Input Pattern Comprised of 20 Zeros Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 73

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Figure 3.13 presents the power consumption when the input pattern was comprised of 50 zeros. Power consumption decreased, on average, by 92.03% for the TGCGFF and by 93.05% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.13: Power Consumption with the Input Pattern comprised of 50 Zeros Temperature is expressed in degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 74

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Figure 3.14 presents the power consumption with the input pattern comprised of 100 zeros. Power consumption decreased, on average, by 94.46% for the TGCGFF and by 95.77% for the LPFF when compared to the power consumption of the TGFF. See Table 3.2. Figure 3.14: Power Consumption with the Input Pattern Comprised of 100 Zeros Temperature is expressed in Celsius degrees The Fanout Unit was a Basic Inverter with WN=4 and WP=8 It can be deduced from Figures 3.12 to 3.14 that as the length of the input pattern, of all zeros, increases the average consumed power decreases for both the TGCGFF and 75

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the LPFF. These decrements in the average consumed power are stronger when the input pattern is formed with all zeros than when the input pattern contains all ones. Figure 3.15 presents the power consumed by the FFs during the total simulation period. The decrease in the power consumed by the TGCGFF was 66.46% and the LPFF realized a 67.03% reduction in consumed power. Figure 3.15: Power Consumed by the FFs During the Total Simulation Period, (FFp) Temperature is expressed in Celsius degrees The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 76

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Figure 3.16 presents the power consumed by the Test Bench circuit during the total simulation period. As expected, this measurement produced similar results for the three flip-flops that were simulated. Figure 3.16 Power Consumed by the Test Bench Circuit During the Total Simulation Period, (tbP). Temperature is expressed in Degrees Celsius The Fanout Unit was a Basic Inverter with WN = 4 and WP = 8 77

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CHAPTER 4 CONCLUSIONS Simulations showed that the new LPFF flip-flop is appropriate for applications that require low switching activity. In low switching activity cases the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increased as the length of the period with no switching activity increased such as the condition when the input data was all ones or all zeros. The LPFF required a longer setup time, which increased the D-to-Q delays but had better internal race immunity than the TGFF and the TGCGFF. The comparison of the LPFF with the TGCGFF indicated that the introduction of Adaptive Body Bias in the LPFF can provide significant additional power savings when the input switching activity is low. The trade-off was an increase in the D-to-Q delays and in the flip-flop area. The LPFF exhibited D-to-Q delays of 60% to 69% longer than the delays for the TGFFF and 9% to 11% longer than the delays for the TGCGFF. LPFF cells have an area that ranges from 15% to 34% larger than TGFFF cells and 6% to 17% larger than TGCGFF cells. The Logical Effort Method proved to be an effective and fast way of obtaining a good approximation to the appropriate transistor sizes. The sizes obtained by the application of the Logical Effort Method to the designs were close enough to the 78

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appropriate transistor sizes that only few steps of additional fine tunning were required in most cases to obtain the optimum transistor sizes for the different cells of the flip-flops. The programs written to serve as an interface between the Cadence transistor-level designs and the Hspice simulation program proved to be a great time-saving tool. Adapting the output of the Cadence transistor-level design programs to the Hspice simulator manually is a lengthy, time-consuming and error-prone task. The matlab visualization programs developed in this research allowed to see a clearer picture of the simulation results. The relationships between the fanout, the temperature, the flip-flop power consumption, and the flip-flop delays are seen more easily in the 3-D graphics generated by the visualization programs. 79

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REFERENCES [1] K. Bernstein, M. Carrig, C. Durham, P. Hansen, D. Hogenmiller, E. Nowak and N. Rohrer, High Speed CMOS Design Styles, Kluwer Academic, 1998 [2] A. Chandrakasan, W. Bowhill and F. Fox, Design of High-Performance Microprocessor Circuits, IEEE Press, 2001 [3] K. H. Cheng and Y. Lin, A Dual-Pulse-Clock Double Edge Triggered Flip-Flop for Low Voltage and High Speed Applications, International Symposium on Circuits and Systems, pp. 425 428, 2003 [4] T. Chen and S. Naffziger, Comparison of Adaptive Body Bias, (ABB), and Adaptive Supply Voltage, (ASV), for Improving Delay and Leakage under the Presence of Process Variation, IEEE Transactions on Very Large Scale Integration, (VLSI), Systems, vol. 11, pp. 888 899, Oct 2003 [5] T. Chen and J. Gregg, A Low Cost Individual-Well Adaptive Body Bias, (IWABB), Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations, Design, Automation and Test in Europe, pp. 240 245, 2004 [6] G. R. Cho and T. Chen, Comparative Assessment of Adaptive Body-Bias SOI Pass-transistor Logic, Fourth International Symposium on Quality Electronic Design, pp. 55 60, 2003 [7] H. Dao, K. Nowka and V. Oklobdzija, Analysis of Clocked Timing Elements for Dynamic Voltage Scaling Effects over Process Parameter Variation, International Symposium on Low Power Electronics and Design, pp. 56 59, 2001 [8] H. Dao and V. Oklobdzija, Application of Logical Effort on Delay Analysis of 64-Bit Static Carry-Lookahead Adder, Asilomar Conference on Signals, Systems and Computers, pp. 1322 1324, 2001 [9] H. Dao and V. Oklobdzija, Application of Logical Effort Techniques for Speed Optimization and Analysis of Representative Adders, Asilomar Conference on Signals, Systems and Computers, pp. 1666 1669, 2001 80

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[10] P. Gray, P. Hurst, S. Lewis and R. Meyer, Analysis and Design of Analog Integrated Circuits, Wiley, 4th edition, 2001 [11] J. Gregg and T. Chen, Post Silicon Power/Performance Optimization in the Presence of Process Variations using Individual Well Adaptive Body Biasing, (IWABB), International Symposium on Quality Electronic Design, pp. 453 458, 2004 [12] M. Hamada, T. Terazawa, T. Higashi, S. Kitabayashi, S. Mita, Y. Watanabe, M. Ashino, H. Hara, and T. Kuroda, Flip-flop Selection Technique for Power-Delay Trade-Off, (Video Codec), Solid-State Circuits Conference, pp. 270 271, 1999 [13] F. Klass, C. Amir, A. Das, K. Aingaran, C. Truong, R. Wang, A. Mehta, R. Heald and G. Yee, A New Family of Semidynamic and Dynamic Flip-Flops with Embedded Logic for High-Performance Processors, IEEE Journal of Solid State Circuits, vol. 34, no. 5, pp. 712 716, 1999 [14] B. Kong, S. Kim and Y. Jun, Conditional Capture Flip-Flop for Statistical Power Reduction, ISSCC Dig. Tech. Papers, pp. 290 291, 2000 [15] W. Liu, MOSFET Models for Spice Simulation, Including BSIM3v3 and BSIM4, Wiley, 2001 [16] D. Markovic, B. Nikolic and R. Brodersen, Analysis and Design of Low-Energy Flip-Flops, in International Symposium on Low Power Electronics and Design, pp. 52 55, 2001 [17] D. Markovic, Analysis and Design of Low-Energy Clocked Storage Elements, Masters Thesis, University of California at Berkeley, 2001 [18] S. Naffziger, G. Colon-Bonet, T. Fischer, R. Riedlinger, T. Sullivan and T.Grutkowski, The Implementation of the Itanium-2-Microprocessor, IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1448 1460, 2002 [19] B. Nikolic, V. Oklobdzija, V. Stojanovic, W. Jia, J. Chiu and M. Leung, Improved Sense-Amplifier-Based Flip-Flop: Design and measurements, IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 876 884, 2000 [20] B. Nikolic and V. Oklobdzija, Low Voltage BiCMOS TSPC Latch for High Performance Digital Systems, IEEE International Symposium on Circuits and Systems, pp. 53 56, 1998 [21] B. Nikolic, V. Stojanovic, V. Oklobdzija, W. Jia, J. Chiu, and M. Leung, Sense Amplifier-Based Flip-Flop, IEEE International Solid-State Circuits Conference, pp. 282 283, 1999 81

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[22] M. Nogawa and Y. Ohtomo, A Data-Transition Look-Ahead DFF Circuit for Statistical Reduction in Power Consumption, IEEE Journal of Solid-State Circuits, vol. 33, pp. 702 706, May 1998 [23] V. Oklobdzija, V. Stojanovic, N. Markovic and D. Nedovic, Digital System Clocking; High-Performance and Low-Power Aspects, Wiley, 2003 [24] H. Partovi, Flow-Through Latch and Edge-Triggered Flip-Flop Hybrid Elements, ISCC Dig. Tech. Papers, pp. 138 139, 1996 [25] B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2001 [26] K. Roy, S. Mukhopadhyay and H. Mahmoodi-Meimand, Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits, Proc. of the IEEE, vol. 91, pp. 305 327, Jan 2003 [27] V. Stojanovic, V. Oklobdzija and R. Bajwa, A Unified Approach in the Analysis of Latches and Flip-Flops for Low-Power Systems, International Symposium on Low Power Electronics and Design, pp. 227 232, 1998 [28] V. Stojanovic, V. Oklobdzija and R. Bajwa, Comparative Analysis of Latches and Flip-Flops for High-Performance Systems, International Conference on Computer Design: VLSI in Computers and Processors, pp. 264 269, 1998 [29] V. Stojanovic and V. Oklobdzija, Comparative Analysis of Master-Slave Latches and Flip-Flops for High-Performance and Low-Power Systems, IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 536 548, 1999 [30] I. Sutherland, B. Sproull and D. Harris, Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann, 1999 [31] J. Uyemura, CMOS Logic Circuit Design, Kluwer Academic, 1999 [32] N. Weste and D. Harris, CMOS VLSI Design: A Circuit and Systems Perspective, Addison-Wesley, 3rd edition, 2005 [33] L. Yan, J. Luo and N. Jha, Combined Dynamic Voltage Scaling and Adaptive Body-Biasing for Heterogeneous Distributed Real-Time Embedded Systems, International Conference on Computer Aided Design, pp. 30 37, 2003 [34] X. Y. Yu, V. Oklobdzija and W. Walker, Application of Logical Effort to the Design of Arithmetic Blocks, Asilomar Conference on Signals, Systems and Computers, pp. 872 874, 2001 82

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APPENDICES 83

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Appendix A Simulation Results The actual results obtained from the Hspice simulations are presented in this Appendix. The results are separated by flip-flop type and cells. The names of the cells follow this pattern of (letters number letters). The initial group of letters in the name corresponds to the type of flip-flop. The low-power flip-flop is represented by, (lp), the transmission-gate flip-flop is represented by, (tg), and transmission-gate with clock-gating flip-flop is represented by, (tgcg). The number in the middle of the name is the cell number. The last group of letters in the name is always ff, which stands for flip-flop. For example, lp3ff is a low-power flip-flop of size 3 and tgcg2ff is a transmission-gate flip-flop of size 2 with clock-gating. The Lambda parameter was always 0.09 m since the spice transistor models were for TMSC 0.18-micron technology. The Clock cycle was kept constant for all the simulations at 2 nanoseconds, which corresponds to a frequency of 500 MHz. The MinFO represents the minimum Fanout for the cell. The Setup time represents the D-clock delay and is expressed in picoseconds. The model file, t18h.lib, was the same for all simulations and was obtained from MOSIS. The different columns are explained in the following paragraphs: The Temp column presents the temperature expressed, which is in Celsius degrees. The Vdd column displays the actual supply voltage, which could be 1.62, 1.8 or 1.98 Volts. These voltage values correspond to 90%, 100% and 110% of the nominal voltage, which was 1.8V. 84

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Appendix A (Continued) The FO column presents the fan-out expressed in basic inverter units. The next 6 columns present delay measurements. All delays are expressed in picoseconds. The cqR column presents the clock-Q delay with D rising. The cqF column presents the clock-Q delay with D falling. The dRc column presents the D-clock delay with D rising. The dFc column presents the D-clock delay with D falling. The dRc and dFc were extracted from the simulations and were equal to the setup delay. The remaining columns represent the average power consumption measurements. All the power consumption measurements are expressed in microwatts. The 1111 column presents the power dissipated when the input pattern was 1111. The 0101 column presents the power dissipated when the input pattern was 0101. The 20_1 column presents the power dissipated when the input pattern was 20 ones. The 100_0 column presents the power consumption when the input pattern was 100 zeros. The FFp column presents the average power consumed by the flip-flop circuit, during the total simulation time, without including the power consumed by the test bench circuit. The tbP column presents the average power consumed by the test bench circuit, without including the power consumed by the flip-flop circuit. 85

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Appendix A (Continued) lp1ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 2 Setup: 400p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 2 375.2 302.2 400 400 775.2 702.2 15.7 51.7 26.4 0 1.62 4 410.3 328.9 400 400 810.3 728.9 19.8 60.0 30.5 0 1.62 6 448.3 355.0 400 400 848.3 755.0 23.9 68.3 34.7 0 1.62 8 484.6 379.1 400 400 884.6 779.1 28.0 76.7 38.8 0 1.62 10 522.8 402.7 400 400 922.8 802.7 32.2 85.0 43.0 0 1.80 2 315.9 258.3 400 400 715.9 658.3 20.1 65.9 33.6 0 1.80 4 347.4 284.0 400 400 747.4 684.0 25.2 76.2 38.8 0 1.80 6 381.2 307.9 400 400 781.2 707.9 30.3 86.3 43.8 0 1.80 8 412.8 331.0 400 400 812.8 731.0 35.4 96.6 48.9 0 1.80 10 446.2 353.9 400 400 846.2 753.9 40.6 107.0 54.1 0 1.98 2 274.8 227.4 400 400 674.8 627.4 25.2 81.9 42.0 0 1.98 4 302.7 251.7 400 400 702.7 651.7 31.4 94.4 48.2 0 1.98 6 333.7 274.3 400 400 733.7 674.3 37.6 106.9 54.3 0 1.98 8 361.8 297.0 400 400 761.8 697.0 43.8 119.2 60.5 0 1.98 10 392.6 318.6 400 400 792.6 718.6 50.1 131.8 66.8 25 1.62 2 409.0 327.7 400 400 809.0 727.7 15.6 51.7 26.3 25 1.62 4 451.5 357.5 400 400 851.5 757.5 19.7 60.0 30.4 25 1.62 6 491.6 383.6 400 400 891.6 783.6 23.9 68.3 34.6 25 1.62 8 532.4 409.7 400 400 932.4 809.7 28.0 76.6 38.8 25 1.62 10 575.0 434.7 400 400 975.0 834.7 32.2 84.9 42.9 25 1.80 2 344.7 281.0 400 400 744.7 681.0 19.8 65.5 33.3 25 1.80 4 381.1 308.4 400 400 781.1 708.4 24.9 75.8 38.5 25 1.80 6 414.7 333.3 400 400 814.7 733.3 30.0 86.2 43.6 25 1.80 8 450.3 357.3 400 400 850.3 757.3 35.2 96.6 48.9 25 1.80 10 486.8 382.0 400 400 886.8 782.0 40.3 106.9 54.0 25 1.98 2 296.0 246.7 400 400 696.0 646.7 25.0 81.6 41.6 25 1.98 4 329.1 272.8 400 400 729.1 672.8 31.1 93.8 47.7 25 1.98 6 359.5 298.3 400 400 759.5 698.3 37.3 106.5 54.0 25 1.98 8 393.3 321.6 400 400 793.3 721.6 43.6 119.0 60.2 25 1.98 10 425.0 345.5 400 400 825.0 745.5 49.9 131.5 66.5 50 1.62 2 449.7 362.9 400 400 849.7 762.9 15.5 51.6 26.2 50 1.62 4 492.9 393.6 400 400 892.9 793.6 19.6 60.0 30.4 50 1.62 6 537.5 422.5 400 400 937.5 822.5 23.8 68.4 34.6 50 1.62 8 583.0 450.4 400 400 983.0 850.4 28.0 76.7 38.8 50 1.62 10 629.1 476.6 400 400 1029.1 876.6 32.1 85.0 42.9 50 1.80 2 374.7 306.9 400 400 774.7 706.9 19.8 65.5 33.3 50 1.80 4 416.3 336.8 400 400 816.3 736.8 24.9 75.8 38.4 50 1.80 6 453.0 363.9 400 400 853.0 763.9 30.1 86.2 43.6 50 1.80 8 493.1 389.1 400 400 893.1 789.1 35.2 96.6 48.8 50 1.80 10 532.1 414.5 400 400 932.1 814.5 40.4 106.9 54.0 50 1.98 2 325.3 267.0 400 400 725.3 667.0 24.7 81.6 41.6 50 1.98 4 358.5 294.6 400 400 758.5 694.6 31.0 94.1 47.9 50 1.98 6 394.0 319.8 400 400 794.0 719.8 37.2 106.6 54.0 50 1.98 8 427.2 343.8 400 400 827.2 743.8 43.4 119.2 60.4 50 1.98 10 461.6 368.0 400 400 861.6 768.0 49.7 131.8 66.6 75 1.62 2 494.2 393.9 400 400 894.2 793.9 15.6 51.8 26.3 86

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Appendix A (Continued) 75 1.62 4 542.5 428.1 400 400 942.5 828.1 19.8 60.1 30.5 75 1.62 6 590.9 457.9 400 400 990.9 857.9 23.9 68.5 34.7 75 1.62 8 640.2 487.6 400 400 1040.2 887.6 28.1 76.8 38.8 75 1.62 10 690.7 515.7 400 400 1090.7 915.7 32.3 85.1 43.0 75 1.80 2 405.6 332.5 400 400 805.6 732.5 19.6 65.4 33.2 75 1.80 4 446.3 363.8 400 400 846.3 763.8 24.8 75.7 38.4 75 1.80 6 488.2 391.1 400 400 888.2 791.1 29.9 86.1 43.6 75 1.80 8 529.7 418.5 400 400 929.7 818.5 35.1 96.4 48.8 75 1.80 10 572.5 445.1 400 400 972.5 845.1 40.3 106.8 53.9 75 1.98 2 345.3 287.5 400 400 745.3 687.5 24.3 80.9 41.1 75 1.98 4 381.3 317.1 400 400 781.3 717.1 30.6 93.4 47.4 75 1.98 6 418.7 343.0 400 400 818.7 743.0 36.9 106.0 53.7 75 1.98 8 455.4 369.0 400 400 855.4 769.0 43.2 118.6 60.0 75 1.98 10 492.9 393.8 400 400 892.9 793.8 49.4 131.2 66.3 100 1.62 2 540.7 430.7 400 400 940.7 830.7 15.5 51.8 26.3 100 1.62 4 593.0 466.3 400 400 993.0 866.3 19.7 60.1 30.5 100 1.62 6 645.2 498.4 400 400 1045.2 898.4 23.8 68.5 34.7 100 1.62 8 698.7 529.6 400 400 1098.7 929.6 28.0 76.8 38.9 100 1.62 10 752.7 559.1 400 400 1152.7 959.1 32.2 85.0 43.0 100 1.80 2 434.1 358.6 400 400 834.1 758.6 19.5 65.2 33.1 100 1.80 4 478.6 392.0 400 400 878.6 792.0 24.8 75.7 38.3 100 1.80 6 521.8 421.8 400 400 921.8 821.8 29.9 86.1 43.5 100 1.80 8 567.6 450.0 400 400 967.6 850.0 35.1 96.4 48.7 100 1.80 10 614.2 478.7 400 400 1014.2 878.7 40.3 106.8 53.9 100 1.98 2 371.0 307.6 400 400 771.0 707.6 24.2 80.6 41.0 100 1.98 4 410.8 338.0 400 400 810.8 738.0 30.5 93.2 47.3 100 1.98 6 448.4 365.9 400 400 848.4 765.9 36.8 105.8 53.5 100 1.98 8 486.9 392.3 400 400 886.9 792.3 43.1 118.3 59.8 100 1.98 10 527.7 419.4 400 400 927.7 819.4 49.4 131.0 66.2 125 1.62 2 584.4 473.2 400 400 984.4 873.2 15.5 51.6 26.2 125 1.62 4 640.9 511.1 400 400 1040.9 911.1 19.7 60.1 30.4 125 1.62 6 697.0 544.8 400 400 1097.0 944.8 23.9 68.5 34.6 125 1.62 8 754.3 577.8 400 400 1154.3 977.8 28.1 76.7 38.8 125 1.62 10 813.9 608.9 400 400 1213.9 1008.9 32.3 84.7 43.0 125 1.80 2 475.3 385.6 400 400 875.3 785.6 19.6 65.1 33.1 125 1.80 4 523.1 421.2 400 400 923.1 821.2 24.8 75.6 38.3 125 1.80 6 569.7 452.1 400 400 969.7 852.1 30.0 86.0 43.5 125 1.80 8 622.7 482.7 400 400 1022.7 882.7 35.2 96.6 48.8 125 1.80 10 672.3 511.3 400 400 1072.3 911.3 40.4 106.9 54.0 125 1.98 2 393.4 328.9 400 400 793.4 728.9 24.2 80.5 40.9 125 1.98 4 435.7 360.3 400 400 835.7 760.3 30.4 93.2 47.2 125 1.98 6 475.4 390.0 400 400 875.4 790.0 36.7 105.7 53.5 125 1.98 8 517.3 418.0 400 400 917.3 818.0 43.0 118.4 59.8 125 1.98 10 560.6 445.7 400 400 960.6 845.7 49.3 131.0 66.1 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 2 11.4 3.5 1.6 1.0 2.6 1.2 0.8 2.8 3.0 0 1.62 4 11.5 4.4 2.0 1.2 2.6 1.3 0.8 3.1 6.3 0 1.62 6 11.4 5.2 2.3 1.3 2.6 1.2 0.8 3.5 9.6 0 1.62 8 11.5 6.0 2.6 1.5 2.6 1.3 0.8 3.9 13.1 0 1.62 10 11.5 6.8 3.0 1.7 2.6 1.2 0.8 4.3 17.1 0 1.80 2 14.6 4.6 2.2 1.4 3.4 1.7 1.1 3.6 4.0 0 1.80 4 14.6 5.6 2.6 1.6 3.4 1.7 1.1 4.1 8.2 87

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Appendix A (Continued) 0 1.80 6 14.6 6.6 3.0 1.7 3.3 1.6 1.0 4.5 13.1 0 1.80 8 14.5 7.6 3.4 1.9 3.3 1.6 1.0 5.0 18.4 0 1.80 10 14.6 8.7 3.8 2.1 3.3 1.6 1.0 5.5 24.6 0 1.98 2 18.3 5.9 2.9 1.9 4.4 2.3 1.6 4.7 5.2 0 1.98 4 18.3 7.2 3.4 2.2 4.4 2.3 1.6 5.3 11.0 0 1.98 6 18.2 8.3 3.9 2.4 4.3 2.2 1.5 5.8 17.2 0 1.98 8 18.2 9.6 4.4 2.6 4.4 2.3 1.5 6.4 24.3 0 1.98 10 18.3 10.9 4.9 2.9 4.4 2.2 1.5 7.0 32.9 25 1.62 2 11.4 3.5 1.6 1.0 2.6 1.2 0.8 2.7 2.9 25 1.62 4 11.3 4.3 1.9 1.1 2.6 1.2 0.8 3.1 6.1 25 1.62 6 11.4 5.1 2.3 1.3 2.6 1.2 0.8 3.5 9.6 25 1.62 8 11.4 6.0 2.6 1.4 2.6 1.2 0.8 3.9 13.0 25 1.62 10 11.4 6.8 3.0 1.6 2.6 1.2 0.8 4.3 16.9 25 1.80 2 14.4 4.5 2.1 1.2 3.3 1.6 1.0 3.5 4.0 25 1.80 4 14.5 5.5 2.5 1.4 3.3 1.6 1.0 4.0 8.4 25 1.80 6 14.5 6.5 2.9 1.6 3.3 1.6 1.0 4.4 13.2 25 1.80 8 14.5 7.5 3.3 1.8 3.3 1.6 1.0 4.9 18.0 25 1.80 10 14.5 8.6 3.7 2.1 3.3 1.6 1.0 5.4 23.5 25 1.98 2 17.9 5.7 2.8 1.7 4.2 2.0 1.3 4.5 5.0 25 1.98 4 18.0 6.9 3.2 2.0 4.2 2.0 1.3 5.0 11.1 25 1.98 6 18.0 8.2 3.7 2.2 4.2 2.0 1.3 5.6 17.1 25 1.98 8 17.9 9.4 4.2 2.4 4.1 2.0 1.2 6.1 24.0 25 1.98 10 18.0 10.7 4.8 2.7 4.2 2.0 1.3 6.8 31.7 50 1.62 2 11.3 3.4 1.6 0.9 2.6 1.2 0.7 2.7 2.9 50 1.62 4 11.4 4.3 1.9 1.1 2.6 1.2 0.7 3.1 6.1 50 1.62 6 11.4 5.1 2.2 1.2 2.6 1.2 0.7 3.5 9.6 50 1.62 8 11.4 5.9 2.6 1.4 2.6 1.2 0.7 3.9 13.1 50 1.62 10 11.4 6.8 2.9 1.6 2.6 1.2 0.7 4.3 16.9 50 1.80 2 14.4 4.4 2.0 1.2 3.2 1.5 0.9 3.4 4.0 50 1.80 4 14.4 5.4 2.4 1.4 3.2 1.5 0.9 3.9 8.1 50 1.80 6 14.4 6.5 2.8 1.6 3.2 1.5 0.9 4.4 12.8 50 1.80 8 14.5 7.5 3.3 1.8 3.2 1.5 0.9 4.9 17.9 50 1.80 10 14.4 8.5 3.7 2.0 3.3 1.5 0.9 5.4 23.2 50 1.98 2 18.0 5.6 2.6 1.5 4.1 1.9 1.2 4.3 5.0 50 1.98 4 18.0 6.8 3.1 1.8 4.1 1.9 1.2 4.9 10.6 50 1.98 6 17.9 8.0 3.6 2.0 4.1 1.9 1.2 5.5 16.8 50 1.98 8 18.0 9.3 4.1 2.3 4.1 1.9 1.2 6.1 23.6 50 1.98 10 18.0 10.6 4.6 2.6 4.1 1.9 1.2 6.7 31.0 75 1.62 2 11.3 3.4 1.6 0.9 2.6 1.2 0.7 2.7 2.9 75 1.62 4 11.3 4.3 1.9 1.1 2.6 1.2 0.7 3.1 6.1 75 1.62 6 11.3 5.1 2.2 1.3 2.6 1.2 0.7 3.5 9.5 75 1.62 8 11.3 6.0 2.6 1.4 2.6 1.2 0.7 3.9 13.0 75 1.62 10 11.4 6.8 3.0 1.6 2.6 1.2 0.7 4.3 16.9 75 1.80 2 14.3 4.4 2.0 1.2 3.2 1.5 0.9 3.4 3.9 75 1.80 4 14.3 5.4 2.4 1.4 3.2 1.5 0.9 3.9 8.3 75 1.80 6 14.3 6.4 2.8 1.6 3.2 1.5 0.9 4.4 12.9 75 1.80 8 14.3 7.5 3.2 1.8 3.2 1.5 0.9 4.9 17.4 75 1.80 10 14.3 8.5 3.7 2.0 3.2 1.5 0.9 5.4 22.7 75 1.98 2 17.7 5.5 2.5 1.5 4.0 1.9 1.1 4.2 5.1 75 1.98 4 17.8 6.7 3.0 1.7 4.0 1.9 1.2 4.8 10.5 75 1.98 6 17.8 7.9 3.5 2.0 4.0 1.9 1.1 5.4 16.5 75 1.98 8 17.9 9.2 4.0 2.3 4.0 1.9 1.1 6.0 23.0 75 1.98 10 17.8 10.5 4.5 2.5 4.0 1.9 1.1 6.6 31.0 100 1.62 2 11.2 3.4 1.5 0.9 2.6 1.2 0.7 2.7 2.9 88

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Appendix A (Continued) 100 1.62 4 11.3 4.2 1.9 1.1 2.6 1.2 0.7 3.1 6.1 100 1.62 6 11.3 5.1 2.2 1.2 2.6 1.2 0.7 3.5 9.4 100 1.62 8 11.3 5.9 2.6 1.4 2.6 1.2 0.7 3.9 12.9 100 1.62 10 11.5 6.8 3.0 1.7 2.6 1.2 0.7 4.3 16.6 100 1.80 2 14.3 4.3 1.9 1.1 3.2 1.5 0.9 3.4 3.9 100 1.80 4 14.3 5.3 2.4 1.4 3.2 1.5 0.9 3.9 8.0 100 1.80 6 14.3 6.4 2.8 1.5 3.2 1.5 0.9 4.4 12.6 100 1.80 8 14.3 7.4 3.2 1.8 3.2 1.5 0.9 4.9 17.3 100 1.80 10 14.4 8.5 3.7 2.0 3.2 1.5 0.9 5.4 22.6 100 1.98 2 17.6 5.4 2.4 1.4 4.0 1.9 1.1 4.2 4.9 100 1.98 4 17.6 6.6 2.9 1.7 4.0 1.9 1.1 4.8 10.4 100 1.98 6 17.6 7.9 3.4 1.9 4.0 1.9 1.1 5.4 16.1 100 1.98 8 17.6 9.1 4.0 2.2 4.0 1.9 1.1 6.0 22.9 100 1.98 10 17.6 10.4 4.5 2.5 4.0 1.9 1.1 6.6 30.5 125 1.62 2 11.2 3.4 1.5 0.9 2.5 1.2 0.7 2.7 3.0 125 1.62 4 11.2 4.2 1.8 1.0 2.5 1.2 0.7 3.0 6.2 125 1.62 6 11.3 5.1 2.2 1.2 2.5 1.2 0.7 3.4 9.4 125 1.62 8 11.3 5.9 2.5 1.4 2.5 1.2 0.7 3.8 12.9 125 1.62 10 11.8 6.7 2.9 1.6 2.5 1.2 0.7 4.2 16.5 125 1.80 2 14.2 4.3 1.9 1.1 3.2 1.5 0.9 3.4 3.8 125 1.80 4 14.2 5.3 2.3 1.3 3.2 1.5 0.9 3.9 7.9 125 1.80 6 14.2 6.4 2.8 1.6 3.2 1.5 0.9 4.4 12.5 125 1.80 8 14.2 7.5 3.2 1.8 3.2 1.5 0.9 4.9 17.3 125 1.80 10 14.3 8.5 3.7 2.1 3.2 1.5 0.9 5.4 22.5 125 1.98 2 17.6 5.3 2.4 1.4 4.0 1.8 1.1 4.2 4.9 125 1.98 4 17.6 6.6 2.9 1.7 4.0 1.8 1.1 4.8 10.3 125 1.98 6 17.6 7.8 3.4 1.9 4.0 1.8 1.1 5.4 16.1 125 1.98 8 17.6 9.1 3.9 2.2 4.0 1.8 1.1 5.9 22.7 125 1.98 10 17.6 10.4 4.5 2.5 4.0 1.8 1.1 6.5 29.6 Run completed Mon May 23 6:15:41 US/Eastern 2005 in 2987 seconds. lp2ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 13 Setup: 400p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 13 504.8 405.8 400 400 904.8 805.8 42.0 111.5 56.2 0 1.62 16 530.5 423.6 400 400 930.5 823.6 48.2 123.9 62.3 0 1.62 19 558.1 441.9 400 400 958.1 841.9 54.4 136.3 68.5 0 1.62 22 584.4 459.8 400 400 984.4 859.8 60.6 148.7 74.8 0 1.62 25 611.4 476.9 400 400 1011.4 876.9 66.8 161.1 81.0 0 1.80 13 433.1 355.9 400 400 833.1 755.9 52.5 139.7 70.4 0 1.80 16 454.9 372.6 400 400 854.9 772.6 60.2 155.2 78.2 0 1.80 19 478.7 390.4 400 400 878.7 790.4 67.9 170.6 85.8 0 1.80 22 503.0 407.3 400 400 903.0 807.3 75.6 186.4 93.7 0 1.80 25 526.8 423.4 400 400 926.8 823.4 83.3 201.7 101.4 0 1.98 13 388.7 321.8 400 400 788.7 721.8 65.0 173.5 87.4 0 1.98 16 408.8 338.1 400 400 808.8 738.1 74.1 192.1 96.7 0 1.98 19 430.0 355.3 400 400 830.0 755.3 83.9 211.2 106.3 0 1.98 22 451.9 371.2 400 400 851.9 771.2 93.2 230.1 115.7 0 1.98 25 473.4 386.6 400 400 873.4 786.6 102.5 248.8 125.1 25 1.62 13 551.5 445.7 400 400 951.5 845.7 41.8 111.2 56.0 89

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Appendix A (Continued) 25 1.62 16 581.4 465.2 400 400 981.4 865.2 48.0 123.8 62.3 25 1.62 19 609.7 483.6 400 400 1009.7 883.6 54.3 136.3 68.5 25 1.62 22 640.5 502.3 400 400 1040.5 902.3 60.5 148.7 74.7 25 1.62 25 671.0 521.8 400 400 1071.0 921.8 66.7 161.1 81.0 25 1.80 13 474.4 386.9 400 400 874.4 786.9 52.5 140.6 70.8 25 1.80 16 498.5 405.6 400 400 898.5 805.6 60.3 155.9 78.5 25 1.80 19 525.0 423.3 400 400 925.0 823.3 68.0 171.5 86.3 25 1.80 22 550.4 440.3 400 400 950.4 840.3 75.8 186.9 94.0 25 1.80 25 578.0 458.7 400 400 978.0 858.7 83.5 202.4 101.7 25 1.98 13 417.4 347.6 400 400 817.4 747.6 64.7 172.7 86.9 25 1.98 16 440.1 364.6 400 400 840.1 764.6 74.1 191.4 96.3 25 1.98 19 463.5 382.4 400 400 863.5 782.4 83.4 210.4 105.8 25 1.98 22 485.6 399.3 400 400 885.6 799.3 92.8 229.1 115.2 25 1.98 25 509.3 415.6 400 400 909.3 815.6 102.2 247.9 124.6 50 1.62 13 608.2 483.3 400 400 1008.2 883.3 41.8 111.4 56.1 50 1.62 16 639.6 503.6 400 400 1039.6 903.6 48.1 123.9 62.4 50 1.62 19 672.9 524.4 400 400 1072.9 924.4 54.3 136.4 68.6 50 1.62 22 705.2 544.2 400 400 1105.2 944.2 60.5 148.7 74.8 50 1.62 25 738.1 565.2 400 400 1138.1 965.2 66.9 160.9 81.1 50 1.80 13 510.3 418.9 400 400 910.3 818.9 52.5 140.0 70.5 50 1.80 16 538.5 438.2 400 400 938.5 838.2 60.2 155.5 78.3 50 1.80 19 566.1 457.6 400 400 966.1 857.6 68.0 171.1 86.1 50 1.80 22 593.3 475.5 400 400 993.3 875.5 75.8 186.6 93.9 50 1.80 25 623.0 494.2 400 400 1023.0 894.2 83.5 201.9 101.6 50 1.98 13 445.4 373.7 400 400 845.4 773.7 64.6 172.5 86.9 50 1.98 16 470.5 391.8 400 400 870.5 791.8 74.1 191.4 96.3 50 1.98 19 495.4 410.4 400 400 895.4 810.4 83.4 210.5 105.9 50 1.98 22 520.2 427.6 400 400 920.2 827.6 92.9 229.3 115.3 50 1.98 25 546.0 445.0 400 400 946.0 845.0 102.3 248.1 124.7 75 1.62 13 662.9 528.7 400 400 1062.9 928.7 42.1 111.5 56.2 75 1.62 16 697.0 547.9 400 400 1097.0 947.9 48.3 124.0 62.5 75 1.62 19 733.7 569.2 400 400 1133.7 969.2 54.6 136.4 68.7 75 1.62 22 769.3 590.9 400 400 1169.3 990.9 60.9 148.6 75.0 75 1.62 25 804.8 611.5 400 400 1204.8 1011.5 67.1 160.4 81.2 75 1.80 13 552.5 454.1 400 400 952.5 854.1 52.4 140.0 70.6 75 1.80 16 582.0 474.1 400 400 982.0 874.1 60.1 155.6 78.3 75 1.80 19 612.5 494.5 400 400 1012.5 894.5 67.9 171.1 86.1 75 1.80 22 643.9 514.2 400 400 1043.9 914.2 75.7 186.5 93.9 75 1.80 25 674.8 533.0 400 400 1074.8 933.0 83.4 201.9 101.7 75 1.98 13 478.4 400.8 400 400 878.4 800.8 64.4 171.9 86.5 75 1.98 16 505.2 419.9 400 400 905.2 819.9 74.0 191.0 96.1 75 1.98 19 532.3 439.1 400 400 932.3 839.1 83.4 209.8 105.5 75 1.98 22 559.1 457.1 400 400 959.1 857.1 92.9 228.7 115.0 75 1.98 25 587.2 475.6 400 400 987.2 875.6 102.4 247.7 124.5 100 1.62 13 724.4 574.6 400 400 1124.4 974.6 42.2 111.7 56.2 100 1.62 16 761.4 597.6 400 400 1161.4 997.6 48.4 124.1 62.5 100 1.62 19 799.9 620.6 400 400 1199.9 1020.6 54.7 136.4 68.8 100 1.62 22 838.7 642.3 400 400 1238.7 1042.3 61.1 148.2 75.2 100 1.62 25 878.4 664.4 400 400 1278.4 1064.4 67.2 159.3 81.4 100 1.80 13 598.8 487.1 400 400 998.8 887.1 52.6 140.3 70.7 100 1.80 16 631.4 508.0 400 400 1031.4 908.0 60.3 155.8 78.5 100 1.80 19 663.8 529.0 400 400 1063.8 929.0 68.2 171.3 86.2 100 1.80 22 697.0 550.0 400 400 1097.0 950.0 76.0 186.7 94.0 100 1.80 25 730.9 569.9 400 400 1130.9 969.9 83.8 201.9 101.9 90

PAGE 101

Appendix A (Continued) 100 1.98 13 518.3 431.0 400 400 918.3 831.0 64.5 172.5 86.8 100 1.98 16 547.0 451.4 400 400 947.0 851.4 74.1 191.5 96.3 100 1.98 19 574.9 470.7 400 400 974.9 870.7 83.7 210.3 105.8 100 1.98 22 603.5 489.5 400 400 1003.5 889.5 93.0 229.2 115.2 100 1.98 25 633.4 509.4 400 400 1033.4 909.4 102.4 248.0 124.7 125 1.62 13 783.3 626.4 400 400 1183.3 1026.4 42.1 111.7 56.3 125 1.62 16 824.2 650.7 400 400 1224.2 1050.7 48.5 124.1 62.6 125 1.62 19 865.3 674.6 400 400 1265.3 1074.6 54.7 136.0 68.9 125 1.62 22 907.1 697.7 400 400 1307.1 1097.7 60.9 147.2 75.2 125 1.62 25 948.2 721.1 400 400 1348.2 1121.1 67.3 157.2 81.5 125 1.80 13 640.0 522.9 400 400 1040.0 922.9 52.6 140.1 70.6 125 1.80 16 673.5 545.4 400 400 1073.5 945.4 60.4 155.7 78.5 125 1.80 19 709.5 566.8 400 400 1109.5 966.8 68.2 171.2 86.2 125 1.80 22 745.0 589.1 400 400 1145.0 989.1 76.0 186.4 94.1 125 1.80 25 783.0 610.2 400 400 1183.0 1010.2 83.8 201.4 101.9 125 1.98 13 547.4 457.1 400 400 947.4 857.1 64.4 172.5 86.8 125 1.98 16 578.7 477.8 400 400 978.7 877.8 73.8 191.4 96.3 125 1.98 19 609.0 498.8 400 400 1009.0 898.8 83.3 210.3 105.8 125 1.98 22 639.8 518.8 400 400 1039.8 918.8 92.8 229.3 115.3 125 1.98 25 671.7 538.5 400 400 1071.7 938.5 102.4 247.9 124.7 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 13 14.9 8.8 3.8 2.1 3.3 1.6 1.0 5.6 20.8 0 1.62 16 14.9 10.1 4.3 2.3 3.4 1.6 1.0 6.2 26.6 0 1.62 19 14.9 11.3 4.7 2.5 3.4 1.6 1.0 6.7 31.7 0 1.62 22 15.0 12.6 5.3 2.9 3.4 1.6 1.0 7.4 38.7 0 1.62 25 15.0 13.8 5.8 3.1 3.4 1.6 1.0 7.9 44.2 0 1.80 13 18.9 11.1 4.7 2.6 4.2 2.0 1.2 7.0 29.0 0 1.80 16 18.9 12.6 5.3 2.9 4.2 2.0 1.2 7.7 35.8 0 1.80 19 18.9 14.1 5.9 3.2 4.2 2.0 1.2 8.4 43.8 0 1.80 22 18.9 15.7 6.6 3.6 4.2 2.0 1.2 9.2 53.1 0 1.80 25 18.9 17.2 7.2 3.9 4.2 2.0 1.2 9.9 63.0 0 1.98 13 23.6 13.8 6.0 3.4 5.4 2.6 1.7 8.8 38.4 0 1.98 16 23.6 15.6 6.7 3.7 5.3 2.6 1.6 9.6 49.4 0 1.98 19 23.6 17.5 7.4 4.0 5.3 2.6 1.6 10.5 61.5 0 1.98 22 23.7 19.5 8.3 4.5 5.4 2.6 1.7 11.5 73.2 0 1.98 25 23.7 21.3 9.0 4.8 5.3 2.6 1.6 12.2 87.0 25 1.62 13 14.9 8.7 3.7 2.0 3.3 1.6 0.9 5.5 21.0 25 1.62 16 14.9 10.0 4.3 2.4 3.3 1.6 1.0 6.1 26.2 25 1.62 19 14.9 11.3 4.8 2.6 3.4 1.6 1.0 6.7 31.6 25 1.62 22 15.0 12.6 5.3 2.9 3.4 1.6 1.0 7.3 38.2 25 1.62 25 15.1 13.8 5.8 3.1 3.4 1.6 1.0 7.9 43.6 25 1.80 13 18.9 11.1 4.7 2.6 4.2 2.0 1.2 7.0 28.0 25 1.80 16 18.9 12.6 5.3 2.9 4.2 2.0 1.2 7.7 36.0 25 1.80 19 18.9 14.1 6.0 3.2 4.2 2.0 1.2 8.4 44.5 25 1.80 22 18.9 15.7 6.6 3.6 4.2 2.0 1.2 9.2 52.4 25 1.80 25 18.9 17.2 7.2 3.8 4.2 2.0 1.2 9.9 61.2 25 1.98 13 23.3 13.6 5.9 3.2 5.1 2.4 1.5 8.6 37.5 25 1.98 16 23.4 15.5 6.6 3.6 5.1 2.4 1.5 9.5 47.9 25 1.98 19 23.4 17.3 7.3 4.0 5.2 2.4 1.5 10.4 59.8 25 1.98 22 23.4 19.2 8.1 4.4 5.2 2.4 1.5 11.2 71.2 25 1.98 25 23.4 21.2 8.9 4.7 5.2 2.4 1.5 12.1 84.5 91

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Appendix A (Continued) 50 1.62 13 14.9 8.7 3.7 2.0 3.3 1.5 0.9 5.5 21.0 50 1.62 16 14.9 10.0 4.2 2.3 3.3 1.5 0.9 6.1 26.0 50 1.62 19 14.9 11.2 4.8 2.6 3.3 1.6 0.9 6.7 31.7 50 1.62 22 15.1 12.6 5.4 2.9 3.3 1.6 0.9 7.3 37.0 50 1.62 25 15.3 13.8 5.8 3.1 3.3 1.6 0.9 7.9 43.6 50 1.80 13 18.8 11.0 4.7 2.6 4.2 2.0 1.2 7.0 27.9 50 1.80 16 18.8 12.5 5.3 2.9 4.2 2.0 1.2 7.7 35.2 50 1.80 19 18.8 14.1 6.0 3.2 4.2 2.0 1.2 8.4 43.9 50 1.80 22 18.9 15.7 6.6 3.6 4.2 2.0 1.2 9.2 51.7 50 1.80 25 19.0 17.3 7.3 3.9 4.2 2.0 1.2 9.9 61.7 50 1.98 13 23.3 13.6 5.8 3.2 5.2 2.5 1.5 8.6 37.3 50 1.98 16 23.3 15.5 6.6 3.6 5.2 2.4 1.5 9.5 47.8 50 1.98 19 23.3 17.4 7.4 4.1 5.3 2.5 1.5 10.4 57.8 50 1.98 22 23.3 19.4 8.3 4.5 5.4 2.6 1.6 11.3 70.7 50 1.98 25 23.3 21.3 8.9 4.8 5.3 2.5 1.5 12.2 81.4 75 1.62 13 14.8 8.8 3.7 2.0 3.4 1.6 1.0 5.6 20.4 75 1.62 16 14.8 10.1 4.3 2.3 3.4 1.6 1.0 6.2 25.7 75 1.62 19 14.9 11.3 4.8 2.6 3.4 1.6 1.0 6.7 31.2 75 1.62 22 15.2 12.6 5.3 2.9 3.4 1.6 1.0 7.4 37.0 75 1.62 25 15.9 13.9 5.8 3.2 3.4 1.6 1.0 7.9 43.4 75 1.80 13 18.8 11.0 4.7 2.6 4.2 2.0 1.2 7.0 27.9 75 1.80 16 18.8 12.5 5.3 2.9 4.2 2.0 1.2 7.7 34.7 75 1.80 19 18.9 14.1 6.0 3.2 4.2 2.0 1.2 8.4 43.5 75 1.80 22 18.9 15.8 6.7 3.6 4.2 2.0 1.2 9.2 51.2 75 1.80 25 19.1 17.3 7.3 4.0 4.2 2.0 1.2 9.9 60.8 75 1.98 13 23.1 13.5 5.7 3.1 5.2 2.4 1.5 8.6 36.5 75 1.98 16 23.1 15.4 6.5 3.6 5.2 2.4 1.5 9.4 46.3 75 1.98 19 23.1 17.4 7.4 4.0 5.2 2.4 1.5 10.4 56.8 75 1.98 22 23.1 19.3 8.1 4.4 5.2 2.4 1.5 11.2 68.6 75 1.98 25 23.2 21.2 8.9 4.8 5.2 2.4 1.5 12.1 79.4 100 1.62 13 14.8 8.8 3.7 2.0 3.4 1.6 1.0 5.5 20.4 100 1.62 16 14.9 10.1 4.3 2.4 3.4 1.6 1.0 6.2 25.7 100 1.62 19 15.2 11.4 4.8 2.6 3.4 1.6 1.0 6.7 31.0 100 1.62 22 15.9 12.7 5.4 3.0 3.4 1.6 1.0 7.4 36.8 100 1.62 25 17.3 13.9 5.9 3.2 3.4 1.6 1.0 7.9 43.0 100 1.80 13 18.7 11.0 4.7 2.6 4.2 2.0 1.2 7.0 27.2 100 1.80 16 18.7 12.6 5.4 2.9 4.2 2.0 1.2 7.7 34.7 100 1.80 19 18.8 14.2 6.0 3.3 4.2 2.0 1.2 8.4 42.9 100 1.80 22 19.0 15.8 6.7 3.7 4.2 2.0 1.2 9.2 50.6 100 1.80 25 19.3 17.5 7.4 4.1 4.2 2.0 1.2 10.0 59.6 100 1.98 13 23.1 13.5 5.7 3.1 5.2 2.4 1.4 8.5 36.2 100 1.98 16 23.1 15.4 6.5 3.5 5.2 2.4 1.4 9.4 45.5 100 1.98 19 23.1 17.4 7.4 4.0 5.2 2.4 1.5 10.4 56.7 100 1.98 22 23.2 19.3 8.1 4.4 5.2 2.4 1.5 11.2 67.8 100 1.98 25 23.3 21.2 8.9 4.8 5.2 2.4 1.5 12.1 79.1 125 1.62 13 14.8 8.8 3.7 2.0 3.3 1.5 0.9 5.5 20.4 125 1.62 16 15.1 10.0 4.3 2.3 3.3 1.5 0.9 6.1 25.4 125 1.62 19 15.8 11.3 4.7 2.5 3.3 1.6 0.9 6.7 31.0 125 1.62 22 17.2 12.6 5.2 2.7 3.4 1.6 1.0 7.3 36.8 125 1.62 25 19.5 13.8 5.8 3.1 3.4 1.6 1.0 7.9 43.1 125 1.80 13 18.8 11.0 4.7 2.5 4.2 2.0 1.2 6.9 27.7 125 1.80 16 18.8 12.6 5.3 2.9 4.2 2.0 1.2 7.7 34.3 125 1.80 19 19.0 14.2 6.0 3.2 4.2 2.0 1.2 8.4 42.0 125 1.80 22 19.3 15.8 6.7 3.6 4.2 2.0 1.2 9.2 50.1 92

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Appendix A (Continued) 125 1.80 25 20.0 17.5 7.4 4.0 4.3 2.0 1.2 9.9 59.1 125 1.98 13 23.2 13.5 5.7 3.1 5.2 2.4 1.5 8.5 35.1 125 1.98 16 23.2 15.4 6.5 3.5 5.2 2.4 1.5 9.4 44.9 125 1.98 19 23.2 17.4 7.4 4.0 5.2 2.4 1.5 10.3 55.5 125 1.98 22 23.3 19.2 8.1 4.3 5.2 2.4 1.5 11.2 66.8 125 1.98 25 23.5 21.2 8.9 4.8 5.2 2.4 1.5 12.1 78.0 Run completed Mon May 23 7:06:00 US/Eastern 2005 in 3019 seconds. lp3ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 29 Setup: 400p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 29 546.1 459.7 400 400 946.1 859.7 77.3 187.0 93.9 0 1.62 33 569.6 475.5 400 400 969.6 875.5 85.7 203.5 102.1 0 1.62 37 592.5 491.4 400 400 992.5 891.4 93.8 220.1 110.5 0 1.62 41 616.3 508.4 400 400 1016.3 908.4 102.1 236.5 118.8 0 1.62 45 639.8 524.2 400 400 1039.8 924.2 110.5 253.0 127.0 0 1.80 29 475.1 411.1 400 400 875.1 811.1 96.3 234.3 117.7 0 1.80 33 495.8 426.2 400 400 895.8 826.2 106.6 255.1 128.1 0 1.80 37 515.8 441.0 400 400 915.8 841.0 117.0 275.7 138.4 0 1.80 41 535.8 457.3 400 400 935.8 857.3 127.3 296.3 148.6 0 1.80 45 557.4 472.6 400 400 957.4 872.6 137.7 317.0 159.0 0 1.98 29 428.3 372.7 400 400 828.3 772.7 118.6 288.1 144.7 0 1.98 33 447.4 387.3 400 400 847.4 787.3 131.0 312.9 157.1 0 1.98 37 465.9 402.9 400 400 865.9 802.9 143.7 338.2 169.8 0 1.98 41 483.7 417.9 400 400 883.7 817.9 156.1 363.2 182.2 0 1.98 45 504.0 432.3 400 400 904.0 832.3 168.6 388.3 194.9 25 1.62 29 602.7 504.4 400 400 1002.7 904.4 77.2 187.1 94.0 25 1.62 33 628.6 521.7 400 400 1028.6 921.7 85.5 203.8 102.3 25 1.62 37 654.0 538.3 400 400 1054.0 938.3 93.9 220.3 110.7 25 1.62 41 680.1 555.7 400 400 1080.1 955.7 102.4 236.7 119.1 25 1.62 45 706.2 573.0 400 400 1106.2 973.0 110.8 252.9 127.4 25 1.80 29 518.8 443.8 400 400 918.8 843.8 96.5 234.2 117.5 25 1.80 33 541.6 459.7 400 400 941.6 859.7 106.9 255.0 127.9 25 1.80 37 563.7 476.6 400 400 963.7 876.6 117.2 275.6 138.2 25 1.80 41 585.9 492.6 400 400 985.9 892.6 127.7 296.3 148.5 25 1.80 45 609.7 508.2 400 400 1009.7 908.2 138.2 316.7 159.0 25 1.98 29 460.7 400.2 400 400 860.7 800.2 118.3 287.6 144.3 25 1.98 33 481.2 415.3 400 400 881.2 815.3 131.1 312.8 156.9 25 1.98 37 500.6 430.6 400 400 900.6 830.6 143.5 337.8 169.5 25 1.98 41 522.2 446.8 400 400 922.2 846.8 156.2 363.1 182.1 25 1.98 45 542.3 462.2 400 400 942.3 862.2 168.8 388.2 194.7 50 1.62 29 662.6 547.0 400 400 1062.6 947.0 77.5 187.4 94.2 50 1.62 33 690.1 564.8 400 400 1090.1 964.8 85.9 203.9 102.5 50 1.62 37 718.9 583.5 400 400 1118.9 983.5 94.0 220.3 110.8 50 1.62 41 746.5 601.5 400 400 1146.5 1001.5 102.7 236.4 119.2 50 1.62 45 776.4 618.9 400 400 1176.4 1018.9 110.7 252.1 127.5 50 1.80 29 560.0 478.0 400 400 960.0 878.0 96.5 234.4 117.6 50 1.80 33 583.9 494.6 400 400 983.9 894.6 107.1 255.1 128.0 50 1.80 37 607.5 512.3 400 400 1007.5 912.3 117.4 275.7 138.3 50 1.80 41 633.3 529.3 400 400 1033.3 929.3 127.7 296.2 148.6 93

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Appendix A (Continued) 50 1.80 45 657.4 545.7 400 400 1057.4 945.7 138.1 316.5 159.0 50 1.98 29 496.1 429.8 400 400 896.1 829.8 118.5 287.3 144.2 50 1.98 33 519.0 446.2 400 400 919.0 846.2 131.3 312.7 157.0 50 1.98 37 540.3 462.9 400 400 940.3 862.9 143.5 337.8 169.5 50 1.98 41 563.1 478.9 400 400 963.1 878.9 156.4 363.0 182.2 50 1.98 45 585.0 494.9 400 400 985.0 894.9 169.0 388.0 194.7 75 1.62 29 719.5 594.2 400 400 1119.5 994.2 77.6 187.4 94.3 75 1.62 33 749.9 614.2 400 400 1149.9 1014.2 86.1 203.8 102.6 75 1.62 37 780.3 633.6 400 400 1180.3 1033.6 94.3 219.9 111.0 75 1.62 41 812.3 652.1 400 400 1212.3 1052.1 102.7 235.3 119.4 75 1.62 45 843.3 671.7 400 400 1243.3 1071.7 111.0 250.0 127.7 75 1.80 29 606.3 514.2 400 400 1006.3 914.2 96.7 234.3 117.7 75 1.80 33 632.6 531.9 400 400 1032.6 931.9 106.8 254.9 128.0 75 1.80 37 659.3 550.1 400 400 1059.3 950.1 117.4 275.5 138.3 75 1.80 41 686.4 568.2 400 400 1086.4 968.2 127.7 295.8 148.8 75 1.80 45 713.6 585.6 400 400 1113.6 985.6 138.3 316.0 159.2 75 1.98 29 530.8 459.3 400 400 930.8 859.3 118.4 287.1 144.1 75 1.98 33 553.6 476.1 400 400 953.6 876.1 130.8 312.2 156.7 75 1.98 37 577.0 493.7 400 400 977.0 893.7 143.5 337.5 169.3 75 1.98 41 601.3 510.5 400 400 1001.3 910.5 156.1 362.5 181.9 75 1.98 45 624.8 527.2 400 400 1024.8 927.2 168.8 387.5 194.5 100 1.62 29 778.7 649.1 400 400 1178.7 1049.1 77.8 187.5 94.4 100 1.62 33 812.1 670.1 400 400 1212.1 1070.1 86.0 203.4 102.7 100 1.62 37 845.2 690.4 400 400 1245.2 1090.4 94.5 218.7 111.1 100 1.62 41 878.1 709.6 400 400 1278.1 1109.6 102.7 233.1 119.5 100 1.62 45 912.3 728.8 400 400 1312.3 1128.8 111.2 246.4 127.8 100 1.80 29 650.6 549.6 400 400 1050.6 949.6 97.0 234.5 117.9 100 1.80 33 684.5 568.5 400 400 1084.5 968.5 107.3 255.2 128.1 100 1.80 37 712.7 587.8 400 400 1112.7 987.8 117.7 275.4 138.6 100 1.80 41 742.5 606.2 400 400 1142.5 1006.2 128.1 295.7 149.1 100 1.80 45 771.5 625.1 400 400 1171.5 1025.1 138.5 315.1 159.4 100 1.98 29 572.9 487.8 400 400 972.9 887.8 118.7 287.5 144.4 100 1.98 33 597.2 505.6 400 400 997.2 905.6 131.3 312.6 156.9 100 1.98 37 623.2 523.8 400 400 1023.2 923.8 143.7 337.7 169.4 100 1.98 41 648.1 541.1 400 400 1048.1 941.1 156.4 362.8 182.2 100 1.98 45 674.6 558.8 400 400 1074.6 958.8 169.3 387.7 195.0 125 1.62 29 840.3 722.6 400 400 1240.3 1122.6 77.8 186.8 94.4 125 1.62 33 875.7 744.3 400 400 1275.7 1144.3 86.3 202.1 102.8 125 1.62 37 910.8 765.6 400 400 1310.8 1165.6 94.5 216.3 111.2 125 1.62 41 947.4 785.7 400 400 1347.4 1185.7 102.8 229.4 119.5 125 1.62 45 983.2 805.9 400 400 1383.2 1205.9 111.2 241.1 127.9 125 1.80 29 698.1 589.6 400 400 1098.1 989.6 97.2 234.5 117.9 125 1.80 33 728.6 609.4 400 400 1128.6 1009.4 107.7 255.1 128.3 125 1.80 37 760.0 629.1 400 400 1160.0 1029.1 118.1 275.1 138.7 125 1.80 41 789.8 649.2 400 400 1189.8 1049.2 128.4 294.6 149.1 125 1.80 45 821.5 668.2 400 400 1221.5 1068.2 138.8 313.2 159.6 125 1.98 29 606.4 517.8 400 400 1006.4 917.8 118.4 287.6 144.4 125 1.98 33 633.0 536.3 400 400 1033.0 936.3 131.3 312.7 157.0 125 1.98 37 659.5 554.3 400 400 1059.5 954.3 143.9 337.9 169.7 125 1.98 41 687.1 573.7 400 400 1087.1 973.7 156.5 362.5 182.4 125 1.98 45 713.7 591.9 400 400 1113.7 991.9 169.2 386.9 195.0 94

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Appendix A (Continued) Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 29 17.2 15.8 6.5 3.5 3.8 1.8 1.1 9.1 49.7 0 1.62 33 17.3 17.6 7.4 4.1 3.8 1.8 1.1 10.0 57.0 0 1.62 37 17.3 19.2 7.9 4.1 3.8 1.8 1.1 10.6 65.5 0 1.62 41 17.4 20.8 8.6 4.5 3.8 1.8 1.1 11.4 73.4 0 1.62 45 17.5 22.6 9.4 4.9 3.8 1.8 1.1 12.2 82.5 0 1.80 29 21.9 19.7 8.2 4.4 4.9 2.3 1.4 11.4 68.1 0 1.80 33 22.0 21.9 9.1 4.8 4.9 2.3 1.4 12.4 81.3 0 1.80 37 22.0 23.9 9.9 5.2 4.9 2.3 1.4 13.3 91.4 0 1.80 41 22.0 26.1 10.7 5.6 4.9 2.3 1.4 14.3 104.9 0 1.80 45 22.1 27.9 11.3 6.0 4.9 2.3 1.4 15.2 119.1 0 1.98 29 27.2 24.5 10.2 5.4 6.2 3.0 1.9 14.1 93.6 0 1.98 33 27.2 26.8 11.1 5.9 6.1 2.9 1.9 15.2 111.2 0 1.98 37 27.2 29.5 12.4 6.6 6.2 3.0 1.9 16.5 126.3 0 1.98 41 27.2 32.0 13.3 7.1 6.2 3.0 1.9 17.6 145.1 0 1.98 45 27.3 34.4 14.3 7.3 6.2 3.0 1.9 18.7 167.1 25 1.62 29 17.3 15.8 6.6 3.5 3.8 1.8 1.1 9.1 49.1 25 1.62 33 17.4 17.6 7.3 3.8 3.8 1.8 1.1 9.8 56.9 25 1.62 37 17.5 19.2 8.0 4.3 3.8 1.8 1.1 10.7 65.3 25 1.62 41 17.7 20.9 8.8 4.7 3.9 1.8 1.1 11.5 73.1 25 1.62 45 18.1 22.5 9.3 4.9 3.8 1.8 1.1 12.2 83.1 25 1.80 29 21.8 19.8 8.2 4.3 4.8 2.2 1.3 11.3 68.4 25 1.80 33 21.8 21.9 9.1 4.7 4.8 2.2 1.3 12.3 79.1 25 1.80 37 21.8 24.0 10.0 5.4 4.8 2.2 1.3 13.3 92.1 25 1.80 41 21.9 26.1 10.8 5.7 4.8 2.2 1.3 14.2 102.9 25 1.80 45 22.1 28.1 11.6 6.1 4.8 2.2 1.4 15.2 116.3 25 1.98 29 27.0 24.4 10.2 5.4 5.9 2.7 1.6 14.0 91.0 25 1.98 33 27.0 26.8 11.0 5.8 5.9 2.7 1.6 15.1 105.0 25 1.98 37 27.0 29.3 12.1 6.4 5.9 2.7 1.6 16.2 123.2 25 1.98 41 27.0 32.0 13.3 7.1 6.0 2.8 1.7 17.5 139.6 25 1.98 45 27.1 34.6 14.4 7.6 6.0 2.8 1.7 18.7 160.5 50 1.62 29 17.2 15.9 6.6 3.5 3.8 1.8 1.1 9.1 48.3 50 1.62 33 17.4 17.6 7.4 3.9 3.8 1.8 1.1 9.9 56.5 50 1.62 37 17.6 19.3 8.0 4.3 3.8 1.8 1.1 10.7 64.2 50 1.62 41 18.2 21.1 8.8 4.7 3.9 1.8 1.1 11.5 73.2 50 1.62 45 19.3 22.8 9.5 5.0 3.9 1.8 1.1 12.3 82.0 50 1.80 29 21.8 19.9 8.4 4.5 4.9 2.3 1.4 11.4 67.1 50 1.80 33 21.8 22.0 9.2 4.9 4.9 2.2 1.4 12.4 77.7 50 1.80 37 21.9 24.1 10.0 5.4 4.9 2.2 1.4 13.4 90.4 50 1.80 41 22.1 26.2 10.9 5.7 4.9 2.2 1.4 14.3 102.5 50 1.80 45 22.3 28.1 11.6 6.1 4.8 2.2 1.4 15.2 115.7 50 1.98 29 26.8 24.5 10.2 5.4 6.0 2.8 1.7 14.0 90.2 50 1.98 33 26.8 26.8 11.1 5.9 6.0 2.8 1.7 15.1 103.1 50 1.98 37 26.8 29.3 12.2 6.5 6.0 2.8 1.7 16.3 119.5 50 1.98 41 26.9 32.1 13.4 7.1 6.1 2.8 1.7 17.6 137.1 50 1.98 45 27.1 34.6 14.3 7.5 6.0 2.8 1.7 18.7 158.7 75 1.62 29 17.4 15.8 6.6 3.5 3.8 1.8 1.1 9.1 48.2 75 1.62 33 17.7 17.5 7.2 3.8 3.8 1.8 1.1 9.8 55.3 75 1.62 37 18.4 19.5 8.1 4.4 3.9 1.8 1.1 10.7 63.7 75 1.62 41 19.6 21.1 8.8 4.7 3.9 1.8 1.1 11.5 72.6 75 1.62 45 21.6 22.4 9.3 4.8 3.8 1.8 1.1 12.2 81.1 75 1.80 29 21.8 19.8 8.3 4.4 4.8 2.2 1.4 11.4 65.7 75 1.80 33 21.8 22.0 9.2 5.0 4.8 2.2 1.4 12.4 77.0 95

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Appendix A (Continued) 75 1.80 37 22.0 24.2 10.2 5.4 4.8 2.2 1.3 13.4 88.7 75 1.80 41 22.4 26.3 11.0 5.8 4.8 2.2 1.3 14.3 101.1 75 1.80 45 23.1 28.2 11.7 6.2 4.8 2.2 1.3 15.3 114.8 75 1.98 29 26.7 24.3 10.1 5.4 5.9 2.7 1.6 13.9 89.2 75 1.98 33 26.7 26.8 11.2 5.9 5.9 2.7 1.6 15.1 103.2 75 1.98 37 26.8 29.3 12.2 6.5 5.9 2.7 1.6 16.3 119.6 75 1.98 41 26.9 31.9 13.2 7.0 5.9 2.7 1.6 17.4 136.4 75 1.98 45 27.2 34.6 14.2 7.5 5.9 2.7 1.6 18.6 155.5 100 1.62 29 17.7 15.9 6.5 3.5 3.8 1.8 1.0 9.1 47.5 100 1.62 33 18.4 17.6 7.3 3.8 3.8 1.8 1.0 9.8 55.4 100 1.62 37 19.8 19.5 8.2 4.4 3.9 1.8 1.1 10.7 63.6 100 1.62 41 22.1 21.1 8.9 4.9 3.9 1.8 1.1 11.6 72.2 100 1.62 45 25.3 22.7 9.5 5.1 3.9 1.8 1.1 12.3 80.9 100 1.80 29 21.7 20.0 8.4 4.5 4.8 2.2 1.3 11.4 64.5 100 1.80 33 21.9 22.1 9.2 4.9 4.8 2.2 1.3 12.4 76.1 100 1.80 37 22.2 24.3 10.1 5.4 4.8 2.2 1.3 13.4 87.8 100 1.80 41 23.0 26.3 10.9 5.8 4.8 2.2 1.3 14.3 100.4 100 1.80 45 24.2 28.3 11.7 6.1 4.8 2.2 1.3 15.2 113.2 100 1.98 29 26.7 24.3 10.1 5.4 5.9 2.7 1.6 13.9 85.8 100 1.98 33 26.8 26.9 11.2 6.0 5.9 2.7 1.6 15.1 100.7 100 1.98 37 26.9 29.4 12.3 6.6 5.9 2.7 1.6 16.4 117.2 100 1.98 41 27.2 32.0 13.3 7.0 5.9 2.7 1.6 17.5 134.1 100 1.98 45 27.7 34.6 14.3 7.5 5.9 2.7 1.6 18.7 151.2 125 1.62 29 18.3 16.0 6.7 3.6 3.8 1.7 1.0 9.1 47.7 125 1.62 33 19.8 17.6 7.3 3.8 3.8 1.7 1.0 9.9 55.1 125 1.62 37 22.3 19.3 8.0 4.2 3.8 1.7 1.0 10.7 63.0 125 1.62 41 26.0 20.9 8.7 4.6 3.8 1.7 1.0 11.5 71.6 125 1.62 45 30.6 22.6 9.4 5.0 3.8 1.7 1.0 12.3 80.2 125 1.80 29 21.8 20.1 8.3 4.4 4.8 2.2 1.3 11.4 64.3 125 1.80 33 22.2 22.2 9.3 5.0 4.8 2.2 1.3 12.4 75.7 125 1.80 37 22.9 24.3 10.2 5.4 4.8 2.2 1.3 13.4 87.1 125 1.80 41 24.3 26.3 11.1 5.9 4.8 2.2 1.3 14.4 99.2 125 1.80 45 26.4 28.5 11.8 6.4 4.8 2.2 1.3 15.4 112.2 125 1.98 29 26.8 24.3 10.1 5.3 5.9 2.7 1.6 13.9 85.7 125 1.98 33 27.0 26.9 11.2 6.0 5.9 2.7 1.6 15.1 100.4 125 1.98 37 27.2 29.6 12.4 6.7 6.0 2.7 1.6 16.4 115.5 125 1.98 41 27.6 32.1 13.3 7.1 5.9 2.7 1.6 17.5 131.6 125 1.98 45 28.5 34.6 14.4 7.6 5.9 2.7 1.6 18.7 149.8 Run completed Mon May 23 7:55:32 US/Eastern 2005 in 2972 seconds. lp4ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 50 Setup: 450p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 50 610.5 520.1 450 450 1060.5 970.1 126.1 294.4 147.7 0 1.62 55 631.2 534.5 450 450 1081.2 984.5 136.4 315.0 158.0 0 1.62 60 652.2 548.4 450 450 1102.2 998.4 147.0 335.5 168.4 0 1.62 65 674.3 563.5 450 450 1124.3 1013.5 157.4 356.1 178.9 0 1.62 70 694.3 578.7 450 450 1144.3 1028.7 167.5 376.0 189.4 0 1.80 50 527.5 462.8 450 450 977.5 912.8 157.1 368.3 184.8 96

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Appendix A (Continued) 0 1.80 55 546.6 477.0 450 450 996.6 927.0 170.0 394.2 197.6 0 1.80 60 564.9 490.7 450 450 1014.9 940.7 183.1 419.8 210.6 0 1.80 65 582.9 504.1 450 450 1032.9 954.1 195.9 445.6 223.6 0 1.80 70 602.9 518.2 450 450 1052.9 968.2 208.9 470.9 236.5 0 1.98 50 474.5 423.8 450 450 924.5 873.8 192.2 450.5 225.9 0 1.98 55 490.7 437.8 450 450 940.7 887.8 207.9 481.8 241.6 0 1.98 60 508.7 451.1 450 450 958.7 901.1 224.0 513.3 257.5 0 1.98 65 525.2 464.0 450 450 975.2 914.0 239.1 544.7 273.1 0 1.98 70 542.1 477.6 450 450 992.1 927.6 254.7 575.9 288.6 25 1.62 50 663.7 566.4 450 450 1113.7 1016.4 126.1 294.9 148.0 25 1.62 55 687.2 582.0 450 450 1137.2 1032.0 136.9 315.3 158.5 25 1.62 60 710.4 597.8 450 450 1160.4 1047.8 147.2 335.5 168.9 25 1.62 65 734.2 613.0 450 450 1184.2 1063.0 157.6 355.1 179.2 25 1.62 70 758.0 628.0 450 450 1208.0 1078.0 168.2 374.2 189.5 25 1.80 50 581.0 501.3 450 450 1031.0 951.3 157.9 369.1 185.2 25 1.80 55 600.8 515.9 450 450 1050.8 965.9 170.6 394.7 198.0 25 1.80 60 621.5 530.2 450 450 1071.5 980.2 183.6 420.2 210.9 25 1.80 65 642.3 544.5 450 450 1092.3 994.5 196.6 445.5 223.7 25 1.80 70 662.3 559.5 450 450 1112.3 1009.5 209.6 470.9 236.8 25 1.98 50 513.8 454.2 450 450 963.8 904.2 192.5 451.0 226.1 25 1.98 55 532.4 468.9 450 450 982.4 918.9 208.3 482.2 241.9 25 1.98 60 551.1 482.8 450 450 1001.1 932.8 224.0 513.6 257.5 25 1.98 65 568.9 496.4 450 450 1018.9 946.4 239.6 544.9 273.2 25 1.98 70 588.6 510.6 450 450 1038.6 960.6 255.5 576.1 289.0 50 1.62 50 729.1 614.9 450 450 1179.1 1064.9 126.4 294.5 148.2 50 1.62 55 754.0 631.1 450 450 1204.0 1081.1 137.1 314.5 158.7 50 1.62 60 780.2 648.0 450 450 1230.2 1098.0 147.7 333.8 169.2 50 1.62 65 805.6 664.7 450 450 1255.6 1114.7 158.0 352.4 179.5 50 1.62 70 832.2 680.8 450 450 1282.2 1130.8 168.3 370.1 189.8 50 1.80 50 624.9 539.1 450 450 1074.9 989.1 157.4 368.1 184.6 50 1.80 55 646.6 554.2 450 450 1096.6 1004.2 170.4 393.8 197.7 50 1.80 60 669.5 569.5 450 450 1119.5 1019.5 183.5 419.1 210.6 50 1.80 65 692.0 585.1 450 450 1142.0 1035.1 196.5 444.3 223.6 50 1.80 70 714.7 600.2 450 450 1164.7 1050.2 209.3 468.7 236.5 50 1.98 50 554.4 487.0 450 450 1004.4 937.0 192.7 451.1 226.2 50 1.98 55 574.3 501.8 450 450 1024.3 951.8 208.3 482.6 242.0 50 1.98 60 594.7 516.0 450 450 1044.7 966.0 224.2 514.1 257.9 50 1.98 65 614.2 530.6 450 450 1064.2 980.6 240.1 545.1 273.4 50 1.98 70 635.5 545.6 450 450 1085.5 995.6 255.7 575.8 289.3 75 1.62 50 791.4 664.6 450 450 1241.4 1114.6 126.7 293.7 148.4 75 1.62 55 819.3 682.6 450 450 1269.3 1132.6 137.0 312.6 158.8 75 1.62 60 847.0 699.7 450 450 1297.0 1149.7 147.6 330.6 169.3 75 1.62 65 875.3 716.1 450 450 1325.3 1166.1 158.2 347.5 179.6 75 1.62 70 902.7 733.0 450 450 1352.7 1183.0 168.4 363.2 190.1 75 1.80 50 673.9 578.2 450 450 1123.9 1028.2 157.8 368.8 185.1 75 1.80 55 697.9 594.9 450 450 1147.9 1044.9 171.1 394.1 198.2 75 1.80 60 722.4 611.1 450 450 1172.4 1061.1 183.9 419.2 211.2 75 1.80 65 746.7 626.6 450 450 1196.7 1076.6 197.0 443.4 224.2 75 1.80 70 771.3 642.8 450 450 1221.3 1092.8 210.2 466.9 237.2 75 1.98 50 593.7 518.3 450 450 1043.7 968.3 193.0 451.9 226.7 75 1.98 55 614.7 533.6 450 450 1064.7 983.6 208.7 482.9 242.2 75 1.98 60 636.4 549.2 450 450 1086.4 999.2 224.4 514.1 258.1 75 1.98 65 661.7 564.1 450 450 1111.7 1014.1 240.2 544.6 274.0 75 1.98 70 682.8 578.9 450 450 1132.8 1028.9 256.1 575.2 289.8 97

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Appendix A (Continued) 100 1.62 50 855.5 723.7 450 450 1305.5 1173.7 127.0 291.5 148.6 100 1.62 55 885.2 741.9 450 450 1335.2 1191.9 137.6 309.0 159.1 100 1.62 60 915.7 759.9 450 450 1365.7 1209.9 147.9 325.2 169.6 100 1.62 65 945.7 776.8 450 450 1395.7 1226.8 158.2 340.1 180.0 100 1.62 70 975.8 792.6 450 450 1425.8 1242.6 168.8 353.7 190.2 100 1.80 50 724.7 619.9 450 450 1174.7 1069.9 157.9 368.1 185.1 100 1.80 55 751.3 636.9 450 450 1201.3 1086.9 171.1 393.0 198.2 100 1.80 60 776.7 653.1 450 450 1226.7 1103.1 184.2 417.1 211.2 100 1.80 65 803.7 670.4 450 450 1253.7 1120.4 197.1 440.2 224.3 100 1.80 70 829.2 687.1 450 450 1279.2 1137.1 209.8 462.2 237.4 100 1.98 50 636.4 550.3 450 450 1086.4 1000.3 192.8 451.1 226.4 100 1.98 55 658.7 565.8 450 450 1108.7 1015.8 208.7 482.3 242.2 100 1.98 60 682.2 581.9 450 450 1132.2 1031.9 224.6 513.1 258.1 100 1.98 65 704.7 598.0 450 450 1154.7 1048.0 240.5 543.4 273.9 100 1.98 70 729.1 613.5 450 450 1179.1 1063.5 256.3 573.2 289.6 125 1.62 50 924.2 802.6 450 450 1374.2 1252.6 127.2 287.7 148.9 125 1.62 55 955.9 821.3 450 450 1405.9 1271.3 137.8 303.4 159.3 125 1.62 60 988.3 840.3 450 450 1438.3 1290.3 148.1 317.6 169.7 125 1.62 65 1021.0 856.6 450 450 1471.0 1306.6 158.7 330.5 180.1 125 1.62 70 1053.0 872.1 450 450 1503.0 1322.1 169.2 342.6 190.6 125 1.80 50 780.0 662.8 450 450 1230.0 1112.8 158.7 368.0 185.8 125 1.80 55 807.5 680.5 450 450 1257.5 1130.5 171.6 391.8 198.8 125 1.80 60 835.8 698.0 450 450 1285.8 1148.0 185.0 414.6 211.9 125 1.80 65 863.1 715.7 450 450 1313.1 1165.7 197.8 436.0 224.8 125 1.80 70 892.1 732.6 450 450 1342.1 1182.6 210.9 456.0 237.8 125 1.98 50 678.4 583.7 450 450 1128.4 1033.7 193.3 451.8 226.9 125 1.98 55 702.8 600.7 450 450 1152.8 1050.7 208.8 482.3 242.6 125 1.98 60 727.0 617.4 450 450 1177.0 1067.4 224.9 512.6 258.6 125 1.98 65 751.7 633.5 450 450 1201.7 1083.5 240.6 542.1 274.3 125 1.98 70 776.5 650.1 450 450 1226.5 1100.1 256.7 570.8 290.1 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 50 22.3 25.7 10.6 5.6 4.8 2.2 1.3 14.1 88.1 0 1.62 55 22.4 28.0 11.6 6.1 4.8 2.2 1.3 15.1 98.7 0 1.62 60 22.7 30.0 12.4 6.6 4.9 2.2 1.3 16.1 110.5 0 1.62 65 23.1 32.4 13.4 7.1 4.8 2.2 1.3 17.1 121.1 0 1.62 70 23.8 34.2 14.4 7.8 4.9 2.2 1.3 18.2 132.5 0 1.80 50 28.1 31.8 13.0 6.9 6.1 2.8 1.7 17.6 124.7 0 1.80 55 28.1 34.0 13.5 7.0 6.1 2.8 1.7 18.6 139.6 0 1.80 60 28.2 36.4 14.6 7.5 6.2 2.8 1.7 19.9 158.2 0 1.80 65 28.4 39.4 15.9 8.3 6.2 2.8 1.7 21.2 174.5 0 1.80 70 28.6 41.8 16.6 8.8 6.2 2.8 1.7 22.3 195.0 0 1.98 50 34.9 39.0 16.1 8.4 7.8 3.7 2.3 21.7 170.7 0 1.98 55 34.9 42.0 17.0 8.7 7.9 3.7 2.3 23.0 193.3 0 1.98 60 35.0 45.9 18.9 10.1 7.8 3.7 2.3 24.8 212.3 0 1.98 65 35.0 48.3 19.6 10.0 7.9 3.7 2.3 25.9 242.5 0 1.98 70 35.2 51.4 20.8 10.6 7.9 3.7 2.3 27.4 269.3 25 1.62 50 22.6 25.6 10.6 5.6 4.8 2.2 1.3 14.1 87.6 25 1.62 55 23.0 28.0 11.6 6.1 4.8 2.2 1.3 15.1 96.9 25 1.62 60 23.6 30.1 12.5 6.6 4.8 2.2 1.3 16.1 107.9 25 1.62 65 24.6 32.2 13.3 7.0 4.8 2.2 1.3 17.1 120.5 25 1.62 70 26.2 34.3 14.2 7.6 4.8 2.2 1.3 18.1 132.6 25 1.80 50 28.1 32.0 13.2 7.0 6.1 2.8 1.6 17.7 120.3 98

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Appendix A (Continued) 25 1.80 55 28.2 34.8 14.4 7.6 6.1 2.8 1.6 18.9 138.7 25 1.80 60 28.4 37.4 15.5 8.2 6.1 2.8 1.6 20.2 154.1 25 1.80 65 28.8 40.0 16.4 8.6 6.1 2.8 1.6 21.3 173.8 25 1.80 70 29.5 42.8 17.6 9.3 6.1 2.8 1.6 22.6 188.4 25 1.98 50 34.6 39.2 16.2 8.6 7.6 3.5 2.1 21.7 164.9 25 1.98 55 34.7 42.6 17.6 9.3 7.6 3.5 2.1 23.2 188.1 25 1.98 60 34.8 45.9 18.9 10.0 7.6 3.5 2.1 24.7 213.0 25 1.98 65 35.0 48.1 19.9 10.4 7.6 3.5 2.1 26.0 233.9 25 1.98 70 35.2 51.1 20.7 10.8 7.6 3.5 2.1 27.4 256.6 50 1.62 50 23.1 25.8 10.6 5.5 4.8 2.1 1.2 14.1 86.0 50 1.62 55 23.9 27.9 11.5 6.1 4.8 2.1 1.2 15.1 97.2 50 1.62 60 25.4 30.1 12.5 6.5 4.8 2.1 1.2 16.1 107.3 50 1.62 65 27.7 32.3 13.3 7.0 4.8 2.1 1.2 17.1 120.2 50 1.62 70 30.8 34.2 14.1 7.4 4.8 2.2 1.2 18.1 130.7 50 1.80 50 28.2 32.0 13.1 6.8 6.0 2.7 1.6 17.6 120.3 50 1.80 55 28.5 34.8 14.4 7.6 6.1 2.7 1.6 18.9 135.0 50 1.80 60 28.9 37.5 15.5 8.1 6.1 2.7 1.6 20.1 152.7 50 1.80 65 29.8 40.1 16.7 8.8 6.1 2.7 1.6 21.4 169.2 50 1.80 70 31.0 42.6 17.5 9.2 6.1 2.7 1.6 22.5 188.3 50 1.98 50 34.6 39.4 16.3 8.5 7.6 3.4 2.0 21.6 162.0 50 1.98 55 34.8 42.5 17.6 9.2 7.6 3.4 2.0 23.1 186.0 50 1.98 60 35.0 45.9 19.1 10.2 7.6 3.5 2.0 24.7 205.2 50 1.98 65 35.3 49.0 20.2 10.6 7.6 3.5 2.0 26.1 228.5 50 1.98 70 35.9 52.1 21.5 11.2 7.6 3.5 2.0 27.5 253.1 75 1.62 50 24.3 25.8 10.7 5.7 4.8 2.1 1.2 14.2 85.6 75 1.62 55 26.2 28.0 11.5 6.0 4.8 2.1 1.2 15.1 96.6 75 1.62 60 29.0 30.0 12.3 6.5 4.8 2.1 1.2 16.1 106.9 75 1.62 65 33.0 32.4 13.3 7.0 4.8 2.1 1.2 17.1 119.4 75 1.62 70 37.8 34.5 14.2 7.5 4.8 2.2 1.2 18.1 130.8 75 1.80 50 28.5 32.2 13.3 7.0 6.1 2.7 1.6 17.7 120.7 75 1.80 55 29.2 34.8 14.4 7.5 6.1 2.7 1.6 18.9 134.7 75 1.80 60 30.2 37.7 15.6 8.2 6.1 2.7 1.6 20.2 151.7 75 1.80 65 31.8 40.3 16.6 8.7 6.1 2.7 1.6 21.4 167.6 75 1.80 70 34.2 42.9 17.6 9.2 6.1 2.7 1.6 22.6 185.1 75 1.98 50 34.7 39.3 16.1 8.4 7.4 3.3 2.0 21.6 158.6 75 1.98 55 34.9 42.5 17.4 9.1 7.4 3.3 2.0 23.1 179.6 75 1.98 60 35.3 45.8 18.9 9.9 7.5 3.3 2.0 24.6 202.6 75 1.98 65 36.0 49.0 20.2 10.6 7.5 3.3 2.0 26.1 227.4 75 1.98 70 37.1 52.1 21.4 11.3 7.5 3.3 2.0 27.6 251.6 100 1.62 50 27.0 26.0 10.8 5.8 4.8 2.2 1.2 14.3 85.6 100 1.62 55 30.4 28.0 11.6 6.2 4.8 2.2 1.2 15.2 96.1 100 1.62 60 34.8 30.1 12.4 6.6 4.8 2.2 1.2 16.2 106.3 100 1.62 65 40.5 32.2 13.3 7.0 4.8 2.2 1.2 17.1 118.2 100 1.62 70 47.6 34.6 14.3 7.5 4.8 2.2 1.2 18.1 129.5 100 1.80 50 29.1 32.2 13.3 7.0 6.1 2.7 1.6 17.7 118.1 100 1.80 55 30.3 34.7 14.3 7.5 6.1 2.7 1.6 18.9 132.6 100 1.80 60 32.2 37.6 15.5 8.1 6.1 2.7 1.6 20.1 149.0 100 1.80 65 35.0 40.2 16.6 8.7 6.1 2.7 1.6 21.4 166.7 100 1.80 70 38.9 42.9 17.7 9.2 6.1 2.7 1.6 22.6 182.7 100 1.98 50 34.8 39.3 16.2 8.5 7.4 3.3 1.9 21.6 156.6 100 1.98 55 35.2 42.3 17.2 9.0 7.4 3.3 1.9 23.0 177.8 100 1.98 60 36.0 45.7 18.9 10.0 7.5 3.4 2.0 24.6 198.7 100 1.98 65 37.3 49.1 20.2 10.6 7.5 3.3 2.0 26.1 222.2 100 1.98 70 39.3 52.2 21.5 11.3 7.4 3.3 2.0 27.6 246.7 99

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Appendix A (Continued) 125 1.62 50 31.3 26.0 10.8 5.7 4.8 2.1 1.2 14.2 84.5 125 1.62 55 36.6 28.0 11.6 6.1 4.8 2.1 1.2 15.2 95.6 125 1.62 60 43.1 30.4 12.6 6.6 4.8 2.1 1.2 16.2 105.9 125 1.62 65 50.4 32.4 13.4 7.0 4.8 2.1 1.2 17.2 117.2 125 1.62 70 58.2 34.8 14.4 7.5 4.8 2.1 1.2 18.2 128.6 125 1.80 50 30.4 32.4 13.3 7.1 6.0 2.7 1.5 17.7 117.4 125 1.80 55 32.6 34.8 14.4 7.6 6.0 2.7 1.5 18.9 131.7 125 1.80 60 35.8 37.6 15.5 8.2 6.0 2.7 1.5 20.2 148.4 125 1.80 65 40.3 40.4 16.7 8.7 6.0 2.7 1.5 21.4 164.5 125 1.80 70 46.0 43.1 17.7 9.3 6.0 2.7 1.5 22.6 181.7 125 1.98 50 35.2 39.4 16.4 8.8 7.5 3.3 1.9 21.8 155.8 125 1.98 55 36.0 42.5 17.6 9.2 7.5 3.3 1.9 23.1 175.3 125 1.98 60 37.4 45.6 18.7 9.8 7.5 3.3 1.9 24.6 195.9 125 1.98 65 39.5 49.1 20.2 10.6 7.4 3.3 1.9 26.1 219.5 125 1.98 70 42.5 52.3 21.5 11.2 7.5 3.3 1.9 27.6 243.6 Run completed Mon May 23 8:45:48 US/Eastern 2005 in 3016 seconds. lp5ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 76 Setup: 450p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 76 669.8 571.6 450 450 1119.8 1021.6 182.2 410.1 206.0 0 1.62 82 689.8 585.5 450 450 1139.8 1035.5 194.9 434.8 218.4 0 1.62 88 708.8 599.4 450 450 1158.8 1049.4 207.6 458.7 230.9 0 1.62 94 729.5 610.0 450 450 1179.5 1060.0 220.1 482.4 243.4 0 1.62 100 749.1 625.7 450 450 1199.1 1075.7 232.6 505.2 255.7 0 1.80 76 584.7 508.6 450 450 1034.7 958.6 227.8 514.1 257.7 0 1.80 82 601.9 521.0 450 450 1051.9 971.0 243.2 544.9 273.3 0 1.80 88 618.6 534.7 450 450 1068.6 984.7 258.7 575.5 288.7 0 1.80 94 637.4 548.2 450 450 1087.4 998.2 274.5 605.9 304.2 0 1.80 100 655.0 560.9 450 450 1105.0 1010.9 290.2 636.2 319.9 0 1.98 76 521.5 466.9 450 450 971.5 916.9 276.8 627.4 314.5 0 1.98 82 538.2 479.0 450 450 988.2 929.0 296.1 665.2 333.5 0 1.98 88 554.2 491.2 450 450 1004.2 941.2 314.9 702.6 352.3 0 1.98 94 569.4 504.4 450 450 1019.4 954.4 333.5 740.0 371.0 0 1.98 100 586.1 517.0 450 450 1036.1 967.0 353.0 777.3 390.2 25 1.62 76 731.0 621.9 450 450 1181.0 1071.9 182.8 410.3 206.7 25 1.62 82 752.3 636.7 450 450 1202.3 1086.7 195.2 433.7 219.0 25 1.62 88 774.7 651.0 450 450 1224.7 1101.0 207.9 456.8 231.5 25 1.62 94 796.4 664.8 450 450 1246.4 1114.8 220.6 478.9 243.9 25 1.62 100 818.6 679.3 450 450 1268.6 1129.3 233.3 500.4 256.4 25 1.80 76 641.4 549.1 450 450 1091.4 999.1 227.8 514.5 258.1 25 1.80 82 661.1 563.2 450 450 1111.1 1013.2 243.8 545.1 273.8 25 1.80 88 680.7 577.1 450 450 1130.7 1027.1 259.0 575.5 289.3 25 1.80 94 698.9 590.4 450 450 1148.9 1040.4 274.7 605.2 304.7 25 1.80 100 719.7 603.5 450 450 1169.7 1053.5 290.0 634.6 320.2 25 1.98 76 569.0 498.3 450 450 1019.0 948.3 278.1 630.0 315.9 25 1.98 82 586.6 512.1 450 450 1036.6 962.1 296.8 667.5 334.6 25 1.98 88 603.2 525.3 450 450 1053.2 975.3 316.5 705.0 353.8 25 1.98 94 621.1 537.9 450 450 1071.1 987.9 335.2 742.2 372.7 100

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Appendix A (Continued) 25 1.98 100 639.1 550.9 450 450 1089.1 1000.9 354.1 779.3 391.7 50 1.62 76 801.1 674.5 450 450 1251.1 1124.5 183.2 408.1 206.7 50 1.62 82 825.5 690.4 450 450 1275.5 1140.4 196.0 430.2 219.2 50 1.62 88 848.8 705.3 450 450 1298.8 1155.3 208.5 451.7 231.9 50 1.62 94 873.5 719.7 450 450 1323.5 1169.7 221.3 471.5 244.2 50 1.62 100 896.7 735.8 450 450 1346.7 1185.8 233.5 490.2 256.7 50 1.80 76 691.2 590.4 450 450 1141.2 1040.4 228.5 514.0 258.3 50 1.80 82 712.3 604.4 450 450 1162.3 1054.4 244.1 544.1 274.0 50 1.80 88 732.5 619.2 450 450 1182.5 1069.2 259.6 573.3 289.3 50 1.80 94 754.7 633.4 450 450 1204.7 1083.4 275.2 602.2 304.7 50 1.80 100 774.8 647.2 450 450 1224.8 1097.2 290.8 630.0 320.5 50 1.98 76 611.6 535.2 450 450 1061.6 985.2 278.5 628.8 315.4 50 1.98 82 629.7 548.6 450 450 1079.7 998.6 297.0 665.7 334.0 50 1.98 88 648.6 561.8 450 450 1098.6 1011.8 316.0 703.3 353.3 50 1.98 94 668.1 576.0 450 450 1118.1 1026.0 334.7 739.9 371.8 50 1.98 100 686.0 589.7 450 450 1136.0 1039.7 354.1 776.2 391.0 75 1.62 76 871.2 729.5 450 450 1321.2 1179.5 183.4 403.9 207.3 75 1.62 82 896.8 745.4 450 450 1346.8 1195.4 196.1 424.1 219.8 75 1.62 88 923.2 760.5 450 450 1373.2 1210.5 208.6 442.8 232.2 75 1.62 94 948.6 776.1 450 450 1398.6 1226.1 221.1 460.2 244.8 75 1.62 100 975.4 790.3 450 450 1425.4 1240.3 233.8 476.3 257.3 75 1.80 76 742.9 635.4 450 450 1192.9 1085.4 228.5 513.1 258.7 75 1.80 82 765.7 650.8 450 450 1215.7 1100.8 244.2 542.1 274.1 75 1.80 88 788.2 665.3 450 450 1238.2 1115.3 259.8 570.6 289.9 75 1.80 94 810.6 679.7 450 450 1260.6 1129.7 274.9 597.5 305.2 75 1.80 100 834.0 695.0 450 450 1284.0 1145.0 290.5 623.4 320.9 75 1.98 76 659.8 569.7 450 450 1109.8 1019.7 278.8 628.8 315.7 75 1.98 82 679.7 583.9 450 450 1129.7 1033.9 297.5 665.7 334.5 75 1.98 88 699.2 597.8 450 450 1149.2 1047.8 316.7 702.1 353.5 75 1.98 94 719.2 612.2 450 450 1169.2 1062.2 335.8 737.8 372.5 75 1.98 100 740.2 626.6 450 450 1190.2 1076.6 354.5 772.9 391.0 100 1.62 76 944.8 793.6 450 450 1394.8 1243.6 183.8 396.1 207.5 100 1.62 82 972.8 808.2 450 450 1422.8 1258.2 196.3 413.6 219.9 100 1.62 88 1001.0 823.2 450 450 1451.0 1273.2 209.1 429.7 232.4 100 1.62 94 1029.0 839.7 450 450 1479.0 1289.7 221.4 444.8 244.9 100 1.62 100 1057.0 853.4 450 450 1507.0 1303.4 234.1 458.9 257.5 100 1.80 76 799.7 680.2 450 450 1249.7 1130.2 229.0 510.6 258.8 100 1.80 82 824.0 695.8 450 450 1274.0 1145.8 244.1 537.9 274.4 100 1.80 88 848.1 711.8 450 450 1298.1 1161.8 259.9 564.2 290.0 100 1.80 94 873.1 727.1 450 450 1323.1 1177.1 275.4 589.2 305.7 100 1.80 100 897.3 741.6 450 450 1347.3 1191.6 291.2 612.6 321.1 100 1.98 76 704.1 604.0 450 450 1154.1 1054.0 278.9 629.0 316.4 100 1.98 82 726.3 618.7 450 450 1176.3 1068.7 297.6 665.3 335.3 100 1.98 88 747.2 633.0 450 450 1197.2 1083.0 316.8 700.6 354.1 100 1.98 94 769.3 648.2 450 450 1219.3 1098.2 335.9 735.1 373.0 100 1.98 100 790.6 662.9 450 450 1240.6 1112.9 354.6 768.6 392.1 125 1.62 76 1020.0 875.8 450 450 1470.0 1325.8 183.9 385.1 208.2 125 1.62 82 1050.0 890.6 450 450 1500.0 1340.6 196.6 400.5 220.8 125 1.62 88 1081.0 903.0 450 450 1531.0 1353.0 209.1 414.9 233.3 125 1.62 94 1111.0 916.2 450 450 1561.0 1366.2 221.7 428.7 245.8 125 1.62 100 1143.0 925.2 450 450 1593.0 1375.2 234.5 441.9 258.3 125 1.80 76 859.5 727.2 450 450 1309.5 1177.2 229.2 506.1 259.1 125 1.80 82 884.9 743.1 450 450 1334.9 1193.1 245.1 531.6 274.7 125 1.80 88 911.6 758.9 450 450 1361.6 1208.9 260.6 555.7 290.5 101

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Appendix A (Continued) 125 1.80 94 936.9 774.2 450 450 1386.9 1224.2 276.1 577.9 306.1 125 1.80 100 963.1 788.5 450 450 1413.1 1238.5 291.7 598.6 321.6 125 1.98 76 748.9 642.1 450 450 1198.9 1092.1 279.3 627.2 316.4 125 1.98 82 770.9 658.1 450 450 1220.9 1108.1 298.3 662.4 335.2 125 1.98 88 794.4 673.4 450 450 1244.4 1123.4 317.4 696.5 354.2 125 1.98 94 816.9 688.2 450 450 1266.9 1138.2 336.3 729.4 373.2 125 1.98 100 840.5 703.8 450 450 1290.5 1153.8 355.5 760.7 392.0 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 76 25.2 37.5 15.5 8.2 5.3 2.4 1.4 19.7 139.6 0 1.62 82 25.8 40.2 17.0 9.2 5.3 2.4 1.4 21.1 151.3 0 1.62 88 26.6 42.7 18.1 9.8 5.3 2.4 1.4 22.3 166.0 0 1.62 94 27.9 45.4 19.2 10.5 5.3 2.4 1.4 23.6 183.4 0 1.62 100 29.7 47.8 20.1 11.0 5.3 2.4 1.4 24.7 197.0 0 1.80 76 31.4 45.6 18.7 9.8 6.9 3.2 1.9 24.5 196.3 0 1.80 82 31.5 48.5 19.9 10.5 6.9 3.2 1.9 26.0 218.2 0 1.80 88 31.8 51.8 21.3 11.1 6.8 3.2 1.9 27.4 243.5 0 1.80 94 32.3 54.8 22.5 11.8 6.9 3.2 1.9 28.9 259.9 0 1.80 100 32.9 58.2 23.9 12.8 6.9 3.2 1.9 30.5 283.9 0 1.98 76 38.9 55.8 22.4 11.2 8.8 4.2 2.6 29.7 271.6 0 1.98 82 38.9 59.7 23.9 11.8 8.8 4.2 2.6 31.4 308.5 0 1.98 88 39.1 63.6 25.5 12.5 8.8 4.2 2.6 33.1 327.9 0 1.98 94 39.3 67.1 26.8 13.1 8.7 4.1 2.6 34.7 361.6 0 1.98 100 39.6 71.0 28.3 13.8 8.7 4.1 2.6 36.5 403.3 25 1.62 76 26.4 37.4 15.5 8.1 5.3 2.4 1.4 19.7 137.1 25 1.62 82 27.7 39.9 16.5 8.7 5.3 2.4 1.4 20.9 150.1 25 1.62 88 29.6 42.9 18.0 9.7 5.3 2.4 1.4 22.3 165.9 25 1.62 94 32.4 45.0 18.9 10.3 5.3 2.4 1.4 23.5 179.2 25 1.62 100 36.0 47.8 20.0 10.9 5.3 2.4 1.4 24.7 197.1 25 1.80 76 31.7 46.1 19.0 10.0 6.8 3.1 1.8 24.6 193.6 25 1.80 82 32.2 49.4 20.4 10.6 6.8 3.1 1.8 26.0 215.4 25 1.80 88 33.0 52.8 21.7 11.4 6.8 3.1 1.8 27.5 234.3 25 1.80 94 34.1 56.0 23.0 12.1 6.8 3.1 1.8 29.0 256.5 25 1.80 100 35.8 59.1 24.4 12.9 6.9 3.1 1.8 30.5 281.8 25 1.98 76 38.7 55.7 23.0 12.1 8.5 4.0 2.4 30.1 264.5 25 1.98 82 38.9 59.2 24.4 12.8 8.5 4.0 2.4 31.8 292.3 25 1.98 88 39.2 63.4 26.1 13.7 8.5 4.0 2.4 33.6 327.1 25 1.98 94 39.9 66.8 27.5 14.4 8.5 4.0 2.4 35.4 353.6 25 1.98 100 40.6 71.0 29.2 15.3 8.5 4.0 2.4 37.2 390.5 50 1.62 76 28.9 37.3 15.4 8.1 5.4 2.4 1.4 19.7 136.0 50 1.62 82 31.7 40.0 16.5 8.7 5.4 2.4 1.4 20.9 150.4 50 1.62 88 35.5 42.9 17.7 9.4 5.4 2.4 1.4 22.1 163.7 50 1.62 94 40.3 45.6 19.2 10.3 5.4 2.4 1.4 23.5 180.4 50 1.62 100 46.1 47.8 20.0 10.8 5.4 2.4 1.4 24.7 194.2 50 1.80 76 32.2 46.7 19.2 10.1 6.7 3.0 1.8 24.6 190.4 50 1.80 82 33.3 49.7 20.5 10.7 6.8 3.0 1.8 26.1 212.3 50 1.80 88 34.8 52.8 21.8 11.4 6.8 3.0 1.8 27.5 235.0 50 1.80 94 37.1 56.0 23.0 12.0 6.8 3.0 1.8 29.0 256.1 50 1.80 100 40.2 59.2 24.3 12.8 6.8 3.1 1.8 30.5 278.6 50 1.98 76 39.0 56.7 23.4 12.3 8.5 3.9 2.4 30.1 261.4 50 1.98 82 39.2 60.4 24.9 13.1 8.5 3.9 2.4 31.9 289.6 50 1.98 88 40.0 64.5 26.6 13.9 8.5 3.9 2.4 33.7 318.3 50 1.98 94 41.0 68.2 28.0 14.7 8.5 3.9 2.4 35.4 350.2 102

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Appendix A (Continued) 50 1.98 100 42.6 72.2 29.7 15.5 8.5 3.9 2.4 37.2 381.9 75 1.62 76 33.9 37.5 15.5 8.2 5.3 2.4 1.4 19.8 136.1 75 1.62 82 38.8 40.1 16.6 8.7 5.3 2.4 1.4 20.9 149.1 75 1.62 88 44.9 42.8 17.6 9.3 5.3 2.4 1.4 22.1 163.3 75 1.62 94 52.0 45.4 19.0 10.2 5.4 2.4 1.4 23.5 177.9 75 1.62 100 60.2 47.4 19.6 10.4 5.3 2.4 1.4 24.5 192.9 75 1.80 76 33.9 46.6 19.3 10.1 6.7 3.0 1.7 24.6 189.4 75 1.80 82 35.8 49.7 20.5 10.7 6.7 3.0 1.7 26.1 210.6 75 1.80 88 38.8 52.9 21.8 11.4 6.7 3.0 1.7 27.5 230.6 75 1.80 94 42.6 56.2 23.1 12.1 6.8 3.0 1.7 29.0 253.7 75 1.80 100 47.6 58.9 24.2 12.6 6.8 3.0 1.7 30.4 276.9 75 1.98 76 39.3 56.8 23.3 12.2 8.3 3.7 2.2 30.0 255.9 75 1.98 82 40.1 60.5 24.9 13.1 8.3 3.7 2.2 31.8 284.2 75 1.98 88 41.5 64.4 26.5 13.9 8.3 3.7 2.2 33.6 311.8 75 1.98 94 43.4 68.6 28.2 14.7 8.3 3.7 2.2 35.4 342.9 75 1.98 100 46.2 72.2 29.6 15.4 8.3 3.7 2.2 37.1 375.6 100 1.62 76 42.3 37.5 15.5 8.1 5.3 2.4 1.4 19.8 134.8 100 1.62 82 49.5 40.0 16.6 8.7 5.3 2.4 1.4 20.9 148.2 100 1.62 88 57.9 42.7 17.8 9.4 5.3 2.4 1.4 22.2 162.4 100 1.62 94 66.9 45.2 18.7 9.9 5.4 2.4 1.4 23.3 176.1 100 1.62 100 76.3 47.9 19.9 10.5 5.4 2.4 1.4 24.5 191.4 100 1.80 76 36.8 46.9 19.3 10.1 6.7 3.0 1.7 24.6 188.6 100 1.80 82 40.4 50.0 20.7 10.8 6.7 3.0 1.7 26.1 208.6 100 1.80 88 45.2 53.1 22.0 11.5 6.7 3.0 1.7 27.6 229.9 100 1.80 94 51.2 56.0 23.1 12.1 6.7 3.0 1.7 29.0 250.4 100 1.80 100 58.5 59.3 24.5 12.8 6.7 3.0 1.7 30.5 273.4 100 1.98 76 40.2 57.0 23.5 12.3 8.2 3.7 2.1 30.1 251.0 100 1.98 82 41.8 60.7 25.0 13.1 8.2 3.7 2.2 31.9 278.7 100 1.98 88 44.2 64.6 26.6 13.9 8.2 3.7 2.2 33.7 306.8 100 1.98 94 47.5 68.2 28.0 14.7 8.2 3.7 2.2 35.4 339.1 100 1.98 100 51.8 72.1 29.7 15.6 8.2 3.7 2.2 37.2 369.9 125 1.62 76 53.3 37.3 15.4 8.0 5.3 2.3 1.3 19.7 133.8 125 1.62 82 62.3 40.0 16.5 8.6 5.3 2.3 1.3 20.9 147.7 125 1.62 88 71.8 42.5 17.5 9.2 5.3 2.3 1.3 22.1 161.6 125 1.62 94 81.3 45.2 18.7 9.9 5.3 2.3 1.3 23.3 175.2 125 1.62 100 90.6 48.2 20.0 10.7 5.3 2.4 1.3 24.6 190.6 125 1.80 76 41.9 46.8 19.3 10.2 6.7 3.0 1.7 24.7 186.5 125 1.80 82 47.5 50.0 20.6 10.8 6.7 3.0 1.7 26.1 206.3 125 1.80 88 54.5 53.0 21.9 11.4 6.7 3.0 1.7 27.6 225.8 125 1.80 94 62.8 56.3 23.2 12.1 6.7 3.0 1.7 29.0 246.8 125 1.80 100 72.4 59.2 24.4 12.7 6.7 3.0 1.7 30.5 268.0 125 1.98 76 42.0 57.0 23.5 12.3 8.2 3.7 2.1 30.1 247.0 125 1.98 82 44.7 60.8 25.0 13.1 8.2 3.7 2.2 31.9 275.0 125 1.98 88 48.4 64.8 26.7 13.9 8.2 3.7 2.1 33.7 304.3 125 1.98 94 53.4 68.6 28.2 14.7 8.2 3.7 2.1 35.4 334.2 125 1.98 100 59.7 72.0 29.6 15.5 8.2 3.7 2.1 37.2 365.6 Run completed Mon May 23 9:37:41 US/Eastern 2005 in 3113 seconds. 103

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Appendix A (Continued) tg1ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 2 Setup: 75p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 2 273.6 269.4 75 75 348.6 344.4 30.3 50.7 35.9 0 1.62 4 301.7 295.3 75 75 376.7 370.3 34.5 59.0 40.0 0 1.62 6 329.1 319.0 75 75 404.1 394.0 38.5 67.3 44.2 0 1.62 8 354.2 342.8 75 75 429.2 417.8 42.6 75.5 48.3 0 1.62 10 380.9 367.0 75 75 455.9 442.0 46.8 83.8 52.4 0 1.80 2 241.5 240.9 75 75 316.5 315.9 38.1 63.8 45.2 0 1.80 4 265.3 264.4 75 75 340.3 339.4 43.1 73.8 50.2 0 1.80 6 289.0 287.1 75 75 364.0 362.1 48.4 84.3 55.4 0 1.80 8 315.1 310.5 75 75 390.1 385.5 53.4 94.4 60.4 0 1.80 10 341.2 332.4 75 75 416.2 407.4 58.6 104.8 65.7 0 1.98 2 220.0 216.6 75 75 295.0 291.6 47.1 78.7 55.7 0 1.98 4 247.3 239.8 75 75 322.3 314.8 53.5 91.5 62.0 0 1.98 6 266.3 261.4 75 75 341.3 336.4 59.7 103.8 68.3 0 1.98 8 290.1 283.7 75 75 365.1 358.7 65.9 116.2 74.5 0 1.98 10 311.9 304.8 75 75 386.9 379.8 72.2 128.8 80.8 25 1.62 2 300.7 299.3 75 75 375.7 374.3 30.4 50.8 36.0 25 1.62 4 332.2 326.6 75 75 407.2 401.6 34.5 59.2 40.1 25 1.62 6 361.9 351.9 75 75 436.9 426.9 38.6 67.4 44.3 25 1.62 8 390.1 377.8 75 75 465.1 452.8 42.8 75.8 48.5 25 1.62 10 419.4 402.0 75 75 494.4 477.0 46.9 84.1 52.6 25 1.80 2 264.1 263.7 75 75 339.1 338.7 38.2 63.7 45.1 25 1.80 4 293.9 288.4 75 75 368.9 363.4 43.3 74.0 50.2 25 1.80 6 320.0 313.1 75 75 395.0 388.1 48.5 84.2 55.5 25 1.80 8 346.8 336.6 75 75 421.8 411.6 53.6 94.5 60.6 25 1.80 10 373.0 359.7 75 75 448.0 434.7 58.8 104.8 65.8 25 1.98 2 241.6 233.3 75 75 316.6 308.3 47.5 79.2 56.1 25 1.98 4 267.3 257.0 75 75 342.3 332.0 53.7 91.6 62.3 25 1.98 6 291.3 281.0 75 75 366.3 356.0 60.0 104.1 68.6 25 1.98 8 316.1 303.0 75 75 391.1 378.0 66.1 116.5 74.7 25 1.98 10 341.3 325.4 75 75 416.3 400.4 72.3 129.0 81.0 50 1.62 2 335.3 328.6 75 75 410.3 403.6 30.4 51.1 36.1 50 1.62 4 365.7 355.6 75 75 440.7 430.6 34.5 59.4 40.2 50 1.62 6 397.2 383.5 75 75 472.2 458.5 38.7 67.7 44.4 50 1.62 8 429.2 409.1 75 75 504.2 484.1 42.8 76.0 48.6 50 1.62 10 462.4 436.3 75 75 537.4 511.3 47.0 84.3 52.7 50 1.80 2 289.5 286.8 75 75 364.5 361.8 38.0 63.8 45.1 50 1.80 4 318.1 311.5 75 75 393.1 386.5 43.2 74.4 50.3 50 1.80 6 347.2 336.7 75 75 422.2 411.7 48.3 84.6 55.5 50 1.80 8 377.3 361.8 75 75 452.3 436.8 53.4 94.8 60.6 50 1.80 10 407.4 386.5 75 75 482.4 461.5 58.7 105.4 65.9 50 1.98 2 256.8 254.8 75 75 331.8 329.8 46.8 78.4 55.5 50 1.98 4 286.6 280.0 75 75 361.6 355.0 53.1 91.0 61.8 50 1.98 6 315.0 304.7 75 75 390.0 379.7 59.3 103.4 68.0 50 1.98 8 340.7 328.7 75 75 415.7 403.7 65.6 116.1 74.3 50 1.98 10 368.5 351.7 75 75 443.5 426.7 71.9 128.6 80.6 75 1.62 2 366.8 358.4 75 75 441.8 433.4 30.5 51.2 36.2 75 1.62 4 402.3 389.6 75 75 477.3 464.6 34.7 59.5 40.3 75 1.62 6 437.0 418.8 75 75 512.0 493.8 38.8 67.8 44.5 104

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Appendix A (Continued) 75 1.62 8 471.8 447.6 75 75 546.8 522.6 43.0 76.1 48.7 75 1.62 10 510.6 474.9 75 75 585.6 549.9 47.2 84.6 52.9 75 1.80 2 316.4 313.7 75 75 391.4 388.7 38.2 64.3 45.4 75 1.80 4 349.7 342.4 75 75 424.7 417.4 43.4 74.5 50.6 75 1.80 6 380.7 368.4 75 75 455.7 443.4 48.6 85.0 55.8 75 1.80 8 411.7 393.8 75 75 486.7 468.8 53.7 95.3 61.0 75 1.80 10 445.6 420.4 75 75 520.6 495.4 58.8 105.6 66.1 75 1.98 2 283.5 274.5 75 75 358.5 349.5 46.9 78.9 55.7 75 1.98 4 314.0 301.0 75 75 389.0 376.0 53.1 91.3 61.9 75 1.98 6 342.1 327.3 75 75 417.1 402.3 59.4 103.9 68.2 75 1.98 8 369.8 351.2 75 75 444.8 426.2 65.7 116.6 74.5 75 1.98 10 400.4 375.7 75 75 475.4 450.7 72.0 129.2 80.8 100 1.62 2 408.4 391.6 75 75 483.4 466.6 30.7 51.5 36.4 100 1.62 4 445.3 423.6 75 75 520.3 498.6 34.9 59.8 40.6 100 1.62 6 484.0 454.6 75 75 559.0 529.6 39.0 68.2 44.8 100 1.62 8 522.1 483.5 75 75 597.1 558.5 43.2 76.5 48.9 100 1.62 10 561.7 513.4 75 75 636.7 588.4 47.3 84.9 53.1 100 1.80 2 345.7 339.5 75 75 420.7 414.5 38.4 64.5 45.6 100 1.80 4 380.4 369.4 75 75 455.4 444.4 43.6 74.7 50.8 100 1.80 6 414.0 396.7 75 75 489.0 471.7 48.8 85.1 55.9 100 1.80 8 447.9 424.9 75 75 522.9 499.9 53.9 95.5 61.1 100 1.80 10 487.4 451.5 75 75 562.4 526.5 59.2 106.0 66.4 100 1.98 2 304.4 300.0 75 75 379.4 375.0 46.6 79.1 55.6 100 1.98 4 337.5 327.3 75 75 412.5 402.3 52.8 91.5 61.8 100 1.98 6 367.3 353.5 75 75 442.3 428.5 59.1 104.1 68.1 100 1.98 8 400.1 379.1 75 75 475.1 454.1 65.4 116.8 74.4 100 1.98 10 431.7 405.7 75 75 506.7 480.7 71.7 129.3 80.7 125 1.62 2 446.6 431.3 75 75 521.6 506.3 30.9 51.8 36.6 125 1.62 4 487.4 465.0 75 75 562.4 540.0 35.0 60.2 40.8 125 1.62 6 528.8 497.0 75 75 603.8 572.0 39.2 68.6 45.0 125 1.62 8 570.8 527.6 75 75 645.8 602.6 43.4 76.9 49.2 125 1.62 10 613.6 559.0 75 75 688.6 634.0 47.5 85.2 53.4 125 1.80 2 380.0 367.1 75 75 455.0 442.1 38.6 64.9 45.9 125 1.80 4 416.6 398.6 75 75 491.6 473.6 43.7 75.1 51.0 125 1.80 6 452.7 428.1 75 75 527.7 503.1 48.9 85.5 56.2 125 1.80 8 492.4 457.3 75 75 567.4 532.3 54.1 96.0 61.4 125 1.80 10 530.4 486.0 75 75 605.4 561.0 59.3 106.3 66.6 125 1.98 2 331.2 321.9 75 75 406.2 396.9 47.0 79.2 55.9 125 1.98 4 364.0 351.6 75 75 439.0 426.6 53.2 91.7 62.1 125 1.98 6 397.1 379.2 75 75 472.1 454.2 59.5 104.3 68.4 125 1.98 8 430.9 406.6 75 75 505.9 481.6 65.8 117.0 74.7 125 1.98 10 465.5 433.2 75 75 540.5 508.2 72.1 129.6 81.0 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 2 26.7 22.9 21.8 21.4 22.1 21.5 21.2 22.4 3.0 0 1.62 4 26.7 23.7 22.1 21.6 22.1 21.5 21.2 22.8 6.1 0 1.62 6 26.7 24.5 22.4 21.7 22.1 21.5 21.2 23.1 9.4 0 1.62 8 26.7 25.3 22.8 21.9 22.1 21.5 21.2 23.5 13.1 0 1.62 10 26.7 26.1 23.1 22.0 22.1 21.5 21.2 23.9 17.0 0 1.80 2 33.5 28.8 27.4 26.9 27.8 27.0 26.7 28.2 3.9 0 1.80 4 33.5 29.8 27.8 27.1 27.8 27.0 26.7 28.6 8.4 0 1.80 6 33.5 30.8 28.2 27.3 27.8 27.0 26.7 29.1 12.8 0 1.80 8 33.5 31.8 28.6 27.5 27.8 27.0 26.7 29.6 18.2 105

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Appendix A (Continued) 0 1.80 10 33.5 32.9 29.0 27.7 27.8 27.0 26.7 30.0 23.2 0 1.98 2 41.3 35.6 33.8 33.2 34.4 33.3 33.0 34.8 5.1 0 1.98 4 41.3 36.8 34.3 33.5 34.4 33.3 33.0 35.4 10.8 0 1.98 6 41.3 38.1 34.8 33.7 34.4 33.3 33.0 36.0 16.6 0 1.98 8 41.3 39.3 35.3 34.0 34.4 33.3 33.0 36.5 24.0 0 1.98 10 41.3 40.6 35.8 34.2 34.4 33.3 33.0 37.1 31.0 25 1.62 2 26.9 23.0 21.9 21.5 22.2 21.6 21.3 22.5 2.9 25 1.62 4 26.9 23.8 22.2 21.6 22.3 21.6 21.4 22.9 6.0 25 1.62 6 26.9 24.6 22.5 21.8 22.3 21.6 21.3 23.2 9.4 25 1.62 8 26.9 25.4 22.8 21.9 22.3 21.6 21.4 23.6 13.0 25 1.62 10 26.9 26.3 23.2 22.1 22.3 21.6 21.4 24.0 16.6 25 1.80 2 33.5 28.9 27.5 27.0 27.9 27.1 26.8 28.3 4.0 25 1.80 4 33.6 29.9 27.9 27.2 27.9 27.1 26.8 28.8 8.0 25 1.80 6 33.6 30.9 28.3 27.4 27.9 27.1 26.8 29.2 12.7 25 1.80 8 33.6 31.9 28.7 27.6 27.9 27.1 26.8 29.7 17.4 25 1.80 10 33.6 32.9 29.1 27.8 27.9 27.1 26.8 30.2 23.0 25 1.98 2 41.8 36.0 34.3 33.7 34.8 33.8 33.4 35.2 5.0 25 1.98 4 41.8 37.2 34.7 33.9 34.8 33.8 33.4 35.8 10.7 25 1.98 6 41.7 38.5 35.3 34.2 34.8 33.8 33.4 36.4 16.7 25 1.98 8 41.7 39.7 35.8 34.4 34.8 33.8 33.4 37.0 23.5 25 1.98 10 41.8 40.9 36.2 34.6 34.8 33.8 33.4 37.5 30.0 50 1.62 2 26.9 23.0 21.9 21.5 22.3 21.6 21.4 22.5 3.0 50 1.62 4 26.8 23.8 22.2 21.7 22.3 21.6 21.4 22.9 6.2 50 1.62 6 26.9 24.6 22.5 21.8 22.3 21.6 21.4 23.3 9.5 50 1.62 8 26.9 25.4 22.8 22.0 22.3 21.6 21.4 23.6 12.7 50 1.62 10 26.9 26.3 23.1 22.1 22.3 21.6 21.4 24.0 16.4 50 1.80 2 33.4 28.6 27.2 26.7 27.7 26.9 26.6 28.0 3.9 50 1.80 4 33.5 29.6 27.6 27.0 27.7 26.9 26.6 28.5 7.9 50 1.80 6 33.5 30.7 28.0 27.1 27.7 26.9 26.6 29.0 12.8 50 1.80 8 33.5 31.7 28.4 27.4 27.7 26.9 26.6 29.5 17.4 50 1.80 10 33.5 32.8 28.9 27.6 27.7 26.9 26.6 30.0 22.5 50 1.98 2 41.2 35.3 33.6 33.0 34.2 33.1 32.8 34.5 5.1 50 1.98 4 41.2 36.6 34.1 33.2 34.1 33.1 32.8 35.1 10.5 50 1.98 6 41.2 37.8 34.6 33.5 34.2 33.1 32.8 35.7 17.1 50 1.98 8 41.2 39.1 35.1 33.7 34.1 33.1 32.8 36.3 22.8 50 1.98 10 41.2 40.3 35.6 34.0 34.2 33.1 32.8 36.9 30.2 75 1.62 2 26.9 23.1 21.9 21.6 22.3 21.6 21.4 22.6 2.9 75 1.62 4 26.9 23.9 22.3 21.7 22.3 21.6 21.4 22.9 6.1 75 1.62 6 26.9 24.7 22.6 21.8 22.3 21.6 21.4 23.3 9.3 75 1.62 8 26.9 25.6 23.0 22.1 22.3 21.6 21.4 23.7 12.7 75 1.62 10 26.9 26.4 23.2 22.2 22.3 21.6 21.4 24.1 16.3 75 1.80 2 33.7 28.9 27.4 27.0 27.9 27.1 26.8 28.3 3.9 75 1.80 4 33.7 29.9 27.8 27.1 27.9 27.1 26.8 28.7 8.0 75 1.80 6 33.8 30.9 28.3 27.4 27.9 27.1 26.8 29.2 12.7 75 1.80 8 33.8 31.9 28.7 27.6 28.0 27.1 26.8 29.7 17.5 75 1.80 10 33.8 32.9 29.0 27.7 28.0 27.1 26.8 30.1 22.2 75 1.98 2 41.3 35.3 33.5 32.9 34.2 33.1 32.8 34.5 5.1 75 1.98 4 41.3 36.5 34.0 33.2 34.2 33.1 32.8 35.1 10.5 75 1.98 6 41.3 37.8 34.5 33.4 34.2 33.1 32.8 35.7 16.3 75 1.98 8 41.3 39.0 35.0 33.7 34.2 33.1 32.8 36.3 22.7 75 1.98 10 41.3 40.2 35.5 33.9 34.2 33.1 32.8 36.9 29.3 100 1.62 2 27.0 23.1 22.0 21.6 22.4 21.7 21.5 22.6 2.9 100 1.62 4 27.0 24.0 22.4 21.8 22.4 21.7 21.5 23.0 6.0 100 1.62 6 27.0 24.8 22.7 21.9 22.4 21.7 21.5 23.4 9.2 106

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Appendix A (Continued) 25 1.62 16 462.2 417.8 75 75 537.2 492.8 61.0 115.4 68.3 100 1.62 8 27.1 25.6 23.0 22.1 22.4 21.7 21.5 23.8 12.7 100 1.62 10 27.1 26.4 23.3 22.2 22.4 21.7 21.5 24.2 16.3 100 1.80 2 33.8 29.0 27.6 27.1 28.0 27.1 26.8 28.4 3.8 100 1.80 4 33.8 30.0 28.0 27.3 28.0 27.1 26.9 28.8 8.0 100 1.80 6 33.9 31.1 28.4 27.5 28.0 27.2 26.9 29.3 12.3 100 1.80 8 33.9 32.1 28.8 27.7 28.0 27.1 26.9 29.8 17.1 100 1.80 10 33.9 33.1 29.2 27.9 28.0 27.1 26.9 30.3 22.1 100 1.98 2 41.1 34.8 33.1 32.6 33.9 32.9 32.5 34.2 5.0 100 1.98 4 41.1 36.1 33.6 32.9 33.9 32.9 32.5 34.8 10.3 100 1.98 6 41.1 37.3 34.1 33.1 33.9 32.9 32.5 35.4 16.4 100 1.98 8 41.1 38.6 34.6 33.3 33.9 32.9 32.5 36.0 22.9 100 1.98 10 41.1 39.9 35.1 33.6 33.9 32.9 32.5 36.6 29.3 125 1.62 2 27.2 23.3 22.2 21.8 22.5 21.8 21.6 22.8 2.9 125 1.62 4 27.2 24.1 22.5 21.9 22.5 21.8 21.6 23.2 6.0 125 1.62 6 27.2 25.0 22.8 22.1 22.5 21.8 21.6 23.6 9.2 125 1.62 8 27.2 25.8 23.1 22.2 22.5 21.8 21.6 23.9 12.6 125 1.62 10 27.2 26.6 23.4 22.4 22.5 21.8 21.6 24.3 16.0 125 1.80 2 34.1 29.1 27.7 27.2 28.2 27.3 27.0 28.5 3.8 125 1.80 4 34.1 30.2 28.1 27.4 28.2 27.3 27.0 29.0 7.9 125 1.80 6 34.1 31.2 28.5 27.6 28.2 27.3 27.0 29.5 12.2 125 1.80 8 34.1 32.2 28.9 27.8 28.2 27.3 27.0 29.9 17.0 125 1.80 10 34.1 33.3 29.3 28.0 28.2 27.3 27.0 30.4 21.8 125 1.98 2 41.4 35.3 33.6 33.0 34.1 33.1 32.7 34.5 4.9 125 1.98 4 41.3 36.6 34.1 33.2 34.1 33.1 32.7 35.1 10.3 125 1.98 6 41.4 37.8 34.5 33.5 34.1 33.1 32.7 35.7 15.9 125 1.98 8 41.4 39.1 35.1 33.7 34.1 33.1 32.7 36.3 22.0 125 1.98 10 41.4 40.3 35.5 34.0 34.1 33.1 32.7 36.9 29.2 Run completed Sun May 22 21:45:22 US/Eastern 2005 in 4537 seconds. tg2ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 13 Setup: 75p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 13 400.5 363.6 75 75 475.5 438.6 54.5 102.9 61.9 0 1.62 16 421.9 381.0 75 75 496.9 456.0 60.8 115.3 68.2 0 1.62 19 445.2 399.0 75 75 520.2 474.0 67.0 127.8 74.4 0 1.62 22 467.6 415.5 75 75 542.6 490.5 73.2 140.3 80.6 0 1.62 25 491.6 433.9 75 75 566.6 508.9 79.4 152.7 86.8 0 1.80 13 348.0 325.5 75 75 423.0 400.5 68.2 128.6 77.5 0 1.80 16 368.1 343.2 75 75 443.1 418.2 75.9 144.2 85.2 0 1.80 19 389.0 359.1 75 75 464.0 434.1 83.7 159.7 93.0 0 1.80 22 409.5 375.6 75 75 484.5 450.6 91.4 175.1 100.7 0 1.80 25 429.6 393.1 75 75 504.6 468.1 98.9 190.4 108.3 0 1.98 13 319.5 293.0 75 75 394.5 368.0 84.2 158.0 95.4 0 1.98 16 336.9 308.9 75 75 411.9 383.9 93.8 176.7 104.8 0 1.98 19 356.6 325.7 75 75 431.6 400.7 103.2 195.6 114.3 0 1.98 22 376.0 341.9 75 75 451.0 416.9 112.6 214.4 123.6 0 1.98 25 394.2 357.4 75 75 469.2 432.4 122.1 233.3 133.0 25 1.62 13 438.3 399.6 75 75 513.3 474.6 54.7 103.0 62.1 25 1.62 19 491.7 437.0 75 75 566.7 512.0 67.3 128.3 74.7 107

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Appendix A (Continued) 25 1.62 22 516.2 454.7 75 75 591.2 529.7 73.5 140.7 80.9 25 1.62 25 541.8 473.5 75 75 616.8 548.5 79.7 153.2 87.2 25 1.80 13 379.5 353.4 75 75 454.5 428.4 68.3 128.5 77.5 25 1.80 16 400.5 370.9 75 75 475.5 445.9 76.0 144.0 85.3 25 1.80 19 423.6 389.1 75 75 498.6 464.1 83.8 159.7 93.1 25 1.80 22 449.8 406.5 75 75 524.8 481.5 91.3 175.6 101.0 25 1.80 25 473.3 423.2 75 75 548.3 498.2 99.1 191.2 108.8 25 1.98 13 344.2 317.1 75 75 419.2 392.1 84.3 157.9 95.5 25 1.98 16 363.5 335.7 75 75 438.5 410.7 93.8 177.1 105.1 25 1.98 19 384.7 351.8 75 75 459.7 426.8 103.0 195.9 114.4 25 1.98 22 405.6 369.3 75 75 480.6 444.3 112.7 214.7 123.9 25 1.98 25 426.2 386.1 75 75 501.2 461.1 121.9 233.4 133.3 50 1.62 13 482.2 435.9 75 75 557.2 510.9 54.8 103.6 62.3 50 1.62 16 510.1 456.0 75 75 585.1 531.0 61.1 116.0 68.5 50 1.62 19 536.9 475.8 75 75 611.9 550.8 67.3 128.5 74.8 50 1.62 22 565.1 494.6 75 75 640.1 569.6 73.6 141.1 81.1 50 1.62 25 592.8 514.6 75 75 667.8 589.6 79.7 153.4 87.3 50 1.80 13 415.5 383.1 75 75 490.5 458.1 68.0 128.9 77.5 50 1.80 16 440.9 402.1 75 75 515.9 477.1 75.7 144.5 85.3 50 1.80 19 464.6 420.1 75 75 539.6 495.1 83.5 159.9 93.0 50 1.80 22 492.5 439.3 75 75 567.5 514.3 91.5 175.8 101.0 50 1.80 25 517.2 456.9 75 75 592.2 531.9 99.3 191.4 108.8 50 1.98 13 370.9 344.0 75 75 445.9 419.0 83.9 158.2 95.3 50 1.98 16 391.3 361.7 75 75 466.3 436.7 93.2 177.0 104.7 50 1.98 19 414.9 378.5 75 75 489.9 453.5 102.7 195.8 114.1 50 1.98 22 437.0 395.9 75 75 512.0 470.9 112.0 214.5 123.5 50 1.98 25 460.8 414.2 75 75 535.8 489.2 121.4 233.5 132.9 75 1.62 13 530.9 478.2 75 75 605.9 553.2 54.9 103.9 62.6 75 1.62 16 561.5 499.8 75 75 636.5 574.8 61.1 116.4 68.8 75 1.62 19 591.0 520.1 75 75 666.0 595.1 67.3 128.9 75.0 75 1.62 22 621.3 540.8 75 75 696.3 615.8 73.6 141.5 81.3 75 1.62 25 651.9 561.5 75 75 726.9 636.5 79.9 154.0 87.6 75 1.80 13 451.5 415.6 75 75 526.5 490.6 68.5 129.3 77.8 75 1.80 16 479.1 435.1 75 75 554.1 510.1 76.2 144.9 85.6 75 1.80 19 506.0 453.6 75 75 581.0 528.6 84.0 160.4 93.4 75 1.80 22 532.4 473.6 75 75 607.4 548.6 91.9 176.0 101.2 75 1.80 25 559.1 492.6 75 75 634.1 567.6 99.7 191.6 109.1 75 1.98 13 401.2 370.0 75 75 476.2 445.0 83.6 158.5 95.3 75 1.98 16 425.1 389.4 75 75 500.1 464.4 93.1 177.4 104.7 75 1.98 19 449.0 407.2 75 75 524.0 482.2 102.6 196.3 114.2 75 1.98 22 473.3 425.2 75 75 548.3 500.2 112.0 215.1 123.7 75 1.98 25 498.0 444.0 75 75 573.0 519.0 121.3 233.9 133.1 100 1.62 13 582.2 521.7 75 75 657.2 596.7 55.1 104.0 62.6 100 1.62 16 614.3 543.7 75 75 689.3 618.7 61.4 116.6 68.9 100 1.62 19 645.9 565.4 75 75 720.9 640.4 67.7 129.1 75.2 100 1.62 22 679.6 587.2 75 75 754.6 662.2 73.8 141.7 81.4 100 1.62 25 712.7 609.1 75 75 787.7 684.1 80.1 154.2 87.7 100 1.80 13 491.8 448.5 75 75 566.8 523.5 68.8 130.1 78.3 100 1.80 16 520.8 468.8 75 75 595.8 543.8 76.5 145.6 86.1 100 1.80 19 549.1 488.5 75 75 624.1 563.5 84.2 161.2 93.9 100 1.80 22 577.5 509.4 75 75 652.5 584.4 92.3 176.8 101.7 100 1.80 25 607.7 529.0 75 75 682.7 604.0 99.9 192.4 109.5 100 1.98 13 427.3 398.4 75 75 502.3 473.4 83.5 158.0 95.0 100 1.98 16 453.9 418.6 75 75 528.9 493.6 93.1 176.9 104.5 108

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Appendix A (Continued) 100 1.98 19 479.0 437.3 75 75 554.0 512.3 102.5 195.8 113.9 100 1.98 22 504.4 456.2 75 75 579.4 531.2 112.0 214.8 123.4 100 1.98 25 534.0 475.8 75 75 609.0 550.8 121.3 234.2 133.1 125 1.62 13 634.1 566.3 75 75 709.1 641.3 55.3 104.5 62.9 125 1.62 16 670.0 589.5 75 75 745.0 664.5 61.6 117.1 69.2 125 1.62 19 705.2 612.7 75 75 780.2 687.7 67.9 129.7 75.5 125 1.62 22 740.1 635.8 75 75 815.1 710.8 74.2 142.2 81.8 125 1.62 25 776.1 658.5 75 75 851.1 733.5 80.4 154.6 88.0 125 1.80 13 532.5 485.5 75 75 607.5 560.5 68.9 130.6 78.6 125 1.80 16 564.5 506.6 75 75 639.5 581.6 76.7 146.2 86.4 125 1.80 19 594.8 528.0 75 75 669.8 603.0 84.4 161.7 94.1 125 1.80 22 625.9 549.4 75 75 700.9 624.4 92.3 177.3 102.0 125 1.80 25 658.1 569.9 75 75 733.1 644.9 100.1 193.0 109.8 125 1.98 13 459.4 427.6 75 75 534.4 502.6 84.1 158.6 95.5 125 1.98 16 487.1 447.5 75 75 562.1 522.5 93.4 177.4 104.8 125 1.98 19 514.8 467.4 75 75 589.8 542.4 102.9 196.4 114.4 125 1.98 22 542.2 487.7 75 75 617.2 562.7 112.4 215.4 123.9 125 1.98 25 570.8 507.5 75 75 645.8 582.5 122.0 234.4 133.4 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 13 28.3 27.6 23.6 22.3 22.4 21.5 21.2 24.7 20.7 0 1.62 16 28.3 28.9 24.1 22.5 22.4 21.5 21.2 25.3 26.4 0 1.62 19 28.4 30.2 24.7 22.9 22.4 21.5 21.2 25.9 31.9 0 1.62 22 28.4 31.4 25.1 23.0 22.4 21.5 21.2 26.4 37.8 0 1.62 25 28.4 32.6 25.6 23.2 22.4 21.5 21.2 27.0 44.0 0 1.80 13 35.6 34.7 29.6 28.0 28.1 27.0 26.6 31.0 28.4 0 1.80 16 35.6 36.2 30.2 28.2 28.1 27.0 26.6 31.7 35.6 0 1.80 19 35.6 37.8 30.9 28.6 28.1 27.0 26.6 32.4 43.7 0 1.80 22 35.6 39.3 31.4 28.9 28.1 27.0 26.6 33.1 53.1 0 1.80 25 35.6 40.7 32.0 29.1 28.1 27.0 26.6 33.8 62.7 0 1.98 13 44.3 43.1 36.9 34.9 35.3 33.9 33.5 38.7 38.7 0 1.98 16 44.3 45.2 37.9 35.5 35.3 33.9 33.5 39.7 48.4 0 1.98 19 44.4 47.1 38.6 35.8 35.3 33.9 33.5 40.6 60.4 0 1.98 22 44.4 48.9 39.4 36.2 35.3 33.9 33.5 41.4 71.9 0 1.98 25 44.4 50.9 40.2 36.6 35.3 33.9 33.5 42.3 83.0 25 1.62 13 28.4 27.8 23.7 22.4 22.5 21.6 21.3 24.8 20.3 25 1.62 16 28.4 29.2 24.4 22.8 22.5 21.6 21.3 25.4 26.0 25 1.62 19 28.5 30.3 24.8 22.9 22.5 21.6 21.3 26.0 31.6 25 1.62 22 28.5 31.5 25.2 23.1 22.5 21.6 21.3 26.6 36.9 25 1.62 25 28.5 32.9 25.8 23.5 22.5 21.6 21.3 27.2 43.1 25 1.80 13 35.8 34.8 29.8 28.1 28.4 27.2 26.8 31.2 28.1 25 1.80 16 35.8 36.4 30.5 28.5 28.4 27.2 26.8 32.0 35.9 25 1.80 19 35.8 38.0 31.1 28.8 28.4 27.2 26.9 32.7 43.5 25 1.80 22 35.8 39.4 31.5 28.9 28.4 27.2 26.9 33.3 52.7 25 1.80 25 35.8 40.9 32.2 29.2 28.4 27.2 26.9 34.0 60.3 25 1.98 13 44.1 43.3 37.2 35.1 35.1 33.7 33.2 38.7 37.6 25 1.98 16 44.1 45.2 37.9 35.4 35.1 33.7 33.2 39.6 47.2 25 1.98 19 44.1 46.8 38.4 35.6 35.1 33.7 33.2 40.3 57.6 25 1.98 22 44.2 49.1 39.5 36.4 35.1 33.7 33.2 41.4 69.1 25 1.98 25 44.2 50.8 40.2 36.6 35.1 33.7 33.2 42.2 81.3 50 1.62 13 28.6 27.8 23.8 22.4 22.6 21.7 21.3 24.9 20.2 50 1.62 16 28.6 29.0 24.2 22.6 22.6 21.7 21.3 25.4 25.9 50 1.62 19 28.6 30.3 24.7 22.9 22.6 21.7 21.3 26.0 30.8 109

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Appendix A (Continued) 50 1.62 22 28.6 31.6 25.3 23.2 22.6 21.7 21.3 26.6 37.1 50 1.62 25 28.6 32.8 25.7 23.4 22.6 21.7 21.3 27.2 42.6 50 1.80 13 35.6 34.4 29.4 27.7 28.1 26.9 26.5 30.9 28.1 50 1.80 16 35.6 36.0 30.0 28.1 28.1 26.9 26.5 31.6 34.9 50 1.80 19 35.6 37.5 30.6 28.3 28.1 26.9 26.6 32.3 42.9 50 1.80 22 35.6 39.2 31.3 28.7 28.1 26.9 26.5 33.0 51.4 50 1.80 25 35.6 40.7 31.9 29.0 28.1 26.9 26.5 33.8 59.6 50 1.98 13 43.8 42.6 36.4 34.4 34.6 33.2 32.7 38.1 36.5 50 1.98 16 43.8 44.4 37.1 34.6 34.6 33.2 32.7 38.9 46.3 50 1.98 19 43.8 46.4 38.0 35.2 34.6 33.2 32.7 39.9 57.2 50 1.98 22 43.8 48.1 38.6 35.4 34.6 33.2 32.7 40.7 68.6 50 1.98 25 43.8 50.0 39.2 35.7 34.6 33.2 32.7 41.5 79.8 75 1.62 13 28.6 27.8 23.7 22.3 22.6 21.7 21.4 24.9 20.2 75 1.62 16 28.6 29.0 24.1 22.5 22.6 21.7 21.4 25.4 25.4 75 1.62 19 28.7 30.2 24.6 22.8 22.6 21.7 21.4 26.0 31.2 75 1.62 22 28.7 31.4 25.1 23.0 22.6 21.7 21.4 26.6 36.6 75 1.62 25 28.7 32.7 25.6 23.3 22.6 21.7 21.4 27.1 42.5 75 1.80 13 35.7 34.8 29.7 28.1 28.2 27.0 26.7 31.1 27.4 75 1.80 16 35.8 36.3 30.3 28.3 28.2 27.0 26.7 31.8 35.1 75 1.80 19 35.8 37.9 31.0 28.7 28.2 27.0 26.7 32.5 42.3 75 1.80 22 35.8 39.6 31.8 29.2 28.2 27.0 26.7 33.3 50.5 75 1.80 25 35.8 41.2 32.4 29.4 28.2 27.0 26.7 34.1 58.7 75 1.98 13 43.8 42.3 36.1 34.0 34.6 33.2 32.7 37.9 36.4 75 1.98 16 43.8 44.2 36.9 34.4 34.6 33.2 32.7 38.8 45.0 75 1.98 19 43.8 46.1 37.7 34.8 34.6 33.2 32.7 39.7 56.9 75 1.98 22 43.9 47.9 38.3 35.1 34.6 33.2 32.7 40.6 67.2 75 1.98 25 43.8 49.7 39.0 35.4 34.6 33.2 32.7 41.4 80.1 100 1.62 13 28.7 27.9 23.9 22.5 22.7 21.8 21.5 25.0 20.1 100 1.62 16 28.7 29.2 24.4 22.8 22.7 21.8 21.5 25.6 25.5 100 1.62 19 28.7 30.5 24.9 23.1 22.7 21.8 21.5 26.2 30.7 100 1.62 22 28.8 31.7 25.3 23.2 22.7 21.8 21.5 26.7 36.7 100 1.62 25 28.8 32.9 25.8 23.4 22.7 21.8 21.5 27.3 42.2 100 1.80 13 36.0 35.0 29.9 28.2 28.4 27.2 26.8 31.3 26.8 100 1.80 16 36.0 36.5 30.5 28.5 28.4 27.2 26.8 32.0 34.2 100 1.80 19 36.0 38.0 31.1 28.7 28.4 27.2 26.9 32.7 42.4 100 1.80 22 36.0 39.6 31.6 29.0 28.4 27.2 26.8 33.4 49.7 100 1.80 25 36.1 41.2 32.4 29.5 28.4 27.2 26.9 34.2 58.5 100 1.98 13 43.6 42.1 35.9 33.8 34.4 33.0 32.5 37.7 36.0 100 1.98 16 43.6 44.0 36.7 34.3 34.4 33.0 32.5 38.7 44.8 100 1.98 19 43.6 45.9 37.4 34.6 34.4 33.0 32.5 39.5 55.2 100 1.98 22 43.7 47.8 38.2 35.0 34.4 33.0 32.5 40.4 66.0 100 1.98 25 43.7 49.6 38.8 35.2 34.4 33.0 32.5 41.2 78.3 125 1.62 13 28.9 28.0 23.9 22.6 22.8 21.8 21.5 25.1 20.2 125 1.62 16 28.9 29.4 24.5 22.9 22.8 21.8 21.5 25.7 25.4 125 1.62 19 28.9 30.6 25.0 23.1 22.8 21.8 21.5 26.3 30.8 125 1.62 22 29.0 31.9 25.5 23.4 22.8 21.9 21.5 26.9 36.3 125 1.62 25 29.1 33.1 26.0 23.6 22.8 21.8 21.5 27.4 42.1 125 1.80 13 36.3 34.9 29.8 28.1 28.6 27.4 27.1 31.3 27.4 125 1.80 16 36.3 36.3 30.2 28.2 28.6 27.4 27.1 32.0 33.9 125 1.80 19 36.3 37.9 31.0 28.6 28.6 27.4 27.1 32.8 41.5 125 1.80 22 36.3 39.6 31.7 29.1 28.6 27.4 27.1 33.5 49.9 125 1.80 25 36.3 41.2 32.4 29.4 28.6 27.4 27.1 34.3 57.6 125 1.98 13 43.8 42.8 36.6 34.5 34.5 33.1 32.6 38.2 35.5 125 1.98 16 43.8 44.6 37.3 34.8 34.5 33.1 32.6 39.0 44.4 110

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Appendix A (Continued) 125 1.98 19 43.8 46.5 38.0 35.2 34.5 33.1 32.6 39.9 54.4 125 1.98 22 43.8 48.4 38.8 35.5 34.5 33.1 32.6 40.7 65.9 125 1.98 25 43.8 50.3 39.5 35.9 34.5 33.1 32.6 41.6 77.2 Run completed Sun May 22 22:58:22 US/Eastern 2005 in 4380 seconds. tg3ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 29 Setup: 75p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 29 459.2 434.3 75 75 534.2 509.3 91.3 180.4 101.2 0 1.62 33 482.6 449.7 75 75 557.6 524.7 99.9 197.7 109.9 0 1.62 37 501.0 465.7 75 75 576.0 540.7 108.3 214.2 118.2 0 1.62 41 521.4 482.5 75 75 596.4 557.5 116.5 230.7 126.4 0 1.62 45 540.4 498.1 75 75 615.4 573.1 124.9 247.4 134.8 0 1.80 29 406.0 393.8 75 75 481.0 468.8 114.7 225.7 127.0 0 1.80 33 423.5 409.3 75 75 498.5 484.3 125.0 246.5 137.3 0 1.80 37 441.6 424.7 75 75 516.6 499.7 135.4 267.5 147.8 0 1.80 41 460.2 440.5 75 75 535.2 515.5 145.6 288.4 158.3 0 1.80 45 478.0 455.5 75 75 553.0 530.5 155.7 308.9 168.6 0 1.98 29 366.1 360.6 75 75 441.1 435.6 140.3 276.3 155.8 0 1.98 33 384.4 375.1 75 75 459.4 450.1 153.1 302.0 168.6 0 1.98 37 400.1 389.3 75 75 475.1 464.3 165.9 327.1 181.2 0 1.98 41 417.7 404.6 75 75 492.7 479.6 178.5 352.3 193.8 0 1.98 45 433.7 419.7 75 75 508.7 494.7 191.1 377.3 206.3 25 1.62 29 507.6 475.0 75 75 582.6 550.0 91.7 181.5 101.8 25 1.62 33 528.1 492.9 75 75 603.1 567.9 100.0 198.2 110.0 25 1.62 37 550.2 509.6 75 75 625.2 584.6 108.4 214.8 118.4 25 1.62 41 570.8 526.0 75 75 645.8 601.0 116.7 231.5 126.7 25 1.62 45 593.7 543.7 75 75 668.7 618.7 124.9 248.1 135.0 25 1.80 29 446.3 422.5 75 75 521.3 497.5 114.6 226.1 127.1 25 1.80 33 466.1 437.8 75 75 541.1 512.8 125.0 246.8 137.5 25 1.80 37 485.0 454.8 75 75 560.0 529.8 135.3 267.6 147.8 25 1.80 41 504.3 470.4 75 75 579.3 545.4 145.5 288.3 158.1 25 1.80 45 524.3 487.0 75 75 599.3 562.0 155.8 308.9 168.5 25 1.98 29 399.2 385.0 75 75 474.2 460.0 140.2 276.5 155.7 25 1.98 33 416.7 400.4 75 75 491.7 475.4 152.7 302.0 168.3 25 1.98 37 434.2 416.4 75 75 509.2 491.4 165.4 326.8 180.8 25 1.98 41 452.3 431.7 75 75 527.3 506.7 177.9 352.1 193.5 25 1.98 45 470.8 446.6 75 75 545.8 521.6 190.1 377.1 205.9 50 1.62 29 552.0 519.2 75 75 627.0 594.2 91.8 181.8 102.1 50 1.62 33 576.0 536.6 75 75 651.0 611.6 100.3 198.4 110.5 50 1.62 37 599.2 555.0 75 75 674.2 630.0 108.6 215.0 118.8 50 1.62 41 623.2 573.1 75 75 698.2 648.1 116.9 231.8 127.1 50 1.62 45 647.0 590.4 75 75 722.0 665.4 125.2 248.3 135.4 50 1.80 29 484.0 460.1 75 75 559.0 535.1 114.7 226.7 127.3 50 1.80 33 504.5 476.6 75 75 579.5 551.6 124.9 247.3 137.6 50 1.80 37 525.4 493.4 75 75 600.4 568.4 135.4 267.9 147.9 50 1.80 41 547.1 510.8 75 75 622.1 585.8 145.7 288.7 158.3 50 1.80 45 568.7 527.4 75 75 643.7 602.4 156.0 309.4 168.6 50 1.98 29 430.2 417.9 75 75 505.2 492.9 139.8 276.5 155.5 50 1.98 33 448.8 433.8 75 75 523.8 508.8 152.3 301.4 167.9 50 1.98 37 467.8 449.3 75 75 542.8 524.3 164.8 326.4 180.4 111

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Appendix A (Continued) 50 1.98 41 490.4 466.6 75 75 565.4 541.6 177.8 352.6 193.5 50 1.98 45 509.4 482.2 75 75 584.4 557.2 190.3 377.8 206.1 75 1.62 29 605.7 564.7 75 75 680.7 639.7 92.1 182.1 102.4 75 1.62 33 631.2 584.1 75 75 706.2 659.1 100.4 198.9 110.8 75 1.62 37 656.9 603.3 75 75 731.9 678.3 108.9 215.6 119.1 75 1.62 41 682.7 621.7 75 75 757.7 696.7 117.3 232.2 127.5 75 1.62 45 709.5 641.3 75 75 784.5 716.3 125.7 249.1 135.9 75 1.80 29 525.4 496.8 75 75 600.4 571.8 115.0 227.4 127.8 75 1.80 33 547.6 513.4 75 75 622.6 588.4 125.2 248.1 138.1 75 1.80 37 570.4 532.0 75 75 645.4 607.0 135.6 268.9 148.5 75 1.80 41 594.0 549.6 75 75 669.0 624.6 146.2 289.5 158.9 75 1.80 45 617.2 567.0 75 75 692.2 642.0 156.4 310.3 169.3 75 1.98 29 463.9 444.8 75 75 538.9 519.8 139.8 277.0 155.5 75 1.98 33 485.1 462.1 75 75 560.1 537.1 152.4 302.2 168.2 75 1.98 37 505.7 479.2 75 75 580.7 554.2 165.0 327.4 180.7 75 1.98 41 526.1 495.5 75 75 601.1 570.5 177.6 352.7 193.4 75 1.98 45 548.4 512.7 75 75 623.4 587.7 190.3 377.8 206.0 100 1.62 29 659.1 616.6 75 75 734.1 691.6 92.3 182.9 102.7 100 1.62 33 686.4 636.6 75 75 761.4 711.6 100.7 199.7 111.1 100 1.62 37 714.6 656.6 75 75 789.6 731.6 109.1 216.3 119.5 100 1.62 41 743.0 677.1 75 75 818.0 752.1 117.4 233.0 127.9 100 1.62 45 770.8 696.7 75 75 845.8 771.7 125.6 249.4 136.1 100 1.80 29 566.8 535.5 75 75 641.8 610.5 115.1 227.4 127.8 100 1.80 33 591.0 554.2 75 75 666.0 629.2 125.4 248.2 138.2 100 1.80 37 616.2 572.2 75 75 691.2 647.2 135.8 269.0 148.6 100 1.80 41 641.0 591.2 75 75 716.0 666.2 146.3 289.7 159.0 100 1.80 45 667.1 610.2 75 75 742.1 685.2 156.7 310.7 169.5 100 1.98 29 500.3 476.0 75 75 575.3 551.0 140.2 277.6 155.9 100 1.98 33 522.2 493.8 75 75 597.2 568.8 152.8 302.9 168.5 100 1.98 37 544.3 510.9 75 75 619.3 585.9 165.5 328.2 181.1 100 1.98 41 567.4 528.8 75 75 642.4 603.8 178.1 353.5 193.8 100 1.98 45 589.5 546.5 75 75 664.5 621.5 190.9 378.7 206.4 125 1.62 29 717.6 667.6 75 75 792.6 742.6 92.6 183.3 102.9 125 1.62 33 748.4 689.6 75 75 823.4 764.6 101.0 199.9 111.3 125 1.62 37 778.6 710.7 75 75 853.6 785.7 109.3 216.6 119.7 125 1.62 41 808.7 732.0 75 75 883.7 807.0 117.5 233.0 128.0 125 1.62 45 840.2 753.4 75 75 915.2 828.4 126.0 249.3 136.4 125 1.80 29 613.8 573.4 75 75 688.8 648.4 115.3 228.3 128.1 125 1.80 33 640.4 593.0 75 75 715.4 668.0 125.7 249.0 138.6 125 1.80 37 666.9 612.9 75 75 741.9 687.9 136.1 269.9 149.0 125 1.80 41 694.4 632.0 75 75 769.4 707.0 146.6 290.8 159.4 125 1.80 45 721.1 652.1 75 75 796.1 727.1 156.8 311.3 169.8 125 1.98 29 536.2 507.5 75 75 611.2 582.5 140.4 278.1 156.2 125 1.98 33 559.5 526.3 75 75 634.5 601.3 153.1 303.4 168.8 125 1.98 37 582.9 544.7 75 75 657.9 619.7 165.7 328.8 181.5 125 1.98 41 607.8 562.3 75 75 682.8 637.3 178.3 353.9 194.1 125 1.98 45 631.6 581.4 75 75 706.6 656.4 191.2 379.2 206.9 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 29 32.0 36.1 27.8 25.0 24.1 22.8 22.4 29.5 48.9 0 1.62 33 32.1 37.7 28.4 25.3 24.1 22.8 22.4 30.2 56.5 0 1.62 37 32.1 39.5 29.2 25.8 24.1 22.9 22.4 31.1 63.9 0 1.62 41 32.1 41.2 29.9 26.1 24.1 22.9 22.4 31.9 72.9 112

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Appendix A (Continued) 0 1.62 45 32.1 42.9 30.6 26.5 24.1 22.9 22.4 32.6 81.7 0 1.80 29 40.8 45.4 35.1 31.7 30.6 29.1 28.6 37.3 68.2 0 1.80 33 40.8 47.5 35.9 32.1 30.6 29.1 28.6 38.3 79.5 0 1.80 37 40.8 49.6 36.8 32.5 30.6 29.1 28.6 39.2 91.3 0 1.80 41 40.8 51.8 37.8 33.0 30.6 29.1 28.6 40.3 104.1 0 1.80 45 40.8 53.5 38.2 33.1 30.7 29.1 28.6 41.1 114.9 0 1.98 29 50.6 56.1 43.5 39.3 38.3 36.4 35.8 46.3 91.4 0 1.98 33 50.6 58.7 44.6 39.8 38.3 36.4 35.8 47.5 106.5 0 1.98 37 50.7 61.5 45.8 40.6 38.3 36.4 35.8 48.8 123.5 0 1.98 41 50.7 64.2 47.0 41.3 38.3 36.4 35.8 50.1 140.8 0 1.98 45 50.7 66.5 47.8 41.6 38.3 36.4 35.8 51.1 159.2 25 1.62 29 32.3 36.1 27.7 24.9 24.1 22.9 22.5 29.5 47.7 25 1.62 33 32.3 37.7 28.4 25.2 24.1 22.9 22.5 30.3 55.4 25 1.62 37 32.3 39.5 29.2 25.7 24.1 22.9 22.5 31.1 62.9 25 1.62 41 32.3 41.1 29.8 26.1 24.1 22.9 22.5 31.9 72.1 25 1.62 45 32.4 42.7 30.3 26.2 24.1 22.9 22.5 32.6 80.1 25 1.80 29 40.5 45.4 35.0 31.5 30.4 28.9 28.4 37.1 67.5 25 1.80 33 40.5 47.5 35.8 32.0 30.4 28.9 28.4 38.1 77.0 25 1.80 37 40.5 49.5 36.6 32.3 30.5 28.9 28.4 39.1 90.2 25 1.80 41 40.6 51.5 37.4 32.6 30.5 28.9 28.4 40.0 100.6 25 1.80 45 40.6 53.4 38.0 32.9 30.5 28.9 28.4 40.9 113.7 25 1.98 29 50.2 56.0 43.3 39.1 37.7 35.9 35.2 46.0 87.7 25 1.98 33 50.2 58.1 43.9 39.2 37.8 35.9 35.2 46.9 104.1 25 1.98 37 50.2 61.0 45.3 40.1 37.8 35.9 35.2 48.3 121.5 25 1.98 41 50.2 63.4 46.2 40.4 37.8 35.9 35.3 49.4 139.9 25 1.98 45 50.2 65.5 46.7 40.5 37.8 35.9 35.3 50.3 155.5 50 1.62 29 32.5 36.2 27.9 25.1 24.3 23.1 22.7 29.7 47.6 50 1.62 33 32.5 37.9 28.5 25.4 24.3 23.1 22.7 30.4 55.1 50 1.62 37 32.5 39.6 29.3 25.9 24.3 23.1 22.7 31.3 62.9 50 1.62 41 32.6 41.3 30.0 26.2 24.3 23.1 22.7 32.0 71.2 50 1.62 45 32.6 43.0 30.6 26.5 24.3 23.1 22.7 32.8 79.7 50 1.80 29 40.4 45.3 34.9 31.5 30.2 28.7 28.2 37.0 65.8 50 1.80 33 40.4 47.2 35.5 31.6 30.2 28.7 28.2 37.9 75.0 50 1.80 37 40.4 49.6 36.7 32.4 30.2 28.7 28.2 39.0 88.9 50 1.80 41 40.4 51.4 37.2 32.5 30.2 28.7 28.2 39.8 98.7 50 1.80 45 40.4 53.4 38.1 33.0 30.2 28.7 28.2 40.8 111.3 50 1.98 29 50.0 55.3 42.6 38.4 37.6 35.7 35.1 45.5 87.8 50 1.98 33 50.0 57.9 43.7 38.9 37.6 35.7 35.1 46.7 104.6 50 1.98 37 50.1 60.4 44.7 39.4 37.6 35.7 35.1 47.9 118.2 50 1.98 41 50.1 62.9 45.6 39.8 37.6 35.7 35.1 49.0 134.7 50 1.98 45 50.2 65.4 46.6 40.3 37.6 35.7 35.1 50.2 153.5 75 1.62 29 32.7 36.2 27.8 25.0 24.5 23.3 22.9 29.8 47.4 75 1.62 33 32.7 37.9 28.5 25.4 24.5 23.3 22.9 30.5 55.2 75 1.62 37 32.7 39.8 29.4 25.9 24.5 23.3 22.9 31.4 62.6 75 1.62 41 32.8 41.5 30.1 26.3 24.5 23.3 22.9 32.2 70.8 75 1.62 45 32.9 43.3 30.9 26.8 24.5 23.3 22.9 33.1 79.2 75 1.80 29 41.0 45.4 35.0 31.5 30.7 29.1 28.6 37.3 64.8 75 1.80 33 41.0 47.4 35.7 31.8 30.7 29.1 28.6 38.2 77.0 75 1.80 37 41.0 49.4 36.5 32.2 30.7 29.1 28.6 39.2 87.0 75 1.80 41 41.0 52.0 37.8 33.1 30.7 29.1 28.6 40.3 99.7 75 1.80 45 41.1 53.8 38.4 33.3 30.7 29.1 28.6 41.2 111.8 75 1.98 29 49.7 55.2 42.5 38.3 37.1 35.1 34.5 45.2 86.4 75 1.98 33 49.7 57.7 43.5 38.8 37.1 35.1 34.5 46.4 100.6 75 1.98 37 49.8 60.2 44.5 39.3 37.1 35.1 34.5 47.5 117.2 113

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Appendix A (Continued) 75 1.98 41 49.8 62.8 45.5 39.8 37.1 35.2 34.5 48.7 134.0 75 1.98 45 49.8 65.3 46.6 40.3 37.1 35.2 34.5 49.9 151.4 100 1.62 29 32.8 36.3 27.9 25.1 24.5 23.3 22.8 29.8 47.6 100 1.62 33 32.9 38.0 28.6 25.4 24.5 23.3 22.8 30.6 54.5 100 1.62 37 32.9 39.6 29.3 25.8 24.5 23.3 22.8 31.4 62.5 100 1.62 41 33.0 41.3 29.9 26.1 24.5 23.3 22.8 32.1 70.8 100 1.62 45 33.2 43.0 30.6 26.4 24.5 23.3 22.8 32.9 79.7 100 1.80 29 40.9 45.5 35.1 31.6 30.6 29.1 28.5 37.3 63.8 100 1.80 33 40.9 47.6 35.9 32.0 30.6 29.1 28.5 38.3 74.4 100 1.80 37 40.9 49.8 36.8 32.5 30.6 29.1 28.5 39.3 86.1 100 1.80 41 41.0 52.0 37.9 33.2 30.6 29.1 28.5 40.4 98.1 100 1.80 45 41.1 53.8 38.4 33.2 30.6 29.1 28.5 41.2 110.4 100 1.98 29 49.8 55.3 42.6 38.4 37.1 35.2 34.6 45.3 84.4 100 1.98 33 49.8 57.8 43.5 38.8 37.1 35.2 34.6 46.4 99.5 100 1.98 37 49.8 60.4 44.6 39.4 37.1 35.2 34.6 47.6 115.6 100 1.98 41 49.8 62.9 45.7 39.9 37.1 35.2 34.6 48.8 131.4 100 1.98 45 49.8 65.7 46.9 40.7 37.1 35.2 34.6 50.1 148.6 125 1.62 29 33.0 36.6 28.2 25.4 24.7 23.4 23.0 30.0 47.3 125 1.62 33 33.1 38.2 28.8 25.7 24.7 23.4 23.0 30.8 54.4 125 1.62 37 33.2 39.8 29.4 25.9 24.7 23.4 23.0 31.5 62.7 125 1.62 41 33.4 41.4 30.0 26.2 24.7 23.4 23.0 32.2 70.6 125 1.62 45 33.8 43.1 30.6 26.5 24.7 23.4 23.0 33.0 78.8 125 1.80 29 41.1 45.6 35.2 31.7 30.7 29.1 28.6 37.4 63.9 125 1.80 33 41.1 47.7 36.0 32.1 30.7 29.1 28.6 38.4 74.1 125 1.80 37 41.1 49.8 36.9 32.5 30.7 29.1 28.6 39.4 85.2 125 1.80 41 41.2 51.9 37.7 33.0 30.7 29.1 28.6 40.3 96.8 125 1.80 45 41.3 53.8 38.3 33.2 30.7 29.1 28.6 41.2 109.4 125 1.98 29 50.0 55.4 42.7 38.4 37.3 35.4 34.8 45.5 84.2 125 1.98 33 50.0 58.0 43.8 39.0 37.3 35.4 34.8 46.7 98.4 125 1.98 37 50.0 60.5 44.7 39.4 37.3 35.4 34.8 47.8 113.1 125 1.98 41 50.0 63.1 45.8 40.0 37.3 35.4 34.8 49.0 128.9 125 1.98 45 50.1 65.7 46.8 40.6 37.3 35.4 34.8 50.2 146.6 Run completed Mon May 23 0:10:36 US/Eastern 2005 in 4333 seconds. tg4ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 50 Setup: 100p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 50 519.6 504.2 100 100 619.6 604.2 148.7 292.0 162.2 0 1.62 55 537.3 519.5 100 100 637.3 619.5 159.0 312.9 172.6 0 1.62 60 554.1 533.9 100 100 654.1 633.9 169.3 333.8 183.0 0 1.62 65 573.0 547.8 100 100 673.0 647.8 179.8 354.6 193.4 0 1.62 70 590.8 562.4 100 100 690.8 662.4 190.2 375.5 203.8 0 1.80 50 464.2 455.5 100 100 564.2 555.5 185.2 364.0 202.3 0 1.80 55 481.1 469.7 100 100 581.1 569.7 198.2 390.3 215.5 0 1.80 60 497.2 483.8 100 100 597.2 583.8 210.9 415.8 228.2 0 1.80 65 513.0 497.2 100 100 613.0 597.2 224.1 441.5 241.1 0 1.80 70 529.7 510.4 100 100 629.7 610.4 237.1 467.5 254.1 0 1.98 50 424.9 418.6 100 100 524.9 518.6 227.1 445.2 247.9 0 1.98 55 439.3 431.7 100 100 539.3 531.7 242.7 476.3 263.4 0 1.98 60 454.8 445.7 100 100 554.8 545.7 258.4 508.2 279.3 0 1.98 65 470.4 459.0 100 100 570.4 559.0 274.0 539.2 294.9 114

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Appendix A (Continued) 0 1.98 70 484.8 471.9 100 100 584.8 571.9 289.8 570.4 310.5 25 1.62 50 573.3 546.4 100 100 673.3 646.4 148.7 292.9 162.6 25 1.62 55 592.2 562.1 100 100 692.2 662.1 159.1 313.6 172.9 25 1.62 60 612.1 577.0 100 100 712.1 677.0 169.4 334.3 183.2 25 1.62 65 632.0 591.8 100 100 732.0 691.8 179.9 355.3 193.8 25 1.62 70 650.9 607.7 100 100 750.9 707.7 190.1 375.9 204.0 25 1.80 50 504.6 492.1 100 100 604.6 592.1 185.2 364.9 202.6 25 1.80 55 522.6 506.8 100 100 622.6 606.8 198.0 390.7 215.5 25 1.80 60 539.7 520.9 100 100 639.7 620.9 211.0 416.7 228.5 25 1.80 65 558.5 535.0 100 100 658.5 635.0 223.9 442.6 241.4 25 1.80 70 576.4 550.0 100 100 676.4 650.0 236.8 468.3 254.3 25 1.98 50 458.8 448.7 100 100 558.8 548.7 226.1 445.1 247.7 25 1.98 55 474.3 463.4 100 100 574.3 563.4 241.9 476.5 263.4 25 1.98 60 491.4 477.4 100 100 591.4 577.4 257.4 508.1 279.2 25 1.98 65 508.2 490.9 100 100 608.2 590.9 273.3 539.5 294.9 25 1.98 70 524.1 504.7 100 100 624.1 604.7 289.2 570.9 310.7 50 1.62 50 625.1 592.1 100 100 725.1 692.1 148.9 293.3 162.8 50 1.62 55 647.1 607.8 100 100 747.1 707.8 159.4 314.2 173.3 50 1.62 60 667.8 624.3 100 100 767.8 724.3 169.9 335.0 183.7 50 1.62 65 690.4 640.5 100 100 790.4 740.5 180.4 355.9 194.2 50 1.62 70 711.7 656.3 100 100 811.7 756.3 190.8 376.5 204.6 50 1.80 50 551.4 528.5 100 100 651.4 628.5 185.8 365.9 203.2 50 1.80 55 570.3 543.8 100 100 670.3 643.8 198.8 391.9 216.3 50 1.80 60 589.9 558.5 100 100 689.9 658.5 211.7 417.7 229.1 50 1.80 65 609.6 573.8 100 100 709.6 673.8 224.7 443.4 242.1 50 1.80 70 628.6 589.3 100 100 728.6 689.3 237.7 469.4 255.1 50 1.98 50 496.0 483.4 100 100 596.0 583.4 226.8 447.1 248.3 50 1.98 55 513.6 498.1 100 100 613.6 598.1 242.8 478.6 264.1 50 1.98 60 530.7 512.4 100 100 630.7 612.4 258.4 509.9 279.8 50 1.98 65 549.6 526.5 100 100 649.6 626.5 274.2 541.5 295.6 50 1.98 70 567.5 541.6 100 100 667.5 641.6 289.9 572.9 311.4 75 1.62 50 680.0 643.2 100 100 780.0 743.2 149.3 293.7 163.0 75 1.62 55 703.2 660.1 100 100 803.2 760.1 159.6 314.7 173.5 75 1.62 60 726.8 677.8 100 100 826.8 777.8 170.1 335.3 183.9 75 1.62 65 749.8 694.6 100 100 849.8 794.6 180.4 355.9 194.3 75 1.62 70 774.1 711.5 100 100 874.1 811.5 190.8 376.4 204.7 75 1.80 50 596.7 566.6 100 100 696.7 666.6 186.1 366.4 203.5 75 1.80 55 617.7 582.8 100 100 717.7 682.8 199.0 392.3 216.5 75 1.80 60 638.3 598.4 100 100 738.3 698.4 212.0 418.2 229.4 75 1.80 65 660.1 614.4 100 100 760.1 714.4 224.9 444.0 242.3 75 1.80 70 680.9 630.7 100 100 780.9 730.7 238.0 469.9 255.4 75 1.98 50 531.7 513.6 100 100 631.7 613.6 226.5 446.4 247.9 75 1.98 55 550.7 529.2 100 100 650.7 629.2 242.4 478.0 263.7 75 1.98 60 570.2 544.4 100 100 670.2 644.4 258.1 509.5 279.4 75 1.98 65 588.8 559.2 100 100 688.8 659.2 273.9 541.1 295.3 75 1.98 70 609.1 574.3 100 100 709.1 674.3 289.6 572.4 311.0 100 1.62 50 739.6 699.9 100 100 839.6 799.9 149.8 294.8 163.9 100 1.62 55 765.0 717.5 100 100 865.0 817.5 160.0 315.5 174.2 100 1.62 60 790.3 735.9 100 100 890.3 835.9 170.5 336.0 184.6 100 1.62 65 815.8 754.2 100 100 915.8 854.2 181.0 356.6 195.2 100 1.62 70 841.9 771.5 100 100 941.9 871.5 191.5 376.8 205.6 100 1.80 50 643.3 609.5 100 100 743.3 709.5 186.1 366.4 203.5 100 1.80 55 665.4 625.9 100 100 765.4 725.9 199.1 392.4 216.5 100 1.80 60 688.6 643.3 100 100 788.6 743.3 212.0 418.3 229.5 115

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Appendix A (Continued) 100 1.80 65 711.2 659.8 100 100 811.2 759.8 225.1 444.1 242.5 100 1.80 70 734.7 676.2 100 100 834.7 776.2 238.0 469.9 255.5 100 1.98 50 570.4 547.6 100 100 670.4 647.6 227.2 447.4 248.7 100 1.98 55 591.2 563.6 100 100 691.2 663.6 242.8 478.7 264.3 100 1.98 60 611.1 579.1 100 100 711.1 679.1 258.7 510.3 280.2 100 1.98 65 632.6 594.8 100 100 732.6 694.8 274.4 541.9 295.9 100 1.98 70 653.2 611.0 100 100 753.2 711.0 290.5 573.6 312.0 125 1.62 50 803.5 760.1 100 100 903.5 860.1 150.0 295.0 164.0 125 1.62 55 831.1 778.9 100 100 931.1 878.9 160.3 315.5 174.3 125 1.62 60 858.3 798.4 100 100 958.3 898.4 170.7 335.7 184.7 125 1.62 65 886.3 817.4 100 100 986.3 917.4 181.2 355.7 195.2 125 1.62 70 914.0 835.7 100 100 1014.0 935.7 191.5 374.9 205.6 125 1.80 50 694.1 655.9 100 100 794.1 755.9 186.5 367.5 204.1 125 1.80 55 717.7 674.2 100 100 817.7 774.2 199.6 393.4 217.1 125 1.80 60 742.9 691.6 100 100 842.9 791.6 212.6 419.2 230.1 125 1.80 65 767.0 709.0 100 100 867.0 809.0 225.5 444.9 243.1 125 1.80 70 792.4 726.9 100 100 892.4 826.9 238.5 470.2 256.0 125 1.98 50 610.6 585.5 100 100 710.6 685.5 227.6 448.7 249.1 125 1.98 55 632.6 601.7 100 100 732.6 701.7 243.4 480.2 264.9 125 1.98 60 654.2 618.0 100 100 754.2 718.0 259.2 511.8 280.9 125 1.98 65 676.8 634.9 100 100 776.8 734.9 275.0 543.3 296.6 125 1.98 70 698.2 651.1 100 100 798.2 751.1 290.6 574.7 312.4 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 50 45.8 55.6 41.7 37.0 34.8 33.1 32.5 44.2 85.6 0 1.62 55 45.8 57.7 42.5 37.4 34.8 33.1 32.5 45.2 97.8 0 1.62 60 45.8 59.6 43.2 37.7 34.8 33.1 32.5 46.1 106.9 0 1.62 65 45.9 62.0 44.3 38.4 34.8 33.1 32.5 47.2 120.1 0 1.62 70 45.9 64.0 45.1 38.8 34.8 33.1 32.5 48.1 129.1 0 1.80 50 57.6 69.4 52.1 46.3 43.9 41.9 41.2 55.5 122.9 0 1.80 55 57.7 71.7 52.8 46.4 43.9 41.9 41.2 56.5 136.0 0 1.80 60 57.7 74.4 53.9 47.0 43.9 41.9 41.2 57.7 154.4 0 1.80 65 57.7 77.5 55.5 48.2 43.9 41.9 41.2 59.2 168.2 0 1.80 70 57.7 80.1 56.5 48.7 44.0 41.9 41.2 60.4 185.5 0 1.98 50 71.3 85.8 64.7 57.6 54.7 52.2 51.3 68.8 163.1 0 1.98 55 71.3 89.0 66.0 58.3 54.7 52.2 51.3 70.3 190.2 0 1.98 60 71.4 91.9 66.9 58.6 54.7 52.2 51.3 71.6 210.1 0 1.98 65 71.4 95.1 68.3 59.3 54.7 52.2 51.3 73.1 235.2 0 1.98 70 71.4 98.5 69.8 60.2 54.7 52.2 51.3 74.7 258.1 25 1.62 50 46.0 55.4 41.4 36.7 34.9 33.2 32.7 44.2 86.3 25 1.62 55 46.0 57.5 42.3 37.2 34.9 33.2 32.7 45.2 95.4 25 1.62 60 46.1 59.7 43.2 37.7 34.9 33.2 32.7 46.2 107.6 25 1.62 65 46.1 61.8 44.0 38.1 34.9 33.2 32.7 47.1 117.0 25 1.62 70 46.2 63.8 44.9 38.5 34.9 33.2 32.7 48.1 130.4 25 1.80 50 57.5 69.4 52.0 46.2 43.6 41.4 40.8 55.3 118.9 25 1.80 55 57.5 71.9 52.9 46.6 43.6 41.4 40.8 56.4 136.3 25 1.80 60 57.5 74.5 54.0 47.1 43.6 41.4 40.8 57.6 150.4 25 1.80 65 57.5 77.1 55.1 47.7 43.6 41.5 40.8 58.8 167.6 25 1.80 70 57.5 79.7 56.1 48.2 43.6 41.4 40.8 60.0 184.4 25 1.98 50 70.9 85.1 63.8 56.8 54.0 51.5 50.6 68.0 162.8 25 1.98 55 70.9 88.4 65.3 57.6 54.0 51.5 50.6 69.6 184.3 25 1.98 60 70.9 91.2 66.2 57.9 54.0 51.5 50.6 70.9 209.4 25 1.98 65 70.9 94.5 67.6 58.7 54.0 51.5 50.6 72.4 229.1 116

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Appendix A (Continued) 25 1.98 70 71.0 97.9 69.2 59.6 54.0 51.5 50.6 74.0 254.6 50 1.62 50 46.0 55.5 41.5 36.8 34.9 33.3 32.7 44.3 85.9 50 1.62 55 46.1 57.6 42.3 37.2 35.0 33.3 32.7 45.2 94.6 50 1.62 60 46.1 59.8 43.2 37.7 35.0 33.3 32.7 46.2 106.6 50 1.62 65 46.2 61.8 44.0 38.1 35.0 33.3 32.7 47.2 115.6 50 1.62 70 46.3 63.9 44.9 38.5 35.0 33.3 32.7 48.1 128.0 50 1.80 50 57.8 69.5 52.0 46.2 43.9 41.9 41.2 55.5 119.6 50 1.80 55 57.9 72.1 53.1 46.7 43.9 41.9 41.2 56.7 134.0 50 1.80 60 57.8 74.7 54.1 47.2 43.9 41.9 41.1 57.9 146.5 50 1.80 65 57.9 77.2 55.1 47.7 44.0 41.9 41.2 59.1 163.9 50 1.80 70 58.0 79.8 56.1 48.2 43.9 41.9 41.2 60.3 181.5 50 1.98 50 70.9 85.0 63.8 56.7 53.7 51.1 50.2 67.9 159.0 50 1.98 55 70.9 88.4 65.3 57.6 53.7 51.1 50.2 69.4 183.0 50 1.98 60 71.0 91.6 66.6 58.2 53.7 51.1 50.2 70.9 200.8 50 1.98 65 70.9 94.8 67.8 58.9 53.7 51.1 50.2 72.4 226.5 50 1.98 70 71.0 97.9 69.1 59.5 53.7 51.1 50.2 73.9 248.5 75 1.62 50 46.2 55.8 41.7 37.1 35.0 33.3 32.8 44.4 83.7 75 1.62 55 46.2 57.7 42.4 37.3 35.0 33.3 32.8 45.3 95.0 75 1.62 60 46.4 59.8 43.3 37.8 35.0 33.3 32.8 46.3 105.1 75 1.62 65 46.5 61.9 44.1 38.2 35.0 33.3 32.8 47.2 116.7 75 1.62 70 46.8 64.0 45.0 38.6 35.0 33.3 32.8 48.2 128.4 75 1.80 50 57.9 69.7 52.2 46.4 44.0 41.9 41.1 55.6 117.2 75 1.80 55 58.0 72.2 53.2 46.8 44.0 41.9 41.1 56.8 132.6 75 1.80 60 58.0 74.8 54.2 47.4 44.0 41.9 41.1 58.0 147.7 75 1.80 65 58.1 77.3 55.2 47.8 44.0 41.9 41.1 59.1 162.3 75 1.80 70 58.2 80.0 56.3 48.4 44.0 41.9 41.1 60.4 180.0 75 1.98 50 70.6 84.8 63.6 56.5 53.4 50.9 50.0 67.6 156.2 75 1.98 55 70.6 88.0 64.8 57.1 53.4 50.9 50.0 69.1 178.3 75 1.98 60 70.6 90.9 65.9 57.5 53.4 50.9 50.0 70.5 197.9 75 1.98 65 70.6 94.1 67.1 58.1 53.4 50.8 50.0 71.9 222.2 75 1.98 70 70.7 97.2 68.4 58.8 53.4 50.8 50.0 73.4 242.4 100 1.62 50 46.8 55.9 41.8 37.1 35.4 33.8 33.2 44.7 84.0 100 1.62 55 46.9 57.9 42.6 37.5 35.4 33.8 33.2 45.6 95.0 100 1.62 60 47.0 59.9 43.4 37.8 35.4 33.7 33.2 46.5 105.1 100 1.62 65 47.5 62.0 44.1 38.2 35.5 33.8 33.2 47.5 115.6 100 1.62 70 48.2 64.4 45.4 39.0 35.5 33.8 33.2 48.6 126.8 100 1.80 50 57.9 69.5 52.1 46.4 43.8 41.7 41.0 55.5 116.1 100 1.80 55 58.0 72.2 53.2 46.9 43.9 41.7 41.0 56.7 130.7 100 1.80 60 58.0 74.8 54.2 47.4 43.9 41.7 41.0 57.9 144.7 100 1.80 65 58.2 77.4 55.3 47.9 43.9 41.7 41.0 59.1 161.5 100 1.80 70 58.4 79.8 56.1 48.2 43.9 41.7 41.0 60.2 179.5 100 1.98 50 71.2 85.1 63.8 56.7 54.0 51.4 50.6 68.1 156.1 100 1.98 55 71.2 88.2 65.1 57.3 54.0 51.4 50.6 69.5 175.1 100 1.98 60 71.2 91.5 66.4 58.1 54.0 51.4 50.6 71.0 196.1 100 1.98 65 71.3 94.6 67.7 58.7 54.0 51.4 50.6 72.5 218.9 100 1.98 70 71.4 97.9 69.0 59.3 54.0 51.4 50.6 74.0 241.5 125 1.62 50 46.8 56.0 41.9 37.2 35.3 33.6 33.0 44.7 83.7 125 1.62 55 47.1 58.0 42.7 37.6 35.3 33.6 33.0 45.6 93.8 125 1.62 60 47.7 60.0 43.4 37.9 35.3 33.6 33.0 46.5 103.9 125 1.62 65 48.6 62.2 44.3 38.4 35.3 33.6 33.0 47.5 114.5 125 1.62 70 49.9 64.2 45.1 38.7 35.3 33.6 33.0 48.4 125.2 125 1.80 50 58.1 69.8 52.3 46.5 44.0 41.9 41.2 55.7 114.5 125 1.80 55 58.2 72.5 53.4 47.0 44.0 41.9 41.1 56.9 129.4 125 1.80 60 58.4 75.1 54.4 47.5 44.0 41.9 41.1 58.1 144.9 117

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Appendix A (Continued) 125 1.80 65 58.7 77.7 55.5 48.1 44.0 41.9 41.2 59.3 161.9 125 1.80 70 59.2 80.3 56.5 48.6 44.0 41.9 41.2 60.5 177.4 125 1.98 50 71.2 85.2 63.9 56.8 53.9 51.3 50.4 68.1 152.5 125 1.98 55 71.3 88.4 65.1 57.4 53.9 51.3 50.4 69.5 172.2 125 1.98 60 71.3 91.5 66.3 58.0 53.9 51.3 50.4 71.0 193.8 125 1.98 65 71.5 94.8 67.8 58.7 53.9 51.3 50.4 72.5 212.6 125 1.98 70 71.7 97.6 68.7 59.0 53.9 51.3 50.4 73.8 237.5 Run completed Mon May 23 1:24:55 US/Eastern 2005 in 4459 seconds. tg5ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 76 Setup: 100p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 76 569.8 546.9 100 100 669.8 646.9 205.0 409.3 220.8 0 1.62 82 586.1 559.9 100 100 686.1 659.9 217.3 434.1 233.2 0 1.62 88 603.3 573.5 100 100 703.3 673.5 229.7 458.8 245.6 0 1.62 94 619.6 587.4 100 100 719.6 687.4 242.3 483.9 258.1 0 1.62 100 636.2 600.7 100 100 736.2 700.7 254.6 508.6 270.5 0 1.80 76 510.6 495.4 100 100 610.6 595.4 255.1 509.5 275.1 0 1.80 82 524.9 507.7 100 100 624.9 607.7 270.9 540.5 290.7 0 1.80 88 541.2 521.2 100 100 641.2 621.2 286.4 571.5 306.2 0 1.80 94 556.4 534.2 100 100 656.4 634.2 301.8 602.5 321.7 0 1.80 100 571.1 546.8 100 100 671.1 646.8 317.3 633.8 337.2 0 1.98 76 466.9 455.3 100 100 566.9 555.3 312.4 622.8 336.8 0 1.98 82 480.2 467.7 100 100 580.2 567.7 331.4 660.8 355.7 0 1.98 88 494.9 479.6 100 100 594.9 579.6 349.9 697.8 374.2 0 1.98 94 509.6 492.3 100 100 609.6 592.3 368.9 735.7 393.2 0 1.98 100 523.3 505.2 100 100 623.3 605.2 387.8 773.5 412.1 25 1.62 76 627.3 592.6 100 100 727.3 692.6 204.8 409.3 220.8 25 1.62 82 644.9 607.6 100 100 744.9 707.6 217.2 434.2 233.3 25 1.62 88 663.7 621.9 100 100 763.7 721.9 229.8 459.1 245.8 25 1.62 94 682.2 635.7 100 100 782.2 735.7 242.3 484.1 258.4 25 1.62 100 699.8 650.0 100 100 799.8 750.0 254.8 508.8 270.8 25 1.80 76 554.9 532.4 100 100 654.9 632.4 255.4 510.3 275.3 25 1.80 82 571.8 545.6 100 100 671.8 645.6 270.8 541.2 290.7 25 1.80 88 587.8 558.6 100 100 687.8 658.6 286.4 572.5 306.4 25 1.80 94 604.9 572.8 100 100 704.9 672.8 301.8 603.3 321.9 25 1.80 100 622.1 586.3 100 100 722.1 686.3 317.4 634.0 337.3 25 1.98 76 506.3 489.3 100 100 606.3 589.3 312.4 623.7 336.8 25 1.98 82 521.3 503.0 100 100 621.3 603.0 331.0 661.0 355.5 25 1.98 88 537.7 516.0 100 100 637.7 616.0 350.0 698.8 374.5 25 1.98 94 552.7 528.7 100 100 652.7 628.7 368.7 736.7 393.4 25 1.98 100 567.4 541.6 100 100 667.4 641.6 387.8 774.5 412.3 50 1.62 76 683.1 642.7 100 100 783.1 742.7 205.2 409.6 220.9 50 1.62 82 704.0 658.3 100 100 804.0 758.3 217.7 434.7 233.6 50 1.62 88 723.7 673.3 100 100 823.7 773.3 230.3 459.4 246.0 50 1.62 94 744.2 687.8 100 100 844.2 787.8 242.7 484.5 258.6 50 1.62 100 764.4 703.6 100 100 864.4 803.6 255.1 508.6 270.9 50 1.80 76 603.9 574.5 100 100 703.9 674.5 255.7 511.0 275.8 50 1.80 82 621.4 588.6 100 100 721.4 688.6 271.2 542.0 291.4 50 1.80 88 639.9 602.3 100 100 739.9 702.3 286.8 572.9 307.0 50 1.80 94 658.5 617.0 100 100 758.5 717.0 302.4 604.2 322.5 118

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Appendix A (Continued) 50 1.80 100 676.0 631.4 100 100 776.0 731.4 318.0 635.0 338.2 50 1.98 76 544.0 526.5 100 100 644.0 626.5 312.3 623.8 336.8 50 1.98 82 560.8 539.6 100 100 660.8 639.6 331.3 661.8 355.8 50 1.98 88 576.7 553.7 100 100 676.7 653.7 350.0 699.3 374.5 50 1.98 94 594.0 567.4 100 100 694.0 667.4 369.1 737.2 393.5 50 1.98 100 611.1 580.7 100 100 711.1 680.7 387.7 774.5 412.2 75 1.62 76 745.6 696.2 100 100 845.6 796.2 205.5 411.3 221.8 75 1.62 82 767.0 712.3 100 100 867.0 812.3 218.0 435.8 234.3 75 1.62 88 788.6 727.8 100 100 888.6 827.8 230.4 460.5 246.8 75 1.62 94 810.9 744.1 100 100 910.9 844.1 243.0 484.7 259.3 75 1.62 100 832.5 760.0 100 100 932.5 860.0 255.4 509.0 271.8 75 1.80 76 654.4 615.5 100 100 754.4 715.5 256.3 512.5 276.6 75 1.80 82 674.6 630.7 100 100 774.6 730.7 271.9 543.4 292.1 75 1.80 88 694.3 645.9 100 100 794.3 745.9 287.7 574.7 307.9 75 1.80 94 713.7 660.6 100 100 813.7 760.6 303.1 605.4 323.3 75 1.80 100 734.4 675.4 100 100 834.4 775.4 318.7 636.3 338.8 75 1.98 76 586.4 559.3 100 100 686.4 659.3 312.2 624.4 336.9 75 1.98 82 603.5 574.0 100 100 703.5 674.0 331.2 662.4 355.9 75 1.98 88 622.1 588.3 100 100 722.1 688.3 350.0 699.9 374.7 75 1.98 94 640.4 602.1 100 100 740.4 702.1 369.0 737.9 393.8 75 1.98 100 657.5 616.2 100 100 757.5 716.2 388.2 775.6 412.8 100 1.62 76 810.2 756.8 100 100 910.2 856.8 206.1 411.4 222.4 100 1.62 82 834.6 773.2 100 100 934.6 873.2 218.5 436.0 234.9 100 1.62 88 857.5 790.6 100 100 957.5 890.6 231.1 460.4 247.5 100 1.62 94 882.0 807.2 100 100 982.0 907.2 243.6 483.9 260.0 100 1.62 100 905.1 823.3 100 100 1005.1 923.3 256.1 506.9 272.5 100 1.80 76 705.1 662.0 100 100 805.1 762.0 256.6 512.9 276.9 100 1.80 82 726.9 677.4 100 100 826.9 777.4 272.2 544.0 292.5 100 1.80 88 747.8 693.1 100 100 847.8 793.1 287.7 574.7 308.0 100 1.80 94 769.7 709.1 100 100 869.7 809.1 303.3 605.4 323.6 100 1.80 100 791.0 724.5 100 100 891.0 824.5 318.8 635.5 339.1 100 1.98 76 628.8 595.9 100 100 728.8 695.9 312.8 625.5 337.8 100 1.98 82 647.7 610.8 100 100 747.7 710.8 332.2 663.9 357.1 100 1.98 88 667.2 625.3 100 100 767.2 725.3 350.9 701.4 375.9 100 1.98 94 686.6 639.9 100 100 786.6 739.9 369.9 739.2 394.8 100 1.98 100 705.1 655.1 100 100 805.1 755.1 388.8 776.6 413.6 125 1.62 76 880.8 822.7 100 100 980.8 922.7 206.4 411.0 222.6 125 1.62 82 905.4 840.4 100 100 1005.4 940.4 218.7 434.8 235.0 125 1.62 88 931.2 858.4 100 100 1031.2 958.4 231.1 457.8 247.5 125 1.62 94 956.5 875.4 100 100 1056.5 975.4 243.6 480.2 259.9 125 1.62 100 982.5 892.2 100 100 1082.5 992.2 256.3 501.9 272.7 125 1.80 76 760.7 712.7 100 100 860.7 812.7 257.2 513.6 277.4 125 1.80 82 783.8 729.1 100 100 883.8 829.1 272.7 544.4 293.0 125 1.80 88 806.3 745.3 100 100 906.3 845.3 288.3 574.8 308.4 125 1.80 94 829.9 762.1 100 100 929.9 862.1 303.8 605.1 324.0 125 1.80 100 852.6 778.1 100 100 952.6 878.1 319.3 634.5 339.5 125 1.98 76 671.4 636.0 100 100 771.4 736.0 313.0 626.5 338.1 125 1.98 82 692.1 651.1 100 100 792.1 751.1 331.9 664.1 357.1 125 1.98 88 712.6 666.3 100 100 812.6 766.3 350.7 701.8 376.0 125 1.98 94 732.8 682.1 100 100 832.8 782.1 369.7 739.1 395.0 125 1.98 100 754.2 697.3 100 100 854.2 797.3 388.6 776.2 413.9 119

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Appendix A (Continued) Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 76 48.1 67.0 46.3 39.4 35.2 33.3 32.6 49.7 135.6 0 1.62 82 48.1 69.5 47.3 39.9 35.2 33.3 32.6 50.8 149.6 0 1.62 88 48.1 72.0 48.3 40.4 35.2 33.3 32.6 52.0 162.0 0 1.62 94 48.2 74.4 49.3 40.9 35.2 33.3 32.6 53.1 174.9 0 1.62 100 48.2 76.9 50.3 41.4 35.2 33.3 32.6 54.3 192.8 0 1.80 76 60.6 83.5 57.7 49.1 44.5 42.1 41.3 62.2 195.5 0 1.80 82 60.6 87.0 59.4 50.2 44.5 42.1 41.3 63.9 212.1 0 1.80 88 60.6 90.1 60.6 50.8 44.5 42.1 41.3 65.3 233.5 0 1.80 94 60.6 93.1 61.8 51.3 44.5 42.1 41.3 66.7 256.0 0 1.80 100 60.6 96.1 62.9 51.8 44.5 42.1 41.3 68.1 277.0 0 1.98 76 75.0 103.0 71.6 61.1 55.4 52.5 51.5 77.1 264.5 0 1.98 82 75.0 106.8 73.2 61.9 55.4 52.5 51.5 78.9 296.3 0 1.98 88 75.0 110.5 74.6 62.7 55.4 52.5 51.5 80.6 322.7 0 1.98 94 75.0 114.3 76.2 63.4 55.4 52.5 51.5 82.3 352.2 0 1.98 100 75.0 118.1 77.7 64.2 55.4 52.5 51.5 84.1 389.5 25 1.62 76 48.3 66.7 46.0 39.1 35.4 33.4 32.8 49.6 134.2 25 1.62 82 48.3 69.2 47.0 39.6 35.4 33.4 32.8 50.8 147.0 25 1.62 88 48.4 71.7 48.0 40.1 35.4 33.4 32.8 52.0 161.4 25 1.62 94 48.5 74.2 49.0 40.6 35.4 33.4 32.8 53.1 173.4 25 1.62 100 48.6 76.7 50.0 41.1 35.4 33.4 32.8 54.3 190.8 25 1.80 76 60.2 83.4 57.6 49.0 44.1 41.7 40.8 62.0 190.3 25 1.80 82 60.2 86.4 58.8 49.6 44.1 41.7 40.9 63.4 209.2 25 1.80 88 60.3 89.5 60.0 50.2 44.1 41.7 40.9 64.8 231.7 25 1.80 94 60.3 92.6 61.2 50.8 44.1 41.7 40.9 66.3 249.8 25 1.80 100 60.4 95.5 62.2 51.1 44.1 41.7 40.9 67.6 275.9 25 1.98 76 74.4 102.5 71.0 60.5 54.7 51.7 50.7 76.5 258.2 25 1.98 82 74.4 106.2 72.5 61.2 54.7 51.7 50.7 78.2 284.9 25 1.98 88 74.4 110.0 74.0 62.0 54.7 51.7 50.7 79.9 315.9 25 1.98 94 74.5 113.8 75.5 62.7 54.7 51.7 50.7 81.7 345.4 25 1.98 100 74.5 117.5 77.0 63.5 54.7 51.7 50.7 83.4 378.4 50 1.62 76 48.2 66.7 46.0 39.1 35.2 33.3 32.7 49.6 132.5 50 1.62 82 48.3 69.3 47.0 39.6 35.3 33.3 32.7 50.8 146.6 50 1.62 88 48.4 71.7 48.0 40.1 35.3 33.3 32.7 51.9 159.5 50 1.62 94 48.7 74.3 49.0 40.6 35.3 33.3 32.7 53.1 175.2 50 1.62 100 49.0 76.7 50.0 41.1 35.3 33.3 32.7 54.2 189.5 50 1.80 76 60.6 83.4 57.6 48.9 44.5 42.1 41.3 62.2 187.0 50 1.80 82 60.7 86.5 58.8 49.6 44.5 42.1 41.3 63.6 204.7 50 1.80 88 60.7 89.6 60.1 50.2 44.5 42.1 41.3 65.1 227.1 50 1.80 94 60.8 92.8 61.3 50.8 44.5 42.1 41.3 66.5 246.8 50 1.80 100 60.9 95.9 62.6 51.4 44.5 42.1 41.3 68.0 268.5 50 1.98 76 74.1 102.4 70.9 60.4 54.3 51.3 50.3 76.2 254.2 50 1.98 82 74.2 106.2 72.4 61.2 54.3 51.3 50.3 78.0 282.9 50 1.98 88 74.2 110.0 73.9 61.9 54.3 51.3 50.3 79.7 312.5 50 1.98 94 74.3 113.8 75.5 62.7 54.3 51.3 50.3 81.5 339.4 50 1.98 100 74.3 117.5 77.0 63.4 54.3 51.3 50.3 83.2 371.8 75 1.62 76 48.7 66.6 45.7 38.8 35.5 33.5 32.9 49.6 132.5 75 1.62 82 48.9 69.1 46.7 39.3 35.5 33.5 32.9 50.8 146.7 75 1.62 88 49.2 71.3 47.4 39.5 35.5 33.5 32.9 51.8 160.4 75 1.62 94 49.8 73.7 48.3 39.8 35.5 33.5 32.9 52.8 173.5 75 1.62 100 50.6 76.1 49.3 40.3 35.5 33.5 32.9 54.0 187.5 75 1.80 76 60.9 83.7 57.8 49.1 44.5 42.1 41.3 62.3 185.0 75 1.80 82 60.9 86.8 59.0 49.8 44.5 42.1 41.3 63.8 204.8 120

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Appendix A (Continued) 75 1.80 88 61.1 89.9 60.3 50.4 44.5 42.1 41.3 65.2 223.5 75 1.80 94 61.2 93.1 61.6 51.1 44.5 42.1 41.3 66.7 245.1 75 1.80 100 61.6 96.2 62.8 51.7 44.5 42.1 41.3 68.1 266.6 75 1.98 76 73.9 101.8 70.2 59.7 54.1 51.1 50.1 75.8 252.1 75 1.98 82 74.0 105.6 71.7 60.5 54.1 51.1 50.1 77.5 277.7 75 1.98 88 74.1 109.4 73.3 61.2 54.1 51.1 50.1 79.3 304.3 75 1.98 94 74.2 113.2 74.8 62.0 54.1 51.1 50.1 81.1 335.6 75 1.98 100 74.3 117.4 76.8 63.3 54.1 51.1 50.1 83.1 364.9 100 1.62 76 49.5 67.1 46.2 39.3 35.9 33.9 33.3 50.1 132.0 100 1.62 82 50.0 69.6 47.2 39.8 35.9 33.9 33.3 51.2 145.2 100 1.62 88 50.8 72.1 48.2 40.2 35.9 33.9 33.3 52.4 158.0 100 1.62 94 52.0 74.5 49.2 40.7 35.9 33.9 33.3 53.5 171.2 100 1.62 100 53.6 77.0 50.1 41.2 35.9 33.9 33.3 54.6 185.5 100 1.80 76 60.9 83.7 57.8 49.1 44.4 42.0 41.1 62.3 184.6 100 1.80 82 61.1 86.6 58.8 49.5 44.4 42.0 41.1 63.6 201.2 100 1.80 88 61.3 89.7 60.0 50.1 44.4 42.0 41.1 65.1 224.8 100 1.80 94 61.7 92.8 61.3 50.8 44.4 42.0 41.1 66.5 244.3 100 1.80 100 62.4 96.0 62.5 51.4 44.4 42.0 41.1 67.9 265.7 100 1.98 76 74.8 102.3 70.7 60.2 54.7 51.7 50.7 76.4 247.4 100 1.98 82 74.9 106.2 72.3 61.0 54.7 51.7 50.7 78.2 273.5 100 1.98 88 75.0 109.9 73.7 61.7 54.8 51.7 50.7 79.9 300.3 100 1.98 94 75.2 113.7 75.2 62.4 54.8 51.7 50.7 81.6 325.7 100 1.98 100 75.4 117.4 76.7 63.2 54.8 51.7 50.7 83.4 357.3 125 1.62 76 50.3 67.3 46.5 39.6 35.8 33.8 33.1 50.1 131.1 125 1.62 82 51.4 69.7 47.3 39.9 35.8 33.8 33.1 51.2 143.3 125 1.62 88 53.0 72.0 48.2 40.2 35.8 33.8 33.1 52.3 156.9 125 1.62 94 55.1 74.5 49.2 40.7 35.8 33.8 33.1 53.4 170.2 125 1.62 100 58.0 77.1 50.2 41.2 35.8 33.8 33.1 54.6 184.1 125 1.80 76 61.2 84.0 58.1 49.4 44.5 42.1 41.3 62.5 184.0 125 1.80 82 61.6 87.2 59.4 50.1 44.5 42.1 41.3 64.0 202.0 125 1.80 88 62.2 90.3 60.6 50.7 44.6 42.1 41.3 65.5 221.9 125 1.80 94 63.1 93.4 61.9 51.3 44.6 42.1 41.3 66.9 241.7 125 1.80 100 64.4 96.5 63.1 52.0 44.6 42.1 41.3 68.3 261.6 125 1.98 76 74.8 102.5 70.9 60.3 54.6 51.5 50.5 76.4 242.8 125 1.98 82 75.0 105.9 72.0 60.7 54.6 51.5 50.5 77.9 268.0 125 1.98 88 75.2 109.4 73.2 61.1 54.6 51.5 50.5 79.5 295.9 125 1.98 94 75.6 113.1 74.5 61.7 54.6 51.5 50.5 81.2 326.0 125 1.98 100 76.0 116.8 76.1 62.5 54.6 51.5 50.5 83.0 354.6 Run completed Mon May 23 2:38:07 US/Eastern 2005 in 4392 seconds. tgcg1ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 2 Setup: 375p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 2 327.3 263.4 375 375 702.3 638.4 14.4 47.4 24.1 0 1.62 4 357.5 290.2 375 375 732.5 665.2 18.5 55.7 28.3 0 1.62 6 389.1 314.5 375 375 764.1 689.5 22.6 64.0 32.4 0 1.62 8 420.2 338.8 375 375 795.2 713.8 26.8 72.3 36.6 0 1.62 10 453.7 363.4 375 375 828.7 738.4 30.9 80.6 40.7 0 1.80 2 281.9 231.8 375 375 656.9 606.8 18.1 59.5 30.3 0 1.80 4 309.8 257.0 375 375 684.8 632.0 23.2 69.9 35.5 0 1.80 6 338.9 279.4 375 375 713.9 654.4 28.4 80.2 40.6 121

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Appendix A (Continued) 0 1.80 8 367.8 302.3 375 375 742.8 677.3 33.5 90.5 45.8 0 1.80 10 400.8 325.4 375 375 775.8 700.4 38.6 100.9 51.0 0 1.98 2 249.6 206.9 375 375 624.6 581.9 22.3 73.5 37.4 0 1.98 4 277.7 229.8 375 375 652.7 604.8 28.5 86.2 43.7 0 1.98 6 304.9 253.0 375 375 679.9 628.0 34.6 98.5 49.9 0 1.98 8 331.0 274.9 375 375 706.0 649.9 40.9 111.3 56.2 0 1.98 10 358.0 295.6 375 375 733.0 670.6 47.3 123.7 62.5 25 1.62 2 351.1 289.2 375 375 726.1 664.2 14.3 47.5 24.1 25 1.62 4 387.1 315.8 375 375 762.1 690.8 18.5 55.9 28.4 25 1.62 6 420.7 341.8 375 375 795.7 716.8 22.6 64.2 32.5 25 1.62 8 455.8 367.5 375 375 830.8 742.5 26.8 72.5 36.7 25 1.62 10 490.8 393.0 375 375 865.8 768.0 30.9 80.8 40.8 25 1.80 2 307.3 254.2 375 375 682.3 629.2 18.1 59.9 30.5 25 1.80 4 341.3 279.8 375 375 716.3 654.8 23.2 70.3 35.7 25 1.80 6 372.8 304.0 375 375 747.8 679.0 28.4 80.6 40.8 25 1.80 8 403.8 328.6 375 375 778.8 703.6 33.5 90.9 46.0 25 1.80 10 436.3 351.5 375 375 811.3 726.5 38.6 101.2 51.1 25 1.98 2 265.9 225.9 375 375 640.9 600.9 22.2 73.5 37.3 25 1.98 4 293.4 250.3 375 375 668.4 625.3 28.4 85.7 43.5 25 1.98 6 323.0 273.5 375 375 698.0 648.5 34.6 98.4 49.8 25 1.98 8 351.7 296.8 375 375 726.7 671.8 40.9 110.9 56.0 25 1.98 10 380.7 319.1 375 375 755.7 694.1 47.1 123.2 62.2 50 1.62 2 389.3 317.3 375 375 764.3 692.3 14.3 47.6 24.2 50 1.62 4 426.5 347.2 375 375 801.5 722.2 18.5 55.9 28.4 50 1.62 6 464.3 373.8 375 375 839.3 748.8 22.6 64.3 32.6 50 1.62 8 502.6 401.0 375 375 877.6 776.0 26.8 72.6 36.7 50 1.62 10 544.2 427.2 375 375 919.2 802.2 31.0 81.1 40.9 50 1.80 2 330.1 277.1 375 375 705.1 652.1 18.1 59.7 30.3 50 1.80 4 367.5 304.1 375 375 742.5 679.1 23.1 70.1 35.5 50 1.80 6 401.4 330.2 375 375 776.4 705.2 28.4 80.5 40.8 50 1.80 8 435.3 355.3 375 375 810.3 730.3 33.5 90.8 45.9 50 1.80 10 469.3 379.6 375 375 844.3 754.6 38.7 101.2 51.1 50 1.98 2 293.3 244.7 375 375 668.3 619.7 22.3 73.9 37.5 50 1.98 4 326.5 270.1 375 375 701.5 645.1 28.5 86.5 43.8 50 1.98 6 358.0 294.9 375 375 733.0 669.9 34.8 98.9 50.0 50 1.98 8 386.8 318.5 375 375 761.8 693.5 41.0 111.5 56.3 50 1.98 10 419.5 343.2 375 375 794.5 718.2 47.3 124.1 62.6 75 1.62 2 426.7 344.0 375 375 801.7 719.0 14.5 48.1 24.4 75 1.62 4 467.2 376.1 375 375 842.2 751.1 18.6 56.4 28.6 75 1.62 6 508.5 404.6 375 375 883.5 779.6 22.8 64.8 32.8 75 1.62 8 550.3 433.4 375 375 925.3 808.4 27.0 73.1 36.9 75 1.62 10 592.7 460.9 375 375 967.7 835.9 31.1 81.4 41.1 75 1.80 2 360.1 299.3 375 375 735.1 674.3 17.9 59.9 30.4 75 1.80 4 395.1 328.8 375 375 770.1 703.8 23.1 70.1 35.6 75 1.80 6 432.0 355.1 375 375 807.0 730.1 28.3 80.5 40.8 75 1.80 8 469.3 381.9 375 375 844.3 756.9 33.4 90.9 45.9 75 1.80 10 506.5 407.7 375 375 881.5 782.7 38.6 101.3 51.2 75 1.98 2 311.5 265.5 375 375 686.5 640.5 22.2 73.7 37.4 75 1.98 4 348.3 292.9 375 375 723.3 667.9 28.4 86.4 43.7 75 1.98 6 381.3 317.9 375 375 756.3 692.9 34.7 98.8 49.9 75 1.98 8 414.0 343.6 375 375 789.0 718.6 41.1 111.4 56.2 75 1.98 10 448.0 369.9 375 375 823.0 744.9 47.3 124.1 62.6 100 1.62 2 465.5 379.8 375 375 840.5 754.8 14.4 48.0 24.4 100 1.62 4 509.7 412.9 375 375 884.7 787.9 18.6 56.4 28.6 122

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Appendix A (Continued) 100 1.62 6 556.6 443.9 375 375 931.6 818.9 22.8 64.8 32.8 100 1.62 8 602.7 473.2 375 375 977.7 848.2 27.0 73.2 37.0 100 1.62 10 648.8 503.2 375 375 1023.8 878.2 31.1 81.5 41.1 100 1.80 2 387.7 324.8 375 375 762.7 699.8 18.1 59.9 30.4 100 1.80 4 431.3 355.4 375 375 806.3 730.4 23.3 70.5 35.7 100 1.80 6 470.9 383.6 375 375 845.9 758.6 28.5 80.8 40.9 100 1.80 8 511.2 412.0 375 375 886.2 787.0 33.7 91.2 46.1 100 1.80 10 551.7 438.9 375 375 926.7 813.9 38.8 101.6 51.3 100 1.98 2 335.3 283.8 375 375 710.3 658.8 22.0 73.9 37.5 100 1.98 4 372.7 313.4 375 375 747.7 688.4 28.3 86.5 43.8 100 1.98 6 408.2 340.2 375 375 783.2 715.2 34.6 99.1 50.1 100 1.98 8 443.5 366.2 375 375 818.5 741.2 40.9 111.8 56.4 100 1.98 10 479.4 392.0 375 375 854.4 767.0 47.2 124.4 62.7 125 1.62 2 509.3 412.6 375 375 884.3 787.6 14.5 48.2 24.5 125 1.62 4 557.1 447.7 375 375 932.1 822.7 18.7 56.5 28.7 125 1.62 6 606.0 480.5 375 375 981.0 855.5 22.9 64.9 32.9 125 1.62 8 656.0 511.3 375 375 1031.0 886.3 27.1 73.2 37.0 125 1.62 10 706.1 543.2 375 375 1081.1 918.2 31.3 81.5 41.3 125 1.80 2 420.6 348.6 375 375 795.6 723.6 18.1 60.4 30.6 125 1.80 4 464.1 381.4 375 375 839.1 756.4 23.3 70.7 35.8 125 1.80 6 506.1 410.9 375 375 881.1 785.9 28.5 81.1 41.0 125 1.80 8 549.8 440.6 375 375 924.8 815.6 33.7 91.5 46.2 125 1.80 10 593.5 468.6 375 375 968.5 843.6 38.9 101.9 51.4 125 1.98 2 359.2 305.9 375 375 734.2 680.9 21.9 73.8 37.4 125 1.98 4 397.6 335.8 375 375 772.6 710.8 28.2 86.3 43.6 125 1.98 6 433.9 364.4 375 375 808.9 739.4 34.5 99.0 50.0 125 1.98 8 471.9 394.0 375 375 846.9 769.0 40.9 111.5 56.2 125 1.98 10 513.4 420.4 375 375 888.4 795.4 47.2 124.4 62.7 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 2 10.4 3.6 1.9 1.4 2.7 1.6 1.2 3.0 3.1 0 1.62 4 10.4 4.4 2.2 1.5 2.7 1.6 1.2 3.3 6.1 0 1.62 6 10.5 5.2 2.6 1.7 2.8 1.6 1.2 3.7 9.8 0 1.62 8 10.5 6.1 2.9 1.8 2.8 1.6 1.2 4.1 13.1 0 1.62 10 10.5 6.9 3.2 2.0 2.8 1.6 1.2 4.5 17.0 0 1.80 2 13.0 4.5 2.4 1.7 3.4 2.0 1.5 3.7 4.1 0 1.80 4 13.0 5.6 2.8 1.9 3.4 2.0 1.5 4.2 8.3 0 1.80 6 13.0 6.6 3.2 2.1 3.4 2.0 1.5 4.7 13.0 0 1.80 8 13.0 7.6 3.7 2.3 3.4 2.0 1.5 5.2 18.2 0 1.80 10 13.0 8.7 4.1 2.6 3.4 2.0 1.5 5.6 23.4 0 1.98 2 16.1 5.6 3.0 2.1 4.2 2.4 1.9 4.6 5.2 0 1.98 4 16.1 6.8 3.5 2.4 4.2 2.4 1.9 5.2 10.7 0 1.98 6 16.1 8.1 4.0 2.6 4.2 2.4 1.9 5.8 17.2 0 1.98 8 16.1 9.5 4.6 2.9 4.2 2.4 1.9 6.4 24.0 0 1.98 10 16.1 10.6 5.0 3.1 4.2 2.4 1.9 6.9 32.2 25 1.62 2 10.5 3.5 1.8 1.3 2.7 1.5 1.1 2.9 3.0 25 1.62 4 10.5 4.3 2.2 1.4 2.7 1.5 1.1 3.3 6.0 25 1.62 6 10.6 5.2 2.5 1.6 2.7 1.5 1.1 3.7 9.6 25 1.62 8 10.6 6.0 2.8 1.8 2.7 1.5 1.1 4.0 12.8 25 1.62 10 10.6 6.8 3.2 1.9 2.7 1.5 1.1 4.4 16.9 25 1.80 2 13.1 4.4 2.3 1.6 3.4 1.9 1.4 3.6 4.0 25 1.80 4 13.1 5.5 2.7 1.8 3.4 1.9 1.4 4.1 8.2 25 1.80 6 13.1 6.5 3.1 2.0 3.4 1.9 1.4 4.6 12.8 123

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Appendix A (Continued) 25 1.80 8 13.2 7.5 3.5 2.2 3.4 1.9 1.4 5.1 17.8 25 1.80 10 13.1 8.5 3.9 2.4 3.4 1.9 1.4 5.5 23.6 25 1.98 2 16.1 5.4 2.8 1.9 4.1 2.3 1.7 4.4 5.1 25 1.98 4 16.0 6.7 3.3 2.2 4.1 2.3 1.7 5.0 10.6 25 1.98 6 16.1 8.0 3.9 2.5 4.1 2.3 1.7 5.6 16.5 25 1.98 8 16.1 9.2 4.3 2.7 4.1 2.3 1.7 6.2 23.9 25 1.98 10 16.1 10.5 4.9 3.0 4.1 2.3 1.7 6.8 31.2 50 1.62 2 10.4 3.5 1.7 1.2 2.6 1.4 1.0 2.8 2.9 50 1.62 4 10.5 4.3 2.1 1.3 2.6 1.4 1.0 3.2 6.1 50 1.62 6 10.5 5.1 2.4 1.5 2.6 1.4 1.0 3.6 9.6 50 1.62 8 10.5 5.9 2.7 1.7 2.6 1.4 1.0 3.9 13.0 50 1.62 10 10.5 6.8 3.1 1.8 2.6 1.4 1.0 4.3 16.4 50 1.80 2 13.0 4.3 2.2 1.5 3.3 1.8 1.3 3.5 3.9 50 1.80 4 13.1 5.4 2.6 1.7 3.3 1.8 1.3 4.0 8.2 50 1.80 6 13.1 6.4 3.1 1.9 3.3 1.8 1.3 4.5 12.7 50 1.80 8 13.1 7.4 3.5 2.1 3.3 1.8 1.3 5.0 17.8 50 1.80 10 13.1 8.5 3.9 2.3 3.3 1.8 1.3 5.5 23.0 50 1.98 2 16.0 5.4 2.8 1.9 4.0 2.2 1.6 4.4 5.0 50 1.98 4 16.1 6.6 3.3 2.2 4.0 2.2 1.6 5.0 10.6 50 1.98 6 16.0 8.0 3.9 2.5 4.0 2.2 1.6 5.6 16.9 50 1.98 8 16.0 9.1 4.3 2.7 4.0 2.2 1.6 6.2 24.0 50 1.98 10 16.0 10.3 4.7 2.9 4.0 2.2 1.6 6.7 30.5 75 1.62 2 10.5 3.4 1.7 1.1 2.6 1.4 0.9 2.7 2.9 75 1.62 4 10.5 4.3 2.0 1.3 2.6 1.4 0.9 3.1 6.1 75 1.62 6 10.5 5.1 2.4 1.4 2.6 1.4 0.9 3.5 9.3 75 1.62 8 10.5 5.9 2.7 1.6 2.6 1.4 0.9 3.9 12.8 75 1.62 10 10.5 6.8 3.0 1.8 2.6 1.4 0.9 4.3 16.5 75 1.80 2 13.1 4.3 2.2 1.5 3.3 1.8 1.3 3.6 3.9 75 1.80 4 13.1 5.3 2.6 1.7 3.3 1.8 1.3 4.0 8.2 75 1.80 6 13.1 6.4 3.0 1.9 3.3 1.8 1.3 4.5 12.9 75 1.80 8 13.1 7.4 3.5 2.1 3.3 1.8 1.3 5.0 17.3 75 1.80 10 13.1 8.5 3.9 2.4 3.3 1.8 1.3 5.5 22.2 75 1.98 2 16.1 5.2 2.6 1.7 4.0 2.1 1.5 4.3 5.0 75 1.98 4 16.0 6.5 3.2 2.1 4.0 2.1 1.5 4.9 10.4 75 1.98 6 16.1 7.8 3.7 2.3 4.0 2.1 1.5 5.5 16.4 75 1.98 8 16.1 9.1 4.2 2.6 4.0 2.1 1.5 6.1 23.2 75 1.98 10 16.1 10.3 4.6 2.8 4.0 2.1 1.5 6.6 30.6 100 1.62 2 10.4 3.4 1.6 1.1 2.5 1.3 0.9 2.7 2.9 100 1.62 4 10.5 4.2 2.0 1.2 2.5 1.3 0.9 3.1 6.1 100 1.62 6 10.5 5.1 2.3 1.4 2.5 1.3 0.9 3.5 9.3 100 1.62 8 10.5 5.9 2.7 1.6 2.6 1.3 0.9 3.9 12.7 100 1.62 10 10.6 6.7 3.0 1.7 2.6 1.3 0.9 4.2 16.4 100 1.80 2 13.0 4.2 2.1 1.3 3.2 1.6 1.1 3.4 3.9 100 1.80 4 13.0 5.3 2.5 1.5 3.2 1.6 1.1 3.9 8.1 100 1.80 6 13.1 6.3 2.9 1.8 3.2 1.6 1.1 4.3 12.3 100 1.80 8 13.1 7.4 3.3 2.0 3.2 1.6 1.1 4.8 17.2 100 1.80 10 13.1 8.4 3.7 2.2 3.2 1.6 1.1 5.3 22.5 100 1.98 2 16.1 5.2 2.6 1.8 4.0 2.1 1.5 4.3 4.9 100 1.98 4 16.1 6.5 3.1 2.0 4.0 2.1 1.5 4.9 10.3 100 1.98 6 16.2 7.7 3.6 2.3 4.0 2.1 1.5 5.5 16.1 100 1.98 8 16.2 9.0 4.2 2.5 4.0 2.1 1.5 6.1 23.0 100 1.98 10 16.2 10.3 4.7 2.8 4.0 2.1 1.5 6.6 29.4 125 1.62 2 10.4 3.4 1.6 1.0 2.5 1.3 0.8 2.7 3.0 125 1.62 4 10.4 4.2 2.0 1.2 2.5 1.3 0.8 3.1 6.1 124

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Appendix A (Continued) 125 1.62 6 10.4 5.0 2.3 1.4 2.5 1.3 0.8 3.4 9.4 125 1.62 8 10.4 5.9 2.7 1.6 2.5 1.3 0.8 3.9 12.8 125 1.62 10 10.6 6.8 3.1 1.8 2.5 1.3 0.8 4.3 16.3 125 1.80 2 13.0 4.2 2.0 1.3 3.1 1.6 1.1 3.3 3.8 125 1.80 4 13.0 5.3 2.4 1.5 3.1 1.6 1.1 3.8 7.8 125 1.80 6 13.1 6.3 2.9 1.7 3.1 1.6 1.1 4.3 12.3 125 1.80 8 13.1 7.4 3.3 1.9 3.1 1.6 1.1 4.8 17.1 125 1.80 10 13.1 8.4 3.7 2.1 3.1 1.6 1.1 5.3 22.3 125 1.98 2 16.0 5.1 2.5 1.6 3.8 2.0 1.3 4.1 5.0 125 1.98 4 16.0 6.4 3.0 1.8 3.9 2.0 1.3 4.7 10.3 125 1.98 6 16.0 7.6 3.5 2.1 3.9 2.0 1.3 5.3 16.1 125 1.98 8 16.0 8.9 4.0 2.3 3.8 2.0 1.3 5.8 22.7 125 1.98 10 16.0 10.2 4.5 2.6 3.8 2.0 1.3 6.4 29.2 Run completed Mon May 23 3:13:52 US/Eastern 2005 in 2145 seconds. tgcg2ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 13 Setup: 375p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 13 437.2 362.8 375 375 812.2 737.8 40.9 107.4 54.2 0 1.62 16 459.0 380.3 375 375 834.0 755.3 47.0 119.8 60.4 0 1.62 19 481.3 398.7 375 375 856.3 773.7 53.2 132.4 66.7 0 1.62 22 504.7 415.8 375 375 879.7 790.8 59.5 144.7 72.8 0 1.62 25 526.8 432.6 375 375 901.8 807.6 65.6 157.2 79.1 0 1.80 13 386.6 324.4 375 375 761.6 699.4 50.9 134.3 67.7 0 1.80 16 405.7 341.7 375 375 780.7 716.7 58.7 150.1 75.6 0 1.80 19 427.6 358.8 375 375 802.6 733.8 66.3 165.3 83.2 0 1.80 22 447.1 374.8 375 375 822.1 749.8 74.0 180.6 90.8 0 1.80 25 468.6 391.4 375 375 843.6 766.4 81.8 196.1 98.6 0 1.98 13 350.2 297.7 375 375 725.2 672.7 62.6 165.6 83.4 0 1.98 16 370.0 313.0 375 375 745.0 688.0 72.1 184.1 92.8 0 1.98 19 387.8 329.1 375 375 762.8 704.1 81.4 203.1 102.2 0 1.98 22 407.4 346.0 375 375 782.4 721.0 90.7 221.6 111.5 0 1.98 25 427.1 361.1 375 375 802.1 736.1 100.1 240.5 120.9 25 1.62 13 479.1 396.7 375 375 854.1 771.7 40.9 108.3 54.6 25 1.62 16 504.6 415.4 375 375 879.6 790.4 47.1 120.8 60.9 25 1.62 19 528.8 434.5 375 375 903.8 809.5 53.4 133.2 67.1 25 1.62 22 554.7 452.5 375 375 929.7 827.5 59.6 145.8 73.3 25 1.62 25 579.4 470.9 375 375 954.4 845.9 65.8 158.1 79.5 25 1.80 13 419.8 352.2 375 375 794.8 727.2 50.9 135.4 68.2 25 1.80 16 443.1 370.9 375 375 818.1 745.9 58.7 150.7 75.9 25 1.80 19 464.3 387.9 375 375 839.3 762.9 66.3 166.0 83.5 25 1.80 22 489.6 404.8 375 375 864.6 779.8 74.5 182.1 91.6 25 1.80 25 513.1 423.0 375 375 888.1 798.0 82.2 197.6 99.4 25 1.98 13 377.0 319.4 375 375 752.0 694.4 62.8 165.9 83.6 25 1.98 16 398.2 336.3 375 375 773.2 711.3 71.9 184.4 92.8 25 1.98 19 417.6 353.8 375 375 792.6 728.8 81.4 203.3 102.3 25 1.98 22 439.2 370.7 375 375 814.2 745.7 90.7 222.1 111.6 25 1.98 25 460.2 386.9 375 375 835.2 761.9 100.4 241.2 121.2 50 1.62 13 523.7 433.4 375 375 898.7 808.4 40.9 108.1 54.5 50 1.62 16 551.0 453.8 375 375 926.0 828.8 47.3 120.8 60.9 125

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Appendix A (Continued) 50 1.62 19 577.8 473.2 375 375 952.8 848.2 53.5 133.3 67.1 50 1.62 22 606.4 492.0 375 375 981.4 867.0 59.7 145.7 73.3 50 1.62 25 633.7 512.3 375 375 1008.7 887.3 65.9 158.1 79.5 50 1.80 13 452.0 382.3 375 375 827.0 757.3 51.1 135.3 68.2 50 1.80 16 477.2 401.6 375 375 852.2 776.6 58.8 150.8 75.9 50 1.80 19 503.8 419.8 375 375 878.8 794.8 66.7 166.8 83.9 50 1.80 22 527.9 437.3 375 375 902.9 812.3 74.5 182.3 91.6 50 1.80 25 553.0 456.5 375 375 928.0 831.5 82.4 197.7 99.4 50 1.98 13 407.1 346.4 375 375 782.1 721.4 62.6 166.4 83.8 50 1.98 16 428.5 365.0 375 375 803.5 740.0 72.0 185.2 93.2 50 1.98 19 450.9 382.1 375 375 825.9 757.1 81.4 204.0 102.6 50 1.98 22 473.9 399.4 375 375 848.9 774.4 90.8 223.1 112.1 50 1.98 25 496.5 417.5 375 375 871.5 792.5 100.3 242.0 121.6 75 1.62 13 570.6 469.7 375 375 945.6 844.7 41.2 108.8 54.9 75 1.62 16 600.7 491.4 375 375 975.7 866.4 47.4 121.2 61.1 75 1.62 19 630.4 511.8 375 375 1005.4 886.8 53.7 133.7 67.4 75 1.62 22 660.0 532.5 375 375 1035.0 907.5 59.8 146.1 73.6 75 1.62 25 691.1 553.3 375 375 1066.1 928.3 66.4 158.5 80.0 75 1.80 13 494.2 413.9 375 375 869.2 788.9 51.3 136.0 68.5 75 1.80 16 521.7 433.3 375 375 896.7 808.3 59.1 151.6 76.3 75 1.80 19 547.6 452.0 375 375 922.6 827.0 66.8 167.1 84.0 75 1.80 22 574.2 472.2 375 375 949.2 847.2 74.6 182.7 91.8 75 1.80 25 602.0 490.9 375 375 977.0 865.9 82.5 198.1 99.6 75 1.98 13 436.5 370.2 375 375 811.5 745.2 62.6 166.6 83.9 75 1.98 16 459.8 389.3 375 375 834.8 764.3 72.1 185.4 93.3 75 1.98 19 483.2 408.0 375 375 858.2 783.0 81.4 204.2 102.7 75 1.98 22 507.9 425.6 375 375 882.9 800.6 90.9 223.2 112.2 75 1.98 25 532.3 444.4 375 375 907.3 819.4 100.3 242.1 121.6 100 1.62 13 625.7 512.4 375 375 1000.7 887.4 41.1 108.6 54.7 100 1.62 16 657.6 534.8 375 375 1032.6 909.8 47.5 121.1 61.0 100 1.62 19 690.5 556.2 375 375 1065.5 931.2 53.7 133.6 67.2 100 1.62 22 723.4 578.8 375 375 1098.4 953.8 60.1 146.0 73.6 100 1.62 25 756.2 600.0 375 375 1131.2 975.0 66.3 158.2 79.8 100 1.80 13 530.3 444.0 375 375 905.3 819.0 51.3 135.9 68.4 100 1.80 16 558.2 464.4 375 375 933.2 839.4 59.1 151.4 76.2 100 1.80 19 587.8 485.3 375 375 962.8 860.3 66.9 167.0 84.0 100 1.80 22 616.8 505.0 375 375 991.8 880.0 74.5 182.4 91.7 100 1.80 25 646.0 525.9 375 375 1021.0 900.9 82.5 197.9 99.6 100 1.98 13 473.8 397.9 375 375 848.8 772.9 63.0 167.1 84.1 100 1.98 16 498.8 417.6 375 375 873.8 792.6 72.4 186.0 93.5 100 1.98 19 523.5 437.2 375 375 898.5 812.2 81.8 204.9 103.0 100 1.98 22 550.5 456.3 375 375 925.5 831.3 91.3 223.8 112.5 100 1.98 25 576.2 474.6 375 375 951.2 849.6 100.7 242.7 121.9 125 1.62 13 683.8 555.8 375 375 1058.8 930.8 41.2 109.0 55.0 125 1.62 16 718.3 580.0 375 375 1093.3 955.0 47.5 121.6 61.3 125 1.62 19 754.0 602.6 375 375 1129.0 977.6 53.9 134.0 67.5 125 1.62 22 789.7 626.5 375 375 1164.7 1001.5 60.1 146.2 73.8 125 1.62 25 825.4 649.0 375 375 1200.4 1024.0 66.5 158.0 80.1 125 1.80 13 570.7 478.4 375 375 945.7 853.4 51.5 136.4 68.8 125 1.80 16 600.8 499.4 375 375 975.8 874.4 59.3 151.9 76.5 125 1.80 19 631.7 521.5 375 375 1006.7 896.5 67.2 167.5 84.4 125 1.80 22 663.3 542.4 375 375 1038.3 917.4 75.1 183.0 92.2 125 1.80 25 694.4 563.8 375 375 1069.4 938.8 82.9 198.3 99.9 125 1.98 13 499.9 425.0 375 375 874.9 800.0 62.9 166.8 84.0 126

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Appendix A (Continued) 125 1.98 16 527.3 445.1 375 375 902.3 820.1 72.4 186.0 93.5 125 1.98 19 554.2 465.6 375 375 929.2 840.6 81.7 204.7 102.9 125 1.98 22 581.3 485.2 375 375 956.3 860.2 91.4 223.7 112.4 125 1.98 25 610.3 505.5 375 375 985.3 880.5 100.6 242.4 121.8 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 13 14.1 9.1 4.3 2.7 3.6 2.0 1.5 6.0 20.7 0 1.62 16 14.2 10.2 4.7 2.9 3.6 2.0 1.5 6.5 26.8 0 1.62 19 14.2 11.6 5.3 3.2 3.6 2.0 1.5 7.1 31.8 0 1.62 22 14.2 12.7 5.7 3.4 3.6 2.0 1.5 7.7 37.5 0 1.62 25 14.2 14.0 6.3 3.7 3.6 2.0 1.5 8.3 44.3 0 1.80 13 17.6 11.2 5.2 3.3 4.4 2.5 1.9 7.4 28.4 0 1.80 16 17.6 12.7 5.8 3.6 4.4 2.5 1.9 8.1 36.3 0 1.80 19 17.6 14.3 6.4 3.9 4.4 2.5 1.9 8.8 43.8 0 1.80 22 17.7 15.8 7.1 4.2 4.4 2.5 1.9 9.5 53.3 0 1.80 25 17.6 17.4 7.7 4.5 4.4 2.5 1.9 10.3 60.9 0 1.98 13 21.7 13.7 6.4 4.0 5.4 3.1 2.3 9.1 36.7 0 1.98 16 21.7 15.7 7.2 4.4 5.4 3.1 2.3 10.0 48.8 0 1.98 19 21.7 17.5 7.9 4.8 5.4 3.1 2.3 10.8 58.7 0 1.98 22 21.7 19.3 8.7 5.1 5.4 3.1 2.3 11.7 72.5 0 1.98 25 21.7 21.2 9.4 5.5 5.4 3.1 2.3 12.6 85.0 25 1.62 13 14.2 9.0 4.1 2.5 3.5 1.9 1.4 5.9 21.4 25 1.62 16 14.2 10.3 4.7 2.8 3.5 1.9 1.4 6.5 26.1 25 1.62 19 14.3 11.5 5.2 3.1 3.5 1.9 1.4 7.0 32.3 25 1.62 22 14.3 12.7 5.6 3.2 3.5 1.9 1.4 7.6 37.3 25 1.62 25 14.3 14.0 6.1 3.5 3.5 1.9 1.4 8.2 44.0 25 1.80 13 17.8 11.2 5.2 3.2 4.4 2.5 1.8 7.4 28.5 25 1.80 16 17.8 12.8 5.8 3.5 4.4 2.5 1.8 8.1 35.9 25 1.80 19 17.8 14.3 6.5 3.8 4.4 2.5 1.8 8.8 44.4 25 1.80 22 17.8 16.0 7.2 4.2 4.4 2.5 1.8 9.6 52.7 25 1.80 25 17.9 17.5 7.8 4.5 4.4 2.5 1.8 10.3 62.3 25 1.98 13 21.7 13.7 6.4 3.9 5.3 3.0 2.2 9.0 37.0 25 1.98 16 21.7 15.5 7.0 4.2 5.3 3.0 2.2 9.8 46.7 25 1.98 19 21.7 17.5 7.9 4.8 5.3 3.0 2.2 10.8 58.3 25 1.98 22 21.8 19.3 8.6 5.1 5.3 3.0 2.2 11.6 70.6 25 1.98 25 21.8 21.1 9.2 5.3 5.3 3.0 2.2 12.4 83.6 50 1.62 13 14.2 8.9 4.0 2.4 3.5 1.9 1.3 5.7 20.8 50 1.62 16 14.2 10.2 4.5 2.6 3.5 1.9 1.3 6.3 25.9 50 1.62 19 14.3 11.4 5.0 2.9 3.5 1.9 1.3 6.9 31.1 50 1.62 22 14.3 12.7 5.6 3.2 3.5 1.9 1.3 7.5 36.7 50 1.62 25 14.4 13.9 6.0 3.4 3.5 1.9 1.3 8.1 42.6 50 1.80 13 17.8 11.1 5.1 3.1 4.4 2.4 1.7 7.3 28.7 50 1.80 16 17.8 12.7 5.7 3.4 4.4 2.4 1.7 8.0 34.8 50 1.80 19 17.8 14.2 6.3 3.6 4.4 2.4 1.7 8.7 43.6 50 1.80 22 17.8 15.9 7.0 4.1 4.4 2.4 1.7 9.5 51.0 50 1.80 25 17.8 17.6 7.8 4.5 4.4 2.4 1.7 10.2 60.2 50 1.98 13 21.9 13.6 6.3 3.8 5.3 2.9 2.1 8.9 37.4 50 1.98 16 21.9 15.5 7.0 4.2 5.3 2.9 2.1 9.8 47.4 50 1.98 19 21.9 17.4 7.8 4.6 5.3 2.9 2.1 10.7 55.7 50 1.98 22 21.9 19.2 8.4 4.8 5.3 2.9 2.1 11.5 68.2 50 1.98 25 22.0 21.1 9.2 5.2 5.3 2.9 2.1 12.4 80.2 75 1.62 13 14.2 8.9 4.0 2.3 3.4 1.8 1.2 5.7 20.3 75 1.62 16 14.2 10.2 4.5 2.6 3.4 1.8 1.2 6.3 25.4 127

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Appendix A (Continued) 75 1.62 19 14.3 11.5 5.0 2.8 3.4 1.8 1.2 6.9 31.3 75 1.62 22 14.3 12.6 5.4 3.1 3.4 1.8 1.2 7.4 36.5 75 1.62 25 14.5 14.2 6.2 3.4 3.4 1.8 1.2 8.1 42.5 75 1.80 13 17.8 11.2 5.1 3.1 4.3 2.4 1.7 7.3 27.5 75 1.80 16 17.8 12.7 5.7 3.4 4.4 2.4 1.7 8.0 34.6 75 1.80 19 17.9 14.3 6.4 3.7 4.4 2.4 1.7 8.7 42.5 75 1.80 22 17.9 15.9 7.0 4.0 4.4 2.4 1.7 9.4 50.4 75 1.80 25 17.9 17.5 7.6 4.3 4.4 2.4 1.7 10.2 58.5 75 1.98 13 21.8 13.6 6.1 3.7 5.2 2.8 2.0 8.8 35.9 75 1.98 16 21.7 15.5 6.9 4.0 5.2 2.8 2.0 9.7 45.6 75 1.98 19 21.8 17.4 7.7 4.4 5.2 2.8 2.0 10.6 55.8 75 1.98 22 21.8 19.3 8.5 4.8 5.2 2.8 2.0 11.5 67.1 75 1.98 25 21.8 21.1 9.2 5.2 5.2 2.8 2.0 12.3 78.4 100 1.62 13 14.1 8.8 3.9 2.3 3.4 1.7 1.2 5.6 20.3 100 1.62 16 14.2 10.2 4.5 2.6 3.4 1.7 1.2 6.2 25.7 100 1.62 19 14.2 11.4 5.0 2.8 3.4 1.7 1.2 6.8 30.7 100 1.62 22 14.4 12.9 5.6 3.1 3.4 1.7 1.2 7.4 36.5 100 1.62 25 14.7 14.0 6.0 3.4 3.4 1.7 1.2 8.0 42.6 100 1.80 13 17.8 11.0 4.9 2.9 4.2 2.2 1.5 7.1 26.9 100 1.80 16 17.9 12.6 5.6 3.2 4.2 2.2 1.5 7.8 34.1 100 1.80 19 17.9 14.2 6.2 3.5 4.2 2.2 1.5 8.5 42.0 100 1.80 22 17.9 15.7 6.8 3.8 4.2 2.2 1.5 9.2 50.2 100 1.80 25 18.0 17.4 7.5 4.2 4.3 2.2 1.5 10.0 58.2 100 1.98 13 21.8 13.7 6.2 3.7 5.2 2.8 2.0 8.8 35.8 100 1.98 16 21.8 15.5 6.9 4.1 5.2 2.8 2.0 9.7 44.9 100 1.98 19 21.8 17.5 7.7 4.4 5.2 2.8 2.0 10.6 55.2 100 1.98 22 21.8 19.4 8.5 4.8 5.2 2.8 2.0 11.5 66.4 100 1.98 25 21.8 21.2 9.2 5.2 5.2 2.8 2.0 12.3 78.3 125 1.62 13 14.2 8.9 4.0 2.3 3.4 1.7 1.1 5.7 20.3 125 1.62 16 14.2 10.2 4.5 2.5 3.4 1.7 1.1 6.2 25.6 125 1.62 19 14.4 11.6 5.1 3.0 3.4 1.7 1.1 6.9 30.6 125 1.62 22 14.8 12.8 5.6 3.2 3.4 1.7 1.1 7.5 36.5 125 1.62 25 15.6 14.2 6.2 3.6 3.4 1.7 1.1 8.1 42.5 125 1.80 13 17.8 11.1 4.9 2.8 4.2 2.1 1.4 7.1 26.8 125 1.80 16 17.8 12.6 5.5 3.1 4.2 2.1 1.4 7.8 34.1 125 1.80 19 17.9 14.3 6.2 3.5 4.2 2.1 1.4 8.5 41.5 125 1.80 22 18.0 16.0 6.9 3.8 4.2 2.1 1.4 9.3 49.6 125 1.80 25 18.2 17.4 7.4 4.1 4.2 2.1 1.4 10.0 57.8 125 1.98 13 21.8 13.5 6.0 3.5 5.1 2.6 1.8 8.6 34.7 125 1.98 16 21.8 15.4 6.9 4.0 5.1 2.6 1.8 9.6 44.3 125 1.98 19 21.8 17.2 7.5 4.2 5.1 2.6 1.8 10.4 54.7 125 1.98 22 21.9 19.3 8.3 4.6 5.1 2.6 1.8 11.3 66.1 125 1.98 25 22.0 21.0 9.0 4.9 5.1 2.6 1.8 12.1 76.8 Run completed Mon May 23 3:46:36 US/Eastern 2005 in 1964 seconds. tgcg3ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 29 Setup: 375p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 29 480.9 417.7 375 375 855.9 792.7 76.6 184.0 92.5 0 1.62 33 498.9 433.3 375 375 873.9 808.3 84.7 200.5 100.8 0 1.62 37 519.5 449.0 375 375 894.5 824.0 93.2 217.0 109.0 128

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Appendix A (Continued) 0 1.62 41 538.5 465.9 375 375 913.5 840.9 101.6 233.7 117.4 0 1.62 45 558.7 481.6 375 375 933.7 856.6 109.8 250.2 125.6 0 1.80 29 427.3 376.9 375 375 802.3 751.9 95.2 229.7 115.4 0 1.80 33 445.9 391.6 375 375 820.9 766.6 105.6 250.4 125.7 0 1.80 37 462.7 407.0 375 375 837.7 782.0 115.8 271.0 136.1 0 1.80 41 481.2 422.8 375 375 856.2 797.8 126.7 292.4 146.8 0 1.80 45 499.7 437.8 375 375 874.7 812.8 136.9 312.9 157.1 0 1.98 29 393.6 347.4 375 375 768.6 722.4 117.0 282.3 141.7 0 1.98 33 410.4 362.4 375 375 785.4 737.4 129.5 307.3 154.2 0 1.98 37 425.9 376.6 375 375 800.9 751.6 142.2 332.7 166.9 0 1.98 41 443.4 391.2 375 375 818.4 766.2 154.5 357.5 179.3 0 1.98 45 460.2 406.7 375 375 835.2 781.7 167.2 382.6 191.9 25 1.62 29 525.6 450.8 375 375 900.6 825.8 76.5 184.8 92.8 25 1.62 33 547.3 468.7 375 375 922.3 843.7 84.9 201.3 101.1 25 1.62 37 568.8 485.3 375 375 943.8 860.3 93.1 218.0 109.4 25 1.62 41 590.1 502.0 375 375 965.1 877.0 101.5 234.5 117.7 25 1.62 45 612.3 519.5 375 375 987.3 894.5 109.8 251.0 126.0 25 1.80 29 464.1 406.6 375 375 839.1 781.6 95.6 230.5 115.9 25 1.80 33 483.8 422.3 375 375 858.8 797.3 105.8 251.3 126.2 25 1.80 37 502.7 439.2 375 375 877.7 814.2 116.2 271.8 136.5 25 1.80 41 522.1 455.1 375 375 897.1 830.1 126.5 292.4 146.8 25 1.80 45 541.8 470.5 375 375 916.8 845.5 136.9 313.1 157.2 25 1.98 29 422.3 373.3 375 375 797.3 748.3 117.2 282.5 141.9 25 1.98 33 439.5 389.8 375 375 814.5 764.8 129.5 307.5 154.3 25 1.98 37 458.2 404.9 375 375 833.2 779.9 142.0 332.7 166.9 25 1.98 41 475.0 419.8 375 375 850.0 794.8 154.6 357.7 179.4 25 1.98 45 493.7 436.2 375 375 868.7 811.2 167.3 382.8 192.0 50 1.62 29 572.7 492.4 375 375 947.7 867.4 77.0 185.2 93.0 50 1.62 33 596.7 510.5 375 375 971.7 885.5 85.3 201.7 101.3 50 1.62 37 619.8 528.2 375 375 994.8 903.2 93.6 218.3 109.6 50 1.62 41 643.9 546.0 375 375 1018.9 921.0 101.9 234.9 117.9 50 1.62 45 667.6 564.4 375 375 1042.6 939.4 110.1 251.3 126.2 50 1.80 29 506.1 437.6 375 375 881.1 812.6 95.6 230.7 115.8 50 1.80 33 527.4 455.2 375 375 902.4 830.2 106.1 251.6 126.3 50 1.80 37 548.5 471.7 375 375 923.5 846.7 116.6 272.2 136.6 50 1.80 41 569.8 489.1 375 375 944.8 864.1 127.0 292.9 147.1 50 1.80 45 591.8 506.1 375 375 966.8 881.1 137.3 313.5 157.4 50 1.98 29 451.9 399.0 375 375 826.9 774.0 117.0 281.8 141.5 50 1.98 33 470.7 414.9 375 375 845.7 789.9 129.8 307.1 154.1 50 1.98 37 489.8 430.4 375 375 864.8 805.4 142.0 331.9 166.5 50 1.98 41 510.3 447.3 375 375 885.3 822.3 154.7 357.7 179.5 50 1.98 45 529.4 463.5 375 375 904.4 838.5 167.4 382.8 192.1 75 1.62 29 621.2 535.1 375 375 996.2 910.1 77.1 185.3 93.1 75 1.62 33 645.8 554.8 375 375 1020.8 929.8 85.4 201.9 101.4 75 1.62 37 672.4 573.8 375 375 1047.4 948.8 93.8 218.5 109.8 75 1.62 41 697.4 592.4 375 375 1072.4 967.4 102.4 234.9 118.2 75 1.62 45 724.6 612.1 375 375 1099.6 987.1 110.4 251.1 126.5 75 1.80 29 542.4 470.9 375 375 917.4 845.9 95.9 231.5 116.2 75 1.80 33 565.4 488.9 375 375 940.4 863.9 106.3 252.1 126.6 75 1.80 37 588.5 506.9 375 375 963.5 881.9 116.7 272.9 137.0 75 1.80 41 611.7 524.2 375 375 986.7 899.2 126.9 293.4 147.3 75 1.80 45 634.9 542.3 375 375 1009.9 917.3 137.2 313.9 157.6 75 1.98 29 485.3 424.2 375 375 860.3 799.2 117.2 283.2 142.1 75 1.98 33 505.3 440.6 375 375 880.3 815.6 129.7 308.2 154.7 129

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Appendix A (Continued) 75 1.98 37 526.1 458.2 375 375 901.1 833.2 142.2 333.3 167.2 75 1.98 41 547.2 474.9 375 375 922.2 849.9 155.0 358.6 179.9 75 1.98 45 568.8 491.3 375 375 943.8 866.3 167.6 383.7 192.5 100 1.62 29 681.7 576.9 375 375 1056.7 951.9 77.2 185.3 93.1 100 1.62 33 709.8 597.9 375 375 1084.8 972.9 85.8 201.9 101.6 100 1.62 37 737.0 617.8 375 375 1112.0 992.8 93.9 218.3 109.8 100 1.62 41 765.9 637.9 375 375 1140.9 1012.9 102.1 234.3 118.2 100 1.62 45 793.7 658.3 375 375 1168.7 1033.3 110.5 250.0 126.6 100 1.80 29 584.2 503.6 375 375 959.2 878.6 95.9 231.0 116.0 100 1.80 33 608.2 522.3 375 375 983.2 897.3 106.3 251.7 126.4 100 1.80 37 633.6 541.3 375 375 1008.6 916.3 116.4 272.4 136.7 100 1.80 41 658.2 559.5 375 375 1033.2 934.5 127.0 292.9 147.2 100 1.80 45 684.6 578.6 375 375 1059.6 953.6 137.6 313.5 157.7 100 1.98 29 523.0 456.0 375 375 898.0 831.0 117.6 283.3 142.3 100 1.98 33 544.6 473.6 375 375 919.6 848.6 130.0 308.6 154.8 100 1.98 37 567.6 490.6 375 375 942.6 865.6 142.8 333.9 167.6 100 1.98 41 589.8 508.7 375 375 964.8 883.7 155.3 359.0 180.1 100 1.98 45 613.0 526.0 375 375 988.0 901.0 168.1 383.8 192.7 125 1.62 29 736.6 631.6 375 375 1111.6 1006.6 77.3 185.8 93.5 125 1.62 33 766.8 653.5 375 375 1141.8 1028.5 85.6 202.1 101.8 125 1.62 37 797.3 674.8 375 375 1172.3 1049.8 94.1 218.2 110.2 125 1.62 41 826.9 695.9 375 375 1201.9 1070.9 102.5 233.7 118.6 125 1.62 45 858.6 717.4 375 375 1233.6 1092.4 110.8 248.4 126.9 125 1.80 29 626.1 541.5 375 375 1001.1 916.5 96.3 231.9 116.7 125 1.80 33 651.6 561.7 375 375 1026.6 936.7 106.6 252.6 127.0 125 1.80 37 679.2 581.4 375 375 1054.2 956.4 117.3 273.3 137.3 125 1.80 41 705.7 600.6 375 375 1080.7 975.6 127.6 293.5 147.9 125 1.80 45 733.4 620.7 375 375 1108.4 995.7 137.8 313.6 158.2 125 1.98 29 553.0 484.6 375 375 928.0 859.6 117.3 283.3 142.2 125 1.98 33 576.1 502.3 375 375 951.1 877.3 130.1 308.6 154.9 125 1.98 37 600.7 521.3 375 375 975.7 896.3 142.4 333.6 167.4 125 1.98 41 624.4 539.5 375 375 999.4 914.5 155.4 358.8 180.2 125 1.98 45 649.4 557.5 375 375 1024.4 932.5 168.2 383.8 192.9 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 29 16.6 16.2 7.1 4.1 4.1 2.2 1.6 9.5 49.3 0 1.62 33 16.6 17.9 7.9 4.5 4.1 2.2 1.6 10.3 57.1 0 1.62 37 16.6 19.6 8.6 4.9 4.1 2.2 1.6 11.1 63.9 0 1.62 41 16.6 21.4 9.3 5.3 4.1 2.2 1.6 11.9 73.5 0 1.62 45 16.6 22.8 9.7 5.4 4.1 2.2 1.6 12.5 81.1 0 1.80 29 21.0 20.1 8.8 5.0 5.1 2.8 2.0 11.8 67.7 0 1.80 33 21.0 22.2 9.6 5.5 5.1 2.8 2.0 12.8 80.0 0 1.80 37 21.0 24.3 10.5 5.9 5.1 2.8 2.0 13.7 90.8 0 1.80 41 21.1 26.4 11.3 6.3 5.1 2.8 2.0 14.7 105.5 0 1.80 45 21.1 28.5 12.2 6.7 5.1 2.8 2.0 15.7 115.1 0 1.98 29 25.5 24.6 10.8 6.2 6.1 3.4 2.5 14.5 92.5 0 1.98 33 25.5 27.2 11.8 6.7 6.1 3.4 2.5 15.7 107.6 0 1.98 37 25.5 29.7 12.8 7.2 6.1 3.4 2.5 16.8 120.4 0 1.98 41 25.6 32.1 13.8 7.7 6.1 3.4 2.5 18.0 140.3 0 1.98 45 25.6 34.8 14.8 8.2 6.2 3.4 2.5 19.2 158.9 25 1.62 29 16.7 16.0 6.9 3.8 4.0 2.1 1.5 9.3 48.1 25 1.62 33 16.8 17.9 7.8 4.4 4.0 2.1 1.5 10.2 56.2 25 1.62 37 16.8 19.4 8.3 4.6 4.0 2.1 1.5 10.9 63.8 130

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Appendix A (Continued) 25 1.62 41 16.8 21.2 9.1 5.1 4.0 2.1 1.5 11.8 73.1 25 1.62 45 16.9 22.9 9.8 5.4 4.0 2.1 1.5 12.5 80.5 25 1.80 29 21.0 20.2 8.9 5.1 5.0 2.7 1.9 11.8 67.6 25 1.80 33 21.0 22.2 9.6 5.4 5.0 2.7 1.9 12.7 77.9 25 1.80 37 21.0 24.3 10.5 5.9 5.0 2.7 1.9 13.7 90.8 25 1.80 41 21.0 26.4 11.4 6.4 5.0 2.7 1.9 14.7 101.7 25 1.80 45 21.1 28.6 12.3 6.9 5.0 2.7 1.9 15.7 114.0 25 1.98 29 25.8 24.7 10.8 6.2 6.1 3.3 2.4 14.5 89.9 25 1.98 33 25.7 27.1 11.7 6.6 6.1 3.3 2.4 15.6 104.5 25 1.98 37 25.8 29.4 12.5 6.9 6.1 3.3 2.4 16.7 123.7 25 1.98 41 25.8 31.9 13.6 7.5 6.1 3.3 2.3 17.8 137.4 25 1.98 45 25.8 34.7 14.8 8.2 6.1 3.3 2.4 19.1 154.7 50 1.62 29 16.7 16.1 6.9 3.8 4.0 2.1 1.4 9.3 47.7 50 1.62 33 16.8 17.9 7.6 4.2 4.0 2.1 1.4 10.1 55.2 50 1.62 37 16.8 19.5 8.3 4.5 4.0 2.1 1.4 10.9 63.5 50 1.62 41 16.9 21.2 9.0 4.9 4.0 2.1 1.4 11.6 71.4 50 1.62 45 17.1 22.8 9.6 5.2 4.0 2.1 1.4 12.4 79.9 50 1.80 29 20.8 19.9 8.6 4.8 5.0 2.6 1.8 11.6 66.1 50 1.80 33 20.8 22.1 9.4 5.2 5.0 2.6 1.8 12.6 76.3 50 1.80 37 20.9 24.2 10.3 5.7 5.0 2.6 1.8 13.6 87.9 50 1.80 41 20.9 26.5 11.4 6.4 5.0 2.6 1.8 14.7 99.9 50 1.80 45 21.0 28.6 12.2 6.8 5.0 2.6 1.8 15.6 112.7 50 1.98 29 25.6 24.5 10.6 6.0 6.1 3.2 2.2 14.3 88.2 50 1.98 33 25.6 27.1 11.7 6.6 6.1 3.2 2.2 15.5 106.0 50 1.98 37 25.6 29.3 12.5 6.8 6.1 3.2 2.2 16.5 118.3 50 1.98 41 25.6 32.1 13.7 7.6 6.1 3.2 2.2 17.8 134.1 50 1.98 45 25.7 34.8 14.9 8.3 6.1 3.2 2.2 19.1 154.6 75 1.62 29 16.7 16.2 6.9 3.8 3.9 2.0 1.3 9.3 47.4 75 1.62 33 16.8 17.8 7.6 4.1 3.9 2.0 1.3 10.0 54.5 75 1.62 37 16.9 19.7 8.4 4.5 3.9 2.0 1.3 10.8 62.6 75 1.62 41 17.2 21.5 9.1 4.9 3.9 2.0 1.3 11.7 71.5 75 1.62 45 17.7 23.0 9.7 5.2 3.9 2.0 1.3 12.4 79.3 75 1.80 29 20.9 20.1 8.7 4.9 5.0 2.6 1.8 11.7 64.6 75 1.80 33 21.0 22.2 9.5 5.3 5.0 2.6 1.8 12.7 75.9 75 1.80 37 21.0 24.4 10.4 5.7 5.0 2.6 1.8 13.7 87.3 75 1.80 41 21.1 26.4 11.2 6.1 5.0 2.6 1.8 14.6 99.5 75 1.80 45 21.3 28.4 12.0 6.5 5.0 2.6 1.8 15.5 111.6 75 1.98 29 25.6 24.5 10.5 5.9 6.0 3.1 2.2 14.2 87.4 75 1.98 33 25.7 27.1 11.6 6.4 6.0 3.1 2.2 15.4 100.7 75 1.98 37 25.6 29.5 12.5 6.9 6.0 3.1 2.2 16.6 118.2 75 1.98 41 25.7 32.2 13.6 7.4 6.0 3.1 2.2 17.8 133.2 75 1.98 45 25.8 34.8 14.7 8.0 6.0 3.1 2.2 18.9 152.3 100 1.62 29 16.7 16.1 6.9 3.8 3.9 1.9 1.3 9.2 46.9 100 1.62 33 16.9 17.9 7.6 4.2 3.9 1.9 1.3 10.0 54.6 100 1.62 37 17.2 19.5 8.2 4.5 3.9 1.9 1.3 10.8 62.1 100 1.62 41 17.9 21.4 9.1 4.9 3.9 1.9 1.3 11.6 70.5 100 1.62 45 18.9 22.9 9.6 5.1 3.9 1.9 1.3 12.3 79.4 100 1.80 29 20.8 20.0 8.5 4.7 4.9 2.4 1.6 11.5 63.6 100 1.80 33 20.9 22.1 9.4 5.1 4.9 2.4 1.6 12.4 74.9 100 1.80 37 21.0 24.0 10.1 5.4 4.9 2.4 1.6 13.4 86.4 100 1.80 41 21.2 26.4 11.1 6.0 4.9 2.4 1.6 14.4 98.3 100 1.80 45 21.6 28.6 12.0 6.4 4.9 2.4 1.6 15.4 110.8 100 1.98 29 25.6 24.6 10.6 5.9 6.0 3.1 2.1 14.2 83.5 100 1.98 33 25.7 27.0 11.5 6.4 6.0 3.1 2.1 15.4 99.7 131

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Appendix A (Continued) 100 1.98 37 25.7 29.7 12.7 6.9 6.0 3.1 2.1 16.6 115.6 100 1.98 41 25.8 32.1 13.6 7.4 6.0 3.1 2.1 17.8 131.5 100 1.98 45 26.0 35.0 14.8 8.0 6.0 3.1 2.1 19.0 148.6 125 1.62 29 16.9 16.4 7.1 4.0 3.9 1.9 1.2 9.3 46.3 125 1.62 33 17.3 17.9 7.7 4.2 3.9 1.9 1.2 10.1 55.0 125 1.62 37 18.0 19.8 8.5 4.8 3.9 1.9 1.2 11.0 62.9 125 1.62 41 19.3 21.6 9.4 5.3 3.9 1.9 1.2 11.8 71.5 125 1.62 45 21.3 23.0 9.7 5.3 3.9 1.9 1.2 12.4 79.7 125 1.80 29 21.1 20.1 8.5 4.6 4.9 2.4 1.6 11.5 63.6 125 1.80 33 21.2 22.0 9.2 5.0 4.9 2.4 1.6 12.4 74.4 125 1.80 37 21.4 24.5 10.4 5.6 4.9 2.4 1.6 13.5 85.3 125 1.80 41 21.9 26.4 11.1 6.0 4.9 2.4 1.6 14.4 96.6 125 1.80 45 22.7 28.5 11.9 6.4 4.9 2.4 1.6 15.4 109.4 125 1.98 29 25.7 24.5 10.4 5.7 5.9 2.9 1.9 14.0 83.9 125 1.98 33 25.7 27.1 11.5 6.2 5.9 2.9 1.9 15.2 97.6 125 1.98 37 25.8 29.4 12.4 6.6 5.9 2.9 1.9 16.4 113.8 125 1.98 41 25.9 32.3 13.6 7.3 5.9 2.9 1.9 17.6 129.2 125 1.98 45 26.2 35.0 14.8 7.9 5.9 2.9 1.9 18.8 146.0 Run completed Mon May 23 4:19:13 US/Eastern 2005 in 1957 seconds. tgcg4ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 50 Setup: 400p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 50 535.2 467.9 400 400 935.2 867.9 125.7 292.7 146.9 0 1.62 55 551.8 483.1 400 400 951.8 883.1 135.9 313.3 157.2 0 1.62 60 570.0 497.5 400 400 970.0 897.5 146.5 334.0 167.6 0 1.62 65 587.1 511.4 400 400 987.1 911.4 156.5 354.6 177.8 0 1.62 70 605.7 526.1 400 400 1005.7 926.1 167.1 375.0 188.2 0 1.80 50 476.5 423.8 400 400 876.5 823.8 156.5 365.5 183.2 0 1.80 55 493.8 438.1 400 400 893.8 838.1 169.8 391.4 196.3 0 1.80 60 510.0 451.2 400 400 910.0 851.2 182.3 417.2 209.1 0 1.80 65 525.4 465.8 400 400 925.4 865.8 195.2 442.7 221.9 0 1.80 70 542.9 479.6 400 400 942.9 879.6 208.4 468.5 234.9 0 1.98 50 437.9 394.8 400 400 837.9 794.8 190.6 447.7 224.7 0 1.98 55 454.0 408.2 400 400 854.0 808.2 206.5 478.5 240.0 0 1.98 60 468.8 421.2 400 400 868.8 821.2 222.0 510.0 255.6 0 1.98 65 483.1 434.0 400 400 883.1 834.0 238.1 541.3 271.4 0 1.98 70 499.5 448.1 400 400 899.5 848.1 253.4 572.8 287.1 25 1.62 50 586.2 508.9 400 400 986.2 908.9 125.8 293.3 147.1 25 1.62 55 605.3 524.0 400 400 1005.3 924.0 136.1 314.0 157.5 25 1.62 60 625.0 538.7 400 400 1025.0 938.7 146.5 334.5 167.8 25 1.62 65 644.9 554.6 400 400 1044.9 954.6 157.0 355.1 178.3 25 1.62 70 663.9 569.9 400 400 1063.9 969.9 168.1 375.5 188.8 25 1.80 50 522.7 458.4 400 400 922.7 858.4 156.9 367.1 184.1 25 1.80 55 540.2 473.2 400 400 940.2 873.2 170.0 392.8 197.0 25 1.80 60 557.5 487.3 400 400 957.5 887.3 183.1 418.8 210.0 25 1.80 65 576.3 501.3 400 400 976.3 901.3 195.8 444.4 222.8 25 1.80 70 593.8 516.4 400 400 993.8 916.4 208.8 469.9 235.6 25 1.98 50 473.8 422.8 400 400 873.8 822.8 191.5 447.6 224.3 25 1.98 55 489.0 436.8 400 400 889.0 836.8 207.0 478.9 240.0 25 1.98 60 505.8 450.3 400 400 905.8 850.3 222.8 510.3 255.8 132

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Appendix A (Continued) 25 1.98 65 522.6 464.1 400 400 922.6 864.1 238.6 542.0 271.6 25 1.98 70 539.8 478.5 400 400 939.8 878.5 254.3 573.3 287.2 50 1.62 50 640.2 551.7 400 400 1040.2 951.7 126.1 293.3 147.1 50 1.62 55 661.6 567.4 400 400 1061.6 967.4 136.5 313.9 157.5 50 1.62 60 682.6 584.0 400 400 1082.6 984.0 147.4 334.4 167.9 50 1.62 65 704.8 600.2 400 400 1104.8 1000.2 157.4 354.8 178.4 50 1.62 70 725.7 615.9 400 400 1125.7 1015.9 167.9 374.6 188.7 50 1.80 50 561.5 492.9 400 400 961.5 892.9 157.0 366.6 183.8 50 1.80 55 579.8 508.0 400 400 979.8 908.0 170.4 392.5 196.9 50 1.80 60 600.3 523.7 400 400 1000.3 923.7 183.2 418.2 209.8 50 1.80 65 619.4 538.7 400 400 1019.4 938.7 196.6 443.8 222.8 50 1.80 70 639.2 553.3 400 400 1039.2 953.3 209.5 469.2 235.7 50 1.98 50 515.3 450.6 400 400 915.3 850.6 191.7 448.6 224.8 50 1.98 55 533.0 465.2 400 400 933.0 865.2 207.6 480.3 240.7 50 1.98 60 549.9 479.3 400 400 949.9 879.3 223.2 511.4 256.3 50 1.98 65 569.1 493.8 400 400 969.1 893.8 239.4 543.1 272.3 50 1.98 70 586.8 508.7 400 400 986.8 908.7 255.2 574.2 288.0 75 1.62 50 699.9 598.8 400 400 1099.9 998.8 126.8 294.3 147.9 75 1.62 55 722.8 616.2 400 400 1122.8 1016.2 137.0 314.7 158.3 75 1.62 60 747.0 633.5 400 400 1147.0 1033.5 147.3 334.9 168.7 75 1.62 65 770.0 650.1 400 400 1170.0 1050.1 157.9 354.4 179.1 75 1.62 70 792.0 667.4 400 400 1192.0 1067.4 168.1 373.7 189.5 75 1.80 50 606.8 529.8 400 400 1006.8 929.8 157.4 367.4 184.4 75 1.80 55 628.7 546.0 400 400 1028.7 946.0 170.2 393.2 197.3 75 1.80 60 649.4 561.6 400 400 1049.4 961.6 183.5 418.9 210.4 75 1.80 65 670.8 577.7 400 400 1070.8 977.7 196.6 444.3 223.3 75 1.80 70 692.2 593.9 400 400 1092.2 993.9 209.2 469.6 236.2 75 1.98 50 544.8 483.1 400 400 944.8 883.1 191.6 448.7 225.0 75 1.98 55 563.9 498.6 400 400 963.9 898.6 207.7 480.3 240.9 75 1.98 60 583.4 513.4 400 400 983.4 913.4 223.6 511.7 256.5 75 1.98 65 601.9 528.3 400 400 1001.9 928.3 239.1 543.0 272.4 75 1.98 70 622.2 544.0 400 400 1022.2 944.0 254.6 573.9 288.0 100 1.62 50 755.5 651.3 400 400 1155.5 1051.3 126.9 293.8 148.0 100 1.62 55 781.1 670.0 400 400 1181.1 1070.0 137.2 313.9 158.4 100 1.62 60 806.2 689.0 400 400 1206.2 1089.0 147.6 333.2 168.8 100 1.62 65 832.1 707.6 400 400 1232.1 1107.6 158.1 352.0 179.2 100 1.62 70 857.8 725.1 400 400 1257.8 1125.1 168.4 369.9 189.7 100 1.80 50 655.8 568.5 400 400 1055.8 968.5 157.5 367.4 184.4 100 1.80 55 679.0 585.6 400 400 1079.0 985.6 170.4 393.1 197.3 100 1.80 60 701.1 602.0 400 400 1101.1 1002.0 183.6 418.5 210.4 100 1.80 65 724.8 619.0 400 400 1124.8 1019.0 197.0 443.6 223.5 100 1.80 70 747.2 638.7 400 400 1147.2 1038.7 209.7 468.0 236.3 100 1.98 50 585.5 512.5 400 400 985.5 912.5 192.1 449.2 225.3 100 1.98 55 606.4 528.9 400 400 1006.4 928.9 207.8 480.3 240.8 100 1.98 60 626.2 544.8 400 400 1026.2 944.8 224.1 511.7 256.8 100 1.98 65 647.7 560.2 400 400 1047.7 960.2 240.2 542.7 272.6 100 1.98 70 668.2 576.2 400 400 1068.2 976.2 255.6 573.7 288.2 125 1.62 50 817.3 713.6 400 400 1217.3 1113.6 127.1 293.3 148.2 125 1.62 55 845.0 733.6 400 400 1245.0 1133.6 137.3 312.4 158.7 125 1.62 60 872.7 752.6 400 400 1272.7 1152.6 147.8 330.6 169.1 125 1.62 65 900.0 771.4 400 400 1300.0 1171.4 158.3 347.7 179.6 125 1.62 70 928.1 790.4 400 400 1328.1 1190.4 168.7 363.7 190.1 125 1.80 50 707.3 611.0 400 400 1107.3 1011.0 158.3 368.3 185.0 125 1.80 55 730.9 629.1 400 400 1130.9 1029.1 171.0 393.6 197.9 133

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Appendix A (Continued) 125 1.80 60 756.1 646.4 400 400 1156.1 1046.4 183.8 418.5 210.8 125 1.80 65 780.1 664.1 400 400 1180.1 1064.1 196.9 442.7 223.9 125 1.80 70 805.5 681.8 400 400 1205.5 1081.8 210.0 466.1 236.9 125 1.98 50 624.8 544.1 400 400 1024.8 944.1 192.2 449.2 225.2 125 1.98 55 646.9 560.4 400 400 1046.9 960.4 208.3 480.6 241.1 125 1.98 60 668.3 576.4 400 400 1068.3 976.4 224.0 511.8 257.0 125 1.98 65 691.1 593.5 400 400 1091.1 993.5 239.9 542.7 272.8 125 1.98 70 712.6 609.7 400 400 1112.6 1009.7 255.6 573.0 288.5 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 50 21.7 25.9 10.9 5.9 5.1 2.7 1.8 14.5 84.2 0 1.62 55 21.8 28.3 12.1 6.7 5.1 2.7 1.8 15.6 98.3 0 1.62 60 21.8 30.2 12.7 6.9 5.1 2.7 1.8 16.4 109.6 0 1.62 65 21.9 32.6 13.9 7.7 5.1 2.7 1.8 17.6 121.0 0 1.62 70 22.0 34.4 14.5 7.9 5.1 2.7 1.9 18.4 132.4 0 1.80 50 27.5 32.2 13.6 7.4 6.4 3.3 2.3 18.0 122.5 0 1.80 55 27.5 35.4 15.2 8.4 6.4 3.3 2.3 19.5 140.5 0 1.80 60 27.5 37.5 15.7 8.5 6.4 3.3 2.3 20.5 154.1 0 1.80 65 27.5 40.1 16.8 9.1 6.4 3.3 2.3 21.7 174.4 0 1.80 70 27.6 43.1 18.3 10.0 6.4 3.3 2.3 23.1 187.5 0 1.98 50 34.1 39.7 17.0 9.5 7.8 4.0 2.8 22.3 167.3 0 1.98 55 34.1 42.9 18.3 10.2 7.8 4.0 2.8 23.8 189.4 0 1.98 60 34.1 45.6 19.1 10.3 7.8 4.0 2.8 25.0 212.0 0 1.98 65 34.1 49.4 21.1 11.7 7.8 4.0 2.8 26.8 232.7 0 1.98 70 34.2 52.1 21.9 11.8 7.8 4.0 2.8 28.1 261.8 25 1.62 50 22.0 25.9 10.9 5.9 5.1 2.6 1.7 14.4 85.8 25 1.62 55 22.1 28.1 11.8 6.4 5.1 2.6 1.7 15.4 95.5 25 1.62 60 22.2 30.2 12.7 6.9 5.1 2.6 1.7 16.4 108.2 25 1.62 65 22.4 32.5 13.8 7.6 5.1 2.6 1.7 17.5 116.4 25 1.62 70 22.7 35.4 15.5 8.9 5.1 2.6 1.7 18.9 131.6 25 1.80 50 27.6 32.8 14.1 7.8 6.4 3.3 2.2 18.3 117.6 25 1.80 55 27.6 35.2 15.0 8.2 6.4 3.3 2.3 19.4 139.3 25 1.80 60 27.7 38.0 16.2 9.0 6.4 3.3 2.3 20.8 150.7 25 1.80 65 27.8 40.2 16.9 9.1 6.4 3.3 2.3 21.8 171.0 25 1.80 70 27.9 43.1 18.2 10.0 6.4 3.3 2.3 23.1 184.7 25 1.98 50 33.7 39.3 16.5 8.9 7.8 4.0 2.7 22.0 163.3 25 1.98 55 33.7 42.5 17.8 9.6 7.8 4.0 2.7 23.5 184.5 25 1.98 60 33.7 45.8 19.2 10.4 7.8 4.0 2.7 25.0 209.1 25 1.98 65 33.8 48.9 20.5 11.0 7.8 4.0 2.7 26.5 230.3 25 1.98 70 33.9 52.1 21.8 11.7 7.8 4.0 2.7 27.9 260.0 50 1.62 50 22.0 25.9 10.8 5.8 5.0 2.5 1.6 14.3 85.6 50 1.62 55 22.1 28.1 11.7 6.3 5.0 2.5 1.6 15.3 94.4 50 1.62 60 22.4 30.3 12.7 6.7 5.0 2.5 1.6 16.3 106.1 50 1.62 65 22.9 32.4 13.5 7.2 5.0 2.5 1.6 17.3 116.4 50 1.62 70 23.7 34.7 14.5 7.7 5.0 2.5 1.6 18.3 127.7 50 1.80 50 27.5 32.4 13.6 7.4 6.3 3.2 2.2 18.0 120.4 50 1.80 55 27.6 35.4 15.1 8.3 6.4 3.2 2.2 19.4 136.7 50 1.80 60 27.7 38.0 16.2 8.9 6.4 3.2 2.2 20.7 147.9 50 1.80 65 27.9 41.2 17.9 10.1 6.4 3.2 2.2 22.2 166.4 50 1.80 70 28.2 43.8 18.9 10.1 6.4 3.2 2.2 23.1 183.7 50 1.98 50 33.7 39.4 16.5 8.9 7.7 3.9 2.7 22.0 161.5 50 1.98 55 33.7 42.6 17.9 9.6 7.7 3.9 2.6 23.5 184.7 50 1.98 60 33.8 45.8 19.2 10.3 7.7 3.9 2.7 25.0 202.6 134

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Appendix A (Continued) 50 1.98 65 33.9 49.6 21.1 11.6 7.7 3.9 2.7 26.8 224.9 50 1.98 70 34.0 52.9 22.5 12.4 7.7 3.9 2.7 28.3 252.5 75 1.62 50 22.3 26.5 11.2 5.9 5.0 2.4 1.5 14.4 84.3 75 1.62 55 22.7 28.6 12.0 6.4 5.0 2.4 1.5 15.4 94.9 75 1.62 60 23.4 30.4 12.6 6.7 5.0 2.4 1.5 16.3 104.6 75 1.62 65 24.5 32.8 13.8 7.3 5.0 2.4 1.5 17.3 116.9 75 1.62 70 26.3 34.8 14.5 7.6 5.0 2.4 1.5 18.3 127.3 75 1.80 50 27.7 32.6 13.8 7.4 6.3 3.1 2.1 18.1 117.1 75 1.80 55 27.8 35.0 14.7 7.9 6.3 3.1 2.1 19.2 132.6 75 1.80 60 28.1 38.0 16.0 8.5 6.3 3.1 2.1 20.5 147.5 75 1.80 65 28.5 40.9 17.2 9.2 6.3 3.1 2.1 21.8 163.1 75 1.80 70 29.3 43.1 18.0 9.5 6.3 3.1 2.1 22.9 180.1 75 1.98 50 33.9 39.4 16.5 8.9 7.7 3.8 2.5 22.0 155.4 75 1.98 55 34.0 42.8 17.9 9.6 7.7 3.8 2.5 23.4 177.4 75 1.98 60 34.1 45.8 19.1 10.2 7.7 3.8 2.5 24.9 199.3 75 1.98 65 34.2 49.1 20.4 10.9 7.7 3.8 2.5 26.4 222.5 75 1.98 70 34.5 52.1 21.6 11.5 7.7 3.8 2.5 27.8 244.9 100 1.62 50 22.8 26.6 11.2 6.0 5.0 2.4 1.5 14.4 84.1 100 1.62 55 23.7 28.4 11.9 6.3 5.0 2.4 1.5 15.3 94.4 100 1.62 60 25.2 30.4 12.7 6.7 5.0 2.4 1.5 16.3 104.5 100 1.62 65 27.4 32.5 13.5 7.1 5.0 2.4 1.5 17.3 115.8 100 1.62 70 30.5 34.7 14.4 7.6 5.0 2.4 1.5 18.2 126.8 100 1.80 50 27.5 32.3 13.4 7.1 6.2 2.9 1.8 17.8 116.3 100 1.80 55 27.9 34.9 14.5 7.6 6.2 2.9 1.8 19.0 130.9 100 1.80 60 28.4 37.8 15.7 8.3 6.2 2.9 1.8 20.2 145.9 100 1.80 65 29.3 40.7 17.0 8.9 6.2 2.9 1.8 21.5 161.8 100 1.80 70 30.8 43.2 17.9 9.4 6.2 2.9 1.8 22.7 178.7 100 1.98 50 33.9 39.7 16.7 9.0 7.6 3.8 2.5 22.0 154.8 100 1.98 55 34.0 42.6 17.8 9.5 7.6 3.8 2.5 23.4 175.3 100 1.98 60 34.2 46.3 19.4 10.3 7.6 3.8 2.5 24.9 196.0 100 1.98 65 34.6 49.9 21.0 11.2 7.6 3.8 2.5 26.5 218.3 100 1.98 70 35.2 52.5 21.9 11.6 7.6 3.8 2.5 27.9 240.2 125 1.62 50 24.1 26.2 11.0 5.9 4.9 2.3 1.5 14.4 83.9 125 1.62 55 25.9 28.3 11.9 6.4 5.0 2.3 1.5 15.4 96.1 125 1.62 60 28.6 30.7 13.0 7.1 5.0 2.3 1.5 16.5 104.9 125 1.62 65 32.4 32.6 13.6 7.3 5.0 2.3 1.5 17.3 117.4 125 1.62 70 37.1 34.8 14.7 7.9 5.0 2.4 1.5 18.4 127.7 125 1.80 50 28.3 32.9 13.8 7.3 6.2 2.9 1.8 17.9 114.7 125 1.80 55 28.9 35.3 14.7 7.8 6.2 2.9 1.8 19.1 128.6 125 1.80 60 30.0 37.9 15.7 8.3 6.2 2.9 1.8 20.3 145.0 125 1.80 65 31.7 40.3 16.7 8.8 6.2 2.9 1.8 21.5 160.5 125 1.80 70 34.2 43.1 17.9 9.4 6.2 2.9 1.8 22.7 177.3 125 1.98 50 33.9 39.4 16.4 8.6 7.5 3.6 2.2 21.7 151.2 125 1.98 55 34.0 42.9 17.8 9.4 7.5 3.6 2.2 23.2 171.2 125 1.98 60 34.6 46.0 19.0 10.0 7.5 3.6 2.2 24.7 193.3 125 1.98 65 35.3 49.2 20.4 10.7 7.5 3.6 2.2 26.2 213.1 125 1.98 70 36.6 52.4 21.7 11.3 7.5 3.6 2.2 27.7 239.0 Run completed Mon May 23 4:52:17 US/Eastern 2005 in 1984 seconds. 135

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Appendix A (Continued) tgcg5ff Measurements. Lambda: 0.09u ClockCycle: 2n Nominal Supply Voltage: 1.8 Volts MinFO: 76 Setup: 400p Model File: t18h.lib Temp Vdd FO cqR cqF dRc dFc dqR dqF 1111 0101 1001 (oC) (V) (ps) (ps) (ps) (ps) (ps) (ps) (uW) (uW) (uW) 0 1.62 76 587.4 515.6 400 400 987.4 915.6 181.9 410.0 205.6 0 1.62 82 604.4 529.1 400 400 1004.4 929.1 194.6 434.5 218.0 0 1.62 88 620.5 542.2 400 400 1020.5 942.2 207.3 459.3 230.5 0 1.62 94 637.2 555.6 400 400 1037.2 955.6 219.6 483.9 242.9 0 1.62 100 654.6 569.1 400 400 1054.6 969.1 232.0 508.6 255.4 0 1.80 76 526.3 467.2 400 400 926.3 867.2 227.0 511.7 256.6 0 1.80 82 540.5 480.1 400 400 940.5 880.1 242.5 542.6 272.0 0 1.80 88 557.0 492.5 400 400 957.0 892.5 258.0 573.6 287.7 0 1.80 94 572.0 505.4 400 400 972.0 905.4 273.3 604.4 303.3 0 1.80 100 586.6 518.8 400 400 986.6 918.8 289.2 635.4 318.7 0 1.98 76 483.4 433.2 400 400 883.4 833.2 276.8 626.3 313.9 0 1.98 82 498.0 446.3 400 400 898.0 846.3 296.2 663.6 332.8 0 1.98 88 511.5 458.9 400 400 911.5 858.9 315.0 700.9 351.5 0 1.98 94 526.9 471.1 400 400 926.9 871.1 333.4 738.7 370.2 0 1.98 100 541.0 483.1 400 400 941.0 883.1 352.3 776.2 389.0 25 1.62 76 642.5 558.7 400 400 1042.5 958.7 182.1 410.1 205.8 25 1.62 82 660.0 573.4 400 400 1060.0 973.4 195.0 434.7 218.3 25 1.62 88 678.9 587.5 400 400 1078.9 987.5 207.8 459.1 230.8 25 1.62 94 697.5 601.4 400 400 1097.5 1001.4 219.8 483.6 243.2 25 1.62 100 714.9 616.0 400 400 1114.9 1016.0 232.3 507.4 255.6 25 1.80 76 573.7 503.7 400 400 973.7 903.7 227.1 512.5 256.9 25 1.80 82 590.8 517.0 400 400 990.8 917.0 243.1 543.6 272.6 25 1.80 88 607.6 531.0 400 400 1007.6 931.0 258.6 574.1 288.0 25 1.80 94 623.7 544.4 400 400 1023.7 944.4 273.9 604.8 303.4 25 1.80 100 641.1 557.6 400 400 1041.1 957.6 289.5 635.3 319.0 25 1.98 76 518.7 465.6 400 400 918.7 865.6 277.6 625.3 313.6 25 1.98 82 534.9 478.9 400 400 934.9 878.9 296.0 663.0 332.4 25 1.98 88 549.9 491.5 400 400 949.9 891.5 315.0 700.9 351.5 25 1.98 94 564.5 504.5 400 400 964.5 904.5 333.9 738.3 370.2 25 1.98 100 581.3 518.0 400 400 981.3 918.0 352.9 775.7 389.1 50 1.62 76 703.7 604.6 400 400 1103.7 1004.6 182.8 410.9 206.4 50 1.62 82 723.6 619.8 400 400 1123.6 1019.8 195.3 435.2 218.9 50 1.62 88 744.3 634.5 400 400 1144.3 1034.5 208.1 459.4 231.5 50 1.62 94 763.4 649.8 400 400 1163.4 1049.8 220.3 482.6 243.8 50 1.62 100 784.6 665.0 400 400 1184.6 1065.0 233.2 505.7 256.5 50 1.80 76 618.0 540.7 400 400 1018.0 940.7 227.4 513.2 257.4 50 1.80 82 636.0 555.6 400 400 1036.0 955.6 242.9 543.7 272.8 50 1.80 88 653.5 569.8 400 400 1053.5 969.8 258.3 574.5 288.3 50 1.80 94 672.8 583.7 400 400 1072.8 983.7 274.9 604.9 304.1 50 1.80 100 690.9 597.9 400 400 1090.9 997.9 289.7 635.2 319.5 50 1.98 76 565.2 497.5 400 400 965.2 897.5 277.4 626.9 314.2 50 1.98 82 581.9 510.2 400 400 981.9 910.2 296.4 664.9 333.3 50 1.98 88 599.1 524.4 400 400 999.1 924.4 315.4 702.5 352.2 50 1.98 94 615.1 538.0 400 400 1015.1 938.0 334.3 739.3 370.9 50 1.98 100 632.3 551.3 400 400 1032.3 951.3 354.1 776.9 390.0 75 1.62 76 767.7 657.4 400 400 1167.7 1057.4 182.8 410.1 206.5 75 1.62 82 789.6 673.5 400 400 1189.6 1073.5 195.8 433.8 219.3 75 1.62 88 811.3 689.7 400 400 1211.3 1089.7 207.9 456.7 231.7 136

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Appendix A (Continued) 75 1.62 94 833.6 705.3 400 400 1233.6 1105.3 220.6 479.0 244.3 75 1.62 100 855.1 721.0 400 400 1255.1 1121.0 233.2 500.4 256.8 75 1.80 76 667.7 581.5 400 400 1067.7 981.5 227.8 512.9 257.4 75 1.80 82 688.0 596.9 400 400 1088.0 996.9 243.3 543.3 272.9 75 1.80 88 707.3 612.0 400 400 1107.3 1012.0 258.2 573.7 288.6 75 1.80 94 727.5 626.6 400 400 1127.5 1026.6 274.8 603.4 304.0 75 1.80 100 747.4 641.5 400 400 1147.4 1041.5 290.4 632.7 319.6 75 1.98 76 600.5 530.3 400 400 1000.5 930.3 277.7 628.4 315.1 75 1.98 82 617.9 544.1 400 400 1017.9 944.1 296.2 665.3 333.6 75 1.98 88 635.8 558.4 400 400 1035.8 958.4 314.9 702.8 352.6 75 1.98 94 654.4 572.9 400 400 1054.4 972.9 335.0 739.7 371.6 75 1.98 100 672.0 586.8 400 400 1072.0 986.8 353.0 777.0 390.5 100 1.62 76 829.8 713.5 400 400 1229.8 1113.5 183.7 408.6 207.1 100 1.62 82 853.5 730.0 400 400 1253.5 1130.0 196.0 431.0 219.6 100 1.62 88 877.5 747.2 400 400 1277.5 1147.2 208.5 452.3 232.1 100 1.62 94 901.1 763.9 400 400 1301.1 1163.9 221.0 472.4 244.6 100 1.62 100 925.0 779.7 400 400 1325.0 1179.7 233.3 491.4 257.1 100 1.80 76 721.7 626.2 400 400 1121.7 1026.2 228.3 513.1 257.9 100 1.80 82 743.3 641.8 400 400 1143.3 1041.8 244.2 543.4 273.7 100 1.80 88 763.8 657.2 400 400 1163.8 1057.2 259.4 572.6 289.1 100 1.80 94 786.1 673.3 400 400 1186.1 1073.3 274.8 601.3 304.6 100 1.80 100 807.0 688.7 400 400 1207.0 1088.7 291.2 629.3 320.4 100 1.98 76 644.6 563.4 400 400 1044.6 963.4 278.7 627.6 315.0 100 1.98 82 664.0 577.7 400 400 1064.0 977.7 297.8 664.9 334.0 100 1.98 88 683.6 593.1 400 400 1083.6 993.1 316.3 702.1 352.8 100 1.98 94 702.1 607.9 400 400 1102.1 1007.9 335.4 738.7 371.7 100 1.98 100 722.5 622.2 400 400 1122.5 1022.2 354.3 774.8 390.6 125 1.62 76 896.2 780.9 400 400 1296.2 1180.9 184.2 404.5 207.3 125 1.62 82 922.1 798.8 400 400 1322.1 1198.8 196.3 424.9 219.8 125 1.62 88 946.9 816.7 400 400 1346.9 1216.7 208.9 443.9 232.3 125 1.62 94 972.8 833.5 400 400 1372.8 1233.5 221.3 461.8 244.8 125 1.62 100 998.9 850.1 400 400 1398.9 1250.1 233.9 478.4 257.2 125 1.80 76 779.1 671.0 400 400 1179.1 1071.0 229.2 512.5 258.7 125 1.80 82 800.0 687.6 400 400 1200.0 1087.6 244.1 541.4 274.0 125 1.80 88 823.4 703.6 400 400 1223.4 1103.6 259.9 569.7 289.7 125 1.80 94 845.9 720.3 400 400 1245.9 1120.3 275.5 596.7 305.2 125 1.80 100 870.8 736.4 400 400 1270.8 1136.4 291.4 622.5 321.0 125 1.98 76 686.6 598.4 400 400 1086.6 998.4 279.1 626.8 315.1 125 1.98 82 707.6 614.4 400 400 1107.6 1014.4 297.2 663.4 333.6 125 1.98 88 727.9 629.8 400 400 1127.9 1029.8 316.0 700.1 352.6 125 1.98 94 748.6 644.7 400 400 1148.6 1044.7 335.4 736.0 371.7 125 1.98 100 769.7 660.5 400 400 1169.7 1060.5 354.5 771.0 390.7 Temp Vdd FO 0000 20_1 50_1 100_1 20_0 50_0 100_0 FFp tbP (oC) (V) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) (uW) 0 1.62 76 24.4 37.4 15.6 8.3 5.7 2.9 2.0 20.0 135.7 0 1.62 82 24.5 40.3 17.1 9.4 5.7 2.9 2.0 21.4 148.5 0 1.62 88 24.7 43.2 18.5 10.3 5.7 2.9 2.0 22.8 166.1 0 1.62 94 24.9 45.6 19.5 10.8 5.7 2.9 2.0 23.9 175.0 0 1.62 100 25.2 47.9 20.2 10.9 5.7 2.9 2.0 24.9 192.3 0 1.80 76 30.5 46.8 19.6 10.5 7.2 3.7 2.6 25.1 197.5 0 1.80 82 30.6 49.8 20.8 11.1 7.2 3.7 2.6 26.5 213.5 0 1.80 88 30.7 53.0 22.1 11.8 7.2 3.7 2.6 27.9 232.0 0 1.80 94 30.8 56.5 23.5 12.5 7.2 3.7 2.6 29.4 258.4 137

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Appendix A (Continued) 0 1.80 100 31.0 59.2 24.6 13.0 7.2 3.7 2.6 30.8 277.6 0 1.98 76 37.8 56.8 23.8 12.8 8.8 4.6 3.3 30.7 268.0 0 1.98 82 37.9 61.2 25.9 13.9 8.8 4.6 3.3 32.6 292.4 0 1.98 88 37.9 65.1 27.4 14.7 8.8 4.6 3.3 34.3 318.9 0 1.98 94 37.9 68.3 28.5 15.2 8.8 4.6 3.3 36.0 357.5 0 1.98 100 38.0 72.2 30.1 16.0 8.8 4.6 3.3 37.7 385.5 25 1.62 76 24.8 37.7 16.0 8.7 5.7 2.9 1.9 20.2 135.2 25 1.62 82 25.0 40.7 17.5 9.7 5.7 2.9 2.0 21.6 147.6 25 1.62 88 25.3 43.6 18.9 10.7 5.7 2.9 1.9 22.9 162.2 25 1.62 94 25.9 45.4 19.2 10.4 5.7 2.9 2.0 23.8 175.0 25 1.62 100 26.8 48.1 20.5 11.2 5.7 2.9 1.9 25.0 196.3 25 1.80 76 30.7 46.6 19.4 10.3 7.1 3.6 2.4 24.9 193.3 25 1.80 82 30.9 49.9 20.9 11.2 7.1 3.6 2.5 26.5 213.1 25 1.80 88 31.0 53.5 22.6 12.4 7.1 3.6 2.4 28.2 231.0 25 1.80 94 31.3 56.4 23.7 12.9 7.1 3.6 2.4 29.6 254.5 25 1.80 100 31.6 59.7 25.2 13.6 7.2 3.6 2.4 31.1 273.1 25 1.98 76 37.8 57.1 24.0 13.0 8.8 4.5 3.0 30.7 263.8 25 1.98 82 37.9 60.5 25.2 13.4 8.8 4.5 3.0 32.2 291.2 25 1.98 88 38.0 65.0 27.4 14.9 8.8 4.5 3.1 34.3 317.5 25 1.98 94 38.2 68.8 28.9 15.7 8.8 4.5 3.1 36.1 353.2 25 1.98 100 38.3 73.0 30.9 16.9 8.8 4.5 3.1 38.1 381.3 50 1.62 76 25.3 37.6 15.7 8.3 5.6 2.8 1.8 19.9 134.4 50 1.62 82 25.8 40.2 16.7 8.8 5.7 2.8 1.8 21.1 146.1 50 1.62 88 26.8 42.9 17.8 9.4 5.7 2.8 1.8 22.3 159.7 50 1.62 94 28.2 45.4 18.9 9.9 5.7 2.8 1.8 23.5 175.1 50 1.62 100 30.2 48.3 20.1 10.6 5.7 2.8 1.8 24.7 188.0 50 1.80 76 31.0 46.9 19.7 10.6 7.1 3.6 2.4 25.1 189.2 50 1.80 82 31.2 50.0 21.0 11.3 7.1 3.6 2.4 26.6 207.3 50 1.80 88 31.6 52.9 22.0 11.7 7.1 3.6 2.4 27.9 230.4 50 1.80 94 32.1 57.6 24.9 14.1 7.1 3.6 2.4 30.2 250.5 50 1.80 100 33.1 59.7 25.1 13.6 7.1 3.6 2.4 31.1 275.1 50 1.98 76 37.9 56.8 23.7 12.6 8.7 4.4 2.9 30.5 261.1 50 1.98 82 38.1 60.8 25.3 13.5 8.7 4.4 2.9 32.3 284.6 50 1.98 88 38.2 64.8 27.1 14.5 8.7 4.4 2.9 34.2 315.2 50 1.98 94 38.6 68.9 29.0 15.7 8.7 4.4 2.9 36.1 341.9 50 1.98 100 39.0 72.8 30.7 16.6 8.7 4.4 2.9 37.9 378.9 75 1.62 76 26.4 37.4 15.5 8.1 5.6 2.7 1.7 19.9 133.5 75 1.62 82 27.8 40.3 16.7 8.8 5.6 2.7 1.7 21.1 145.7 75 1.62 88 29.8 42.6 17.6 9.2 5.6 2.7 1.7 22.2 159.6 75 1.62 94 32.6 45.2 18.7 9.8 5.6 2.7 1.7 23.4 173.4 75 1.62 100 36.3 47.8 19.8 10.3 5.6 2.7 1.7 24.6 187.8 75 1.80 76 31.4 47.0 19.6 10.4 7.1 3.6 2.4 25.0 186.0 75 1.80 82 31.9 50.0 20.8 11.0 7.1 3.6 2.4 26.4 203.8 75 1.80 88 32.7 53.4 22.3 11.8 7.1 3.6 2.4 27.9 223.4 75 1.80 94 33.9 56.3 23.4 12.3 7.1 3.6 2.4 29.3 244.7 75 1.80 100 35.7 59.5 24.7 13.0 7.1 3.6 2.4 30.8 267.1 75 1.98 76 38.1 57.3 23.9 12.7 8.7 4.3 2.9 30.5 250.2 75 1.98 82 38.3 60.8 25.2 13.3 8.7 4.3 2.9 32.2 278.0 75 1.98 88 38.7 64.5 26.7 14.1 8.7 4.3 2.9 33.9 305.1 75 1.98 94 39.2 69.5 29.1 15.3 8.7 4.3 2.9 35.9 336.2 75 1.98 100 40.2 72.5 30.0 15.8 8.7 4.3 2.9 37.5 365.4 100 1.62 76 28.9 38.0 15.9 8.3 5.5 2.6 1.7 20.0 132.5 100 1.62 82 31.7 40.2 16.7 8.7 5.6 2.6 1.7 21.1 144.9 100 1.62 88 35.3 42.8 17.7 9.2 5.6 2.7 1.7 22.2 158.3 138

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Appendix A (Continued) 100 1.62 94 40.0 45.3 18.7 9.7 5.5 2.6 1.7 23.4 171.1 100 1.62 100 45.6 47.6 19.5 10.1 5.6 2.6 1.7 24.5 185.4 100 1.80 76 32.2 46.9 19.4 10.2 7.0 3.3 2.1 24.8 183.8 100 1.80 82 33.3 50.4 20.9 11.0 7.0 3.3 2.1 26.3 202.2 100 1.80 88 34.9 53.3 22.1 11.5 7.0 3.3 2.1 27.7 223.9 100 1.80 94 37.2 56.2 23.1 12.0 7.0 3.3 2.1 29.1 243.3 100 1.80 100 40.5 60.2 25.1 13.1 7.0 3.3 2.1 30.8 265.6 100 1.98 76 38.1 57.7 24.1 12.8 8.6 4.2 2.8 30.5 247.8 100 1.98 82 38.6 61.8 25.9 13.7 8.6 4.2 2.8 32.3 273.2 100 1.98 88 39.3 65.0 27.0 14.2 8.6 4.2 2.8 34.0 299.2 100 1.98 94 40.5 69.1 28.8 15.1 8.6 4.2 2.8 35.8 328.1 100 1.98 100 42.2 72.8 30.2 15.9 8.6 4.2 2.8 37.5 359.5 125 1.62 76 33.6 37.9 15.9 8.5 5.5 2.6 1.6 20.1 133.6 125 1.62 82 38.4 40.4 16.9 9.1 5.5 2.6 1.6 21.2 145.3 125 1.62 88 44.0 43.1 18.1 9.8 5.5 2.6 1.6 22.5 159.4 125 1.62 94 50.9 46.0 19.6 10.7 5.6 2.6 1.6 23.8 170.7 125 1.62 100 58.7 48.1 20.1 10.7 5.5 2.6 1.6 24.8 187.1 125 1.80 76 33.8 47.4 19.8 10.4 6.9 3.3 2.0 24.9 182.6 125 1.80 82 35.9 49.9 20.6 10.8 6.9 3.3 2.0 26.2 201.9 125 1.80 88 38.9 53.2 22.0 11.5 6.9 3.3 2.0 27.7 221.4 125 1.80 94 42.9 56.3 23.2 12.1 6.9 3.3 2.0 29.1 241.6 125 1.80 100 48.1 59.7 24.7 12.9 6.9 3.3 2.0 30.6 262.3 125 1.98 76 38.7 58.1 24.4 12.9 8.5 4.2 2.7 30.6 242.2 125 1.98 82 39.6 61.2 25.5 13.4 8.5 4.2 2.7 32.2 268.1 125 1.98 88 41.0 64.8 26.8 14.1 8.5 4.2 2.7 33.9 294.8 125 1.98 94 43.0 69.0 28.7 15.1 8.5 4.2 2.7 35.8 325.9 125 1.98 100 45.8 73.1 30.4 16.0 8.5 4.2 2.7 37.6 355.2 Run completed Mon May 23 5:25:54 US/Eastern 2005 in 2017 seconds. 139

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Appendix B Interface Programs Two programs, written in C++, were implemented for establishing an interface from Cadence Schematics to Hspice. Each flip-flop was initially designed using the Cadence Schematic Tool. An hspice netlist was extracted from the flip-flop schematic. The extracted netlist can be flat or hierarchical. Flatad.exe, the first program, was designed for adapting flat netlists to Hspice. An example of a flat Netlist, which was extracted from the Cadence Schematic and used as an input to flatad.exe program follows: net n1 = gnd! net n0 = vdd! net n2 = /Qb net n3 = /net0133 net n5 = /S net n6 = /net075 net n7 = /net0196 net n8 = /net16 net n9 = /net056 net n10 = /net0129 net n11 = /net0171 net n12 = /R net n13 = /scan net n14 = /Q net n15 = /D net n16 = /net0177 net n17 = /net085 net n18 = /net25 net n20 = /net073 net n21 = /Sb net n22 = /net079 net n23 = /net077 net n24 = /net044 net n25 = /Rb net n26 = /clearb net n27 = /SD net n28 = /Clk net n29 = /net088 net n30 = /net20 .model modelm2 nmos level=2 vto=0.7 gamma=0.2 kp=3e-05 +lambda=0.02 tox=6e-07 nmos(x0) = /I23/n0 mx0 n20 n15 n1 n1 modelm2 w=4 l=2u .model modelm3 pmos level=2 vto=-0.7 gamma=0.4 kp=1.5e-05 +lambda=0.03 tox=6e-07 pmos(x1) = /I23/P0 mx1 n20 n15 n0 n0 modelm3 w=4 l=2u nmos(x2) = /I24/n0 140

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Appendix B (Continued) mx2 n6 n27 n1 n1 modelm2 w=4 l=2u pmos(x3) = /I24/P0 mx3 n6 n27 n0 n0 modelm3 w=4 l=2u nmos(x4) = /I25/n0 mx4 n23 n6 n1 n1 modelm2 w=4 l=2u pmos(x5) = /I25/P0 mx5 n23 n6 n0 n0 modelm3 w=4 l=2u nmos(x6) = /I26/n0 mx6 n7 n13 n1 n1 modelm2 w=4 l=2u pmos(x7) = /I26/P0 mx7 n7 n13 n0 n0 modelm3 w=4 l=2u nmos(x8) = /I19/n0 mx8 n12 n25 n1 n1 modelm2 w=4 l=2u pmos(x9) = /I19/P0 mx9 n12 n25 n0 n0 modelm3 w=4 l=2u nmos(x10) = /I18/n0 mx10 n5 n21 n1 n1 modelm2 w=4 l=2u pmos(x11) = /I18/P0 mx11 n5 n21 n0 n0 modelm3 w=4 l=2u nmos(x12) = /I21/n0 mx12 n17 n26 n1 n1 modelm2 w=4 l=2u pmos(x13) = /I21/P0 mx13 n17 n26 n0 n0 modelm3 w=4 l=2u nmos(x14) = /N19 mx14 n21 n25 n30 n1 modelm2 w=11.5 l=2u nmos(x15) = /N20 mx15 n25 n21 n18 n1 modelm2 w=16 l=2u nmos(x16) = /N21 mx16 n25 n17 n1 n1 modelm2 w=16 l=2u nmos(x17) = /N17 mx17 n30 n0 n18 n1 modelm2 w=11.5 l=2u nmos(x18) = /N22 mx18 n30 n23 n3 n1 modelm2 w=16 l=2u nmos(x19) = /N23 mx19 n18 n20 n10 n1 modelm2 w=16 l=2u nmos(x20) = /N24 mx20 n18 n6 n3 n1 modelm2 w=16 l=2u nmos(x21) = /N11 mx21 n14 n21 n24 n1 modelm2 w=5u l=2u nmos(x22) = /N12 mx22 n14 n12 n1 n1 modelm2 w=5u l=2u nmos(x23) = /N13 mx23 n9 n14 n1 n1 modelm2 w=5u l=2u nmos(x24) = /N14 mx24 n2 n25 n9 n1 modelm2 w=5u l=2u nmos(x25) = /N15 mx25 n2 n5 n1 n1 modelm2 w=5u l=2u nmos(x26) = /N16 mx26 n24 n2 n1 n1 modelm2 w=5u l=2u nmos(x27) = /N2 mx27 n8 n28 n1 n1 modelm2 w=27.5 l=2u nmos(x28) = /N1 mx28 n30 n15 n10 n1 modelm2 w=16 l=2u nmos(x29) = /N25 141

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Appendix B (Continued) mx29 n3 n13 n8 n1 modelm2 w=11.5 l=2u nmos(x30) = /N3 mx30 n10 n7 n8 n1 modelm2 w=11.5 l=2u pmos(x31) = /P10 mx31 n16 n17 n0 n0 modelm3 w=2 l=2u pmos(x32) = /P13 mx32 n25 n21 n0 n0 modelm3 w=2 l=2u pmos(x33) = /P4 mx33 n14 n21 n0 n0 modelm3 w=10u l=2u pmos(x34) = /P5 mx34 n14 n12 n22 n0 modelm3 w=10u l=2u pmos(x35) = /P6 mx35 n29 n14 n0 n0 modelm3 w=10u l=2u pmos(x36) = /P7 mx36 n22 n2 n0 n0 modelm3 w=10u l=2u pmos(x37) = /P8 mx37 n2 n25 n0 n0 modelm3 w=10u l=2u pmos(x38) = /P9 mx38 n2 n5 n29 n0 modelm3 w=10u l=2u pmos(x39) = /P11 mx39 n21 n26 n0 n0 modelm3 w=2 l=2u pmos(x40) = /P2 mx40 n11 n17 n0 n0 modelm3 w=5 l=2u pmos(x41) = /P3 mx41 n25 n28 n11 n0 modelm3 w=2 l=2u pmos(x42) = /P1 mx42 n21 n25 n0 n0 modelm3 w=25 l=2u pmos(x43) = /P0 mx43 n21 n28 n16 n0 modelm3 w=test l=2u The following is the corresponding ouput produced by the flatad.exe program. FILE: sarsaff.hsp HSPICE netlist for sarsaff subckt. .param dDiff = 4 drain Diffusion length from gate (in lambda) .param sDiff = 6 source Diffusion length from gate (in lambda) * * * .SUBCKT sarsaff Clk D Db Q Qb Mn0 <==> I23.n0 Mn0 n20 D gnd gnd cmosn W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mp1 <==> I23.P0 Mp1 n20 D vdd vdd cmosp W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mn2 <==> I24.n0 Mn2 n6 SD gnd gnd cmosn W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' 142

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Appendix B (Continued) + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mp3 <==> I24.P0 Mp3 n6 SD vdd vdd cmosp W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mn4 <==> I25.n0 Mn4 n23 n6 gnd gnd cmosn W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mp5 <==> I25.P0 Mp5 n23 n6 vdd vdd cmosp W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mn6 <==> I26.n0 Mn6 n7 scan gnd gnd cmosn W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mp7 <==> I26.P0 Mp7 n7 scan vdd vdd cmosp W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mn8 <==> I19.n0 Mn8 R Rb gnd gnd cmosn W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mp9 <==> I19.P0 Mp9 R Rb vdd vdd cmosp W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mn10 <==> I18.n0 Mn10 S Sb gnd gnd cmosn W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mp11 <==> I18.P0 Mp11 S Sb vdd vdd cmosp W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mn12 <==> I21.n0 Mn12 n17 clearb gnd gnd cmosn W=4 L=2 GEO=1 + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mp13 <==> I21.P0 Mp13 n17 clearb vdd vdd cmosp W=4 L=2 GEO=1 143

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Appendix B (Continued) + AS='4*sDiff' AD='4*dDiff' + PS='2*(sDiff+4)' PD='2*(pDiff+4)' + NRS='sDiff/4' NRD='dDiff/4' Mn14 <==> N19 Mn14 Sb Rb n30 gnd cmosn W=11.5 L=2 GEO=1 + AS='11.5*sDiff' AD='11.5*dDiff' + PS='2*(sDiff+11.5)' PD='2*(pDiff+11.5)' + NRS='sDiff/11.5' NRD='dDiff/11.5' Mn15 <==> N20 Mn15 Rb Sb n18 gnd cmosn W=16 L=2 GEO=1 + AS='16*sDiff' AD='16*dDiff' + PS='2*(sDiff+16)' PD='2*(pDiff+16)' + NRS='sDiff/16' NRD='dDiff/16' Mn16 <==> N21 Mn16 Rb n17 gnd gnd cmosn W=16 L=2 GEO=1 + AS='16*sDiff' AD='16*dDiff' + PS='2*(sDiff+16)' PD='2*(pDiff+16)' + NRS='sDiff/16' NRD='dDiff/16' Mn17 <==> N17 Mn17 n30 vdd n18 gnd cmosn W=11.5 L=2 GEO=1 + AS='11.5*sDiff' AD='11.5*dDiff' + PS='2*(sDiff+11.5)' PD='2*(pDiff+11.5)' + NRS='sDiff/11.5' NRD='dDiff/11.5' Mn18 <==> N22 Mn18 n30 n23 n3 gnd cmosn W=16 L=2 GEO=1 + AS='16*sDiff' AD='16*dDiff' + PS='2*(sDiff+16)' PD='2*(pDiff+16)' + NRS='sDiff/16' NRD='dDiff/16' Mn19 <==> N23 Mn19 n18 n20 n10 gnd cmosn W=16 L=2 GEO=1 + AS='16*sDiff' AD='16*dDiff' + PS='2*(sDiff+16)' PD='2*(pDiff+16)' + NRS='sDiff/16' NRD='dDiff/16' Mn20 <==> N24 Mn20 n18 n6 n3 gnd cmosn W=16 L=2 GEO=1 + AS='16*sDiff' AD='16*dDiff' + PS='2*(sDiff+16)' PD='2*(pDiff+16)' + NRS='sDiff/16' NRD='dDiff/16' Mn21 <==> N11 Mn21 Q Sb n24 gnd cmosn W=5u L=2 GEO=1 + AS='5u*sDiff' AD='5u*dDiff' + PS='2*(sDiff+5u)' PD='2*(pDiff+5u)' + NRS='sDiff/5u' NRD='dDiff/5u' Mn22 <==> N12 Mn22 Q R gnd gnd cmosn W=5u L=2 GEO=1 + AS='5u*sDiff' AD='5u*dDiff' + PS='2*(sDiff+5u)' PD='2*(pDiff+5u)' + NRS='sDiff/5u' NRD='dDiff/5u' Mn23 <==> N13 Mn23 n9 Q gnd gnd cmosn W=5u L=2 GEO=1 + AS='5u*sDiff' AD='5u*dDiff' + PS='2*(sDiff+5u)' PD='2*(pDiff+5u)' + NRS='sDiff/5u' NRD='dDiff/5u' Mn24 <==> N14 144

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Appendix B (Continued) Mn24 Qb Rb n9 gnd cmosn W=5u L=2 GEO=1 + AS='5u*sDiff' AD='5u*dDiff' + PS='2*(sDiff+5u)' PD='2*(pDiff+5u)' + NRS='sDiff/5u' NRD='dDiff/5u' Mn25 <==> N15 Mn25 Qb S gnd gnd cmosn W=5u L=2 GEO=1 + AS='5u*sDiff' AD='5u*dDiff' + PS='2*(sDiff+5u)' PD='2*(pDiff+5u)' + NRS='sDiff/5u' NRD='dDiff/5u' Mn26 <==> N16 Mn26 n24 Qb gnd gnd cmosn W=5u L=2 GEO=1 + AS='5u*sDiff' AD='5u*dDiff' + PS='2*(sDiff+5u)' PD='2*(pDiff+5u)' + NRS='sDiff/5u' NRD='dDiff/5u' Mn27 <==> N2 Mn27 n8 Clk gnd gnd cmosn W=27.5 L=2 GEO=1 + AS='27.5*sDiff' AD='27.5*dDiff' + PS='2*(sDiff+27.5)' PD='2*(pDiff+27.5)' + NRS='sDiff/27.5' NRD='dDiff/27.5' Mn28 <==> N1 Mn28 n30 D n10 gnd cmosn W=16 L=2 GEO=1 + AS='16*sDiff' AD='16*dDiff' + PS='2*(sDiff+16)' PD='2*(pDiff+16)' + NRS='sDiff/16' NRD='dDiff/16' Mn29 <==> N25 Mn29 n3 scan n8 gnd cmosn W=11.5 L=2 GEO=1 + AS='11.5*sDiff' AD='11.5*dDiff' + PS='2*(sDiff+11.5)' PD='2*(pDiff+11.5)' + NRS='sDiff/11.5' NRD='dDiff/11.5' Mn30 <==> N3 Mn30 n10 n7 n8 gnd cmosn W=11.5 L=2 GEO=1 + AS='11.5*sDiff' AD='11.5*dDiff' + PS='2*(sDiff+11.5)' PD='2*(pDiff+11.5)' + NRS='sDiff/11.5' NRD='dDiff/11.5' Mp31 <==> P10 Mp31 n16 n17 vdd vdd cmosp W=2 L=2 GEO=1 + AS='2*sDiff' AD='2*dDiff' + PS='2*(sDiff+2)' PD='2*(pDiff+2)' + NRS='sDiff/2' NRD='dDiff/2' Mp32 <==> P13 Mp32 Rb Sb vdd vdd cmosp W=2 L=2 GEO=1 + AS='2*sDiff' AD='2*dDiff' + PS='2*(sDiff+2)' PD='2*(pDiff+2)' + NRS='sDiff/2' NRD='dDiff/2' Mp33 <==> P4 Mp33 Q Sb vdd vdd cmosp W=10u L=2 GEO=1 + AS='10u*sDiff' AD='10u*dDiff' + PS='2*(sDiff+10u)' PD='2*(pDiff+10u)' + NRS='sDiff/10u' NRD='dDiff/10u' Mp34 <==> P5 Mp34 Q R n22 vdd cmosp W=10u L=2 GEO=1 + AS='10u*sDiff' AD='10u*dDiff' + PS='2*(sDiff+10u)' PD='2*(pDiff+10u)' + NRS='sDiff/10u' NRD='dDiff/10u' 145

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Appendix B (Continued) Mp35 <==> P6 Mp35 n29 Q vdd vdd cmosp W=10u L=2 GEO=1 + AS='10u*sDiff' AD='10u*dDiff' + PS='2*(sDiff+10u)' PD='2*(pDiff+10u)' + NRS='sDiff/10u' NRD='dDiff/10u' Mp36 <==> P7 Mp36 n22 Qb vdd vdd cmosp W=10u L=2 GEO=1 + AS='10u*sDiff' AD='10u*dDiff' + PS='2*(sDiff+10u)' PD='2*(pDiff+10u)' + NRS='sDiff/10u' NRD='dDiff/10u' Mp37 <==> P8 Mp37 Qb Rb vdd vdd cmosp W=10u L=2 GEO=1 + AS='10u*sDiff' AD='10u*dDiff' + PS='2*(sDiff+10u)' PD='2*(pDiff+10u)' + NRS='sDiff/10u' NRD='dDiff/10u' Mp38 <==> P9 Mp38 Qb S n29 vdd cmosp W=10u L=2 GEO=1 + AS='10u*sDiff' AD='10u*dDiff' + PS='2*(sDiff+10u)' PD='2*(pDiff+10u)' + NRS='sDiff/10u' NRD='dDiff/10u' Mp39 <==> P11 Mp39 Sb clearb vdd vdd cmosp W=2 L=2 GEO=1 + AS='2*sDiff' AD='2*dDiff' + PS='2*(sDiff+2)' PD='2*(pDiff+2)' + NRS='sDiff/2' NRD='dDiff/2' Mp40 <==> P2 Mp40 n11 n17 vdd vdd cmosp W=5 L=2 GEO=1 + AS='5*sDiff' AD='5*dDiff' + PS='2*(sDiff+5)' PD='2*(pDiff+5)' + NRS='sDiff/5' NRD='dDiff/5' Mp41 <==> P3 Mp41 Rb Clk n11 vdd cmosp W=2 L=2 GEO=1 + AS='2*sDiff' AD='2*dDiff' + PS='2*(sDiff+2)' PD='2*(pDiff+2)' + NRS='sDiff/2' NRD='dDiff/2' Mp42 <==> P1 Mp42 Sb Rb vdd vdd cmosp W=25 L=2 GEO=1 + AS='25*sDiff' AD='25*dDiff' + PS='2*(sDiff+25)' PD='2*(pDiff+25)' + NRS='sDiff/25' NRD='dDiff/25' Mp43 <==> P0 Mp43 Sb Clk n16 vdd cmosp W=test L=2 GEO=1 + AS='test*sDiff' AD='test*dDiff' + PS='2*(sDiff+test)' PD='2*(pDiff+test)' + NRS='sDiff/test' NRD='dDiff/test' .ENDS $ sarsaff .GLOBAL gnd vdd Assumed parameters hdif=dDiff=4 hdif2=sDiff=6 cgate=2.0 resSD=1 Hiead.exe, the second program, adapts hierarchical netlists to hspice. 146

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Appendix B (Continued) The following is an example of a hierarchical netlist extracted from the Cadence Schematic Tool and used as input to hiead.exe program. $********************************************* $ Main Circuit Netlist: $ $ Block: tg1ff $ Last Time Saved: May 22 08:53:09 2005 $********************************************* xi30 cn cpi inv xi29 bb cn inv xi28 aa bb inv xi27 clk aa inv mxp3 sm cn net095 n0 pfet w=4 l=2 mxp2 net095 qm vdd n0 pfet w=4 l=2 mxp6 net099 qsb vdd n0 pfet w=4 l=2 mxp4 qm sm vdd n0 pfet w=4 l=2 mxp7 ss cpi net099 n0 pfet w=4 l=2 mxp5 qm cn ss n0 pfet w=4 l=2 mxp9 q qsb vdd n0 pfet w=12 l=2 mxp8 qsb ss vdd n0 pfet w=8 l=2 mxp1 db cpi sm n0 pfet w=4 l=2 mxn9 q qsb gnd gnd nmos w=6 l=2 mxn5 qm cpi ss gnd nmos w=2 l=2 mxn6 ss cn net0120 gnd nmos w=2 l=2 mxn7 net0120 qsb gnd gnd nmos w=2 l=2 mxn8 qsb ss gnd gnd nmos w=4 l=2 mxn0 db d gnd gnd nmos w=2 l=2 mxn3 net2 qm gnd gnd nmos w=2 l=2 mxn2 sm cpi net2 gnd nmos w=2 l=2 mxn1 db cn sm gnd nmos w=2 l=2 mxn4 qm sm gnd gnd nmos w=2 l=2 mxp0 db d vdd vdd pmos w=4 l=2 The following is the corresponding ouput produced by the hieadad.exe program. FILE: tg1ff.sp HSPICE netlist for tg1ff subckt. .param dDiff = 5 drain Diffusion length from gate (in lambda) .param sDiff = 7 source Diffusion length from gate (in lambda) .GLOBAL gnd vdd * * * .SUBCKT inv a y nw=2 pw=5 mxn0 y a gnd gnd cmosn w=nw L=2 + AS='nw*sDiff' AD='nw*dDiff' PS='(2*sDiff)+nw' PD='(2*dDiff)+nw' + NRS='sDiff/nw' NRD='dDiff/nw' mxp0 y a vdd vdd cmosp w=pw L=2 147

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Appendix B (Continued) + AS='pw*sDiff' AD='pw*dDiff' PS='(2*sDiff)+pw' PD='(2*dDiff)+pw' + NRS='sDiff/pw' NRD='dDiff/pw' .ENDS $ inv * * * .SUBCKT tg1ff Clk D Q xi30 cn cpi inv nw=3 pw=6 m=1 xi29 bb cn inv nw=3 pw=6 m=1 xi28 aa bb inv nw=2 pw=4 m=1 xi27 clk aa inv nw=2 pw=4 m=1 mxp3 sm cn net095 n0 cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxp2 net095 qm vdd n0 cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxp6 net099 qsb vdd n0 cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxp4 qm sm vdd n0 cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxp7 ss cpi net099 n0 cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxp5 qm cn ss n0 cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxp9 q qsb vdd n0 cmosp w=12 L=2 m=1 + AS='12.00*sDiff' AD='12.00*dDiff' PS='(2*sDiff)+12.00' + PD='(2*dDiff)+12.00' + NRS='sDiff/12.00' NRD='dDiff/12.00' mxp8 qsb ss vdd n0 cmosp w=8 L=2 m=1 + AS='8.00*sDiff' AD='8.00*dDiff' PS='(2*sDiff)+8.00' + PD='(2*dDiff)+8.00' + NRS='sDiff/8.00' NRD='dDiff/8.00' mxp1 db cpi sm n0 cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxn9 q qsb gnd gnd cmosn w=6 L=2 m=1 + AS='6.00*sDiff' AD='6.00*dDiff' PS='(2*sDiff)+6.00' + PD='(2*dDiff)+6.00' + NRS='sDiff/6.00' NRD='dDiff/6.00' mxn5 qm cpi ss gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' 148

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Appendix B (Continued) mxn6 ss cn net0120 gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' mxn7 net0120 qsb gnd gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' mxn8 qsb ss gnd gnd cmosn w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' mxn0 db d gnd gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' mxn3 net2 qm gnd gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' mxn2 sm cpi net2 gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' mxn1 db cn sm gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' mxn4 qm sm gnd gnd cmosn w=2 L=2 m=1 + AS='2.00*sDiff' AD='2.00*dDiff' PS='(2*sDiff)+2.00' + PD='(2*dDiff)+2.00' + NRS='sDiff/2.00' NRD='dDiff/2.00' mxp0 db d vdd vdd cmosp w=4 L=2 m=1 + AS='4.00*sDiff' AD='4.00*dDiff' PS='(2*sDiff)+4.00' + PD='(2*dDiff)+4.00' + NRS='sDiff/4.00' NRD='dDiff/4.00' .ENDS $ tg1ff 149

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ABOUT THE AUTHOR Jorge Galvis received his B.S. in Electronics Engineering from the Universidad Distrital Francisco Jose de Caldas in Bogota, Colombia. Jorge obtained a M.S. in Electrical Engineering from the Universidad de Los Andes, Bogota, Colombia. He obtained a second M.S. in Electrical Engineering from the University of South Florida. This dissertation represents the culmination of Jorges Ph.D. studies under the supervision of Dr. Wilfrido Moreno at the University of South Florida. Jorges current research interests are in Digital and Analog VLSI Design, Computer Architecture and Digital Signal Processing.


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Galvis, Jorge Alberto.
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Low-power flip-flop using internal clock gating and adaptive body bias
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by Jorge Alberto Galvis.
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[Tampa, Fla] :
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2006.
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ABSTRACT: This dissertation presents a new systematic approach to flip-flop design using Internal Clock Gating, (ICG), and Adaptive Body-Bias, (ABB), in order to reduce power consumption. The process requires careful transistor resizing in order to maintain signal integrity and the functionality of the flip-flop at the target frequency.A novel flip-flop architecture, based on the Transmission Gate Flip-Flop, (TGFF), which incorporated ICG and ABB techniques, was designed. This architecture was simulated intensively in order to determine under what conditions its use is appropriate. In addition, it was necessary to establish a methodology for creating a standard testbench and environment setup for the required Hspice simulations. Software tools were written in C++ and Perl in order to facilitate the interface between Cadence Design Tools and Hspice.The new flip-flop, which was named the Low-Power Flip-Flop, (LPFF), was compared to the Transmission-Gate Flip-Flop, (TGFF), and to the Transmission-Gate with Clock-Gating Flip-Flop, (TGCGFF). Comprehensive Hspice simulations of the three flip-flop designs, implemented with Bsim3v3 transistor models for TSMC 180 nm technology, were used as the means of comparison.Simulations demonstrated that the new flip-flop is appropriate for applications that require low switching activity. In such a situation the LPFF consumes 7.8% to 95.7% less power than the TGFF and 0.8% to 23.7% less power than the TGCGFF. Power savings obtained by the LPFF increase as the length of the period with no switching activity increases, especially when the input data is all zeros. The trade-off is an increase in the D-to-Q delays and in the flip-flop area. The LPFF presented D-to-Q delays of 60% to 69% longer than the delays of the TGFF and 9% to 11% longer than the delays of the TGCGFF. The LPFF cells require an area that is 15% to 34% larger than the TGFF cells and 6% to 17% larger than the TGCGFF cells.
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Dissertation (Ph.D.)--University of South Florida, 2006.
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Adviser: Wilfrido Moreno, Ph.D.
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Clocked Storage Elements.
Logical effort.
Spice simulations.
Power consumption.
Clocked logical units.
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Dissertations, Academic
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