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Growth of 3C-SiC via a hot-wall CVD reactor

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Title:
Growth of 3C-SiC via a hot-wall CVD reactor
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Harvey, Suzie
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Silicon carbide
Heteroepitaxy
SOI
Crystal defects
Chemical vapor deposition
Dissertations, Academic -- Electrical Engineering -- Masters -- USF   ( lcsh )
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theses   ( marcgt )
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Abstract:
ABSTRACT: The heteroepitaxial growth of cubic silicon carbide (3C-SiC) on silicon (Si) substrates at high growth rates, via a horizontal hot-wall chemical vapor deposition (CVD) reactor, has been achieved. The final growth process was developed in three stages; an initial "baseline" development stage, an optimization stage, and a large area growth stage. In all cases the growth was conducted using a two step, carbonization plus growth, process. During carbonization, the surface of the Si is converted to 3C-SiC, which helps to minimize the stress in the growing crystal. Propane (C3H8) and silane (SiH4), diluted in hydrogen (H2), were used as the carbon and silicon source, respectively. A deposition rate of approximately 10 um/h was established during the baseline process. Once the baseline process proved to be repeatable, optimization of the process began. Through variations in temperature, pressure, and the Si/C ratio, thick 3C-SiC films (up to 22 um thick) and high deposition rates (up to 30 um/h) were obtained. The optimized process was then applied to growth on 50 mm diameter Si(100) wafers. The grown 3C-SiC films were analyzed using a variety of characterization techniques. The thickness of the films was assessed through Fourier Transform infrared (FTIR) spectroscopy, and confirmed by cross-section scanning electron microscopy (SEM). The SEM cross-sections were also used to investigate the 3C-SiC/Si interface. The surface morphology of the films was inspected via Nomarsky interference optical microscopy, atomic force microscopy (AFM), and SEM. The crystalline quality of the films was determined through X-ray diffraction (XRD) and low-temperature photoluminescence (LTPL) analysis. A mercury probe was used to make non-contact CV/IV measurements and determine the film doping.
Thesis:
Thesis (M.S.E.E.)--University of South Florida, 2006.
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by Suzie Harvey.
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Growth of 3C-SiC via a Hot-Wall CVD Reactor by Suzie Harvey A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Stephen E. Saddow, Ph.D. Andrew M. Hoff, Ph.D. John T. Wolan, Ph.D. Date of Approval: October 3, 2006 Keywords: silicon carbide, heteroepitaxy, SOI, crystal defects, chemical vapor deposition Copyright 2006, Suzie Harvey

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ACKNOWLEDGEMENTS There are many people whom I would like to acknowledge for making this thesis possible. First and foremost, I would like to thank my advisor and mentor Dr. Stephen E. Saddow, for providing me with the research opp ortunity and introducing me to the world of silicon-carbide. I appreciate your gui dance and support and thank you for opening my eyes to a fascinating area of research that I had known nothing about. Next, I would also like to thank the other members of the SiC growth team; to Dr. Y. Shishkin for his continual help, and always having answers to my questions, and to M. Reyes, my growth buddy, for training me on the reactor and assisting me with my research. I would like to acknowledge D. Edwards with USF-COT, Largo, FL for performing much of the AFM and SEM analysis, and Dr. W.J. Choyke and his group at the University of Pittsburgh for performing the LTPL analysis. I would also like to thank Dr. Andrew M. Hoff and Dr. John T. Wolan for taking time to be a part of my committee, and offering suggestions on how to improve my thesis. Fi nally, I would like to thank the members of the SiC group, past and present, for all their help and support, especially I. Haselbarth and C.L. Frewin for ensuring reactor operations ran smoothly. This work was supported by grants from th e Office of Naval Research under Grant No. W911NF-05-2-0028 (Dr. C. E. C. Wood) and the Army Research Laboratory under Grant No. DAAD19-R-0017 (B. Geil), which is gratefully acknowledged.

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TABLE OF CONTENTS LIST OF TABLES .............................................................................................................iii LIST OF FIGURES ...........................................................................................................iv ABSTRACT ...................................................................................................................vii CHAPTER 1 INTRODUCTION ......................................................................................1 1.1 3C-SiC Overview .................................................................................................1 1.2 3C-SiC Applications ............................................................................................3 1.3 Summary ..............................................................................................................5 CHAPTER 2 3C-SiC HETEROEPITAXY .......................................................................7 2.1 Epitaxy .................................................................................................................7 2.1.1 CVD epitaxy ...............................................................................................8 2.1.2 3C-SiC epitaxy ..........................................................................................11 2.2 Defects in 3C-SiC Epitaxy .................................................................................11 2.2.1 Planar defects ............................................................................................12 2.2.2 Voids.........................................................................................................13 2.2.3 Hillocks .....................................................................................................14 2.3 Review of 3C-SiC Growth Literature ................................................................15 2.3.1 Single source precursors ...........................................................................15 2.3.2 Chlorine additives .....................................................................................16 2.4 Summary ............................................................................................................16 CHAPTER 3 3C-SiC CVD PROCESS DEVELOPEMENT ..........................................18 3.1 CVD Reactor System Review ............................................................................18 3.2 Process Development .........................................................................................19 3.2.1 Initial baseline process ..........................................................................20 3.2.2 Optimized process .....................................................................................22 3.2.3 Growth on 50 mm Si(100) wafers ............................................................24 3.2.4 Intentional doping of the 3C-SiC films .....................................................26 3.3 3C-SiC Film Characterization ............................................................................27 3.3.1 FTIR ..........................................................................................................27 3.3.2 Optical microscopy ...................................................................................29 3.3.3 SEM ..........................................................................................................30 3.3.4 AFM ..........................................................................................................32 3.3.5 XRD ..........................................................................................................33 3.3.6 LTPL .........................................................................................................34 i

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3.3.7 CV/IV........................................................................................................35 3.4 Summary ............................................................................................................37 CHAPTER 4 3C-SiC FILM APPLICATIONS ...............................................................39 4.1 Growth on Wafer-Bonded Films (SOI) .............................................................39 4.2 MOSCAPs ..........................................................................................................43 4.3 MEMS ................................................................................................................44 4.4 3C-SiC/SOI Gas Sensor .....................................................................................45 4.5 Summary ............................................................................................................46 CHAPTER 5 CONCLUSIONS AND FUTURE WORK ...............................................47 5.1 Summary ............................................................................................................47 5.2 Future Work .......................................................................................................49 REFERENCES .................................................................................................................52 APPENDICIES .................................................................................................................57 Appendix A Hot Zone Design Drawings..................................................................58 Appendix B Low Temperature Photoluminescence (LTPL) ....................................61 ii

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LIST OF TABLES Table 1.1: Basic electrical and thermal propert ies of 3C, 4H, 6H SiC and Si [2,5,7]. .........................................................................................................3 Table 3.1: 3C-SiC growth optimization experiments. ...............................................23 Table 3.2: Thickness measurements taken on two wafers depostited at different growth rates. Thickne ss measured via FTIR reflection spectroscopy. .............................................................................................29 Table 3.3: Doping measurements taken on two wafers depostited at different growth rates. Doping determined by the CV method. .............................37 iii

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LIST OF FIGURES Figure 1.1: Stacking order of a few commonly studied SiC polytypes [3]. ..................1 Figure 2.1: Overall reaction rate vs. reciproc al temperature for CVD [6,16]...............9 Figure 2.2: Illustration of boundary layer in horizontal reactor with: (a) flat susceptor design, and (b) til ted susceptor design [13,17]. ........................10 Figure 2.3: Illustration of stacking faults in crystal growth [30]. ................................13 Figure 3.1: Horizontal hot-wall CVD reactor at USF. ................................................19 Figure 3.2: 3C-SiC initial process schedule. ...............................................................21 Figure 3.3: Growth rate versus silane mole fraction. ..................................................24 Figure 3.4: Cross-section of the growth zone using: (a) original susceptor design and (b) modified susceptor design. C represents temperature gradient across a 50 mm wafer. ............................................26 Figure 3.5: N2 mole fraction versus carrier co ncentration of the 3C-SiC films. .........27 Figure 3.6: Diagram of wafer mapping for th ickness measurements shown in Table 3.2. ..................................................................................................29 Figure 3.7: Optical images taken at 500X of (a) 5.4 m thick film deposited at 18 m/h on 8x10 mm die (b) 5 m thick film deposited at 18 m/h on 50 mm wafer (c) 10 m thick film deposited at 18 m/h on 50 mm wafer (d) 10 m thick film deposited at 30 m/h on 50 mm wafer. ........................................................................................................30 Figure 3.8: SEM secondary electron image, at 5,000X, of a cross-section of a ~11.5 m thick 3C-SiC film on Si(100), deposited at 30 m/h. Image courtesy of D. Edwards, USF-COT, Largo, FL. ............................31 Figure 3.9: SEM backscatter electron image of a cross section of: (a) a hillock at 8k magnificaion and (b) same hillock at 30k magnification. Image courtesy of D. Edwards, USF-COT, Largo, FL. ............................32 iv

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Figure 3.10: 50 x 50 m AFM scans of 10 m thick 3C-SiC films on 50 mm Si wafers, deposited at: (a) 18 m/h and (b) 30 m/h. Tapping mode with a z-height of 100 nm was used. Images courtesy of D. Edwards, USF-COT, Largo, FL. ...............................................................33 Figure 3.11: XRD of 10 m thick 3C-SiC epilayers on 50 mm Si(100) wafers. Powder diffraction of films deposited at: (a) 18 m/h and (b) 30 m/h. Rocking curve of the 3C-SiC (200) peak of films deposited at: (c) 18 m/h and (b) 30 m/h. ...............................................................34 Figure 3.12: Plot of the log of the current vs. voltage of an unintentionally doped 10 m thick 3C-SiC film. The film is clearly n-type. Note measurements made A to C (ins et shows device cross-section). Anode contact, A, made via Hg probe. .....................................................35 Figure 3.13: Plot of capacitance vs. voltage for an unintentionaly doped n-type, 10 m thick 3C-SiC film. Inset sh ows device cross-section. Note measurement made A to C. .......................................................................36 Figure 3.14: Plot of calculated carrier c oncentration vs. depth for an unintentionaly doped n-type, 10 m thick 3C-SiC film. A doping density of ND-NA ~ 1015 cm-3 was estimated for this film. .......................36 Figure 3.15: Diagram of wafer mapping for doping measurements shown in Table 3.3. ..................................................................................................37 Figure 4.1: Process flow used to produce SOI substrates for 3C-SiC growth [61]. ...........................................................................................................40 Figure 4.2: SEM images taken at 5,000X of: (a) 1 m thick 3C-SiC epi on SOI substrate, and (b) 11 m thick 3C-SiC epi on SOI substrate. ...................41 Figure 4.3: SEM cross-section of: (a) 1 m thick 3C-SiC epi on SOI substrate, with Si layer present, and (b)11 m thick 3C-SiC epi on SOI substrate with no Si layer present. ............................................................42 Figure 4.4: Process schedule developed for high temperature growth of 3CSiC on SOI. ...............................................................................................42 Figure 4.5: Growth rate of 3C-SiC on SO I as a function of temperature. ...................43 Figure 4.6: SEM cross section of 52 m deep trench in Si mold: (a) before deposition and, (b) after de position of 3C-SiC [65]. ................................45 v

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Figure 4.7: A packaged resistive H2 gas sensor fabricated on 1.4 m thick 3CSiC film on SOI substrate. Image courtesy of T.J. Fawcett, USF, Tamp, FL [12]. ..........................................................................................46 Figure 5.1: Illustration of: (a) SiGe epitaxy on Si, with a graded SiXGe1-X alloy layer in between (b) 3C-SiC epita xy on Si, and (c) 3C-SiC epitaxy on Si, with a degenerately doped 3C -SiC layer in between to serve as a buffer layer. ........................................................................................51 Figure A.1: Original design of insulating graphite foam used in the developement of the baseline an d optimized 3C-SiC processes on Si die. The graphite susceptor is shown in A.3. All units are shown in mm. Drawing courtesy of I. Haselbarth, USF, Tampa, FL..............................................................................................................58 Figure A.2: Modified design of insulating graphite foam used during the development of the 3C-SiC growth process on 50 mm diameter Si wafers. The graphite susceptor is shown in A.4. All units are shown in mm. Drawing courtesy of I. Haselbarth, USF, Tampa, FL..............................................................................................................59 Figure A.3: Original design of tilted su sceptor (only top shown here) used in the development of the baseline and optimized 3C-SiC process on Si die. All units shown in mm. Dr awing courtesy of I. Haselbarth, USF, Tampa, FL.......................................................................................60 Figure A.4: Modified design of tilted su sceptor (only top shown here) used in the development of the 3C-SiC growth process on 50 mm diameter Si wafers. All units shown in mm. Drawing courtesy of I. Haselbarth, USF, Tampa, FL....................................................................60 Figure B.1: LTPL (2 K) spectrum of 10 m thick 3C-SiC film deposited at: (a) 18 m/h and (b) 30 m/h. Images courtesy of W.J. Choyke, University of Pittsburgh, PA.....................................................................62 vi

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GROWTH OF 3C-SiC VIA A HOT-WALL CVD REACTOR Suzie Harvey ABSTRACT The heteroepitaxial growth of cubic si licon carbide (3C-SiC) on silicon (Si) substrates at high growth ra tes, via a horizontal hot-wa ll chemical vapor deposition (CVD) reactor, has been achieved. The fi nal growth process was developed in three stages; an initial baseline development stag e, an optimization stage, and a large area growth stage. In all cases the growth wa s conducted using a two step, carbonization plus growth, process. During carbonization, the surface of the Si is converted to 3C-SiC, which helps to minimize the stress in the growing crystal. Propane (C 3 H 8 ) and silane (SiH 4 ), diluted in hydrogen (H 2 ), were used as the carbon a nd silicon source, respectively. A deposition rate of approximately 10 m/h was established during the baseline process. Once the baseline process proved to be repeatable, optimizatio n of the process began. Through variations in temperature, pressure, a nd the Si/C ratio, thick 3C-SiC films (up to 22 m thick) and high deposition rates (up to 30 m/h) were obtained. The optimized process was then applied to growth on 50 mm diameter Si(100) wafers. The grown 3CSiC films were analyzed using a variety of characterization technique s. The thickness of the films was assessed through Fourier Transform infrared (FTIR) spectroscopy, and confirmed by cross-section scanning electron microscopy (SEM). The SEM crosssections were also used to investigate the 3C-SiC/Si interface. The surface morphology of the films was inspected via Nomarsky in terference optical microscopy, atomic force vii

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microscopy (AFM), and SEM. The crystalline quality of the films was determined through X-ray diffraction (XRD) and lowtemperature photoluminescence (LTPL) analysis. A mercury probe was used to make non-contact CV/IV measurements and determine the film doping. viii

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CHAPTER 1 INTRODUCTION 1.1 3C-SiC Overview Silicon carbide has been heralded as a promising candidate to replace silicon for power device applications due to its large band gap and high electron mobility. Its mechanical strength and robust nature make it an ideal material for military applications in harsh environments. Unlike Si based devices, which can only operate up to 200 C, SiC devices have been shown to operate effectively at temperatures up to 600 C [1]. SiC forms in more than 170 known polytypes, or crystal structures. However, 95% of all publications concerning SiC deal primarily with the polytypes 4H-, 6H-, and 3C-SiC [2]. The designations denote the structure of the cr ystal as being either cubic or hexagonal ( Figure 1.1 ). In the case of 3C-SiC, the cubic crys tal repeats three times to comprise the unit cell. Figure 1.1: Stacking order of a few co mmonly studied SiC polytypes [3]. 1

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This thesis focuses on the growth of th e only purely cubic polytype, 3C-SiC. The advantage of 3C-SiC over the more commonl y studied hexagonal polytypes (6Hand 4HSiC), is its ability to be hetero-epitaxial ly grown on Si, providing a cost effective alternative to homo-epitaxy on bulk SiC. Bu lk SiC is expensive, approximately $1500$2000 per wafer, and is currently only available commercially in a maximum diameter of 4 inches [4]. At this time, 3C-SiC bulk crystals are not commercially available. However, Si wafers are inexpensive and ar e manufactured as large as 12 inches. In theory, 3C-SiC could be epitaxially grown on large-area Si wafers to produce seeds for bulk growth. Additionally, bulk SiC contains sc rew dislocations that can penetrate into the epitaxial layer during growth. Because Si can be manufactured as nearly defect free, these dislocations can be eliminated in 3C heteroepitaxy. However, despite the advantages there exist many challenges to the successful heteroepitaxy of 3C-SiC on Si. One is the difference in latt ice constants between 3C-SiC and Si, which is approximately 20%. The latti ce constant or space between atoms for Si is approximately 5.43 [5], whereas for 3C-SiC it is 4.36 [2]. Because the substrate is thicker than the epitaxial layer, the latt ice misfit causes all of the strain to be accommodated in the epilayer, which leads to shear stresses in the crystal planes. Often the bonds along these planes will break and re form to relieve stress, leaving behind dangling bonds which are referred to as misfit dislocations [6]. Further information on crystallographic defects and the methods of reducing and eliminating them can be found in section 2.2 Another disadvantage of heteroep itaxy is the difference in thermal expansion coefficients between 3C-SiC and Si (see Table 1.1 ). At the higher temperatures typically used for growth (1350 C-1400 C), this difference becomes 2

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smaller [2,5]. These are a few of the issues th at must be addressed before 3C-SiC can be realistically considered as a replacemen t for Si based electronic devices. 1.2 3C-SiC Applications The thermal, electrical, and mechanical properties of 3C-SiC make it a promising candidate in device fabrication. Table 1.1 compares some of the basic electrical and thermal properties of 3C-, 4H-, 6H-SiC, and Si. What makes 3C-SiC based devices more appealing than Si is its abil ity to function at higher volta ges, higher frequencies, and higher temperatures. Table 1.1: Basic electrical a nd thermal properties of 3C, 4H, 6H SiC and Si [2,5,7]. 3C-SiC 4H-SiC 6H-SiC Si Bandgap Eg (eV) 2.4 3.2 3.0 1.12 Mobility n (cm 2 /v*s) 1000 950 500 1350 Sat. drift V (x10 7 cm/s) 2.5 2.0 2.0 1.0 Thermal cond. (W/cm K) 5.0 5.0 5.0 1.5 Thermal expansion @300 K @1500-1600 K (10 -6 K -1 ) 3.8 5.5 NA 4.3 c axis 4.7 c axis 2.6 4.56-4.6 For high voltage devices, SiC can handle about ten-times the critical electric field for Si, which means a lower on-resistance for the same blocking voltage [7]. For example, power MOSFETs have better output ch aracteristics for paralleling devices than BJTs, and the high input impedance allo ws for simpler gate drive circuitry. Unfortunately, the advantage is lost with a Si power MOSFET, due to the high onresistance for high breakdown voltages. An ideal 3C-SiC power MOSFET operating at 3

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room temperature, for a breakdown voltage of 5 kV, has a specific on-resistance which is three orders of magnitude smaller than fo r a similar Si device [8]. High frequency devices also benefit from the high critical fi eld of SiC, because it allows for smaller and therefore faster devices [7]. From Table 1.1 we can see that 3C-SiC has a larger saturated drift velocity than both 4Hand 6H-S iC polytypes, and is more than twice that of Si, which is advantageous for obtaining higher channel currents in microwave devices [9]. Additionally, of the three SiC polytypes shown in Table 1.1 3C-SiC has the highest electron mobility. The carrier mobility in fluences the frequency response or time response behavior of a device in two ways. First, the mobility is proportional to the carrier velocity for low electric field. Theref ore a higher mobility material is likely to have a higher frequency response, because carriers can move more readily through the device. Second, the device current is dependa nt on the mobility; i. e. higher motilities result in larger currents. At larger curre nts, the capacitance will charge more rapidly, which will result in a highe r frequency response [10]. At high temperatures, SiC also holds the advantage over Si. The failure of Si devices at high temperatures is mostly attri buted to the thermal i onization of electrons from the valence band to the conduction band [9 ]. The ionization of a large number of electrons into the conduction ba nd causes the material to be come intrinsic; meaning there is no longer a p-n junction to block the voltage in, say, a bipolar device [7]. Because of the large bandgap, SiC has a mu ch higher intrinsic temperat ure and does not suffer the same fate; SiC devices have been shown to operate effectively up to 600 C, while most Si based devices fail at around 200 C [1]. The ability to operate at high temperatures is a major advantage for military and space ap plications. Researchers at NASAs Glenn 4

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Research Center believe SiC technology will reduce satellite launch costs by eliminating the need for bulky cooling radiators, allow future missions into harsh environments (e.g. Venus 450 C atmosphere), and provide high temperature sensors and control electronics in aircraft and automobiles [11]. Closer to home, hydrogen fuel cell research at the University of South Fl orida has led to the successful fabrication of 3C-SiC based H 2 gas sensors [12], further motivating the research performed during this thesis. The benefits of 3C-SiC and SiC research span across a vast number of disciplines; from power electronics to chemical sensors to medical applications and biotechnology. As bulk and epitaxial SiC growth processes continue to improve, so too will the many applications for which they are used since this is the key limiting factor for SiC technology insertions. 1.3 Summary SiC is a robust material with electrical, mechanical, and thermal advantages over Si. The quality of 6Hand 4H-SiC bulk crystals and epitaxy continues to improve towards device grade material, and Intrinsic Semicond uctor, now part of Cree Inc [4], has reported the development of micropipe-free and low density (1 cm -2 ) 100 mm 4Hand 6H-SiC wafers[4]. However, problems con tinue to plague this technology, with no serious reductions in screw dislocations in 4Hand 6H-SiC. 3C-SiC heteroepitaxy on Si does not suffer from these inherent problems, which is the main motivation besides cost reduction, for using this material. Noneth eless, 3C-SiC technology must overcome its own limitations arising from process instability, defects, and a lack of interest/research. Therefore, it is the goal of this thesis to investigate the growth of 3C-SiC on Si via Hotwall CVD epitaxy, improve upon the current crystal quality, and apply these advances for 5

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useful applications. In Chapter 2, the basic theory of CVD will be discussed since this is the primary method used to grow 3C-SiC In addition, common defects found in the heteroepitaxy of 3C-SiC on Si will be presented along with a review of the literature concerning recent developments and methods of 3C-SiC heteroepitaxy. In Chapter 3, the development of a 3C-SiC on Si growth pr ocess in a hot wall CVD reactor will be presented, where growth rates up to 30 m/h and whole wafer films up to 22 m thick were achieved. Also, the results of several ch aracterization methods used to analyze the grown films will be discussed. In Chapter 4, several applications for which we are using the grown 3C-SiC epitaxial layers will be discussed, namely, growth on wafer bonded films (SOI), MOSFETs, and MEMS. Finally, th e thesis will conclude with a discussion of the work performed during this researc h, and future projects which are the logical extension of this work. 6

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CHAPTER 2 3C-SiC HETEROEPITAXY 2.1 Epitaxy Epitaxy is the layered growth of a crystallin e film on a crystalline substrate [13]. The substrate acts as the seed crystal, and therefore its structure influences the growing crystal due to a degree of matching at the inte rface between the two [6]. In homoepitaxy, the lattice parameter of the deposited materi al matches that of the substrate, and the film/substrate interface should vanish into the bulk material so that the interface energy, i is approximately zero [6,13]. In heteroepitaxy, the deposited material has a different lattice parameter than the substrate. The epitaxial film orients itself to minimize i and maximize bonding at the interface [6]. If the difference in lattice para meters is too great, epitaxy is not possible [13]. The fractional mismatch, f at the interface should be relatively small ( f < 0.1), and is defined as: sse se seaaa aa aa f / 2/ (2.1) where a e and a s are the atomic sp acings of the epitaxial film a nd substrate, respectively [6]. If there is a difference in thermal expansion coefficients between the two materials, then f becomes a function of temperat ure, as in the cas e of 3C-SiC on Si [6]. Because the substrate acts as a seed for the epitaxy, the structure of its surface is important in determining the growth mechanism. If th e surface is atomically smooth, the rate of growth is determined by two independent proce sses: (i) the formation of steps, and (ii) the lateral movement of thes e steps [14]. In vapor phase epitaxy (VPE), the following 7

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mechanisms contribute to the overall growth process: (1) the atoms from the vapor adsorb onto the step terraces, which creates a population of adatoms, (2) the surface diffusion of the adatoms towards the step edges, (3) the adatoms incorporate along the kinks in the steps, which leads to the latera l movements of the steps, and contributes to the growth of the crysta l. If dislocations are present in the crystal, growth is no longer determined by step formation but instead it is influenced by other factors, such as the rate of surface diffusion, interaction between step s, encounters with surface defects and impurities, etc. [14]. 2.1.1 CVD epitaxy A common technique used to grow crystalline films epitaxially is chemical vapor deposition (CVD), which is a type of VPE. The types of CVD include: thermal CVD, such as low pressure (LPCVD) and atmo spheric pressure (APCVD), and plasma enhanced (PECVD). CVD is controlled by two basic process; mass transfer, and surface reaction [15]. These two processes can be br oken down into a sequence of five steps. The reactant gas molecules or precursors, dilu ted in a carrier gas, are introduced into the reaction chamber, where: (1) The gases diffu se through a boundary layer to the surface, (2) the reactants adsorb to th e surface, (3) a chemical react ion takes place, resulting in deposition, (4) the adsorbed species are deso rbed, and (5) the by-products of the reaction are diffused out [13]. For example, during 3C-SiC CVD, propane and silane thermally decompose and form C and Si subspecies, which then adsorb to the heated Si surface, resulting in a 3C-SiC epitaxial layer. Many variables must be taken into consideration in order for CVD epitaxy to be successful, such as, reactor design, gas chemistry, and process parameters. For instance, the temperat ure and pressure inside the reactor greatly 8

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affect the deposition process. The pressure controls the thickness of the boundary layer and therefore determines the amount of diffusi on that can occur [13]. At low pressures, the boundary layer is thinner, which minimizes the diffusion process. This is known as a surface controlled regime; where the rate of deposition is limited by the reaction at the surface [13,16,17]. If temperature is low, th e molecules react slow ly and create an oversupply [18]. If temperatur e is high, the molecules react quickly on the surface and the deposition is then limited by the diffusi on (transport) of the molecules through the boundary layer [17]. The growth regime (transport-limited or surface reaction-limited) is determined by the slowest process (diffusion or reaction) [13]. Figure 2.1 illustrates how both the temperature and pressure during CVD affects the growth rate. Figure 2.1: Overall reaction rate vs. r eciprocal temperature for CVD [6,16]. In a horizontal CVD reactor, the boundary layer increases along the x direction, which leads to an exponential decrease in the deposition. A tilted susceptor design is often employed to increase th e gas velocity, and thus redu ce the boundary layer [17]. 9

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Figure 2.2 (a) and (b) illustrate how the tilted su sceptor design not only helps to reduce the boundary layer, but also improves deposition uniformity. (a) (b) Figure 2.2: Illustration of boundary layer in horizontal reactor with: (a) flat susceptor design, and (b) tilted susceptor design [13,17]. Gas flow susceptor Gas flow In PECVD, the growth mechanisms are sim ilar to that of thermal CVD, with the addition of a plasma to assist in the depositi on process. A plasma is a partially ionized gas that when subjected to an applied electric field the electrons can achieve higher energies than atoms and molecules. This results in more free radicals by electron bombardment than would be possible therma lly [17]. The free radicals have a high chemical reactivity which allows for nucleation at a much lower temperature than what is required for thermal reaction [6]. There are two main reasons plasma CVD is used rather than thermal CVD. The first is the abili ty to crack the same molecules at lower temperatures, which is a necessity for many integrated circuit (IC) technologies. In fabricating ICs, silicon nitride (SiN) is often deposited as a final passivation layer, which if deposited thermally, would require a temper ature of 750 C. However, most metal contacts are aluminum (Al), which melts at approximately 600 C. If a plasma is used, SiN can be deposited below 500 C and damage to the contacts can be avoided [6,17,18]. The second reason for using plasmas is that th e film surface becomes denser due to the increase in ion bombardment. This gives one the ability to adjust the density, and therefore stress, in a film through the manipulation of process conditions [18]. 10

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2.1.2 3C-SiC epitaxy The most common technique used to grow 3C-SiC epitaxially is CVD [7,9]. The epitaxial growth of 3C-SiC on Si has been achieved usin g atmospheric pressure, low pressures, and even a combina tion of both. Refer to section 2.3 for more details on the variety of growth processes in use. Typically a two stage growth process, first developed by Nishino et. al [19], is used for 3C-SiC heteroep itaxy. Growth has been achieved with some success when the carbonization step was omitted [20], but this usually resulted in lower quality films [21-23]. In the first st age, a carbonization of the surface is performed using a hydrogen-hydrocarbon gas mixture. Th e carbonization step converts the surface of the Si substrate to SiC, which serves as a quasi buffer layer for the epitaxial growth [19]. In the second stage, a silicon source pr ecursor is added to the gas mixture and the primary growth takes place. The more commonly used carbon and silicon sources are propane (C 3 H 8 ) and silane (SiH 4 ), respectively. Simulations of 4H-SiC growth in a horizontal hot-wall CVD reactor (same reactor used for the 3C-SiC growth presented in this thesis) performed by Shishkin et. al [24], found that the primary C and Si species contributing to growth were CH 4 SiH 2 and Si. Other species, such as C 3 H 8 and SiH 4 as well as C 2 H 5 C 2 H 2 and CH 3 likely give negligible contributions to the growth due to their small presence in th e growth zone. Although the simulation parameters were established for 4H-SiC homoep itaxy, the propane/silane precursor chemistry is similar to that used for 3C-SiC hereroepitaxy. 2.2 Defects in 3C-SiC Epitaxy Impurities and defects can cause disruptions in the deposition of films because the arriving atoms need to sense the crystallogr aphic order of the unde rlying substrate. 11

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Therefore, surface structure is important fo r controlling defects and obtaining charge neutrality at the inte rface during heteroepitaxy. A signi ficant difference in charge can produce large electrostatic fiel ds which disrupt smooth grow th [6]. There are several defects typically associated with 3C-SiC hete roepitaxy; planar defects, such as stacking faults (SFs) and anti-phase boundaries (APBs), and other defects, such as interface voids and hillocks [20,25,26]. 2.2.1 Planar defects A major contributor to the defects in heteroepitaxy is the lattice mismatch and difference in thermal expansion coeffici ents between 3C-SiC and Si, which is approximately 20% and 8%, respectively [25,27,28]. The misfit caus es stress in the epilayer which can lead to dislocations in the crystal structure [6]. Misfit dislocations occur when the crystal plane breaks to reli eve stress, leaving behind dangling bonds. The lattice mismatch also forces the crystal to grow as three-dimensional islands, known as island growth mode [25]. Each island has a slightly different orientation and as neighboring islands coalesce, the periodicity of the lattice is broke n, creating an APB or grain boundary [29]. At th e interface between two APBs, there is an exchange of Si and C atoms in an effort to minimize the number of dangling bonds, resulting in Si-Si or C-C bonds (twins) along the planes [ 26]. The inversional stacking of the Si and C bilayers introduces parasitic hexagonal pha ses within the 3C-SiC films. These errors in stacking sequences are known as stacking faults (see Figure 2.3 ). In 3C-SiC heteroepitaxy, it is energetically favorable for small misfits in th e crystal lattice to be accompanied by SFs, because the lattice spacing of the parasitic hexagonal (0006 ) plane and the cubic (111) plane are similar [29]. SFs and APBs are two of the primary defects influencing the 12

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electrical properties and ther efore performance of devices [20,29]. They are thought to be the origin of current leakage when they penetrate the pn junction [26], and SFs also act as recombination centers for car riers in bipolar devices [9]. Yun et. al [25] and Zheng et. al [29] both found a direct co rrelation between the size of the crystallites and the number of SFs; thicker epi films lead to la rger crystallites and fewer planar defects. Figure 2.3: Illustration of stacking faults in crystal growth [30]. Many different techniques have been empl oyed to try and reduce the strain in the 3C-SiC epilayer caused by th e lattice mismatch, such as, growth on undulant-Si [26] or on porous substrates [31,32]. The carbonization step performed prior to growth also helps to reduce the strain at the 3C-SiC /Si interface. The carbonization converts the surface layer of Si to 3C-SiC, and acts as a quasi buffer layer for the subsequent growth [19]. Unfortunately, carbonizing the Si surface has b een found to contribute to the formation of voids at the film/substrate interface [27]. 2.2.2 Voids It is generally believed that voids are caused by the out-diffusion of Si atoms from the substrate, which reacts with carbon in the vapor phase to form SiC during the carbonization [27,33,34]. However, Leycuras proposed voids could be caused by the 13

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formation of carbon monoxide from the carbon reacting with oxygen impurities in the Si substrate [35]. Voids form as inverted pyramids at the 3C-SiC/Si interface and are bridged by the growing SiC layer [28]. Th ere are many techniques used to reduce or eliminate voids at the interface. Nagasawa et. al [36] and Chiu et. al [37] used only hydrocarbon sources during carbonization, such as C 2 H 4 and C 2 H 2 to suppress void formation. Burkland et. al [27] used the addition of SiH 4 during carbonization to suppress the out-diffusion of Si by providing an alternative Si source for the C to react with. Seo et. al [34] were able to achieve vo id-free interfaces by employing low temperature nucleation with tetramethylsilane (TMS) prior to high temperature growth. Other researchers have varied process conditions such as ramp times, temperature, and pressure to obtain void-free interfaces [38-40]. 2.2.3 Hillocks Another defect in 3C-SiC heteroepitaxy which becomes more prominent at higher growth rates, is hillocks [20] Hillocks are surface protrusions that have a negative impact on the surface morphology of a 3C-SiC film. Not much information can be found in the 3C-SiC growth literature on the cause of hillock forma tion, nor on their point of origination. However, in section 3.3.3 this thesis will present results of an investigation into the nature of these defects, from whic h the following conclusions can be drawn: (1) as the thickness of the film increases, the de fects appear to increase in size and density, and (2) hillocks are more pronounced along the edges of the samples, where defects are more abundant in the underlying substrate due to dicing. This is one reason why growth on larger areas is necessary to increase the amount of usable surface area. 14

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2.3 Review of 3C-SiC Growth Literature Although SiH 4 and C 3 H 8 are most often used as the Si and C sources for 3C-SiC heteroepitaxy [7], there are many different type s of precursor chemistries that have been successfully used, such as single source me tal organics and chlorine additives. 2.3.1 Single source precursors Hexamethyldisilane [(CH 3 ) 6 Si 2 ], or HMDS, is an organom etallic precursor that can be used as the sole source for both Si and C. Because HMDS has a pre-existing Si-C bond, growth can be achieved at lower temperatur es [33]. HMDS is in corporated into the deposition process by using the metal organi c (MO) CVD technique In MOCVD, the source material is in liquid form and is held in a separate container usually maintained at room temperature. The vapor phase species are transported into the reaction chamber by bubbling a carrier gas, such as H 2 through the liquid. The reactants then thermally decompose when coming into contact with th e hot susceptor. The advantage of using MOCVD is that deposition is not diffusion limited, as is the case with other CVD processes [41]. Gupta et. al [33] was able to achieve single crystal 3C-SiC films on Si(100) and (111) substrates using H 2 bubbled through HMDS as a sole source. The carbonization step was performe d prior to growth using C 3 H 8 Growth was conducted for 1-2 hours at temperature between 1150 C and 1250 C. Teker et. al [21] also conducted growth experiments on Si(100) and (111) us ing HMDS. However, they used an Ar/H 2 carrier mix and omitted the carbonization step in favor for a nucleation stage. The nucleation stage took place at 1250 C for 2 mi nutes with an HMDS flow of 1.25 sccm. Growth took place at 1380 C with HMDS fl ow rates between 0.625 and 5 sccm. They reported the films to have a high density of pl anar defects and voids at the substrate/epi 15

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interface. Trimethylsilane [(CH 3 ) 3 SiH], or 3MS, has also been used as a single source in 3C-SiC heteroepitaxy. Madapura et. al [22] was able to achieve high growth rates (up to 35 m/h), with and without the carbonization st ep, using 3MS. They found the growth rate to be highly dependan t on temperature and the non -carbonized samples had higher growth rates, but lower quality films. The advantage of 3MS over the traditional silane/propane precursor chemistry is its non-corosive, non-pyrophoric properties. 2.3.2 Chlorine additives The addition of chlorines in 3C-SiC CVD epitaxy has gained recent interest, due to its apparent ability to help suppress the homogeneous nuclea tion of Si in the gas phase [42,43]. Wang et. al [44] was able to deposit 3C-SiC epitaxially at low temperatures (750 C-900 C), using dichlorosilane (SiH 2 Cl 2 ) and acetylene (C 2 H 2 ). However, the deposited films were amorphous at 750 C an d highly grainy at 900 C. Here at the University of South Florida, M. Reyes et. al [42] has achieved growth rates up to 38 m/h with the addition of HCl to the C 3 H 8 /SiH 4 precursor chemistry. The 3C-SiC layers were deposited on Si(100) substrates at temperatures between 1370 C-1380 C. The resulting films were single-crystalline and spec ular. The addition of HCl has also helped to achieve growth of 3C-SiC on Si at lower temperatures. However, the growth rates are much lower and the quality not yet comparable to the films grown at higher temperatures [45]. 2.4 Summary Chemical vapor deposition is a common technique used to grow crystal films epitaxially. CVD is governed by two basi c mechanisms; mass transfer and surface 16

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reaction [15]. Reactant gas molecules, or precursors, diluted in an inert carrier gas such as H 2 or Ar, are injected into the CVD reaction chamber, where they diffuse through a boundary layer and chemically react with the surface to create an epitaxial layer. Many variables must be taken into consideration in order for CVD epitaxy to be successful, such as the temperature and pressure inside the reactor. At lower chamber pressures, the boundary layer thickness is reduced and depos ition is more uniform [13]. At higher temperatures, surface reaction is quicker and deposition rates are higher [17]. If the depositing film and substrate have matching latt ice parameters, then the growth is said to be homoepitaxial. If the lattice parameters are different, then the growth is said to be heteroepitaxial, as in 3C-SiC growth on Si. In 3C-SiC CVD, precursor molecules c ontaining Si and C elements, thermally decompose and adsorb to the heated Si surface to form a heteroepitaxial layer of 3C-SiC. There are many different precursor chemistries used in 3C-SiC epitaxy, such as propane and silane (the most common), hexamethyldisilane (used as single source for both C and Si) and hydrochloride (used as chlorine addi tive), each with their own advantages and disadvantages. Yet despite the variety of proc esses available, there are still many defects associated with 3C-SiC hetero epitaxy. Some defects, such as APBs, SFs, and twins, are caused by strain in the crystal planes due to the lattice mismatch be tween 3C-SiC and Si [25,26,29]. Other defects, such as interface voids, are caused by the outdiffusion of Si from the substrate, which reacts with th e gas phase carbon source [27,33,34]. The researcher must minimize these defects, th rough CVD reactor design, gas chemistry and process parameter modification, before epitaxially grown 3C-S iC can be considered as a viable alternative to Si based devices. 17

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CHAPTER 3 3C-SiC CVD PROCESS DEVELOPEMENT 3.1 CVD Reactor System Review The reactor used in this work was a horizontal hot-wall CVD reactor. Figure 3.1 is a photograph of the CVD reactor used, wh ich was built by the SiC group at the University of South Florida [46]. The cham ber consists of a quartz tube supported by stainless steel endplates which are water cooled. The gas lines connect to the head of the tube and pass though a gas diffuser cap, similar to a shower head, which helps to disperse the gases and establish laminar flow. An inner quartz liner funnels the gases into the hot zone. The copper coils, shown in Figure 3.1 provide radial heating of the hot zone through radio frequency (RF) induction. A 50 kw/10 kHz Mesta Electronics Inc. [47] solid state RF generator provides the source for the RF induction and is capable of producing temperatures inside the hot zone in excess of 1800 C. A pyrometer is mounted on the outside of the chamber housing and is aimed at a machined recess in the top portion of the hot zone. Infrared imaging allows the user to determine the temperature inside the hot zone and regulate it through a feedback control loop via a computer interface. The hot zone consists of either silicon carbide or tantalum carbide coated graphite parts, which are called su sceptors, and an insulating graphite foam support. The top susceptor wa s designed with a downward til t toward the outlet of the gas stream (see Appendix A); this was done to increases the gas velocity, which reduces the boundary layer and leads to more uniform deposition [17]. 18

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The graphite foam helps prevent radiation losses to maintain temperature uniformity, which in turn improves the uniformity of the epitaxial growth. The gas flow is controlled though mass flow controllers (MFCs). A computer program written in Labview [48] allows the user to specify gasses and flow rates. Figure 3.1: Horizontal hot-wa ll CVD reactor at USF. The current reactor configuration is capable of running propane (C 3 H 8 ), silane (SiH 4 ), hydrochloride (HCl) and methylchloride (CH 3 Cl) precursors, nitrogen (N 2 ) as a doping gas, and argon (Ar) or hydrogen (H 2 ) as carriers. H 2 is primarily used as the carrier gas and is delivered through a palladium purifier to remove all gas contaminants. The pressure in the chamber is regulated th rough a control valve and dry vacuum pump, and is capable of maintaining pressures fr om 70 Torr to 760 Torr, depending on the gas load. 3.2 Process Development The 3C-SiC heteroepitaxial process descri bed in this chapter was developed in several stages. The initial process began from the research started by R.L. Meyers in her 19

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thesis work [31]. Once a stable growth pr ocess that yielded specular films was achieved, optimization of that process began. The goal was to improve the growth rate and crystalline quality in order to produce thick films for power device applications. In the final stage, modifications were made to the CVD reactor and the optimized process applied to growth on 50 mm diameter Si wafers. 3.2.1 Initial baseline process The 3C-SiC on Si growth process was de veloped using the two step carbonization and growth method described in Chapter 2. C 3 H 8 and SiH 4 were used as the precursor gases to provide the carbon a nd silicon sources, respectiv ely. Ultra high purity (UHP) hydrogen, purified in a palladi um diffusion cell, was employe d as the carrier gas. The substrates used in the experiments were 8 mm x 10 mm die of n-type Si(100). Prior to growth, the samples were prepared usi ng the standard RCA cleaning method [49], followed by a 30 second immersion in diluted hydrofluoric acid (HF), to remove surface contaminants and the native oxide. The fi rst stage of the pr ocess, known as the carbonization step, involved hea ting the reactor from room temperature to 1140 C in a C 3 H 8 and H 2 only environment at atmospheric pressure. The temperature was then maintained for two minutes to carbonize the surface of th e substrate. Experiments performed by R.L. Myers-Ward and M. Reye s on the same CVD reactor, determined the ideal carbonization conditions we re at atmospheric pressure w ith a gas flow of 6 standard cubic centimeters per minute (sccm) of C 3 H 8 and 10 standard liters per minute (slm) of H 2 [50]. After carbonization, SiH 4 was introduced into the system at 4 sccm and the temperature increased to growth temperatur es. A series of experiments were then 20

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conducted to determine the ideal conditions for growth, which included variations in temperature, silicon to car bon (Si/C) ratio, and pressure. The initial growth conditi ons previously developed by R.L. Myers-Ward and M. Reyes were as follows: The precurso r flows were set to 6 sccm for C 3 H 8 8 sccm for SiH 4 and 30 slm for H 2 ; the temperature set to 1375 C; th e pressure set to 200 Torr. For each set of experiments only one variable was changed at a time. First, the temperature experiments were conducted in the range from 1355 C to 1385 C with the best morphology occurring in the range from 1375 C to 1385 C. Next, the chamber pressure was varied from 100 Torr to 400 Torr with the best film occurring at 100 Torr. Once the ideal temperature and pressure were established, the flow of C 3 H 8 was fixed and the amount of SiH 4 systematically increased. The maximum SiH 4 flow achieved, that still resulted in a specular film, was 13 sccm. Th e resulting Si/C ratio was calculated to be 0.72 and the growth rate measured to be approximately 10 m/h. Details of the process schedule can be found in Figure 3.2 below. Figure 3.2: 3C-SiC initial process schedule. (oC) 3C-SiC Growth Carbonization T 1140 1375 t ~20 2 ~ 85 -x Cool Down ( min ) ~ 30 H2 C3H8 SiH4 H2 C3H8 SiH4 H2 C3H8 Ar RT Atmospheric pressure 100 Torr 21

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3.2.2 Optimized process Once the baseline 3C-SiC process had been developed, efforts continued to improve the growth rate and morphology of the epitaxial films. The sample preparation was performed in the manner described in the pr evious section. Th e carbon source was the 100% C 3 H 8 used in the initial process, however, the silicon source was replaced with a 10% SiH 4 in H 2 mixture. For all the subsequent expe riments, the flow rates were fixed at 10 slm of H 2 and 6 sccm of C 3 H 8 during the initial temp erature ramp, two minute carbonization step, and the second temperature ramp to the growth step. Because SiH 4 is introduced into the reaction chamber immediat ely after carbonization, deposition starts to occurr during the second ramp, albeit at low growth rates. This was confirmed by terminating the experiment prior to the growth stage, and visually inspecting the surface. Multi-colored growth rings were clearly visibl e; indicating the presence of a thin film measured to be approximately 300 nm thick, via FTIR. It was found that by increasing the carbonization temperature from 1140 C to 1175 C, and thus introducing SiH 4 at a higher temperature, the morphology of the films improved. In addition, SiH 4 was gradually introduced after car bonization as a function of temp erature, to a maximum flow of 4 sccm, to help minimize defect formati on during the initial gr owth phase. Because the majority of the deposition occurs during the growth stage, where the Si/C ratio plays a major role, this became the focus of the next set of experiments. 22

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Table 3.1: 3C-SiC growth optimization experiments. Silane (sccm) Propane (sccm) Growth Rate ( m/h) Si/C Ratio 13 6 10 0.72 16 7 14 0.76 18 8 16 0.75 23 10 18 0.77 28 10 22 0.93 35 11.5 30 1.01 Using the initial process growth conditions described in the previous section as the starting point, a series of Si/C ratio experiments were conducted ( Table 3.1 ). First, C 3 H 8 was fixed at 6 sccm and SiH 4 was increased until morphology began to degrade. Once the maximum Si/C ratio was found, which resulted in specular f ilms, both precursors were then increased, while maintaining a constant Si/C ratio, until th e morphology began to degrade. Different Si/C ratios were necessa ry depending on the mole fractions of both SiH 4 and C 3 H 8 For higher mole fractions, a larger Si/C ratio was necessary. At growth rates above 18 m/h, the Si/C ratio had to be increased in order to maintain a specular film morphology. This is possibly due to th e contribution of the particular species C 3 H 8 to the growth [51]. As described in section 2.2, simulations performed on 4H-SiC epitaxial growth by Y. Shishkin et. al found that the particular gas species C 3 H 8 contributed negligibly to the epi growth [24]. However, in higher concentrations it may in fact begin to affect the process, thus result ing in the need to increase the Si/C ratio to maintain process stability [51]. Figure 3.3 shows the relationship is linear between the SiH 4 mole fraction and growth rate. Films deposited at rates of 18 m/h or less were of 23

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comparable quality to each other, whereas films deposited at rates greater than 18 m/h resulted in successive film degradation. The maximum growth rate and thickest (specular) film achieved during these experiments were 30 m/h and 22 m, respectively. The process schedule is identic al to that described in Figure 3.2 except the carbonization temperature was 1175 C and the gr owth temperature was 1385 C. Figure 3.3: Growth rate vers us silane mole fraction. 3.2.3 Growth on 50 mm Si(100) wafers Once the high deposition rate processes we re developed, the ne xt step was to apply them to larger surface areas, specifically 50 mm diameter Si wafers. The wafers were n-type, low resistivity, Si(100). Initial experiments found that specular growth over the entire wafer was not possible due to a large temperature gradient in the hot zone. Lower temperatures at the inlet caused depos ition on the upstream portion of the wafer to be polycrystalline, whereas higher temperatures at the outlet caused the downstream portion of the Si wafer to melt. Through a seri es of melt tests, wher eby a drop of Si is melted to calibrate the hot zone temperature reading of the pyrometer it was determined that the temperature gradient was approxi mately 35 C along the length of the 50 mm 24

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growth zone (see Figure 3.4 ). It was suggested that, by increasing the length of the hot zone and the volume of the insulating graphite foam, the temperature gradient could be reduced [51]. By having a longer hot zone, as shown in Figure 3.4 (b), the gases would have more time to heat up and reach a steady-state temperature and the increase in volume of the insulating foam would help to maintain hot zone heating uniformity. The length of the hot zone was increased by ~32 % and the overall volume of the insulating foam was increased by nearly 100%. This re sulted in a less than 5 C difference across the length of the 50 mm growth zone. Furthe r details of the hot z one design can be found in Appendix A. The growth was conducted in the same manner descri bed in the previous section. The growth process on the 50 mm Si wafers was found to be more affected by the condition of the CVD reactor and hot zone than growth on the die. Because of the larger surface area of the wafe rs and the temperature gradie nt inside the hot zone, the temperature window for single cr ystal growth was smaller. Completely specular films could only be obtained in the range between 1380 C and 1390 C; below 1380 C polycrystalline areas formed on the edges of the wafers, and above 1390 C the wafer edges began to melt. If the same graphite foam was used for too long of a period and it began to degrade, the temperature gradient worsened. Also, if the CVD reactor had remained idle for several days, a condi tioning run was usually necessary. The conditioning run entailed performing the ba seline process (deposition rate of 10 m/h) for 10 to 15 minutes on a Si die. 25

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250 mm C (a) (b) Figure 3.4: Cross-section of the growth zone us ing: (a) original susceptor design and (b) modified susceptor design. C represents temperature gradient across a 50 mm wafer. 3.2.4 Intentional doping of the 3C-SiC films Once the 3C-SiC growth on 50 mm diameter Si wafers was successful, intentional doping experiments of the 3C-SiC film s were then conducted. Nitrogen (N 2 ) mixed in H 2 was used as an n-type dopant. In th e first experiment, 100 sccm of a 1% N 2 in H 2 mix was used to obtain a doping value around 10 16 cm -3 In the second experiment, 50 sccm and 100 sccm of a 10% N 2 in H 2 mix was used to obtain a doping value around 10 17 cm -3 Figure 3.5 shows the correlation between the N 2 mole fraction and the doping of the 3CSiC films. The ability to achieve variously doped 3C-SiC epilayers is an important step in developing 3C-SiC based electronic devi ces. Intentionally doped 3C-SiC films produced from this work will be used to fabricate a 3C-SiC MOSCAP (see section 4.3 ). 190 m m C 26

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1.0E+15 5.1E+16 1.0E+17 1.5E+17 2.0E+17 2.5E+17 0 5101520253035 N2 Mole Fraction (x10^-5)Doping (cm^-3) Figure 3.5: N 2 mole fraction versus carrier concentration of the 3C-SiC films. 3.3 3C-SiC Film Characterization The thickness of the 3C-SiC epilayers was a ssessed with Fourier Transform infrared (FTIR) spectroscopy, and confirmed by cr oss-section scanning electron microscopy (SEM). The SEM cross-sections were also used to investigate the 3C-SiC/Si interface. Surface morphology was inspected via Nomarsky interference optical microscopy, atomic force microscopy (AFM), and SEM. The quality of the crystalline films was determined through X-ray diffraction (XRD) and low-temperature photoluminescence (LTPL) analysis. A non-contact mercury probe was employed to perform the CV/IV measurements, and the doping profil es of the grown 3C-SiC films. 3.3.1 FTIR The thickness of the epitaxially grown laye rs was measured with an Accent [52] QS1200 model FTIR. The FTIR uses a direct ed IR beam which passes through the epilayer and reflects off of the substrate crea ting, a primary and secondary interferogram. This signal is then subtracted from a reference sample and the thickness of the film is 27

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determined. A major benefit in using an FTIR is the ability to make quick, nondestructive and accurate thickness measurem ents, which allows the measurement of many points on the film to determine growth uniformity. Measurements of the 8 x 10 mm die were taken at the center of the die to tr y and avoid variations du e to edge effects. Measurements of the 50 mm wafers were coll ected at five points, as illustrated in Figure 3.6 Variations in thickness across all measured wafers were found to be less than 15%. Table 3.2 contains thickness measurements taken of two 3C-SiC epi-layers deposited at 18 m/h and 30 m/h. Note the decrease in film th ickness along the direction of the gas flow (A to E); this is likely attributed to the partial depletion of species along the gas stream. Also, the film deposited at the hi gher rate had less varia tion in thickness across the wafer, 5.5% compared to 12.7 %. This is probably due to the higher mole fractions of SiH 4 and C 3 H 8 present in the higher deposition ra te process. The deposition rate was calculated by measuring the thickness for a particular growth tim e, subtracting 0.4 m for the epilayer grown during the second temperat ure ramp, and multiplying by a factor to determine the rate in m/h. A slight decrease in deposition rate and an improvement in morphology were observed when transferring th e growth process from 8 x 10 mm die to 50 mm wafers. For example, a part icular process which yielded 20 m/h on the die, yielded 18 m/h when applied to a 50 mm wafer. These results remained consistent throughout numerous experiments. Details on how the size of the growth area affected morphology can be found in the next section. 28

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Figure 3.6: Diagram of wafer mapping for thickness measurements shown in Table 3.2 Table 3.2: Thickness measurements taken on two wafers depostited at different growth rates. Thickness measured via FTIR reflection pectroscopy. s Point Thickness ( m) rate = 18 m/h Thickness ( m) rate = 30 m/h A 10.4 11.3 B 9.5 10.8 C 9.7 11.0 D 9.4 10.7 E 9.2 10.8 Precursor Flow A B C D E 3.3.2 Optical microscopy A Normarski interference optical microsc ope was used to visually inspect the surface of the 3C-SiC epilayers. The ava ilable objectives ranged from 100 to 500 times magnification. Figure 3.7 (a) and (b) are optical images of 3C-SiC films taken at 500X using the same growth process and deposit ion rate, applied to an 8x10 mm die and a 50 mm wafer, respectively. From theses images one can clearly see how the surface of the film improves when depositing on larger growth areas. Figure 3.7 (c) and (d) are optical images of 10 m thick 3C-SiC films at 500X, which we re deposited at different growth rates on 50 mm wafers. A hi gher concentration of hilloc ks can be seen on the film deposited at 30 m/h ( Figure 3.7 (d)) compared to the one deposited at 18 m/h ( Figure 3.7 (c)). Note also the larger size of the hillocks in the film deposited at the higher growth rate. The hillock defect dens ities were approximately 1.9 x 10 4 cm -2 and 0.23 x 10 4 cm -2 respectively. These values are comparable to, and in the case of the film deposited at 18 m/h, better than those reported in the literature [20]. 29

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(a) (b) (c) (d) Figure 3.7: Optical images taken at 500X of (a) 5.4 m thick film deposited at 18 m/h on 8x10 mm die (b) 5 m thick film deposited at 18 m/h on 50 mm wafer (c) 10 m thick film deposited at 18 m/h on 50 mm wafer (d) 10 m thick film deposited at 30 m/h on 50 mm wafer. 3.3.3 SEM A Hitachi [53] model SEM at the USF COT f acility in Largo, FL [54] was used to confirm the FTIR thickness measurements a nd investigate the 3C-SiC/Si interface. Cross-sections taken of several films with varying thickness and deposition rates found very few voids present at the 3C-SiC/Si interface. Figure 3.8 is a cross-section of a 10 m thick film deposited at 30 m/h, and no voids are visible at the 3C-SiC/Si interface. The near absence of voids is likely attribut ed to the longer ramp-up and cool-down times used during the growth of the crystalline films. 30

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Figure 3.8: SEM secondary electron image, at 5,000X, of a crosssection of a ~11.5 m thick 3C-SiC film on Si(100), deposited at 30 m/h. Image courtesy of D. Edwards, USFCOT, Largo, FL. Si 3C-SiC Cross-section SEM was also employed in the investigation of the hillock defects. A 3C-SiC film with a high de nsity of hillocks was chosen for study. The sample was prepared by mechanically polishing the edge with diamond impregnated paper. With each polish, a finer grit size was used, until the edge was mirror-like. This edge was then studied under the SEM, using both secondary and backscattered electrons. Figure 3.9 (a) and (b) are SEM backscatter electron images of a hillock cross-section. Root-like features can be seen penetra ting down into the crystal from the hillock. From the SEM images, it is not clear what initiates the defe ct formation; possibly dislocations in the crystal growth or precipitates interrupting the nucleation. Whatever the cause, it is apparent that hillocks extend beyond th e surface into the epitaxial layer. 31

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(a) (b) Figure 3.9: SEM backscatter el ectron image of a cross sec tion of: (a) a hillock at 8k magnificaion and (b) same hillock at 30k magnification. Image courtesy of D. Edwards, USF-COT, Largo, FL. 3.3.4 AFM A Veeco Digital Instruments [55] model AFM was used to quantify the surface morphology of the grown films. An AFM is a type of scanning probe microscope which employs a cantilever and laser feedback system. As the cantilever passes over the sample surface, a position sensitive photo detector meas ures the changes in the laser signal and creates a topographical representation of the surface. For all of the surface studies, tapping mode AFM was used. Figure 3.10 (a) and (b) are 50 x 50 m scans, taken at a zheight of 100 nm, of films grown at 18 m/h and 30 m/h, respectively. Note the slightly larger grain sizes in Figure 3.10 (a). AFM and optical data would suggest the film deposited at 18 m/h was of higher quality than the film deposited at 30 m/h. However, despite the lower hillock defect density and smoother surface, XRD and LTPL analysis suggests the crystalline struct ure to be slightly superior in the film deposited at 30 m/h. 32

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(a) (b) Figure 3.10: 50 x 50 m AFM scans of 10 m thick 3C-SiC films on 50 mm Si wafers, deposited at: (a) 18 m/h and (b) 30 m/h. Tapping mode with a z-height of 100 nm was used. Images courtesy of D. Edwards, USF-COT, Largo, FL. 3.3.5 XRD XRD was used to analyze the crystalline qu ality of the 3C-SiC films deposited on the 50 mm Si(100) wafers. In XRD, x-rays are used to determine the normal spacing between adjacent crystallographic planes by mean s of Braggs law. If a crystal has few defects, then less scattering of the x-rays will occur, and the intensity peak of the reflected beam will be narrow [56]. The epitaxial layers were not removed from the substrate prior to measurement. Powder diffraction measurements, in which the sample is scanned over a wide range of angles, were taken first, in order to determine the orientation of the grown layers. Figure 3.11 (a) and (b) are powder diffractions taken on 10 m thick 3C-SiC on Si(100) films deposited at 18 m/h and 30 m/h, respectively. Note the strongest peaks for both films occur at approximately 41, which corresponds to the <200> plane of 3C-SiC. Additional p eaks can be found at approximately 90 and 69. These peaks corresponds to the <400> plane of 3C-SiC and the <200> plane of cubic Si, respectively. The presence of a peak at 69 is likel y due to the X-Rays penetrating through the 3C-SiC film and diffr acting off of the underlying Si substrate. No other peaks were present, confirming that the grown epitaxial layers are single crystal 33

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3C-SiC oriented in the <100> direction. Figure 3.11 (c) and (d) are rocking curve measurements taken on the <200> 3C-SiC peak. The full-width half-maximum (FWHM) values were slightly improved in the higher growth rate process; the FWHM was measured to be 300 arcseconds, compared to a FWHM of 340 arcseconds. Theses values were found to be comparable [25] and in several cases better [27,57] than those reported in literature. (a) (b) (c) (d) Figure 3.11: XRD of 10 m thick 3C-SiC epilayers on 50 mm Si(100) wafers. Powder diffraction of films deposited at: (a) 18 m/h and (b) 30 m/h. Rocking curve of the 3CSiC(200) peak of films deposited at: (c) 18 m/h and (b) 30 m/h. 3.3.6 LTPL Two samples of the epitaxially gr own 3C-SiC films, deposited at 18 m/h and 30 m/h, were sent to Dr. Choykes group at the University of Pittsburgh for LTPL (2 K) 34

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analysis. The results indicate that the film deposited at the higher growth rate is of slightly better quality than th e lower growth rate film. Details of the measurements can be found in Appendix B. 3.3.7 CV/IV A mercury (Hg) probe was used to make non-contact CV and IV measurements of the as grown 3C-SiC films. Figure 3.12 is a plot of the current versus voltage for a 10 m thick, unintentionally doped 3C -SiC film. The voltage wa s swept from -3V to 3V using front to back contacts. The results cl early indicate the 3C-SiC film is n-type. Figure 3.12: Plot of the log of the current vs. voltage of an unintentionally doped 10 m thick 3C-SiC film. The film is clearly n-t ype. Note measurements made A to C (inset shows device cross-section). Anode contact, A, made via Hg probe. C A 3C-SiC Si Instrument noise level Once the IV characteristics were determined, the capacitance versus voltage was measured for the same film by making front to front contacts and applying a reverse bias (see Figure 3.13 ). The reverse bias creates a depl etion region of width W, which is dependent on the applied voltage [58]. From this relationship, the carrier concentration of the film can be determined. Figure 3.14 is the plot of the calculated carrier 35

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concentration versus depth (W ) of the 3C-SiC film. Th e carrier conc entration was estimated to be around 10 15 cm -3 ; this value remained consistent for all the unintentionally doped 3C-SiC f ilms that were measured. Figure 3.13: Plot of capacita nce vs. voltage for an unint entionaly doped n-type, 10 m thick 3C-SiC film. Inset shows device cros s-section. Note measurement made A to C. U S F06250 Si/C ratio = 0 7 6 gr owt h rat e = 18 m/ h C A 3C-SiC Si Figure 3.14: Plot of calculated carrier concentration vs. dept h for an unintentionaly doped n-type, 10 m thick 3C-SiC film A doping density of N D -N A ~ 10 15 cm -3 was es tim ated f o r this f ilm U S F06250 Si/C ratio = 0 7 6 gr owt h rat e = 18 m/ h The CV and IV plots shown above were from m easure m ents taken at the center of the 50 mm dia m eter wafer. A doping density of N D -N A ~ 10 15 cm -3 was estim a ted f o r this f ilm. Additional m easure m ents were taken on various points across the wafer (see Figure 3.15 ) 36

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to determine the doping uniformity. There were slight variations in doping across the 50 mm wafers, with higher values on the upstream portion of the wafers. Table 3.3 shows the variations in doping for tw o 3C-SiC films grown at different deposition rates. This could possibly be due to preferential deplet ion of certain species along the gas stream, resulting in sl ight variations across the wafe r in the Si/C ratio. It is clear from the values listed in the table be low, that the lower de position rate process resulted in a more uniform doping profile than the higher deposition rate process. Figure 3.15: Diagram of wafer mapping for doping measurements shown in Table 3.3: Doping measurements taken on two wafers depostited at differ ent growth rates. Doping etermined by the CV method. Precursor Flow Table 3.3 d Point N D -N A (x10 15 cm -3 ) rate = 18 m/h N D -N A (x10 15 cm -3 ) rate = 30 m/h A 3.4 4.6 B 3.2 3.2 C 3.1 4.5 D 3.2 3.2 E 3.2 5.1 A B C D E 3.4 Summary A stable 3C-SiC heteroepitaxial growth process on Si substrates, with deposition rates up to 30 m/h, has been developed. First, a ba seline process was achieved; the 3CSiC films were specular, but the deposition rate was low (~ 10 m/h). The baseline process was then optimized through temperature, pressure, and Si/C ratio experiments. With the optimized process, thick 3C-SiC films (up to 22 m thick) and high deposition rates (up to 30 m/h) were obtained. Next, the optim ized process was applied to growth on 50 mm diameter Si(100) wafers Before large area growth could be achieved, the CVD 37

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reactor was modified to reduce the temperature gradient from ~35 C to ~5 C in the growth zone. This resulted in the ability to produce specular films on 50 mm diameter Si(100) wafers. Growing over the larger areas has helped to reduce defects and improve production, which is an important st ep for 3C-SiC device research. 38

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CHAPTER 4 3C-SiC FILM APPLICATIONS 4.1 Growth on Wafer-Bonded Films (SOI) Now that a repeatable high deposition ra te 3C-SiC on Si process has been established on 50 mm diameter wafers, efforts are underway to apply the grown films in numerous applications, such as growth on wafer-bonded films (SOI). One of the disadvantages of 3C-SiC heteroepitaxy is that growth temperature is limited by the melting point of the underlying Si substrate, which is approximately 1410 C In recent years, interest has surfaced in developing 3C-SiC processes on novel substrates. Work was done in this field by R.L. Myers-Ward at USF, and one of the substrates she investigated was wafer-bonded silicon on insulator (SOI) [31]. SOI typically consists of a thin layer of Si bonded to a semi-insulating or insu lating substrate, such as polycrystalline SiC [59,60]. Th e advantage of using SOI substr ates is that the thin layer of Si is consumed during growth, thereby allowing high temperature growth to proceed. SOI technology is also advantageous to device fabricati on; the insulating layer helps to reduce power consumption and increase speeds in ICs [60]. The following work picks up where Dr. Myers research left off. 39

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Figure 4.1: Process flow used to produce SO I substrates for 3C-SiC growth [61]. The SOI substrates consisted of a thin layer of (001)Si, directly bonded onto a polycrystalline SiC substrate using the SmartCut technique ( Figure 4.1 ). The SOI substrates were provided by M. Sherwin at Northrop Grumman [62] in several batches with the Si layer varying from 0.3 m to 1 m thick. Samples were cut into 8x10 mm die and prepared in the same manner described in section 3.2.1. In all of the CVD experiments, a bare Si(100) control sample was placed along side the SOI samples. Batch 1 consisted of the 1 m thick Si layer, and was the initial sample used. The experiment was conducted using the low deposition rate (10 m/h) process described in section 3.2.1. It was found that the Si layer was to o thick, and all attempts resulted in polycrystalline 3C-SiC growth even though the control samples were always single crystal. Batch 2 consisted of SOI with 0.5 m thick Si layers. Specular growth, up to 2 m thick, was achieved on these samples. Th e following three batches: Batch 4 (0.3-0.4 m thick), Batch 5 (0.4-0.5 m thick), and Batch 6 (0.5-0.6 m thick), contained some thinner Si layers for the purpose of high temperature growth. Growth on all three of these batches resulted in crystalline films. Figure 4.2 (a) is an SEM surface image of a 1 m thick 3C-SiC film, deposited at 10 m/h, on a 0.5 m thick SOI substrate. Although the surface was specular, it was found to be highly grainy under SEM. Figure 4.3 (b) is 40

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an SEM surface image of an 11 m thick 3C-SiC film, deposited at 14 m/h, on a 0.4 m thick SOI substrate. It is clear from the imag es that the thicker film is of higher quality. (a) (b) Figure 4.2: SEM images taken at 5,000X of: (a) 1 m thick 3C-SiC epi on SOI substrate, and (b) 11 m thick 3C-SiC epi on SOI substrate. The challenge to performing high temperat ure growth was determining when the entire Si layer had been consumed. Severa l experiments were conducted to produce films of varying thickness, which were then examin ed via cross-section SEM to determine if any of the Si remained. It is critical that the en tire Si layer is consumed before high temperature growth is attempted, otherwise me lting of the Si can cause bubbles to appear on the surface of the film. Figure 4.3 (a) is a SEM cross-section of a 1 m thick 3C-SiC epilayer, and clearly shows the presence of a Si layer between the epi and polycrystalline substrate. Figure 4.3 (b) is a SEM cross-section of an 11 m thick 3C-SiC epilayer with no Si remaining between the epi a nd the polycrystalline substrate. 41

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3C-SiC 3C-SiC Si Poly-SiC Poly-SiC (a) (b) Figure 4.3: SEM cross-section of: (a) 1 m thick 3C-SiC epi on SOI substrate, with Si layer present, and (b)11 m thick 3C-SiC epi on SOI substr ate with no Si layer present. T (oC) 1175 t ( min ) 3C-SiC Growth Carbonization 1375 ~20 2 ~ 845Cool Down ~ 30 H2 C3H8 SiH4 H2C3H8 SiH4 H2C3H8 RT Atmospheric pressure 100 Torr 15 1450 1StSta g e 2ndSta g e Figure 4.4: Process schedule developed for hi gh temperature growth of 3C-SiC on SOI. Once the initial Si layer is consumed in th e first stage of growth, the temperature is increased and a second stage of growth is conducted ( Figure 4.4 ). The first stage of growth was conducted at 1385 C for 45 minut es, followed by 15 minutes at the higher temperature. Temperatures of 1450 C, 1500 C and 1550 C were used for the second stage, and the effects on morphology and growth rate were compared. Figure 4.5 shows a 42

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slight increase in the growth rate of about 0.5 m/h for every 50 C. The morphology however, was similar under an optical mi croscope for all three temperatures. Figure 4.5: Growth rate of 3C-SiC on SOI as a function of temperature. Although growth rates as high as 30 m/h have been achieved on bare Si(100) substrates, it was found that 18 m/h was the maximum growth rate possible to maintain single crystal growth on the SOI substrates. In section 3.3.2 it was shown that growth performed on 50 mm diameter Si(100) wafers had a significant improvement in morphology over growth on 8x10 mm die. Therefore, it is likely that if the 3C-SiC on SOI process was applied to a 50 mm diameter SOI wafer the quality of the 3C-SiC film would improve. 4.2 MOSCAPs Several of the 3C-SiC films described in this thesis work, which were grown on 50 mm diameter Si(100) wafers, ar e currently being used in th e fabrication of MOSCAPs. The following 3C-SiC films were chosen as substrates for the MOSCAPs: a 10 m thick 43

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unintentionally doped film, with a carrier concentration of 10 15 cm -3 ; and a 12 m thick intentionally doped film, with a carrier concentration of 10 16 cm -3 Both films were deposited at a rate of 18 m/h. The 3C-SiC epilayers were sent to Nova SiC [63] for chemical mechanical polishing, or CMP. The oxidation, fabrication and testing of the device will be performed here at the University of South Fl orida (USF), by A. Joseph, I. Haselbarth, and E. Short. Simulations of the MOSCAP in Medici are being conducted by A. Joseph [64]. 4.3 MEMS 3C-SiC heteroepitaxial layers have b een successfully grown on MEMS molds, using C 3 H 8 /SiH 4 /HCl precursor chemistry [65]. Th e experiments were conducted by M. Reyes, M. Waites, S. Harvey, Y. Shishkin, an d S.E. Saddow here at USF, using the same CVD reactor described in this work. The substrates, provided by M. Waits at the Army Research Laboratory (ARL) [66], were 22, 52, and 123 m deep, DRIE etched Si(100), MEMS structures. The two stage, carbonizatio n plus growth step process was used to deposit the 3C-SiC films. Carbonization was conducted at 1115 C for 2 minutes at atmospheric pressure, and growth was conducted at 1375 C at a pressure of 100 Torr. The Si/C and Si/Cl ratios used durin g growth were 0.9 and 1.5, respectively. Figure 4.6 (a) and (b) are SEM images of the cross-section of a 52 m deep trench before and after the 3C-SiC deposition, respectively. In Figure 4.6 (b), the thickness of the 3C-SiC layer is greater along the top and edge of the mold compared to the base. If the thickness of the film were to increase, a key-holing effect would eventually occur. New Si MEMS structures are being designed to eliminate this problem by angling the trench side-walls, at which point deposition experiments will continue. 44

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3C-SiC Si (a) (b) Figure 4.6: SEM cross section of 52 m deep trench in Si mold : (a) before deposition and, (b) after deposition of 3C-SiC [65]. 4.4 3C-SiC/SOI Gas Sensor A resistive hydrogen gas sensor was fabric ated on a 3C-SiC film deposited during the course of this research, on a SOI substrate [67]. A 1.4 m thick 3C-SiC film was deposited on a 15 nm thick Si layer bonded to polycrystalline SiC, us ing a growth process similar to that described in 3.2.1. The fabrication and testing of the device was performed by Dr. T. J. Fawcett at both the USF and COT facilities in Tampa and Largo, FL. A 5000 thick SiO 2 layer was deposited via PECVD, followed by etching of the active area, and metal c ontact deposition. After deposition, the contacts were annealed to produce ohmic-like behavior. The samples were then sent to A.L. Spetz at Linkping University, Sweden to be packaged. When tested, the device was capable of detecting 10% to 100% H 2 concentration in N 2 at a temperature of 673 K. 45

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Figure 4.7: A packaged resistive H 2 gas sensor fabricated on 1.4 m thick 3C-SiC film on SOI substrate. Image courtesy of T. J. Fawcett, USF, Tamp, FL [12]. 4.5 Summary Baseline and optimized 3C-SiC epitaxial growth processes on (100)Si were developed during this thesis work. These processes have been applied to growth on bonded substrates (SOI), and the fabrication of MOSCAPs, MEMS, and gas sensors. The SOI substrates with thin la yers of Si, ranging from 0.3 m to 1 m thick, were bonded to polycrystalline SiC. Crystalline growth was achieved on all but the 1 m thick sample. Additional high temperature (>1410 C) e xperiments were also conducted, which resulted in an increase in the growth rate of about 0.5 m/h per 50 C. The samples provided for the MOSCAPs were two 50 mm di ameter 3C-SiC on Si(100) wafers, with doping values of ~10 15 cm -3 and ~10 16 cm -3 3C-SiC epitaxial growth was also achieved on 22, 52, and 123 m deep, DRIE etched Si(100), MEMS structures, provided by ARL [65]. The growth process used on the molds was similar to the baseline process, with the addition of HCl to the precursor chemistry. Because key-holing effects prevented the filling of the trenches, new molds are being fabricated with angled side-walls. 46

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CHAPTER 5 CONCLUSIONS AND FUTURE WORK 5.1 Summary A 3C-SiC heteroepitaxial CVD growth process on 50 mm diameter Si(100) substrates, with deposition rates up to 30 m/h, has been developed and characterized during this thesis work. The growth proce ss was developed in three stages; an initial baseline development stage, an optimizati on stage, and a large area growth stage. The baseline process was achieved using a two step growth method. First the sample was heated from room temperature to 1140 C, at atmospheric pressure, using a H 2 /C 3 H 8 (10 slm/6 sccm) gas mixture. The temp erature was maintained at 1140 C for 2 minutes to carbonize the Si surface. Then SiH 4 was introduced into the gas mixture at a flow rate of 4 sccm, and the temperature increased to 1375 C, which is the growth temperature. Once the growth temperature was reached, the pressure was lowered to 100 Torr and H 2 and SiH 4 were increased to 30 slm and 13 sccm, respectively. The resulting 3C-SiC films were specular, but the deposition rate was low (~ 10 m/h). The baseline process was then optimized through temperature and Si/C ratio experiments. The growth was conducted in the same manner as th e baseline process. However, the carbonization temperat ure was raised to 1175 C and SiH 4 was introduced incrementally during the second temper ature ramp. During growth, the C 3 H 8 and SiH 4 mole fractions were significantly increased. With the optimized process, thick 3C-SiC films (up to 22 m thick) and high deposition rates (up to 30 m/h) were obtained. 47

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Finally, the optimized process was applie d to growth on 50 mm diameter Si(100) wafers. Before large area growth could be achieved, the CVD reacto r was modified to reduce the temperature gradient from ~35 C to ~5 C in the effec tive growth zone (see Figure 3.4 ). This resulted in the ability to produce specular films on 50 mm diameter Si(100) wafers. There was a slight decrea se in the growth rate, but a significant improvement in the surface morphology when th e process was transf erred from the 8 x 10 mm die to the 50 mm diameter wafers. The 3C-SiC films grown during this work were characterized using a variety of methods. The thickness of the 3C-SiC epilayers was assessed through Fourier Transform infrared (FTIR) spectroscopy, and conf irmed by cross-secti on scanning electron microscopy (SEM). The SEM cross-sections we re also used to investigate the 3C-SiC/Si interface and study hillock defect s. There were very few voi ds found at the epi/substrate interface. Cross-sections of the hillocks reve aled root-like features penetrating down into the epitaxial layer. However, the cause and origin of these defects could not be determined without further investigation. The surface morphology of the films was inspected via Nomarsky inte rference optical microscopy, atomic force microscopy (AFM), and SEM. The density of the hilloc k defects was estimated to be between 1.9 x 10 4 cm -2 and 0.23 x 10 4 cm -2 depending on the deposition rate. The surface defects became larger and denser with higher depositi on rates and thicker film s. The crystalline quality of the 3C-SiC films was determined through X-ray diffraction (XRD), performed at USF, and low-temperature photoluminescence (LTPL) analysis, performed at the University of Pittsburgh. Results from th e powder diffraction measurements revealed peaks only from the <200> and <400> 3C-SiC and <200> Si crystallographic planes, 48

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indicating that the epitaxially grown layers are cubic SiC. Rocking curve measurements on the <200> 3C-SiC peak of two 10 m thick films, deposited at different rates, resulted in FWHM values of 300 and 340 acrsec. The narrower peak corresponded to the film grown at the higher deposition rate, indicat ing possibly a higher quality crystalline structure. This was confirmed by the LTPL (2 K) measurements. A mercury probe was used to make non-contact CV/IV measurements of the 3C-SiC films. It was determined from the IV measurements that the films were n-type. Doping densities of 10 15 and 10 16 were extracted from the CV measurements for the unintentionally and intentionally doped films, respectively. There were sli ght variations in doping across the films deposited on 50 mm diameter Si wafers. Ov erall, the 3C-SiC films grown during this work were of comparable quality to th e best films reported in the literature. The 3C-SiC CVD processes developed dur ing this work, and many of the grown 3C-SiC films, were used in numerous appli cations. The baseline process was used to deposit 3C-SiC films on MEMS structures with 22, 52 and 123 m deep trenches. The optimized process was used to conduct high temperature 3C-SiC epitaxy on Si bonded to polycrystalline SiC (SOI) substrates. Als o, a 3C-SiC on SOI film was used in the fabrication of a wide-range resistive H 2 gas sensor and two 3C-SiC films deposited on 50 mm Si wafers were used in the fabrication of MOSCAPs. 5.2 Future Work The development of a high growth rate 3C-S iC epitaxial process, and the ability to deposit films over 50 mm diameter Si wafers, which has helped to reduce defects and improve production, is an important step in the on-going SiC resear ch being conducted here at USF. However, the optimization pr ocess is never complete; there are many 49

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techniques available to try and further impr ove the 3C-SiC growth process. Currently, M. Reyes is investigating the addition of HCl to the SiH 4 /C 3 H 8 precursor mix, and shortly experiments will begin to develop a 3C-SiC growth process using methylchloride (CH 3 Cl) in addition to the standard chemistry. A second CVD reactor has been built, by C. Frewin in our group and work will soon begi n to establish a 3C-SiC growth process on 100 mm diameter Si wafers. Also in collabora tion with O. Kordina at Caracal [68], work has begun to grow a thick (+100 m) 3C-SiC layer, using the 18 m/h deposition process developed during this thesis, for use as a seed wafer for the growth of bulk 3C-SiC crystals. One of the challenges affecting the bulk gr owth process is the in ability to grow high quality thick films (> 50 m) of 3C-SiC on Si. The thicke r the 3C-SiC films become, the greater the density of surface defects, to the point in which the surface is no longer specular. The likely culprits are the latt ice mismatch between 3C-SiC and Si and precipitates in the reactor. The precipita tes could be minimized by following a more rigorous reactor cleansing schedule, such as cleaning the reactor after every growth run, and/or swapping out graphite part s sooner, so that degradation is not an issu e. However, the cost of parts can make this an uneconomi cal solution. There also is the matter of the lattice mismatch at the 3C-SiC/Si interface, which causes stress in the epitaxial layer and can lead to the formation of defects. Unlike SiGe, 3C-SiC can not all oy with Si to form a defect-free buffer layer betw een the two materials. Figure 5.1 (a) illustrates how Si and Ge can be alloyed to create a buffer layer between the two materials. Note the difference at the interface in the case of 3C-SiC layer on Si (Figure 5.1 (b)). One way in which defects due to the stress at the interface could possibly be reduced is by growing a 50

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compliance layer betwee n 3C-SiC and Si ( Figure 5.1 (c)). If a thin 3C -SiC layer could be degenerately doped with larger substitutional atom s, so that the lattice constant is larger than that of an unintentionally doped 3C-SiC f ilm, it could serve as an intermediate layer between the Si substrate and 3C-SiC epi. Another way defects coul d possibly be reduced is by growing in stages. First, an initia l 3C-SiC layer would be grown using a low deposition rate process to produce a high quality thin film (1-2 m thick). This would be followed by a short H 2 etch to clean the surface and a cool down to room temperature. Finally, the sample would be re-grown on without breaking vacuum, using a higher deposition rate process. The H 2 etch and cool down could be repeated periodically, say every 45-60 minutes, to try and minimize the propagation of defect s. Whether or not these suggestions can improve the current growth process has yet to be determined. The key to ensuring that 3C-SiC research here at USF remains on the forefront, is to continue finding ways to improve the growth process. Si SiGe alloy Si 3C-SiC ( a ) ( b ) (c) Si 3C-SiC degenerately do p ed 3C-SiC Figure 5.1: Illustration of: (a) SiGe epitaxy on Si, with a graded Si X Ge 1X alloy laye r in between (b) 3C-SiC epitaxy on Si, and (c) 3C -SiC epitaxy on Si, with a degenerately doped 3C-SiC layer in between to serve as a buffer layer. 51

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REFERENCES [1] K. Shenai, Scott, R.S., and Baliga, B.J., Optimum semiconductors for high-power electronics IEEE Trans. Electron Devices Vol. 36, 1811 (1989). [2] Y. Goldburg, M. E. Levinshtei n, and S. L. Rumyantsev, in Properites of Advanced Semiconductor Materials edited by M. E. Levinshtein, S. L. Rumyantsev, and M. S. Shur (John W iley & Sons, New York, NY, 2001), p. 9395. [3] Foll, H. www.tf.uni-kiel.de/matwis/amat/s emi_en/kap_a/backbone/ra_1_1.html [4] Cree Inc www.cree.com [5] R. Hull, Properties of Crystalline Silicon (INSPEC, London, UK, 1999). [6] D. L. Smith, Thin-Film Deposition: principles and practice (McGraw-Hill, 1995). [7] C.-M. Zetterling, S.-M Koo, and M. Ostling, Devices in SiC (INSPEC, The Institution of Electrical Engineers, London, UK, 2002). [8] M. a. B. Bhatnagar, B.J., Comparison of 6H-SiC, 3C-SiC, and Si for Power Devices IEEE Trans. Electron Devices Vol. 40 (3), 646-654 (1993). [9] O. Kordina and S. E. Saddow, in Advances in Silicon Carbide Processing and Applications edited by S. E. a. A. Saddow, Anant (Artech House, Inc., Norwood, MA, 2004), p. 2-22. [10] D. K. Schroder, Semiconductor Material and Device Characterization 2nd ed. (John Wiley & Sons, Inc., New York, NY, 1998). [11] NASA www.grc.nasa.gov/www/sic/benifits.html [12] T. J. Fawcett, Investigation into the Hydrogen Ga s Sensing Mechanism of 3C-SiC Resistive Gas Sensors PhD. Dissertation, University of South Florida, 2006. [13] H. O. Pierson, Handbook of Chemical Vapor Deposition: Principles, Technology, and Applications (Noyes Publications/William Andrew Publishing, LLC, Norwich, NY, 1999). [14] I. V. Markov, Crystal Growth for Beginners 2nd ed. (World Scientific Publishing Co. Pte. Ltd., River Edge, NJ, 2003). 52

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[15] R. C. Rossi, Low Pressure Chemical Vapor Deposition (Noyes Publications, Park Ridge, NJ, 1988). [16] M. L. Hammond, Silicon Epitaxy by Chemical Vapor Deposition (Noyes Publications, Park Ridge, NJ). [17] A. Sherman, Chemical Vapor Deposition for Microelectronics (Noyes Publications, Westwood, NJ, 1987). [18] Principles of Chemical Vapor Deposition edited by D. M. Dobkin and M. K. Zuraw (Kluwer Academic Publishers, Norwell, MA, 2003). [19] S. Nishino, J. A. Powell, and H. A. Will, Production of large-area single-crystal wafers of cubic SiC for semiconductor devices Appl. Phys. Lett. Vol. 42, 460-462 (1983). [20] J. Yun, T. Takahashi, M. Takeshi, Y. Ishida, and H. Okumura, Reductions of twin and protrusion in 3C-SiC heteroepitaxial growth on Si(100) J. of Cryst. Growth Vol. 291, 148-153 (2006). [21] K. Teker, C. Jacob, J. Chung, and M. H. Hong, Epitaxial growth of 3C-SiC on Si(001) using hexamethyldisilane a nd comparison with growth on Si(111) Thin Solid Films Vol. 371, 53-60 (2000). [22] S. Madapura, A. J. Steckl, and M. Loboda, Heteroepitaxial growth of SiC on Si(100) and (111) by chemical v apor deposition using trimethylsilane J. of The Electrochemical Society Vol. 146, 1197-1202 (1999). [23] K.-W. Lee, K.-S. Yu, and Y. Kim, Heteroepitaxial growth of 3C-SiC on Si(001) without carbonization J. of Cryst. Growth Vol. 179, 153-160 (1997). [24] Y. Shishkin, R. L. Myers-Ward, S. E. Saddow, A. Galyukov, A. Vorob'ev, D. Brovin, D. Bazarevskiy, R. Ta lalaev, and Y. Makarov, in Analysis of SiC CVD growth in a horizontal hot-wall re actor by experiment and 3D modeling ECSCRM, Newcastle-Gateshead, UK, 2006 (TMS). [25] J. Yun, T. Takahashi, Y. Ishida, and H. Okumura, Dependence of stacking fault and twin densities on deposition conditions during 3C-SiC heteroepitaxial growth on on-axis Si(001) substrates J. of Cryst. Growth Vol. 291, 140-147 (2006). [26] H. Nagasawa, K. Yagi, T. Kawahara, N. Hatta, and M. Abe, Heteroand homoepitaxial growth of 3C-SiC for MOS-FETs Microelectronic Engineering Vol. 83, 185-188 (2006). [27] B. Burkland, Z. Y. Xie, J. H. Edgar, M. Ervin, J. Chaudhuri, and S. Farsinivas, Effects of the Addition of Silane during Carbonizatio n on the Epitaxy of 3C-SiC on Si J. of the Electrochemical So ciety Vol. 149, G550-G554 (2002). 53

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[28] R. Scholz, U. Gosele, F. Wischmeyer, and E. Niemann, Prevention of micropipes and voids at -SiC/Si(100) interfaces Appl. Phys. Vol. A 66, 59-67 (1998). [29] X. H. Zheng, B. Qu, Y. T. Wang, Z. Z. Dai, J. Y. Han, H. Yang, and J. W. Liang, Comprehensive analysis of microtwins in the 3C-SiC films on Si(001) substrates J. of Cryst. Growth Vol. 233, 40-44 (2001). [30] Foll, H. www.tf.uni-kiel.de/matwis/amat/def_en/kap_5/backbone/r5_4_1.html [31] R. L. Myers, CVD Growth of SiC on Novel Si Substrates MS Thesis, University of South Florida, 2003. [32] Y. Irokawa, M. Kodama, and T. Kachi, Growth of 3C-SiC layers on Si substrates with a novel stress relaxation structure J. Appl. Phys. Vol. 40, 5907-5908 (2001). [33] A. Gupta, D. Paramanik, S. Varma, and C. Jacob, CVD growth and characterization of 3C-SiC thin films, Bull. Mater. Sci. Vol. 27, 445-451 (2004). [34] Y. H. Seo and K. S. Nahm, Epitaxial growth of void free -sic on Si by the pyrolysis of tetramethylsilane J. Korean Physical So ciety Vol. 33, S324-S329 (1998). [35] A. Leycuras, Role of oxygen in the formation of voids at the SiC-Si interface Appl. Phys. Lett. Vol. 70, 1533-1535 (1997). [36] H. Nagasawa and Y.-I. Yamaguchi, Suppression of etch pit and hillock formation on carbonization of Si substrate and low temperature growth of SiC J. of Cryst. Growth Vol. 115, 612-616 (1991). [37] C. C. Chiu and S. B. Desu, Conversion of single crystal Si(100) to SiC film by C 2 H 2 J. of Materials Research Vol. 8, 535 (1993). [38] X. Fu, C. A. Zorman, and M. Mehregany, Surface roughness control of 3C-SiC films during the epitaxial growth process J. of The Electrochemical Society Vol. 151, G910-G914 (2004). [39] O. Kordina, L.-O. Bjorketun, A. Henry, C. Hallin, R. C. Glass, L. Hultman, J.-E. Sundgren, and E. Janzen, Growth of 3C-SiC on on-axis Si(100) substrates by chemical vapor deposition J. of Cryst. Growth Vol. 154, 303-314 (1995). [40] A. J. Fleischman, C. A. Zorman, M. Mehregany, C. Jacob, S. Nishino, and P. Pirouz, Epitaxial growth of 3C-SiC films on 4-inch diameter (100) silicon wafers by APCVD Vol. 142 (IOP Publishing Ltd., 1996). [41] J. L. Zilko, Metal-Organic Chemical Vapor Deposition: Technology and Equipment (Noyes Publications, Park Ridge, NJ, 1988). 54

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[42] M. Reyes, Y. Shishkin, S. Harvey, and S. E. Saddow, in Development of a highgrowth rate 3C-SiC on Si CVD process MRS Spring ( invited ), 2006. [43] F. La Via et al, High growth rate process in a SiC horizontal CVD reactor using HCl Microelectronic Engineer ing Vol. 83, 48-50 (2006). [44] C.-F. Wang and D.-S. Tsai, Low pre ssure chemical vapor deposition of silicon carbide from dichlorosilane and acetyle ne, Mat. Chem. & Phys. Vol. 63, 196-201 (2000). [45] Y. Gao, J. H. Edgar, J. Chaudhuri, S. N. Cheema, M. V. Sidorov, and D. N. Braski, Low-temperature chemical-vapor deposition of 3C-SiC films on Si(100) using SiH 4 -C 2 H 4 -HCl-H 2 J. of Cryst. Growth Vol. 191, 439-445 (1998). [46] M. T. Smith, Design and Developement of a Silicon Carbide Chemical Vapor Deposition Reactor, MS Thesis, University of South Florida, 2003. [47] Mesta Electronics Inc. www.mesta.com [48] National Instruments www.ni.com [49] W. Kern and D. A. Puotinen, Cleaning solutions based on hydrogen peroxide for use in silicon semi conductor technology RCA Rev. Vol. 31, 187-206 (1970). [50] R. L. Myers and M. Reyes Unpublished work (April, 2005). [51] Personal communication w ith Y. Shishkin, 10 July 2006. [52] Accent www.accentopto.com/index.asp [53] Hitachi High Technologies America, Inc. www.hitachi-hta.com [54] Center for Ocean Technology http://cot.marine.usf.edu/ [55] Veeco www.veeco.com [56] L. B. Freund and S. Suresh, Thin Film Materials: Stress, Defect Formation and Surface Evolution (Cambridge University Press, New York, NY, 2003). [57] T. Takahashi, Y. Ishida, H. Tsuchida, I. Kamata, H. Okumura, S. Yoshida, and K. Arai, Comparative study of heteroepitaxially and homoepitaxially grown 3C-SiC films Mater. Sci. Forum Vol. 389-393, 323-326 (2002). [58] D. K. Schroder, Semiconductor Material and Device Characterization (John Wiley & Sons, Inc., New York, NY, 1990). 55

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[59] K. D. Hobart, F. J. Kub, M. Fatemi C. Taylor, E. Eshun, and M. G. Spencer, Transfer of ultrathin silicon layers to polycrystalline SiC substrates for the growth of 3C-SiC epitaxial films J. of The Electrochemical Society Vol. 146, 3833-3836 (1999). [60] Soitec www.soitec.com/en/techno/t_2.htm [61] C. H. Carter et al. Materials Science Forum, Switzerland, 2001 (Trans Tech Pub.), p. 3-6. [62] Northrop Grumman www.northropgrumman.com [63] NovaSiC www.novasic.com [64] A. Joseph, MS Thesis, 2006. [65] M. Reyes, M. Waits, S. Harvey, Y. Shishkin, B. Geil, J. T. Wolan, and S. E. Saddow, Growth of 3C-SiC on Si molds for MEMS applications, Mater. Sci. Forum Vol. 527-529, 307 (2005). [66] Army Research Laboratory www.arl.army.mil/main/Main/default.htm [67] T. J. Fawcett, J. T. Wolan, A. L. Spetz, M. Reyes, and S. E. Saddow, Thermal detection mechanism of SiC based hydrogen resistive gas sensors Appl. Phys. Lett. Vol. ( In press ) (2006). [68] Caracal www.caracalsemi.com [69] W. J. Choyke, Z. C. Feng, and J. A. Powell, Low-temperature photoluminescence studies of chemical-vapor-de position-grown 3C-SiC on Si J. Appl. Phys. Vol. 64, 3163-3175 (2006). 56

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APPENDICIES 57

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Appendix A Hot Zone Design Drawings 190 Figure A.1: Original design of insulating graphite foam used in the developement of the baseline and optimized 3C-SiC processes on Si die. The graphite su sceptor is shown in A.3. All units are shown in mm. Drawing c ourtesy of I. Haselbarth, USF, Tampa, FL. 58

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Appendix A (Continued) 250 Figure A.2: Modified design of insulating graphite foam used during the development of the 3C-SiC growth process on 50 mm diameter Si wafers. The graphite susceptor is shown in A.4. All units are shown in mm. Drawing courtesy of I. Haselbarth, USF, Tampa, FL. 59

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Appendix A (Continued) 150 Figure A.3: Original design of tilted susc eptor (only top shown here) used in the development of the baseline and optimized 3C-SiC process on Si die. All units shown in mm. Drawing courtesy of I. Haselbarth, USF, Tampa, FL. 2 10 Figure A.4: Modified design of tilted susceptor (only to p shown here) used in the development of the 3C-SiC growth process on 50 mm diameter Si wafers. All units shown in mm. Drawing courtesy of I. Haselbarth, USF, Tampa, FL. 60

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Appendix B Low Temperature Photoluminescence (LTPL) Two 3C-SiC samples were sent to W.J. C hoyke at the University of Pittsburgh for low temperature photoluminescence (LTPL) anal ysis [69]. Both samples were 3C-SiC layers, approximately 10 m thick, on Si(100) substrates, which were cut into 1 cm x 1 cm die from a 50 mm diameter wafer. The two films were grown at different deposition rates; one at 18 m/h and the other at 30 m/h. The measurements were conducted at a temperature of 2 K. The excitation source was a 40 mW He-Cd ion laser, operating at a wavelength of 325 nm, and the detector wa s a UV sensitive CCD-9000. Details of the experimental setup can be found in [69]. At a wavelength of 325 nm, the light penetration depth into 3C-SiC is 2.9 m. Therefore, the laser source was suitable for the 10 m thick 3C-SiC films because the influence of the underlying Si substrate on the detected LTPL spectrum was minimal. Figure B.1 (a) and (b) below are the measured PL spectrums from the 3C-SiC films deposited at 18 m/h and 30 m/h, respectively. The spectrum of the film deposited at 30 m/h (Figure B.1 (b)) has a better signal to noise ratio and stronger L A peak, than the film deposited at 18 m/h (Figure B.1 (a)). However, both near-band-edge spectra did not exhibit the N 0 zero-phonon line. The peaks labeled (2) are attributed to the D II intrinsic defect which normally occurs at 5373 but due to stress in the epilay er there is likely a red-shift. 61

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(a) (b) Figure B.1: LTPL (2 K) spectrum of 10 m thick 3C-SiC film deposited at: (a) 18 m/h and (b) 30 m/h. Images courtesy of W.J. Choyke, University of Pittsburgh, PA. 62


xml version 1.0 encoding UTF-8 standalone no
record xmlns http:www.loc.govMARC21slim xmlns:xsi http:www.w3.org2001XMLSchema-instance xsi:schemaLocation http:www.loc.govstandardsmarcxmlschemaMARC21slim.xsd
leader nam Ka
controlfield tag 001 001919655
003 fts
005 20071220111758.0
006 m||||e|||d||||||||
007 cr mnu|||uuuuu
008 071220s2006 flu sbm 000 0 eng d
datafield ind1 8 ind2 024
subfield code a E14-SFE0001823
035
(OCoLC)184940332
040
FHM
c FHM
049
FHMM
090
TK145 (ONLINE)
1 100
Harvey, Suzie.
0 245
Growth of 3C-SiC via a hot-wall CVD reactor
h [electronic resource] /
by Suzie Harvey.
260
[Tampa, Fla] :
b University of South Florida,
2006.
3 520
ABSTRACT: The heteroepitaxial growth of cubic silicon carbide (3C-SiC) on silicon (Si) substrates at high growth rates, via a horizontal hot-wall chemical vapor deposition (CVD) reactor, has been achieved. The final growth process was developed in three stages; an initial "baseline" development stage, an optimization stage, and a large area growth stage. In all cases the growth was conducted using a two step, carbonization plus growth, process. During carbonization, the surface of the Si is converted to 3C-SiC, which helps to minimize the stress in the growing crystal. Propane (C3H8) and silane (SiH4), diluted in hydrogen (H2), were used as the carbon and silicon source, respectively. A deposition rate of approximately 10 um/h was established during the baseline process. Once the baseline process proved to be repeatable, optimization of the process began. Through variations in temperature, pressure, and the Si/C ratio, thick 3C-SiC films (up to 22 um thick) and high deposition rates (up to 30 um/h) were obtained. The optimized process was then applied to growth on 50 mm diameter Si(100) wafers. The grown 3C-SiC films were analyzed using a variety of characterization techniques. The thickness of the films was assessed through Fourier Transform infrared (FTIR) spectroscopy, and confirmed by cross-section scanning electron microscopy (SEM). The SEM cross-sections were also used to investigate the 3C-SiC/Si interface. The surface morphology of the films was inspected via Nomarsky interference optical microscopy, atomic force microscopy (AFM), and SEM. The crystalline quality of the films was determined through X-ray diffraction (XRD) and low-temperature photoluminescence (LTPL) analysis. A mercury probe was used to make non-contact CV/IV measurements and determine the film doping.
502
Thesis (M.S.E.E.)--University of South Florida, 2006.
504
Includes bibliographical references.
516
Text (Electronic thesis) in PDF format.
538
System requirements: World Wide Web browser and PDF reader.
Mode of access: World Wide Web.
500
Title from PDF of title page.
Document formatted into pages; contains 62 pages.
590
Adviser: Stephen E. Saddow, Ph.D.
653
Silicon carbide.
Heteroepitaxy.
SOI.
Crystal defects.
Chemical vapor deposition.
690
Dissertations, Academic
z USF
x Electrical Engineering
Masters.
773
t USF Electronic Theses and Dissertations.
4 856
u http://digital.lib.usf.edu/?e14.1823