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Low temperature hermetically sealed 3-D MEMS device for wireless optical communication

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Title:
Low temperature hermetically sealed 3-D MEMS device for wireless optical communication
Physical Description:
Book
Language:
English
Creator:
Agarwal, Rahul
Publisher:
University of South Florida
Place of Publication:
Tampa, Fla
Publication Date:

Subjects

Subjects / Keywords:
CCR
MOEMS
Packaging
Hermetic seal
DRIE
Micromachining
Dissertations, Academic -- Electrical Engineering -- Doctoral -- USF   ( lcsh )
Genre:
bibliography   ( marcgt )
theses   ( marcgt )
non-fiction   ( marcgt )

Notes

Abstract:
ABSTRACT: Novel processes were developed that resulted in a self-packaged device during the system integration, along with a transparent lid for inspection or optical probing. A new process was developed for improving the verticality in Micro Electro Mechanical Systems (MEMS) structures using Deep Reactive Ion Etching (DRIE). A self-pattered, mask-less photolithography technique was developed to metallize these vertical structures while maintaining a transparent window, for packaging of various MEMS devices. The verticality and metallization coverage were evaluated by incorporating the MEMS structures into an optical Corner Cube Retroreflector (CCR). A low temperature, hermetic sealing technique was also developed using In-Au thermo-compression bonding at 160°C.Cross-shaped 550um deep vertical mirrors, with sidewall angles of 90.08° were etched with this new DRIE technique. This is the best reported sidewall angle for such deep structures.^ The typical scalloped DRIE sidewall roughness was reduced to 40nm using wet polishing. A bonded Pyrex wafer was used as the handle wafer during DRIE; it eventually forms the package window after DRIE. The metallized, vertical mirrors were bonded to a MEMS device chip to assemble and package the CCR. The MEMS device chip consisted of an array of torsion mirrors. The mirrors were designed to modulate at 6Vp-p - 20Vp-p, with the resonant frequencies ranging from 25 KHz - 50 KHz. The design and simulation results are presented. To test the hermetic seal, helium leak tests were performed on the packaged device. Leak rates of as low as 2.8x10-8 atm cc/s air were detected, which is better than the MIL-STD-883G of 5x10-8 atm cc/s air for a package volume of 7.8x10-3 CC. A microprocessor and temperature/humidity sensor was then integrated with the CCR to assemble a passive optical digital data communicator.^ A flexible circuit design and a folded packaging scheme were utilized to minimize the overall form factor. Flat, flexible polymer batteries were incorporated to reduce the thickness of the package to a few millimeters. The fully packaged sensor system was about 30mmx30mmx6mm. Recorder sensor data was transmitted to a remote location using the CCR, and those results are presented.
Thesis:
Dissertation (Ph.D.)--University of South Florida, 2007.
Bibliography:
Includes bibliographical references.
System Details:
System requirements: World Wide Web browser and PDF reader.
System Details:
Mode of access: World Wide Web.
Statement of Responsibility:
by Rahul Agarwal.
General Note:
Title from PDF of title page.
General Note:
Document formatted into pages; contains 180 pages.
General Note:
Includes vita.

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University of South Florida Library
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University of South Florida
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All applicable rights reserved by the source institution and holding location.
Resource Identifier:
aleph - 001939472
oclc - 227810940
usfldc doi - E14-SFE0002181
usfldc handle - e14.2181
System ID:
SFS0026499:00001


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ABSTRACT: Novel processes were developed that resulted in a self-packaged device during the system integration, along with a transparent lid for inspection or optical probing. A new process was developed for improving the verticality in Micro Electro Mechanical Systems (MEMS) structures using Deep Reactive Ion Etching (DRIE). A self-pattered, mask-less photolithography technique was developed to metallize these vertical structures while maintaining a transparent window, for packaging of various MEMS devices. The verticality and metallization coverage were evaluated by incorporating the MEMS structures into an optical Corner Cube Retroreflector (CCR). A low temperature, hermetic sealing technique was also developed using In-Au thermo-compression bonding at 160¨C.Cross-shaped 550um deep vertical mirrors, with sidewall angles of 90.08¨ were etched with this new DRIE technique. This is the best reported sidewall angle for such deep structures.^ The typical scalloped DRIE sidewall roughness was reduced to 40nm using wet polishing. A bonded Pyrex wafer was used as the handle wafer during DRIE; it eventually forms the package window after DRIE. The metallized, vertical mirrors were bonded to a MEMS device chip to assemble and package the CCR. The MEMS device chip consisted of an array of torsion mirrors. The mirrors were designed to modulate at 6Vp-p 20Vp-p, with the resonant frequencies ranging from 25 KHz 50 KHz. The design and simulation results are presented. To test the hermetic seal, helium leak tests were performed on the packaged device. Leak rates of as low as 2.8x10-8 atm cc/s air were detected, which is better than the MIL-STD-883G of 5x10-8 atm cc/s air for a package volume of 7.8x10-3 CC. A microprocessor and temperature/humidity sensor was then integrated with the CCR to assemble a passive optical digital data communicator.^ A flexible circuit design and a folded packaging scheme were utilized to minimize the overall form factor. Flat, flexible polymer batteries were incorporated to reduce the thickness of the package to a few millimeters. The fully packaged sensor system was about 30mmx30mmx6mm. Recorder sensor data was transmitted to a remote location using the CCR, and those results are presented.
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Low Temperature Hermetically Sealed 3-D MEMS Device for Wireless Optical Communication by Rahul Agarwal A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engineering College of Engineering University of South Florida Co-Major Professor: Sh ekhar Bhansali, Ph.D. Co-Major Professor: Scott Samson, Ph.D. Ashok Kumar, Ph.D. Jing Wang, Ph.D. Thomas Weller, Ph.D. Date of Approval: June 1, 2007 Keywords: CCR, MOEMS, packaging, hermetic seal, DRIE, micromachining Copyright 2007, Rahul Agarwal

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ACKNOWLEDGEMENTS I would like to thank Dr. S. Bhansali a nd Dr. S. Samson, my co-major professors, for their encouragement, guidance and support throughout my Ph.D. program. Additionally I would like to ex tend my thanks to the whole staff of COTSTAR Center, now known as SRI-St. Pete. Special thanks to S. Kedia for preparing MEMS mirrors, Dr. W. Wang for his help and di scussions for bonding/packaging, D. Edwards for SEM help, B. Rossie for FIB help and Dr. J. Bumgarner for useful discussions and ideas. I would also like to thank B. Flanery, B. Brantley and G. Gonzales for their help in putting together the receiver for PODC and R. Hazen and G. Gonzales for their help in developing the drive electronics and plastic packaging for the PODC. I would also like to thank my family back in India for their support and encouragement during my research, and how can I not thank my lovely wife Shruti Agarwal, and my cute daughter Aaliya Agarwa l, for their love, aff ection and sacrifices during the course of my resear ch. Without them it wouldn't ha ve been possible for me to complete this work and this manuscript. Last but not the least, I w ould like to thank all my friends and colleagues in USF and back in India.

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NOTE TO READER The original of this document contains color that is necessary for understanding the data The original dissertation is on file with the USF library in Tampa, Florida.

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i TABLE OF CONTENTS LIST OF TABLES...............................................................................................................v LIST OF FIGURES..........................................................................................................vii ABSTRACT....................................................................................................................... xv 1 INTRODUCTION............................................................................................................1 1.1 Research Focus in This Dissertation..................................................................4 1.2 Fabrication and Assembly..................................................................................9 1.2.1 DRIE and KOH:IPA Polishing Method..............................................9 1.2.2 KOH Etching on (110) Si Wafer......................................................10 1.3 Contributions and Layout of Dissertation........................................................11 2 CORNER CUBE RETROREFLECTORS.....................................................................14 2.1 Retroreflectors..................................................................................................16 2.2 Modulation Schemes for Retroreflectors.........................................................17 2.3 Free Space Optical Communication................................................................20 2.4 MEMS CCR and Principle of Operation.........................................................22 3 DEEP REACTIVE ION ETCHING (DRIE)..................................................................25 3.1 Introduction......................................................................................................25 3.2 Problems With DRIE.......................................................................................27

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ii 3.3 Techniques for Reducing Loading Effect in DRIE..........................................28 3.4 Techniques for Reducing Roughness on Etched Surface................................30 4 WET ANISOTROPIC ETCHING..................................................................................33 4.1 Isotropic Etching..............................................................................................33 4.2 Anisotropic Etching.........................................................................................34 4.3 Etching Vertical Structur es in (110) Si Wafer.................................................37 5 FABRICATION OF VERTICAL MIRRORS................................................................42 5.1 Dry Etching......................................................................................................42 5.1.1 Process Flow.....................................................................................42 5.1.2 DRIE Results and Discussion...........................................................44 5.2 Reducing Sidewall Roughness: Ma sking Layer Optimization........................49 6 IMPROVING SURFACE QUALITY AND ORTHOGONALITY...............................54 6.1 Improving the Orthogonality of the Mirrors....................................................59 6.2 Improving the Surface Quality by Wet Polishing............................................61 7 METALLIZATION OF VERTICAL MIRRORS WITH TRANSPARENT PACKAGE WINDOW..........................................................................................66 7.1 Liftoff Using Self-Masking Technique............................................................68 7.2 Improving the Metal Coverage........................................................................70 8 SURFACE MICROMACHINING: MEMS TORSION MIRRORS..............................73 8.1 Surface Micromachining..................................................................................73 8.2 Nitride MEMS.................................................................................................74

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iii 8.3 Fabrication.......................................................................................................75 8.4 Modeling and Simulation Using Fi nite Element Analysis (FEA)...................81 9 PACKAGING AND ASSEMBLY.................................................................................85 9.1 MEMS Packaging Techniques: Prior Art........................................................87 9.1.1 Integrated Encapsulation...................................................................87 9.1.2 Wafer Bonding..................................................................................87 9.1.2.1 Bonding Without Intermediate Layers...............................88 9.1.2.1.1 Anodic Bonding..................................................88 9.1.2.1.2 Fusion Bonding...................................................90 9.1.2.2 Intermediate Layer Bonding..............................................90 9.1.2.2.1 Eutectic Bonding.................................................91 9.1.2.2.2 Adhesive Bonding...............................................92 9.1.2.2.3 Glass Frit Bonding..............................................92 9.2 Assembly of CCR............................................................................................93 9.2.1 Au-Au Thermo-Compression Bonding.............................................93 9.2.2 CCR Assembly Using Au-Au Bonding............................................93 9.3 Hermetic Sealing Techniques..........................................................................95 9.3.1 Low Temperature Hermetic Sealing Methods..................................97 9.3.1.1 Laser Welding....................................................................97 9.3.1.2 Micro Heaters.....................................................................98 9.3.1.3 Nanostructure Foils............................................................98 10 HERMETIC PACKAGING WITH LATERAL FEED-THROUGHS.......................101 10.1 Low Temperature Hermetic Bonding Using In-Au.....................................102

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iv 10.2 Principle of In-Au Bonding.........................................................................105 10.3 Bonding Procedure and Results...................................................................106 11 TESTING OF THE CCR............................................................................................112 11.1 Microsensor System.....................................................................................112 11.2 Transceiver...................................................................................................116 11.3 Sensor Data Using LabVIEW......................................................................118 11.4 Test Setup and Results.................................................................................122 12 RESULTS AND DISCUSSIONS...............................................................................129 12.1 Two Step DRIE and Sidewall Improvement...............................................129 12.2 Low Temperature Hermetic Packaging Scheme..........................................131 12.3 Surface Micromachining and Testing..........................................................132 12.4 Investigation for Improving the Range........................................................133 12.4.1 Future Work: Medium Range Passive Optical Digital Communicator (MRPODC).....................................................................134 12.4.1.1 Silicon-On-Insulator (SOI)............................................141 12.5 Conclusions..................................................................................................144 REFERENCES................................................................................................................145 APPENDICES.................................................................................................................160 Appendix A: Process Recipes..............................................................................161 Appendix B: Power and Range Calculations.......................................................175 ABOUT THE AUTHOR.......................................................................................End Page

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v LIST OF TABLES Table 1: Various Parameters Used For the St andard Bosch Cycles in This Work. 45 Table 2: Comparison of Sidewall Angles Across the Wafer With Different DRIE Recipes. 49 Table 3: Comparison of Various Bonding Techniques. 100 Table 4: Hermetic Sealing Results From Samples Bonded at Different Temperatures and Different Times. 111 Table 5: Comparing the Raw and Physical Sensor Data at Various Levels of Testing. 128 Table 6: Parameters and Process Flow For Anodic Bonding. 162 Table 7: Various Oxygen Plasma Recipes Which Were Used. 163 Table 8: PECVD Recipe for SiO2 Deposition. 164 Table 9: LPCVD Recipe for Si3N4 Deposition. 164 Table 10: RIE Etch Recipe for Si3N4. 165 Table 11: List of Tools, Their Manufacturer and Model Numbers. 174 Table 12: Table Showing the Area of the Input Traces and Bond Pads. 177

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vi Table 13: Calculating the Distance Be tween the Reflected Beams With the Deviation of the Orthogonal Mirrors From the Dihedral Angle. 179

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vii LIST OF FIGURES Figure 1: Shows Different Chips Which We re Bonded Together to Assemble the CCR. 8 Figure 2: Fabrication Steps for Different CCRs. 9 Figure 3: Schematic of a CCR Used in a Communication Link [27]. 19 Figure 4: Simple Layout of a Retror eflective Communication System. 21 Figure 5: Relation Between Power Losses With Increase in Incident Angle at Various Refractive Indexes. 22 Figure 6: Profile of DRIE Trench Using Bosch Process [41]. 26 Figure 7: DRIE Etch Profiles (a) Ideal, (b) Typical. 27 Figure 8: Examples of Micro-load ing Effect and RIE Etch Condition Incompatibility. 28 Figure 9: Cross Sectional Overview of Tr enches Etched Using Different Kind of Etching Methods. 35 Figure 10: Etching Mechanis m of Beam Structure in (110) Si [9]. 38

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viii Figure 11: SEM Image Illustrating the C onvex Corner Undercutting Problem in (110) Si. 39 Figure 12: Simulation Results of KOH Etchi ng on (110) Si Wafer, When a Mask in the Shape of Cross-Hair was Used. 40 Figure 13: KOH Etching Performed on Stru ctures With Gap in the Center to Facilitate Bonding of Second Set of Mirrors to Assemble Cross-Shape Structures. 41 Figure 14: Cross Sectional View of the DR IE Etch Process to Fabricate Vertical Mirrors. 45 Figure 15: Cross Sectional SEM Image of the Uniform Width Narrow Channels Etched in Si Using Modified DRIE Process (23mTorr Pressure). 48 Figure 16: Shows the SEM Images of Cro ss-Hair Structures, Which Were Etched in Si Using the Described Two Step DRIE Process 50 Figure 17: SEM Images of Various Vertical Structures Etched on the Same Wafer Along With the Cross-Hair Shown in Figure 7. 51 Figure 18: Optical Profilometer Scan of the Vertical Mirrors After DRIE, Ra = 217.62nm. 52 Figure 19: Optical Profilometer Scan of the Vertical Mirrors After DRIE With Improved Lithography Steps, Ra = 122.62nm. 53

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ix Figure 20: Scattering Loss Vs. RMS Roughne ss at Various Incident Angles for He-Ne Laser. 55 Figure 21: KOH:IPA Polishing Was Used to Improve the Sidewall Roughness and Angle. 56 Figure 22: Cross Sectional View of the DR IE Etch Process to Fabricate Vertical Mirrors. 57 Figure 23: Mask Layout Used to Fabricat e Vertical Mirrors in the Shape of a Cross-Hair. 60 Figure 24: Optical Profilometer Scan of the Vertical Surface After O2 Plasma Etching, Which Removes the Polymer From the Sidewall Surface. 64 Figure 25: Optical Profilometer Scan of the Vertical Mirror After O2 Plasma and Isotropic Etching in KOH:IPA Solution For One Hour, Ra = 38.97nm. 65 Figure 26: Sidewall Angles After Tw o Step DRIE and One Hour KOH:IPA Polishing. 65 Figure 27: Process For the Self-M asking Liftoff Process. 67 Figure 28: Cross Sectional View of the Self-Masking Liftoff Process. 68 Figure 29: Metal Coverage on the Vertical Mirrors After Spu ttering and Liftoff Using Standard Lithography. 70

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x Figure 30: Metal Coverage on the Vertical Mirrors With Transparent Package Lid Using NR9-1000PY Photoresist, Sp in Speed – 3000 rpm, Exposure Dose – 360mJ/cm2, Developing Time – 3 minutes. 72 Figure 31: Metal Coverage on the Vertical Mirrors With Transparent Package Lid Using NR9-1000PY Photoresist, Spin Speed – 3000 rpm, Exposure Dose – 360mJ/cm2, Developing Time – 3 minutes. 72 Figure 32: Mask Layers as Applied to Th in Films for NitrideMEMS Process. 75 Figure 33: Solid Model of the NMEMS Fabric ation Steps for Torsion Mirrors. 76 Figure 34: Optical Image of the Active ME MS Device Chip With Torsion Mirrors Shown in the Inset. 79 Figure 35: Optical Profilometer Scan of a Single Torsion Mirror to Measure the Mirror Curvature After Release. 80 Figure 36: 2-D Analysis of NMEMS To rsion Mirrors Using Veeco Optical Profilometer. 80 Figure 37: Finite Element Analysis (FEA) of Torsion Mirror. 81 Figure 38: Changes in Pull-In Voltage a nd Resonant Frequency of the Torsion Mirrors With Changes in Spring Thickness. 83 Figure 39: Changes in Pull-In Voltage a nd Resonant Frequency of the Torsion Mirrors With Changes in Center Width. 83

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xi Figure 40: Frequency Response of the Mirror s for 50V Polarization Voltage. 84 Figure 41: Flow Chart Showing Vari ous Bonding Techniques Which Can Be Used for MEMS Packaging. 88 Figure 42: (a) Anodic Bonding Setup, (b ) Formation of Oxygen Bonds. 89 Figure 43: Binary Phase Diagram of Au-Si Alloy. 91 Figure 44: Setup for the Wafer to Wafer Eutectic Bonding. 92 Figure 45: Optical Image, Taken Through the Pyrex Package Lid, Consisting of Nitride MEMS Active Torsion Mirrors and Passive Vertical Mirrors. 95 Figure 46: MEMS Packaging Scheme Usi ng an Integrated Encapsulating Micro Shell. 97 Figure 47: Experimental Setup of Gl ass-Silicon Bonding Using Indium as Intermediate Layer. Laser is Used to Locally Heat the In. 98 Figure 48: Schematic View of Packaging Usi ng Nanofoils for Localized Heating. 99 Figure 49: SEM Image of a Test Sample Bonded to the NMEMS Device Chip. 103 Figure 50: Optical Image of the Bond Interface. 103 Figure 51: In-Au Phase Diagram. 106 Figure 52: SEM Image of the MEMS Chip With Torsion Mirrors and On Chip Lateral Feed-Throughs. 108

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xii Figure 53: Solid Model of the Vertical Mirror Chip With Metallized Vertical Mirrors and Package Frame. 108 Figure 54: Schematic View of the Au-In Bonding Using Flip-Chip Bonder. 109 Figure 55: Bonding Interface at the Metal Feed-Throughs. 110 Figure 56: System Level Block Diag ram for Passive Optical Digital Communication. 112 Figure 57: Form Factor of the Packaged CCR 7.2mm7.2mm1.5mm. 114 Figure 58: Fully Integrated PODC Microsensor Unit. 115 Figure 59: Block Diagram of the Transceiver Unit. 116 Figure 60: Mechanical Drawi ng for the CCR Transceiver. 117 Figure 61: Optical Image of the Actual Transceiver. 118 Figure 62: LabVIEW Block Diagram for RS232 Interface. 119 Figure 63: LabVIEW Front Panel Show ing the Temperature and Humidity Reading. 120 Figure 64: The Packaged CCR Was Tested by Modulating the Torsion Mirrors With an Amplitude Modulated Signal. 123 Figure 65: The Test Setup For Reading the Sensor Data With the Use of a CCR is Shown. 124

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xiii Figure 66: The Oscilloscope Data Shows th e Digital Output From the CCR Unit. 125 Figure 67: The ASCII Character H Was Manually Generated Using HyperTerminal to Compare With the Transmitted Data. 126 Figure 68: Sensor Data as Tran smitted From the PODC Unit. 127 Figure 69: Digital Data Received by the Receiver. 128 Figure 70: Solid Model of the Process De scribing the Assembly of CCR by Using Vertical Mirrors Etchin g on (110) Si Wafer. 136 Figure 71: Optical Image of the Assembled Device. 139 Figure 72: Surface Deformation After Laser Micromachining. 139 Figure 73: AFM Scan on the KOH Etched Mirror. 140 Figure 74: Veeco Optical Profilometer Scan of KOH Etched (110) Silicon Wafer. 141 Figure 75: Optical Scan of the Released SOI Chip. 143 Figure 76: Optical Scan of the Released SO I Chip Showing the Mirror Curvature. 143 Figure 77: Waveform S howing the Signal Used to Modulate the NMEMS Mirrors. 176 Figure 78: Calculating the Distance Be tween the Reflected Beams With the Deviation of the Orthogonal Mirrors From the Dihedral Angle. 178

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xiv Figure 79: Graph Showing the Change in Distance Between the Reflected Light With Deviation From Dihedral Angle. 180

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xv LOW TEMPERATURE HERMETICALLY SEALED 3-D MEMS FOR WIRELESS OPTICAL COMMUNICATION by Rahul Agarwal ABSTRACT Novel processes were devel oped that resulted in a self -packaged device during the system integration, along with a transparent lid for inspection or optical probing. A new process was developed for improving the ve rticality in Micro Electro Mechanical Systems (MEMS) structures using Deep Reac tive Ion Etching (DRIE). A self-pattered, mask-less photolithography technique was de veloped to metallize these vertical structures while maintaining a transparen t window, for packaging of various MEMS devices. The verticality and metallization coverage were evaluated by incorporating the MEMS structures into an optic al Corner Cube Retroreflect or (CCR). A low temperature, hermetic sealing technique was also devel oped using In-Au thermo-compression bonding at 160C. Cross-shaped 550 m deep vertical mirrors, with sidewall angles of 90.08 were etched with this new DRIE technique. This is the best reported sidewall angle for such deep structures. The typical scalloped DR IE sidewall roughness was reduced to 40nm using wet polishing. A bonded Pyrex wafer was us ed as the handle wafer during DRIE; it eventually forms the package window after DRIE.

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xvi The metallized, vertical mirrors were bonded to a MEMS device chip to assemble and package the CCR. The MEMS device chip c onsisted of an array of torsion mirrors. The mirrors were designed to modulate at 6Vp-p 20Vp-p, with the resonant frequencies ranging from 25 KHz 50 KHz. The design and simulation results are presented. To test the hermetic seal, helium leak tests were perf ormed on the packaged device. Leak rates of as low as 2.8x10-8 atm cc/s air were detected, which is better than the MIL-STD-883G of 5x10-8 atm cc/s air for a package volume of 7.8x10-3 CC. A microprocessor and temperature/humidity sensor was then integrated with the CCR to assemble a passive optical digital da ta communicator. A flex ible circuit design and a folded packaging scheme were utilized to minimize the overall form factor. Flat, flexible polymer batteries were incorporated to reduce the thickness of the package to a few millimeters. The fully packaged se nsor system was about 30mm30mm6mm. Recorder sensor data was transmitted to a remote location us ing the CCR, and those results are presented.

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1 1 INTRODUCTION There are various ways to fabricate/ assemble 3-D structures using MEMS techniques. Structures can be etched in the bul k of Si substrate or built on a Si substrate by bulk micromachining and surface micromachini ng respectively. The inherent nature of bulk micromachining leads to 3-D structures in the bulk of Si [1]; whereas surface micromachined parts can be rotated [2] or popped up [3] to assemble 3-D structures. Surface micromachined structures usually su ffer from surface curvature due to film stresses, and hence are not the ideal way to fabricate long vert ical structures. An example of a 3-D structure is a vertical mirror. Vertical etching is a necessary component in various applications including the fabrication of through wafer vias [4]. Vertical etching is also used in the fabricat ion of variety of devices, such as external cavity lasers, filters, resonators, capacitive acce lerometers, optical cross connects, optical CCR communicators etc. Various processes such as anis otropic wet etching, LIGA [Lithography, Electroforming (German: Ga lvanoformung), and molding (German: Abformung)] process or DRIE can be used to fabricate vertical structures. While the DRIE plasma etching results in rough sidewalls and tapered profile, crystal orientation limits the use of wet etching to fabricate vertical mirrors in various shapes. Vertical structures with atomically smooth surfaces [5, 6, 7] can be etched by wet anisotropic etching of Si on (110) wafer with the mask aligned to the (111) crystal plane.

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2 Various devices like accelerometer [8], beam splitters [5], and comb structures [9] have been realized using vertical st ructures etched in (110) Si wafer. However, the shape of structures which can be realized using wet an isotropic etching is hi ghly restricted by the crystallography of the silicon wafer. For example, while it is possible to wet etch straight vertical mirrors on a (110) Si, structures in the shape of cross are not possible to be etched on a (110) Si as the (111) planes intersect at an angle to the (110) plane. LIGA process [10] can be used to fabricate verti cal metallic or polymer microstructures or molds. However these require expensive X -ray exposure which is not common in most facilities. DRIE techniques can allow etching of extremely complex geometries, but has loading dependent etch charac teristics, and rougher sidewa lls. Fabricating long vertical mirrors is a challenge MEMS industry ha s always faced. Exte nsive and expensive characterization of etch tools are required to characterize the process for a given feature size. Hence there was a need to develop a process which can be used to etch different features with vertical sidewalls on the same wa fer, with little characterization or changes in the etch recipe. The various factors affecting the DRIE process in SF6 + C4F8 chemistry includes pressure, gas flow rates, RF power, distri butions of fluorine ra dicals, ions, waste products, etc. In SF6 plasma, active fluorine atoms are released from the plasma and react with the Si surface to form a volatile fl uoride species. The fluorine atoms reach the surface from all directions. But as the etch depth increases, it limits the transport of fluoride atoms reaching the Si surface which results in reduction in etch rates and increased roughness. The geometry of the patter n to be etched also has a major influence

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3 on the etch depth, profile and other process characteristics. These effects include aspect ratio dependent etching and th e micro-loading effect where large open areas have a high reactant consumption rate. This leads to reac tant deficits since th e transport of etching species across the wafer is limited by diffusi on process as described earlier. With the increase in density of open areas, the micr o-loading effects increases resulting in decreased etch rates along with changes in et ch profiles. The DRIE process also leaves scallops on the morphology of the etched stru ctures because of th e process sequence of etch and passivation cycles. To use these et ched surfaces as mirrors, the roughness has to be reduced. The packaging of MEMS devices is one of the most difficult and cost sensitive process in product development due to its many requirements [11]. MEMS packaging techniques are borrowed from IC industry, bu t the functionality of MEMS devices differ a lot from the IC devices. MEMS packagi ng presents various challenges which were never faced by the IC packagi ng industry due to the diversity of MEMS devices and the requirement that many of MEMS devices are in continuous and/or intimate contact with their environment. Even though application spec ific packaging is not an efficient method of sealing MEMS based products, a new and sp ecialized package is designed nearly for each new MEMS device. Consequently, most manufacturers find that packaging is the single most expensive and time consuming task in a MEMS product development program, and is also often the first to influence the system response. To package an optical MEMS sensor, a transparent window and electrical connections to the outside world need to be integrated into the design. Processes, which

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4 can create a package and simultaneously assist in the fabrication of the needed optical surfaces, will be beneficial to ward meeting the growing need for low cost packaging solutions. Past works have presented various methods and approaches to package an optical device with integrated window for optical access [12, 13]; however these techniques requires extra complex processe s to package 3-D optical structures. In many devices hermetic sealing is required, allowing only a negligible amount of gas to be exchanged between the passages in the MEMS body and the atmosphere during the life of the MEMS, in order to prev ent the device from becoming contaminated. Moisture can be readily absorbed by some materials (for example Al) used in MEMS device fabrication. This can cause failure of MEMS devi ces due to stiction, swelling, stress, and possibly delamination at vari ous stages. To minimize these failure mechanisms, MEMS packages needs to be hermetically sealed. Also low temperature packaging is desired as high temperature ca n cause thermal stress/mismatch problems. Developing a low temperature packaging scheme, which can be used to hermetically package various devices at die and/or wafer level, will be beneficial for the development of the MEMS industry. 1.1 Research Focus in This Dissertation In this dissertation DRIE along with KOH:IPA isotropic polishing on (100) Si wafer will be discussed to fabricate vertical mirrors and package frame for assembling and packaging MEMS devices. A novel self -masking photolithography method will also be presented to selectively metallize long ve rtical structures and leave transparent package window. This transparent window is required for optical MEMS devices for

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5 optical probing and can be used for device inspection in non optic al MEMS devices. A versatile, CMOS compatible low temperat ure hermetic bonding technique (temperature as low as 160C) will also be presented which can be used to hermetically seal various temperature sensitive MEMS devices. The re sults will be presen ted using CCR as an example, but the processes are also app licable for many other MEMS devices. Novel DRIE technique was developed whic h reduces the loading effect in Bosch process and results in vertical sidewalls for MEMS structures. The anodically bonded Pyrex which was used as the handle wafer duri ng DRIE was later used as the package lid for zero level packaging of MEMS devices. This work focuses on developing packaging techniques for MEMS devices which are asse mbled by bonding bulk etched wafer/chip to surface micromachined wafer/chip. The packag ing on such devices was achieved during assembly and no separate lid or packaging schemes were n ecessary. Hence the processing steps are reduced and more importantly the most difficult and expensive issue of MEMS packaging was addressed during the assembly of the device rather than addressing it after the device has been assembled. Bonding at 1 60C was used to hermetically seal the package during assembly, which reduces th e thermal stresses the device go through during high temperature hermetic sealing tec hniques. Lateral feed-t hroughs through the package lid were used to electrically comm unicate with the packaged MEMS mirrors. In total twelve electrodes were us ed to modulate the mirrors in four different quadrants. The validation of the fabrication and packaging technique was performed by assembling and packaging a MEMS modula ting CCR. A CCR consists of an active mirror surface and two orthogonal static mirrors. Optical ra y tracing analysis shows that

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6 an incident optical ray which is reflected by three mirrors, exits in the direction of the incident ray. By moving or dist orting the active mirror, the re turned ray is directed away from the incident ray. Moving the mirror in synchrony with information from a sensor, for example a temperature and humidity sens or, one can impart this information onto a probing laser beam using very little power; thus, the sensi ng signal can be transmitted back into central stati on to realize remote fr ee space communications. A CCR is a 3-D structure, which requires three orthogonal mirrors. In this work the CCRs were fabricated by mating MEMS act ive device chip to th e static vertical mirror chip. The static vertical mirror chip also consists of a package frame and Pyrex package lid for packaging the devices. The ME MS device chip and the vertical mirror chip with package frame were bonded toge ther using thermo-compression bonding, which results in hermetic packaging of the device. The packaged devices can then be placed in a leadless chip carrier (LCC) package or in a dual inline package (DIP). In this work the packaged CCRs were directly bonded to a flexi board for electrical actuation and optical testing. Folded assembly for th e flexi board was used to reduce the form factor of the final device. A single structural layer surface micr omachining process for creating MEMS actuators and sensors is disc ussed. A base metal layer allo ws electrical routing. The structural layer is made of a stack of metal, dielectric, an d metal to allow electrostatic actuation of parts, stiffness, and high optical reflectivity. The lower structural metal is patternable to allow isolated patterns for el ectrical switching appli cations. All structural layers are self-aligned.

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7 Figure 1(a) shows the solid model of the vertical mirrors a nd the package frame which will be used to assemble and pack age the CCR. Figure 1(b) shows the SEM image of the MEMS chip on which the chip in Figure 1(a) will be flip-chi p bonded to assemble the CCR. The mirrors in the cross shape will form the two static mirrors of the CCR and the MEMS mirrors will form the thir d mirror (modulating) of the CCR. Different data rates were required for di fferent applications depending on the kind of receiver which can be used to detect the signal. Hence di fferent CCRs were fabricated with the max data rate of 9600bps to as lo w as 2400bps. Instead of using full aperture tilting mirrors which limited the resonant freq uency of the mirrors [35], small torsion mirrors (100 m x 100 m) with low stress silicon nitride as the structural layer were used, with resonant frequency of approximately 25 KHz 50 KHz. 6Vp-p – 20Vp-p were used to modulate the MEMS mirrors depending on the design of the MEMS mirrors. 2.63pF capacitance was measured per CCR quadrant (8 0 mirrors per quadran t), which leads to low power consumption to 95 W (10nJ/bit at a data rate of 9600bps), see Appendix B. Test data at 9600bps was transmitted and the CCR was tested for optical communication at 10-20 meters. Also temp erature and humidity sensor data was transmitted at 2400bps to a distance of 1020 meters and the received data was transferred using RS232 to a computer. A La bVIEW program was developed to convert this digital data to the physical temperature and humidity values and display that data on the computer.

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8 (a) (b) Figure 1: Shows Different Chips Which Were Bonded Together to Assemble the CCR. (a) Shows the Solid Model of the Two Static Mirrors of the CCR Which Were Fabricated Using DRIE and KOH:IPA Polishing. (b) SE M Image of the MEMS Mirror Chip.

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9 Figure 2: Fabrication Steps for Different CCRs. 1.2 Fabrication and Assembly Different methods to fabric ate vertical mirrors and ME MS torsion mirrors were investigated. Most of the work in this dissert ation concentrates on et ching vertical mirrors using DRIE and using Si3N4 as the structural layer for the MEMS torsion mirrors. Other methods like etching vertical mirrors in ( 110) Si and using SOI wafer for making MEMS mirrors were also investigated and will be discussed as the future work. The different steps are shown as a fabri cation tree in Figure 2. 1.2.1 DRIE and KOH:IPA Polishing Method In this method two different wafers were pr ocessed, one to fabric ate vertical static mirrors along with package frame and packag e lid and the second to fabricate the MEMS torsion mirrors. The processed wafers were bonded together to fa bricate the packaged

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10 CCR. This is a very versatile method and ca n be used to enable packaging of various MEMS devices with optical and electrical feed-thr oughs. Vertical mirrors were fabricated using DRIE and followed by KOH:IPA polishing, which will be discu ssed in detail in Chapter 5 and Chapter 6. Further, the issue of selective metallization of vertical structures will be addressed in Chapter 7. The etch process circumvents the need for performing difficult photolithography, uses simple DRIE techniques, and includes only one long etch to cr eate highly vertical structures. Additionally, the op tical window is not subjected to potentially damaging etch chemistries. A single structural layer su rface micromachining process was used for fabricating MEMS torsion mirrors. A base metal layer allows electrical routing. The structural layer was made of a stack of metal, dielectric, and metal to allow electrostatic actuation of parts, stiffness, and high opt ical reflectivity. A package frame bonding area was also designed on this wafer with Au as the top metal. The metal traces, for connection to the outside world runs beneat h this package frame area and are isolated from each other by Si3N4. This will be discussed in de tail in Chapter 8. The CCRs were then assembled by bonding the vertical mirror ch ip to the base Si chip which contains active MEMS mirrors for modulati ng the incident laser beam. 1.2.2 KOH Etching on (110) Si Wafer The KOH:IPA polishing on the DRIE surfaces reduces the sidewall roughness but it doesn't polish it to an atomically smooth surface. Hence the mirrors fabricated by DRIE and KOH:IPA polishing method suffers from scat tering losses, which in turn limits the range of the CCR. To overcome this limita tion a new method was developed using KOH

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11 etching on (110) Si wafer. This method gi ves atomically smooth sidewalls, however it suffer from structure dependent etching char acteristic of wet an isotropic etching. To circumvent these problems three different ch ips, first with active MEMS devices, second with single straight vertical mirror with a gap in the center and third with another vertical mirror with package frame were used to as semble the CCR. Laser liftoff was developed to facilitate three chip bonding and will be discussed in Chapter 12. SOI wafer was used to fabricate the MEMS active mirrors. This reduces the mirror curvature as the single crystal silicon layer was used as the active structure. This will also be discussed in Chapter 8. 1.3 Contributions and Layout of Dissertation Various different CCR designs have been proposed where MEMS technique was used to modulate one of the mirrors of th e CCR. No packaging techniques have been developed for such CCRs. The CCRs results pres ented also suffer from slow data rates of upto 300bps, high Q and lengthy ring down time, and mirror alignments of 0.18 were reported. This work focuses on improving these factors. Higher data rates were used to transmit data from sensor to the receiver. The MEMS mirrors developed have low Q of ~3 and hence can be used at various opera ting frequencies. The mirror alignment was also improved to 0.08. The important fact ors for improving the quality of a CCR are mirror alignment, mirror curvature, mirror r oughness, size of the modulator and size of static mirrors and the accepta nce angle of the CCR. In this dissertation attempts were made to improve the CCR quality by impr oving the alignments of the CCR mirrors, reducing the mirror curvature and static mi rror roughness. Larger size modulators and

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12 large vertical mirrors were used and a pack aging scheme was developed to increase the life time of the device. Various novel and versatile fabrication a nd packaging techniques to assemble the CCR were developed. DRIE and wet anisotr opic etching techniques were used to fabricate vertical mirrors. DRIE was performed to first etch 550 m deep structures in Si while maintaining uniform etch profile. Wet anisotropic etching was then used to improve the verticality of the etched struct ures and to reduce the roughness. The process also resulted in an integrated package window [14]. Extremely vertical and deep structures with various fill factors and uniform etch rate and etch profile were etched across the Si wafer. Self-patterning liftoff wa s performed to get metal coated vertical mirrors with along with the integrated tran sparent package lid [ 15] for assembling, packaging and testing of MEMS devices. Thes e bonded Si vertical mirrors and the glass window form the package lid devices which were then subseque ntly bonded to active torsion mirrors to fabricate 3-D MOEM S device called CCR [16]. Low temperature hermetic seal technique was also developed and will be presented. MEMS torsion mirrors were designed, modeled and fabr icated using low stress Si3N4 as the structural layer. Thermal cy cling on the final packaged device was successfully performed to a temperature of 320 C to room temperature. The package also passed the MIL-STD-883G for the given pack age volume. The MEMS torsion mirrors were also modulated successfu lly for around 8 billion cycles. Another method with atomically smooth side wall to fabricate ve rtical mirrors will also be discussed which can be potentially us ed to improve the range of the CCR. Laser

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13 liftoff technique was developed to facilita te multiple stack bonding of chips with free standing structures. This dissertation will start with the introducti on and literature review about CCRs in Chapter 2. Since dry and wet etch processing are important parts of this research to fabricate vertical structures, a literature re view will be summarized for dry etching in Chapter 3, followed by the literature review for wet processing in Chapter 4. Further the dissertation is divided into di fferent chapters which talk ab out different processes which were used to finally assemble the devices. In Chapter 5 the DRIE results obtained by the modified process which was used to etch vertical structures will be presented and in Chapter 6 the polishing results on these etched surfaces will be discussed. In Chapter 7 the issue of metallization of vertical mirro rs with transparent package lid will be addressed. In Chapter 8 various aspects of the surface micromachining technique will be discussed. Surface micromachining was used to fabricate torsion mirrors using Si3N4 as structural layer on Si wafer. Further SOI wafe rs were also used to fabricate cantilevers. This gives very flat surfaces and will also be discussed in Chapter 8. Introduction to various bonding techniques and processes for packaging MEMS devices will be discussed in Chapter 9. Various hermetic sealing techniques and low temperature hermetic sealing technique which was developed will be discussed in Chapter 10. Testing results of the CCR will be presented in Chap ter 11. Chapter 12 concludes this dissertation with results and discussions.

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14 2 CORNER CUBE RETROREFLECTORS In the modern era, radio and optical wireless communication are getting more attention as they provide increased mobility and access to information where a wired network cannot exist. Several options, such as radio frequencies (RF) and optical links, are available which can act as wireless communication systems. The choice between radio link and the optical link depends mainly on the application they are to be used on. RF method usually requires low power transmitter, complex modulation/demodulation circuitry and a relatively large antenna. In recent times opti cal communication is getting more attention as more and more electro-ma gnetic frequency spectra have been governed by Federal Communicati ons Commission (FCC). As the communication systems in the cla ndestine locations, as in battlefields, become more reliant on sensor networks to provide up-to-date information, there emerges a need for low power, compact, and steal thy communication capability between the probing station and the sensor locations. The co mmunication systems need to be such that they can prevent or minimize any possible interception of the location/communication signal by the opposition. Such communication syst em is necessary for applications that include identify-friend-or-f oe interrogation, air-to -ground links, and unmanned autonomous vehicle monitoring. Standard tec hniques such as use of radio or optical transmitter generate cones of energy that in some cases could compromise the

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15 clandestine locations. With the increased use of powerful and miniature mobile communication devices the limitations on the we ight and power required to transmit data is getting more and more stringent. An attr active system to circumvent many of these challenges is one that makes use of sensors with modulating retroreflectors, such as a CCR as first described by Stockman in 1948 [ 17]. The interrogating transmitter can use a low power laser and a low power CCR is used to transmit the digital signal to the detector. It is a passive communicati on scheme which doesn’t require any beam generating capacity at the sensor end. Using such a scheme the source, the receiver and the larger power supply can be located at a single location. The pr obing beam from the transmitter/detector location would illuminate the sensor location; the modulating retroreflectors at the sensor locations can modulate the probing signal using the sensor data and reflect it back to the detector. The sensor receiver would involve a photodiode and some digital circuitry, thus using less pow er than the equivalent RF receiver [18]. Such a system can provide line-of-sight comm unication for sensors having limited energy capability and/or limited size. The free space optical (FSO) communication only requires a clear line-of-sight path (non-line of sight optical communica tion is also possible [18]) between the transmitter and receiver to form a communication link. No buried cables, switch networks or complex amplifiers are needed in FSO communication, unlike radio or fiber optics communication network, without compromising the bandwidth of the network. The major limitations in FSO communication systems are: weather changes, clea r line-of-sight path and noise induced by sunli ght on the receiver end.

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16 2.1 Retroreflectors A retroreflector [17] is a de vice which reflects the light back to its source, just like a plane mirrors reflects the light back to its source when the light is incident normal to the mirror. The advantage of using a retroreflector over a plane mirror is that the reflection is independent of the angle of incidence (to some extend). CCRs have a wide range of applications ranging from street signs and road markings to wireless optical communications. Amongst other applications pa ssive CCRs have been used as targets for displacement sensing [19], as reflectors for improving spatial resolution of scintillation detectors [20] and X-ray image intensifier scr een in reflective liquid crystal displays [21]. Retroreflection can be obtained by two different techniques: 1. Non focusing retroreflectors: CCR is an optical device which consists of three mutually orthogonal flat mirrors forming a c oncave corner. If the light comes from a quadrant of hemisphere defined by the concav e side of the CCR, th e light entering the CCR is reflected back parallel to th e source. CCRs are most common type of retroreflector in modulati ng retroreflectors (MRRs). Th eir size, weight, and wide acceptance angle make them attractive. Being single, non focusing elements, they reduces alignment concerns. 2. Focusing retroreflectors: Cat’s Eye Re troreflector (CERR) is a device where reflecting and refractive optical elements are arranged so that the focal surface of the refractive element coincides with the reflectiv e surface, typically a transparent sphere and spherical mirror. CERRs come in many fo rms all containing a mirrored surface (not necessarily a plane) onto which light is focu sed. This enables CE RR MRR to have large

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17 optical apertures with small mirrored modulat ors. This benefit comes at a cost: the location of the focal point on the mirror depend s on the angle of incidence. In order to cover a large field of view (FOV), the focal surface must be covered with an array of modulators. Maximum benefit is gained from CERRs if the modulator array can reach to the angle of the incoming light, switching off unilluminated pixels. This decreases both power consumption and self-heating, but requi res more complex circuitry than for a CCR MRR. 2.2 Modulation Schemes for Retroreflectors There are two basic techniques to modul ate the retroreflectors. They are: 1. A modulating shutter in front of a pa ssive optical retror eflector, where the modulation is achieved by reducing the inte nsity of light entering and leaving the retroreflector. 2. Modulating one of the reflective surfaces of the retroreflector itself, where the modulation is achieved by spoi ling the orthogonality of the retroreflector, by tilting or modulating one of the faces of retroreflector. The most common form of shutter modul ator is the multiple quantum well (MQW) device. MQWs are exceptionally fa st, solid-state components, capable of switching at frequencies up to many hundreds of megahertz. However MQWs are very expensive as their construction requires precis ely controlled deposition of up to a hundred layers of thin films. A limitation of this type of modulator is the re latively small contrast achieved by the shutter. Also as the range is increased, large apertures are required. MQW are RC time limited, so as the modulator si ze increases the data rate decreases.

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18 Also the exact wavelength at which such devi ces operate is determined by the choice of materials used to fabricate the MQW devices. MEMS technology provides an attractive technique to modulate the mirrored face(s) of retroreflector. MEMS devices hold the promise of being inexpensive to produce, they can be made with optical quality surfaces, and they can be actuated with sufficient speed to achieve data rates of up to megahertz. Further, electrostatic actuation offers an inherently low pow er means to modulate a retror eflector. This dissertation focuses on the fabrication and testing of MEMS CCR style retroreflectors. In general, CCRs are defined by their height hre, front surface radius rre and resulting beam divergencere Div. The relations between these parameters are given by [22]: re reh r 707 0 Equation 1 re re re Divr L r 2 44 2 2 Equation 2 where is the transmitting wavelength and L is the distance form the CCR to the transmitter. The Gaussian beam curvature at th e aperture output of CCR is given by re Div re rer F2 Equation 3 A transmitter is characterized by its aperture radius rtx, beam divergenceo Div, and Gaussian beam curvature at the aperture output Ftx where 02Div tx txr F Equation 4

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19 Tilting and realigning one or more mirro rs, the CCR can intermittently reflect light away from the direction of the inte rrogating light source. Modulating the mirror(s) in synchrony with information, one can impart this information onto a probing laser beam using only the power required to modulate the MEMS mirrors. A schematic of a CCR used in a communication link is shown in Figure 3. An assembly of a receiver and a transmitter is shown where the receiver is th e base station consisting of a laser source, and a detector to detect the modulated light. The transmitter consists of a CCR which is modulated by the data received from the data source (sensor). This sensor data is then transferred to the probing laser beam and is detected by the sensor in the base station. CCRs have therefore been proposed for us e in FSO communication links. Modulated CCRs have previously been used for opti cal data link between unmanned airborne vehicle (UAV) [23], passive radar transponde r [24], vehicle to vehicle communication [25], or for free space optical communication [26]. Figure 3: Schematic of a CCR Used in a Communication Link [27].

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20 2.3 Free Space Optical Communication Traditional FSO communication require d optically active transceivers (transmitters and detectors) at each end of the communication link, whereas an optical retro modulating communication link consists of a single transceiver at one end of the communication link, and a modulating retrorefl ectors (MRR) at the remote end of the link. Retro communication is base d on the principle that an inte rrogating laser is used to extract information from a retro modulation re ceiver where the laser light is modulated and retro reflected back to the transmitting unit. The advantages of using MRR for FSO includes reduced weight, size, hardware required and power requirements at the remote end of the communication link. It also provi des less critical pointing requirement as retroreflectors provide large field of view. Also since no active emitter is used at the MRR end, the risk for detection of the unit is low. Figure 4 shows the schematic of an optical communication system using a retrorefl ector at the remote station. A transmitter with an optical aper ture of diameter 2rtx is transmitting light with wavelength The light strikes the retroreflector which is placed at a distance of L from the source and the receiver. The retroreflector is of diameter 2rre. The light gets attenuated at the rate of a dB/km by the atmosphere. The retr oreflected light is collected by a detector (receiver) of diameter 2rrx. If a single attenuation factor representing atmos pheric absorption and mean scattering is used, the major factors determining the refl ected power captured by the receiver are [28]:

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21 Figure 4: Simple Layout of a Re troreflective Comm unication System. 4 4 2 2 2 42 2 2 L e r r r PL rx tx re rxa Equation 5 A CCR reflects maximum power when the li ght is incident at the body diagonal of the cube corner. The off-axis performan ce of the retroreflector can be analyzed by calculating the reduction in effective aperture area due to geometrical effects as the source moves away from the axis of the re troreflector. The total reflected power will reduce in direct proportion to the area reducti on factor. Also the reduction in the effective linear dimensions of the aperture will in crease the diffractive loss, once again in proportion to the area reduction fact or of the aperture. For a retr oreflector the variation in the reflected power ) ( Pwith angle of incidence is given by: 2 2 2cos tan 3 2 1 tan 2 1 ) 0 ( ) ( P P Equation 6 where) 0 ( P is the on-axis reflected power, and n sin sin1and n is the refractive index of the material fill ing the retroreflector. L 2rtx Attenuation a 2rre 2rrx

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22 Figure 5 shows the graphical representati on of Equation 6 for different refractive indexes of material filling the CCR. For a gi ven incident angle the power loss decreases with increase in the refractive index of the materi al filling the CCR. This is due to the fact that acceptance angle of the CCR increases with increased re fractive index. Figure 5: Relation Between Power Losses With Increase in Incident Angle at Various Refractive Indexes. 2.4 MEMS CCR and Principle of Operation MEMS comprises of a range of technolog ies that enables the fabrication of miniature devices such as sensors and actu ators. “Optical MEMS ”, or “Opto-MEMS”, has recently been replaced by the term “MOE MS”, for Micro Opto Electro Mechanical Systems. MOEMS derive thei r functionality from the mi niaturization of Optics, Electronics and Mechanics. They employ MEMS to sense, detect or manipulate data, to change light intensity or phase modulation by using refractions, re flection or diffraction principles.

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23 In principle MEMS technology can allo w low cost, compact CCRs to be integrated with sensors and CMOS circuits. Unfortunately, the fabrication tolerances are extremely tight, since imperfections and misa lignments of the mirrors can rapidly result in low optical performance [29]. Early CCR de vices [30, 31, 32] were fabricated as polysilicon optical MEMS, for example usi ng the Multi-User MEMS Process (MUMPS), with mirrors folded out-of-plane on micromach ined staple hinges [33]. However, stressinduced curvature in the Au coated polysilic on has a radius of cu rvature ranging from 79.8mm, and slope in the hinges seriously de graded optical performance, even with improved hinge designs [34]. In addition, assembly of these C CRs either involved manual operation of a microprobe [31], or a de dicated on-chip micro-actuator [35]. Both approaches were unsatisfactory; the former was extremely time-consuming, even when parts were linked together to speed assemb ly, while the latter can require a complex mechanism with a large chip area. Other devices [36] have used single-crystal silicon-oninsulator wafers to produce very flat mirror surfaces, t hough manual assembly of the two passive mirrors was needed to create the three mirror surfaces. MEMS CCR have been demonstrated using full aperture tilting mirro r [35], which limits the performance of the device by the slow resonant frequency of the big mirrors (1kbps). Diffractive MEMS devices with /4 deflection provide faster modula tion (~1 Mhz) but require wavelength and angle matching, limiting the operating a ngle range even for low contrast [37]. Another method to fabricate CCR was demonstr ated by Hong et al. [38] in which selfassembled CCRs were fabricated using out-o f-plane rotation of bonde d Si parts powered by the surface tension of thick photoresist pads. The CCRs were tested for one-two

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24 meters and the modulated using 52 Vp-p, at the resonant frequency of the torsion mirrors. Only very small distance communication was possible because of the gaps between the three mirrors. The Q value of the torsion mirro rs was ~20, which resulted in relatively lengthy ring-down and limited the maximum data rate to around 200bps. In another design [39] it was shown that the CCR can be assembled by bonding three KOH etched surfaces. But the design suffered from a lignment issues and manual assembly. Moreover, designs reported to date do not directly address the need for packaging windows for the devices and do not lend th emselves to economical mass production. Processes which can create a package, and simultaneously assist in the fabrication of the needed optical surfaces, will be beneficial to ward meeting the growing need for low cost packaging solutions.

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25 3 DEEP REACTIVE ION ETCHING (DRIE) 3.1 Introduction Bulk micromachining is an important processing category in MEMS. Bulk micromachining can be classified into two different categories de pending on the medium of etchant used: dry etching and wet etchi ng. Dry etching uses plasma (high energy ionized radicals) or vapor phase etchants to etch bulk of material, typically Si, whereas wet etching uses liquid chemical solutions for etching. DRIE is one of the most important and popular techniques in the MEMS field to perform dry etching in the bulk of Si. Bosch pro cess is usually used to etch structures in the bulk of Si wafer. The Bosch process can be briefly described as consisting of sequential etching and passivation steps using appropriate gas chemis try in each step (SF6 for etching, C4F8 for passivation). The etch cycle, typically lasting 5-15 seconds, uses SF6 to etch silicon. In the next cycle, a fl uorocarbon polymer (made of a chain of CF2 molecules similar to composition of Teflon), is plasma deposited using C4F8 as a source gas. In the following etch cy cle the energetic ions (SFx +) remove the protective polymer from the bottom of the trench, using sputter et ching, but the film remains relatively intact along the sidewalls. The repetitive alternation of etch and passivation steps results in a very directional etch, but it also results in the scalloped sidewalls as shown in Figure 6. High aspect ratios and fast etch rates are the major advantages of using DRIE.

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26 Ideally the etch profile should look like as shown in Figure 7(a), with smooth and vertical sidewalls with flat bottom. Howeve r the real etch profile looks more like as shown in Figure 7(b). It shows exaggerations of the typical et ch profile obtained in DRIE, the structures have tapered sidewalls and bowl shaped bottom [41]. The sidewalls are rough because of the scalloping effect, and the bottom of the et ch pit is bowled shape due to the cyclic nature of the dry etch process. The angle is usually less than 90 and is approximately equal to; ) / 2 ( tan1 b pW W h Equation 7 where Wp is the pattern width, Wb is the mask width, and h is the etch depth. Figure 6: Profile of DRIE Trench Using Bosch Process [41].

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27 (a) (b) Figure 7: DRIE Etch Profiles (a) Ideal, (b) Typical. 3.2 Problems With DRIE There are two major problems with DRIE: one is micro-loading effect [40] or aspect ratio dependence etching (ARDE), and the other is RIE condition incompatibility [41]. The ARDE is the decrease of the et ching speed along with the aspect ratio; the higher the aspect ratio, the slower the etching speed. This phenomenon is understood by the transport limitation of radicals and ions. The etch rate is diffu sion limited and drops significantly for narrow trench es. The ARDE causes a very long RIE lag between an etch time of large openings and that of narrow openings. The second problem, the RIE condition incompatibility, is that the best tool parameters for narrow openings are not necessarily suitable for large openings. Micr o masking is another problem which occurs when the Teflon-like passivation material, wh ich is supposed to be removed by ion bombardment at the successive etching, is not removed perfectly from the bottom and it causes a micromask protecting a small part at the bottom from etching. Extensive research has been done to characterize geometri c effects on etch rate s; large open areas and small trenches etch at different rates a nd produce different amounts of lateral etching

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28 [42]. Scalloping is another potential issue which causes scattering loses when using the scalloped surfaces as mirrors. There problems are visible in Figure 8. Structures with different width (350 m and 200 m) were etched using the same process in a single run. While the wider features got etched ~300 m the narrower features were only etched to ~260 m. Etching was performed for 400 DRIE cycles (Appendix A). The sidewall angle was calculated to be 79.69 and 80.72 for Figure 8(a) and Figur e 8(b) respectively, using Equation 7. Figure 8: Examples of Micro-loading Effe ct and RIE Etch Condition Incompatibility. 3.3 Techniques for Reducing Loading Effect in DRIE Maintaining vertical etch profile for th rough-wafer etches has been an important area of research in MEMS. It is difficult to maintain vertical etch profile during long DRIE runs as the etch profile depends highl y on etching patterns and plasma conditions [43]. Efforts to realize extremely vertical sidewalls using various methods to overcome the micro-loading in DRIE continue to be an active area of investigation [44, 45, 46, 47,

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29 48]. A model to etch vertical st ructures was demonstrated by Ja nsen et al. [44]. They used the black silicon (continuous monitoring of the etched surface was done until it turns black) method to determine optimum etches parameters. As continuous monitoring is required to determine th e right process parameters, this method was not feasible for batch fabrication. Bertz et al. [45] used a fusion bonded mask ed Si wafer to etch vertical structures in a Si substrate. This masking wafer was first etched using wet anisotropic etching to define the masks for the device wafer. This anisotropic wet etching of masking wafer limited the structures that can be real ized using DRIE in this method. In the method used by Ikehara et al. [ 46], vertical structures were first defined by etching deep trenches around the structures. To maintain the verticality, uniform width trenches were used. The remaining areas were then rem oved by successive DRIE. Since spray coating photoresist was used to patter n the high topography structures the vertical structures defined by first DRIE etch were found to be damaged around the sharp corners, because of the non uniform coating of the masking phot oresist. Two long DRIE etches along with lithography on high topography struct ures was used to maintain the vertical profile during the long DRIE etches. Hsieh et al. [47] desc ribed the use of guarding walls where many uniform width stripes were defined in the pe ripheral of the main structures. DRIE was performed in three different steps and lit hography was performed on high topographies. Finally the guarding walls were released using wet etching. Mita et al. introduced the concept of contour-lithography [48] using tw o different lithography steps and subsequent DRIE to negotiate the loading effect in DRIE while etching high aspect ratio features.

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30 This was demonstrated to fabricate vertical structures in nano and micro domain in the same wafer. So far the methods developed have used multiple long DRIE steps and/or multiple lithography steps on high topogra phy structures were perfor med. One way to reduce the micro-loading effect is to reduce the density of the open areas in DR IE. This can be done by using uniform narrow width channels all across the wafer. A new two step DRIE process was developed, wher e long DRIE was performed on ly once to etch thought the 550 m thick Si wafer, along with one short initial DRIE. While simple lithography steps were employed, the unwanted Si blocks were released automatically without the use of any etchant and vertical structures were fabr icated with an incorporated package lid. Uniform width trenches ensured that there wa s no DRIE lag between different structures. The process flow and the results obtained using this technique will be presented in Chapter 5. 3.4 Techniques for Reducing Roughness on Etched Surface The scalloped sidewall which results from alternate etching and passivation cycles in DRIE is not suitable for optical applications, as the scalloped sidewall causes scattering losses. Various researchers have tr ied different methods to overcome or reduce the scalloping effect and other reasons for sidewall roughness. One of the methods to reduce the sidewall roughness is by improvi ng the sidewall roughness of the masking layer [49]. The sidewall roughness of the et ched surfaces was improved by reducing the roughness of the photoresist edges. The polymer chain density is higher at the edges which results in rough sidewalls. This roughness was reduced by hard baking the

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31 photoresist followed by isotropic etching in O2 plasma. During hard bake, photoresist reflows and the edge roughness was reduced. By applying O2 plasma descum, the edge roughness is reduced due to the isot ropic nature of the process. Similarly a trilayer photoresist method [ 50] was described which also reduced the roughness of the masking layer. A Cl2 based plasma generate d by electron cyclotron resonance (ECR) was used to etch st ructures were used to etch ~40 m deep in Si. Oxidation and etch back was then used to further improve the sidewall roughness to ~6nm. The authors have presented 40 m deep features and the 6nm surface roughness was measured on a surface area of 4x4 m2. To reduce the scalloping effect, Volland et al. [51] have presented an improved gas chopping method where ion enhanced etch ing step was used instead of isotropic chemical etch steps, which etches the polym er from the bottom of the etch pit. This process reduces the etch selectiv ity to the masking layer and 40 m deep features with root mean square (rms) roughne ss of ~10nm was presented. In another method described by Juan et al [52, 53], boron diffusion and etch back in EDP was suggested as a way to improve the sidewall roughness of 50 m deep Si structures to 5nm. A few other techniques can be used [6, 54, 55, 56, 57, 58, 59] to polish the rough DRIE surface including oxidation and etch back, EPW (ethylenediamine, pyrocatechol and water), HNA (hydrofluoric acid nitric acid and acetic acid ) electropolishing, KOH:IPA (potassium hydroxide and is opropyl alcohol) etching, etc.

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32 Though, all the above mentioned methods we re effective for reducing the sidewall roughness, many of them require to change the DRIE recipe which mi ght adversely affect the sidewall profile. Some of them are very hazardous solutions an d others have the potential to damage the co-bonded Pyrex surface which is used in this work as the handle wafer and the package lid. Standard KOH solution in H2O has etch rates for different crystal planes in the order of (110)>(100)>(111). However with th e addition of IPA in the solution the etch rates in the (110) plane is decreased by about 90% while only reducing it by 20% in (100) plane, hence the etch rate of different crystal planes in KOH:IPA solution is (100)>(110)>(111) [6, 57, 58, 59]. Dry etching and wet etching ha ve been used before to get vertical mirrors. Juan et al. [60] and Marxer et al. [ 57] have fabricated high aspect ratio vertical micromirrors 40 m and 75 m deep with sidewall roughness of 30n m respectively. However, in many optical applications including the CCR presente d hereunder, a larger vertical reflective area is needed for the light to interact with the mirrors, to increase optical signal. Also as the depth of dry etches increases, the r oughness, etch rates and sidewall profiles are adversely affected. In this dissertation 550 m thick Si wafer was etched through the wafer and was wet etched later to polish th e surface. The average roughness obtained was 37nm. The results will be presented in Chapter 6.

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33 4 WET ANISOTROPIC ETCHING Wet etchants in aqueous solution offe r the advantage of low cost batch fabrication. Wet etching is defined as th e removal of the exposed surface from the material using chemical reactions in a liquid solution. First the reactants are transported to the exposed surface and then a chemical r eaction takes place, and the reaction products are transported away from the reaction site and repl aced by the new reactants. The etch rate depends highly on the composition of the et chants, the temperature of the etch bath and the etched material. It is a versatile pr ocess which can be used to perform isotropic and anisotropic etching. 4.1 Isotropic Etching Isotropic etchants by definition etch in all directions with a uniform rate. The resulting geometry in a silicon substrate ha s rounded corners. Th e most commonly used silicon etchants are mixtures of nitric acid (HNO3) and hydrofluoric acid (HF). Isotropic etchants can be diffusion limited and therefor e process parameters including agitation can affect the results. Since precisely controlling agitation in a bulk process can be difficult, isotropic etching provides le ss lateral and vertical contro l than anisotropic etching. Isotropic etchants are available for oxide, nitride, aluminum, polysilicon, gold, silicon, etc. Isotropic etchants remove material horizontally under the etch mask (undercutting) at the same rate as they etch through the material.

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344.2 Anisotropic Etching Isotropic etchants etch uniformly in a ll directions, resulting in rounded cross sectional features. In contrast anisotropic etchants etch in one direction preferentially over others, resulting in trench es or cavities delineated by fl at and well-defined surfaces; with the etch rate slower in one direction th an others. Single crystal silicon wafers are manufactured using ingots of single crystal silicon. In this method upon solidification from liquid, the atoms position themselves in a repetitive 3-D pattern. The orientations of the planes for crystal structure are re presented in a similar manner, and the crystallographic planes are specified by Mill er indices. Each set of Miller indices corresponds to a different cross section of th e crystal. Each cross section has different atomic layout pattern and atomic densities. The etch rate varies in different orientations as the layout pattern and the atomic densities are different in each direction. The surfaces of the slowest etch crystal planes get exposed after long etching peri ods and acts as etch stop. Anisotropic etchants are di rection dependant etchants which attack the silicon wafer at different rates in diffe rent directions, and so there is more control of the shapes produced. Anisotropic etching results in tren ches or cavities as shown in Figure 9. Anisotropic etching produces 3-D shapes fr om 2-D mask features. The resulting 3-D profiles are made of various cr ystal planes. It has been used to realize a membrane based silicon pressure sensor, one of the ear liest MEMS commercial products [61]. Wet anisotropic etching has also been used to fabricate the suspended cantilevers [62] and protruded tip of an atomic fo rce microscope probes [63].

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35 Figure 9: Cross Sectional Overview of Trench es Etched Using Different Kind of Etching Methods. The most popular anisotropic etchant is potassium hydroxide (KOH), since it is the safest to use. The chemistry of the reac tion is shown here under [64]. Silicon atoms at the surface react with hydroxyl ions. The silicon is oxidized, and four electrons are injected from each silicon atom into the conduction band e OH Si OH Si 4 ) ( 22 2. Simultaneously, water is reduced, lead ing to the evolution of hydrogen, 2 22 4 4 4 H OH e O H The complex silicon, 2 2) ( OH Si, further reacts with hydroxyl ions to form a soluble silicon complex and water, 2 2 2 2 2 22 ) ( 4 ) ( H OH SiO OH OH Si Thus, the overall reaction is e H OH Si O H OH Si 2 2 ) ( 2 22 2 2 2

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36 Seidel et al. [64] presented a model whic h suggests that the etching rate of silicon depends on the product of hydroxide ions a nd free water concentration. Because the K+ and OHions, resulting from the dissociation of KOH, undergo hydration in the solution, they consume quite essential portion of wate r. At a higher level of KOH concentration, the free water content drops drastically, which in effect causes remarkable reduction in etching rate. A very interesting trend in studyi ng the anisotropic etch ing processes is the application of different additions modify ing the etching behavior and improving the smoothness of resulted surfaces both in KOH [ 65] and organic solutions [66]. Isopropyl alcohol (IPA) has been known for many years as a very effective admixture to KOH solutions influencing the smoothness of resulted silicon surfaces [67, 68]. The addition of IPA generally causes reduction of etching rate on (110) plane of se veral percent with respect to pure KOH aqueous solution. IPA acts as an agent hi ndering hydration of K+ and OHions and liberating the water particles in the close vicinity of silicon surface. This results in more water particles that can take part in the etching process. V-grooves with an angle of 54.74 can be etched in (100) Si wafer using KOH or tetra methyl ammonium hydroxide (TMAH) as the etchant with Si3N4 or SiO2 as the masking layer. Precise alignment of the mask features to the crysta llographic orientation is very important to get nice and smooth si dewalls with least undercutting. Slight misalignment can create striations and othe r defects in the etched sidewalls during anisotropic etching [69]. In the case of a (100) silicon wafe r, the straight edges of the mask features has to be parallel or perpe ndicular to the (110) pl ane, which is usually identified as the primary wafer flat of (100) Si wafer. The wafer flat s are mechanical cuts

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37 on the wafer and are typically misaligned to th e crystal flat by an angle of 1-2, the range of which is usually specified by the wafe r suppliers. A fan out structure can be used to perform an initial etching on the wafer to lo cate the crystal flat, by visually finding the feature with least undercutting [70]. Mostly (100) and (110) orientation silicon wafers are used because of their fast etch rates in the out of plane directions in anisotropic wet chemical etchants. Also, (110) oriented sili con is used since nice deep trenches with straight walls with re spect to the wafer surface can be made. However, (111) oriented Si is rarely used since it etches slowly in anisotropic etching solutions. 4.3 Etching Vertical Structures in (110) Si Wafer Smooth surfaces are frequently required in the optical devices as the reflective mirror. An anisotropically etched (111) surface can be used for that purpose, however the (111) surface at an angle of 54.7 to the (100) Si surface is not good at constructing the optical system. For optical applications 45 or 90 surfaces are frequently required. (110) silicon wafer can be used to construct these kinds of features. Howe ver a straight through four sided hole cannot be etched through a (1 10) oriented silicon wafer using a square mask opening. A six sided structure is obtai ned which has four {111} planes which are perpendicular to the (110) wafer surface and two {111} planes which make an angle of 35.3 to the wafer surface. If this pattern is etched long enough, a self-stopping condition will be achieved as the two low angles {111} planes meet along a line. This limits the kind of structure that can be fabric ated using (110) silicon wafer. Long narrow slits in (110) oriented silic on can be fabricated if the mask is accurately oriented to the (111) plane. Howe ver at the outside corners (convex corners),

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38 many crystal planes exist and some etch faster than others, leading to corner undercutting. There are various methods descri bed in literature which can be used to minimize corner undercutting [71, 72, 73], but sharp outside corners, on a (110) Si, cannot be achieved by any of the methods wh ich are required in many applications like the vertical mirrors required for CCR. As desc ribed in [9], when etching a (110) silicon using a rectangular mask, the convex corners ar e etched to form two fast etched planes, which meet each other to form triangular etched structures at criti cal etch time (the two 311 planes meet). Hence the actual beam lengt h is significantly shorter than the designed length as shown in Figure 10, and a SEM image of one such structure is shown in Figure 11. Figure 10: Etching Mechani sm of Beam Structure in (110) Si [9].

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39 Figure 11: SEM Image Illustrating the Convex Co rner Undercutting Problem in (110) Si. Figure 12 shows the simulation results (using CoventorWare Memulator 2006.5 module) obtained when KOH etching was perf ormed on a (110) Si wafer with the edges of the horizontal rectangle ali gned to the (111) wafer flat. KOH etching was performed at 80C using 30% w/w KOH solution. 250 m thick (110) Si wafer was used for the simulation purpose. The mask with a cross structure (3500 m x 370 m) was used. Severe undercutting was noticed as shown in Figure 12. Since mirrors were required in the shape of a cross to act as the two orthogonal mirro rs of the CCR, fabricat ing vertical mirrors using KOH etching on (110) Si wa s not a feasible option. To over come this issue two different sets of vertical mirrors which can fi t into each other to form the cross structure were fabricated. This approach also suffers from the convex corner undercutting problem, especially the corners at the gap which will be there to facilitate the insertion of second set of mirrors. This is shown in Figure 13. KOH etching was perf ormed using the same

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40 parameters as before. Severe undercutti ng and tapered corners were obtained as predicted. Figure 12: Simulation Results of KOH Etching on (110) Si Wafer, When a Mask in the Shape of Cross-Hair was Used. Severe Undercutting was Noticed.

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41 Figure 13: KOH Etching Performed on Structures With Gap in the Center to Facilitate Bonding of Second Set of Mirr ors to Assemble Cross-Shape Structures. The Top Figure Shows the Mask Used and the Bottom Figure Shows the Simulated Top View of the Structure After KOH Etching on (110) Si Wafer. To overcome this problem of undercutti ng dicing was used to create the gap between long vertical structures so that the second set of vertical mirrors can fit into it. This approach is discussed in detail in Section 12.4.1.

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42 5 FABRICATION OF VERTICAL MIRRORS 5.1 Dry Etching As discussed before to etch vertical structures using DRIE the micro-loading effect needs to be reduced. One of the ways to do this is by reducing the density of the areas exposed to the plasma. This was done by using uniform narro w width channels all across the wafer. Uniform width trenches also ensured that there was no DRIE lag between different structures. The masks for fabricating the vertical mirro rs were designed such that the vertical mirrors and the encapsulating package frame are defined simultaneously. To avoid the aforementioned loading effects in the DRIE, which limits etch uniformity and results in non-vertical structures, a two step DRIE process was devise d with uniform etch trench width as illustrated in Figure 14. 5.1.1 Process Flow The process consists of an initial de position of a thin layer of 100nm LPCVD (low pressure chemical vapor deposition) nitride on a 4" double side polished (DSP) (100) Si wafer in a Tystar LPCVD furnace (mini Tytan 4600, at 840C, 200mTorr) as shown in Figure 14(a) (Appendix A). This wa s followed by an indentation patterning on the front side of the wafer to define open ar eas of the package window as in Figure 14(b). The nitride film was etched using reac tive ion etching (RIE ) tool using CHF3 and O2

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43 plasma (Appendix A), and is followed by ve ry short silicon DRIE, using the photoresist as the mask. This creates a few microns (10-15 m) indentation into the surface of the wafer as illustrated in Figure 14(c). Next the re sist was stripped off the wafer and then the indented side (front side of Si wafer) was anodically bonded in vacuum to a DSP Pyrex 7740 glass wafer (EVG 501 bonder, 1 kV, 400C, 10 minu tes), creating a Pyrex-Si3N4 bond everywhere except where th e indentation exists, as sh own in Figure 14(d). Higher voltage than what is typi cally required for Pyrex-Si bonding was used during anodic bonding to ensure anodic bonding via th e thin Si3N4 layer. Next the ba ckside of the Si wafer was coated with 1000 thick Al layer through sputtering as s hown in Figure 14(e). The Al acts as an etch mask for DRIE w ith high etch selectiv ity, while the underlying Si3N4 was used as wet etching mask in further processing. The Al and the Si3N4 layers were patterned using photolithography with a mask that defines a uniform narrow (50 m wide) trench opening around the fi xed features. The Al layer was etched in Al etchant (Type A, Transene Inc.) at 50C for 22 seconds and the nitride film was RIE etched as shown in Figure 14(f). The trenches were et ched through the Si wafer using DRIE. Once the trench etch reaches the indentation areas, the large indented area of the Si detaches from bonded Si and falls onto the Pyrex surface as shown in Figure 14(g). These pieces are then removed just by inverting the wafe r stack. The remaining parts still bonded to the glass wafer are the vertical mirrors with rough sidewalls and the package frame, as in Figure 14(h).

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445.1.2 DRIE Results and Discussion Various kinds of features were etched on the same wafer with different fill factors. In all of them the same masking techniques, as descri bed above, were used. Therefore, since DRIE was performed only on the uniform 50 m wide areas, excellent uniformity was noticed. The etch profile was inspected across the wa fer by selecting nine chips from across the 4" wafer. Five chips we re selected from the center row to determine the uniformity of etch across the wafer for identical structures and four chips were selected from the center column to determine the etch profile when a different density of Si was removed. The density of area remove d using two step DRIE method varied from 71% to 99% across the wafer, as per the desi gned masks, demonstrating the removal of large areas. The standard devi ation of 0.15 was calculated fo r the sidewall profiles across the wafer. The DRIE was performed in a Unaxis SLR-7701-10R-B Bosch DRIE System, and the passivation cycle and the etch cycles parameters are shown in Table 1.

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45 Figure 14: Cross Sectional View of the DRIE Et ch Process to Fabricate Vertical Mirrors. (a) LPCVD Si3N4 Coated Si, (b) Lithography to Define the Eventual Window Area, (c) RIE of Si3N4 Followed by 10m Deep DRIE of Si, (d) Phot oresist Was Stripped Off and Anodic Bonding Was Performed on the Front Side (e) Sputtering of Al on the Back Side of Si, (f) Lithography Was Performed to Define DRIE Channels and Al and Si3N4 Were Etched Using Photoresist as Masking Layer, (g) After Completion of DRIE the Free Standing Features Falls Off on Pyrex, (h) Highly Vertical Mirrors and Package Frame Were Left After Removing the Bulk Si. Table 1: Various Parameters Used For th e Standard Bosch Cycles in This Work. Passivation Cycle Etch A Etch B Pressure (mTorr) 22 23 23 Cycle time (sec) 5 2 6 C4F8 (cc) 70 0.5 0.5 SF6 (cc) 0.5 50 100 Ar (cc) 40 40 40 RIE Power (RF1) (W) 1 9 9 ICP Power (RF2) (W) 825 825 825

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46 As mentioned before, etch profile duri ng DRIE dependents on several variables such as coil and electrode power, the durati on of the etching and passivation cycles, and chamber pressure. Relative etch time and pa ssivation time can change the tapering of the sidewalls. If the etching cycle is long with respect to the passivation cycle, a negatively tapered profile will be formed as etching con tinues long after the protective film has been etched. Similarly if the etch cycle is too s hort as compared to the passivation cycle, a positively tapered profile is formed as the protective film is not removed completely by the subsequent etch cycles (as was shown in Fi gure 7(b)). Thus, the settings that promote the deposition of thicker passivation films, i.e., higher pressure or longer passivation cycle have a significant impact on side wall profile in DRIE. Figure 15 shows the scanning electron microscope (SEM) image of the 50 m wide channel etched ~300 m deep in Si with vertical sidewalls. 23mT orr pressure was used during the passivation cycle to produce the desired near-vertical pr ofile (slightly more than 90). Due to the increased pressure, excessive polymer gets de posited during the pa ssivation cycle which was not being removed during the successive etch cycle. This results in the formation of micro-grass as can be seen in Figure 15. This micro-grass was removed during the KOH:IPA polishing step. The pressure and time were changed in the passivation cycle to monitor their effect on the sidewall profile using the above described two step DRIE method. The passivation cycle duration was increased by 1 second in DRIE process or the C4F8 gas pressure was changed from 22mtorr to 23mto rr and the changes in sidewall angles were noted. The sidewall angles obtained from all of these samples were 0.2 of 90

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47 indicating that the described process maintain s its vertical profile even with slight variations in the DRIE process parameters The sidewall angle variations on these samples are summarized in Table 2. The averaged variation across the wafers was 0.3, with a 1.5% measurement uncertainty. (100) Si wafers and (110) Si wafers were etched using the above described two step DRIE pr ocess without any sign ificant variation in sidewall angles. Due to slight variation in etch rates acr oss the wafer in the DRIE tool, an over etch of ~50 cycles in the second DRIE step wa s performed to make sure that all the chips across the wafer were through etch ed and the unwanted blocks of Si falls off as shown in Figure 14(h). The sidewall profile was measured using the SEM images and the data is shown in Table 2. Samples were picked from across the wafer and the sidewall angle variation was 0.3 across the wafer with average angle of 89.8. This variation can be attributed to the over etching or tool non-uniformity. Average sidewall roughness after DRIE was measured to be ~250nm using an optical profilometer. This sidewall roughness was improved by various post-proces sing to ~40nm and the average sidewall angle was improved to 90.08 as de scribed in the next chapters.

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48 Figure 15: Cross Sectional SEM Image of the Uniform Width Narrow Channels Etched in Si Using Modified DRIE Process (23mTorr Pressure).

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49 Table 2: Comparison of Sidewall Angles Acro ss the Wafer With Diff erent DRIE Recipes. Sample Sidewall angle (6 sec. passivation, 22mtorr in DRIE) Sidewall angle (5 sec. passivation, 22mtorr in DRIE) Sidewall angle (5 sec. passivation, 23mtorr in DRIE) Left 89.62 90.04 89.72 Left Center 90.03 90.17 89.80 Center 90.01 90.10 89.91 Right Center 89.84 90.15 90.05 Right 89.67 90.08 89.80 Top 89.45 90.15 90.05 Top Center 89.85 90.20 89.82 Center 90.01 90.10 89.91 Bottom Center 90.10 90.09 89.85 Bottom 89.90 90.65 89.90 Average 89.85 90.17 89.86 Figure 16 shows the SEM image of the vert ical structures, in the shape of the cross, etched in 550 m thick silicon. The glass lid and the package frame area are also shown. Figure 17 shows the SEM images of vertical structures of di fferent shapes and chips with various densities of area removed by DRIE. 5.2 Reducing Sidewall Roughness: Masking Layer Optimization The average sidewall roughness measured on the dry etched surface varied from 200nm to 250nm. A Wyko NT3300 op tical profilometer was used to measure the surface roughness. Atomic Force Microscopy (AFM) was not a feasible option for the roughness measurement on these surfaces because of th e package frame area which prevented the AFM tip to touch the surface unde r inspection. Figure 18 show s the optical scan of one such surface. The roughness was mainly due to etch and passivation cycles of the DRIE as described earlier. The other factor which affects the sidewall roughness is the

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50 photoresist edge roughness. The phot oresist with rough edges (which is due to the nature of photoresist development process) was used to pattern the DRIE masking layer (Al) hence transferring the ro ughness to the Al layer. When this Al mask was used to perform the DRIE the roughness gets transferred to the bulk of silicon and it increases the sidewall roughness. Hence characterization of the photoresist was re quired to minimize the sidewall roughness after DRIE. Figure 16: Shows the SEM Images of Cross-Hair Structures, Which Were Etched in Si Using the Described Two Step DRIE Process. The sidewall roughness coming from the phot oresist edge roughness is inherent to photoresists and is due to th e higher entangling of the polymer chain around the edges. These entangled polymer chains have highe r density than surrounding polymer chains which results in lower development rate [74]. The photoresist edge roughness can be reduced by hard baking the photoresist and O2 plasma descum. During hard bake, photoresist reflows and the edge roughness is reduced. The optimum temperature for hard

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51 baking is different for differe nt photoresist. By applying O2 descum, the edge roughness is reduced due to the isotropic nature of the process. Figure 17: SEM Images of Various Vertical Structures Etched on the Same Wafer Along With the Cross-Hair Shown in Figure 7.

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52 Figure 18: Optical Profilometer Scan of the Vertical Mirrors After DRIE, Ra = 217.62nm. Shipley 1813 positive photoresis t was used to pattern the Al and nitride layers for DRIE trenches. The adhesion promoter HMDS (hexamethyldisilazane) was spun on top of Al which was followed by spinning of 1813 photoresist at 3000rpm for 40 seconds. The photoresist was soft baked on a hot plat e at 90C for 60 seconds. The resist was exposed for 2.5 seconds with the DRIE tr ench mask using EVG 620 double sided mask aligner. The resist was deve loped in the MF319 developer fo r 40 seconds. and hard baked at 120C for 4 minutes. This helps to reflow of photoresist which reduces the sidewall roughness. Next the photoresist was descum in O2 plasma using a Tepla plasma asher (200sccm of O2, at 260W for 7 minutes). Due to the isotropic nature of the process it

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53 helps in further reduction of the sidewall roughness. Almost 50% improvement was noticed in the DRIE etched sidewall roughness. Figure 19 shows the optical profilometer scan of the vertical mirror. The lithogra phy was performed using the above described processes and DRIE was performed as disc ussed earlier. The average roughness was measured to be around 122nm. Figure 19: Optical Profilometer Scan of the Vertical Mirrors After DRIE With Improved Lithography Steps, Ra = 122.62nm.

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54 6 IMPROVING SURFACE QUAL ITY AND ORTHOGONALITY The average sidewall angle of the etch ed structures, measured from the SEM images, using the methods described in Chap ter 5 was 89.8. Since DRIE was performed using uniform width etch channels, very unifo rm etch features of different shapes and sizes were obtained across the wafer. For opt ical applications an d other applications which require vertical structures, the 0.2 vari ation in sidewall angle might be detrimental to the performance of the device, see Appendix B. Test chips were diced, so that the etched sidewall is visible when the chip is placed on its edge, to allow the measurement of the roughness of the etched surfaces. The average sidewall roughness obtained on the vert ical structure etched using DRIE was measured to be 122nm using an optical profilomete r, as discussed in the previous chapter. It has been shown that as long as the root mean square (rms) roughness of the mirror stays below 5% of the wavelength of th e incident light, the reflected light flux is proportional to the incident power spectral dens ity [57]. For a gently sloped surface, the amount of scattered light may be calculated from the rms surface roughness using the relationship: etot ScatP P2cos 41 Equation 8

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55 where Pscat is the scattered light flux and Ptot is the total reflected light flux, is the wavelength of the incident light beam and is the angle of incidence. Figure 20 shows the change in scattering loss Vs. RMS roughness at various incident angles for a He-Ne laser ( =632.8nm). Figure 20: Scattering Loss Vs. RMS Roughness at Various Incident Angles for He-Ne Laser. The average roughness on the DRIE sidewalls with modified lithography steps, was measured to be ~122nm. For visible opt ical applications the 122nm rms roughness is unacceptable, as 98% of the incident light (at an angle of 45) would be lost in scattering at each mirror surface. Since the etched surface has the roughness of approximately 122nm even after the improved lithography step s, there was a need to improve the

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56 surface roughness for optical applications. A novel process was developed where along with the improvement in surface quality, slig ht improvement in sidewall angle was also achieved. This was achieved by using two step masking process, instead of using a single mask as described before, and by using KOH:IPA anisotropic polishing. Figure 21: KOH:IPA Polishing Was Used to Improve the Sidewall Roughness and Angle. Figure 21 shows the cross section schematic of the DRIE structures before and after KOH:IPA polishing. Two lithography steps we re performed to define two different masking layers for wet polishi ng and dry etch ing. The nitride mask, which was used as the masking layer for wet polishing, was defi ned narrower than the Al mask, which was used as the DRIE mask. Thus with the slig ht undercutting (0.2) which occurs during DRIE we get a slightly tapered side wall as shown in Figure 21(a). The Si3N4 layer was protected while doing a nodic bonding, as shown in Figure 21. This was done to prevent damage and etch pit formation at the Si -Pyrex interface, whic h was noticed during Pyrex Wafer 89.80 Al Si3N4 Near (110) Scalloped Planes Pyrex Wafer 90.080 Al Removed Si3N4 Polished (110) Plane

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57 KOH:IPA polishing tests. Thus the LPCVD Si3N4, which was sandwiched between Si and Pyrex, acts as the masking layer for the bonded interface and is of the same dimension as the wet etch Si3N4 masking layer. Thus when the KOH:IPA polishing was performed the etching slows at the (110) planes when using KOH:IPA solution, and forms the vertical mirrors. Figure 22 show s the modified process flow to fabricate vertical structures. Figure 22: Cross Sectional View of the DRIE Et ch Process to Fabricate Vertical Mirrors. (a) LPCVD Si3N4 Coated Si, (b) RIE of Si3N4 Followed by 10m Deep DRIE of Si, (c) Photoresist Was Stripped O ff and Anodic Bonding Was Performed on the Front Side, (d) Si3N4 Was Patterned to Define the Wet Polish ing Mask, (e) Sputtering of Al on the Back Side of Si, (f) Lithography Was Performed to Define DRIE Channels With Al as DRIE Masking Layer, Which Over laps the Underlying Si3N4,, (g) After Completion of DRIE the Unbonded Structures are Freed From the Bonde d Structures, (h) Highl y Vertical Mirrors and Package Frame Were Left After Removing the Bulk Si.

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58 The process consists of an initial de position of a thin layer of 100nm LPCVD silicon nitride on a 4" double side polished (DSP) (100) Si wafer (840C, 200mTorr) in a Tystar LPCVD furnace (mini Tytan 4600) as s hown in Figure 22(a). A fan out structure was again used to determine the crystal flat as discussed in previous chapter. This was followed by an indentation patterning on the front side of the wafer to define eventual open areas of the package window, with the ma sk rectangles aligned to the wafer flat <110> direction. The nitride film was etched using RIE using a CHF3 and O2 plasma, followed by a very short silicon DRIE, using pho toresist as the mask as shown in Figure 22(b). This creates a few microns indentation into the surface of the wafer. Next the resist was stripped off the wafer and then this inde nted side (front si de of Si wafer) was anodically bonded in vacuum to a DSP Pyrex 7740 glass wafer (EVG 501 bonder, 1kV, 400C, 10 minutes), creating a bond everywhere except where the inde ntation exists, as shown in Figure 22(c). The nitride layer wa s sandwiched between the Pyrex and Si. It prevents the formation of etch pit holes in Si, which was noticed during the wet etching tests. The bonding strength was tested using shear tester and it passed the maximum tool load of 2Kg. The Si3N4 on the backside of the Si wafer was then patterned with the KOH:IPA mask (the masks designs are shown in Figure 23) as shown in Figure 22(d). Standard lithography was used to pattern the Si3N4 and RIE was performed to etch the Si3N4. The stack of the wafer wa s then coated with 1000 thick Al layer through sputtering as shown in Figure 22(e). The Al acts as a hard mask for DRIE with high selectivity, while the underlying Si3N4 was used as wet etching mask in further processing. The Al was then patterned with a DRIE mask which overlaps the KOH:IPA

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59 mask by 10 m. Modified lithography steps, as descri bed in the previous chapter, were used to reduce the sidewall roughness on the Al. This defines the narrow uniform width (50 m wide) channels around all fixe d features. The Al layer was etched in an Al etchant (Type A, Transene Inc.) at 50C for 22 seconds and is as shown in Figure 22(f). Thus, different masking layers we re created for DRIE and s ubsequent KOH:IPA polishing. These narrow uniform width ch annels were etched through the Si wafer using DRIE. Once the uniform width channel etch reaches the indentation areas, the large indented area of the Si detaches from the bonded Si and falls onto the Pyrex surface as shown in Figure 22(g). After etching these pieces were removed just by inverting the wafer stack. The remaining parts still bonded to the glas s wafer are the vertical mirrors and the package frame, as in Figure 22(h). Al wa s stripped off using Al etchant and wet anisotropic polishing was performed to improve the surface quality as di scussed in later. 6.1 Improving the Orthogonality of the Mirrors Figure 23 shows the layout of the masks wh ich were used to fabricate vertical mirrors for four CCRs in a cross shape, a nd the package frame with package lid. The indentation mask (Figure 23(a) ) was patterned using a nega tive photoresist so that the dark area which is shown in the mask gets etched in the first DRIE step for 10-15 m. The KOH:IPA mask, shown in Figure 23(b) was then used to pattern the Si3N4 layer on the back side of the wafer. Al was then sputte red on the back side and DRIE mask (Figure 23(c)) was used to pattern this Al which will act as DRIE masking layer. The indentation mask lies between the 50 m wide DRIE mask features so that the misalignment which

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60 might occur in front and back side alignment does not affect the DRIE process which will release the unwanted areas from the wafer. (a) (b) (c) (d) Figure 23: Mask Layout Used to Fabricat e Vertical Mirrors in the Shape of a CrossHair. (a) The Indentation Mask Where Only the Masked Area Was Shallow Etched in DRIE, (b) The KOH:IPA Etch Mask. This Mask Was Used to Pattern Si3N4 Before Using DRIE Mask to Make Different Masking Layers For KOH:IPA Polishing and DRIE, (c) DRIE Mask With Only Narrow Uniform Width Channels of 50m. It Defines the Narrow Channels Where Through-Wafer DRIE Was Performed. This Mask Overlaps the KOH:IPA Polish Mask by 10m, (d) Shows All the Three Masks Overlaying Each Other.

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61 The DRIE mask overlaps the KOH:IPA mask by 10 m, which is more than the alignment tolerance of the mask aligner, and to account for the tool non-uniformity during long etches. The Si3N4 layer will be used as the KOH:IPA etch mask, which was performed to improve the smoothness and vert icality of DRIE et ched surfaces. DRIE over etching for approximately 50 cycles was done to make sure that all the unwanted Si blocks fall off on the Pyrex. No effect of th is over etch was noticed on the roughness or verticality of the structures. Figure 23(d) shows how the different masks overlap each other. Various kinds of features were etched on the same wafe r with different fill factors. In all of them the same masking techniques, as described above, were used. Therefore, since DRIE was performed only on the uniform 50 m wide areas, excellent uniformity was noticed. 6.2 Improving the Surface Quality by Wet Polishing The DRIE process leaves scallops on the morphology of the etched structures because of the process sequence of etch and passivation cycles as shown in Figure 7(b). To use these etched surfaces as mirrors the roughness has to be reduced. Standard KOH solution in H2O has etch rates for different cr ystal planes in the order of (110)>(100)>(111). However with the addition of IPA in the solution the etch rates in the (110) plane is decreased by about 90% while only reducing it by 20% in (100) plane, hence the etch rate of different crystal pl anes in KOH:IPA soluti on is (100)>(110)>(111). Since after DRIE the ve rtical structures are very near the {110} planes, the isotropic etching using KOH:IPA solution was stopped at {110} planes hence resulting in smooth surface.

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62 DRIE and wet anisotropic etching techniques were us ed to fabricate highly vertical structures with mirror like fini sh. DRIE was performed to first etch 550 m deep structures in Si while maintaining uniform et ch profile, and then we t anisotropic etching to reduce the roughness of the sidewalls. Two different mask ing layers were used as shown in Figure 23, for wet anisotropic polishing and dry etching. With this mask design it was also possible to improve the verticality of the etched structures and reduce the roughness, along with an in-s itu developed package window using the two masking layers etch process. The average roughness on the DRIE sidewall s in the test samples was measured to be approximately 250nm. This was re duced to approximately 122nm by using the improved lithography steps as were described in previous chapter. Also Teflon like polymer (polymerized CF2) layer of about 50nm gets deposited on all the exposed surfaces including the etched mirrors which prohibits any kind of post DRIE chemical etching on this surface. This polymer was plasma cleaned in a Tepla plasma etcher at RF power of 400W and 400 sccm of O2 flow for 1 hour. This decreases the roughness of the etched surface from 122nm to 90nm, as shown in Figure 24. At 90nm roughness the scattering loss is still expect ed to by around 80% at 45 in cidence angle of light. This scattering loss increases when li ght is reflected off two orthogona l mirrors as in the crosshair design of our vertical mirrors. To d ecrease this scattering loss the roughness of the vertical mirrors was further reduced using an isotropic etching in KOH:IPA solution with nitride as the masking layer.

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63 KOH:IPA::3M:2M solution was used at 50C, to anisotropically etch the vertical mirrors. Using this there was visibly no damage to the co-bonded Pyrex window. Experiments were conducted with various et ch times and temperatures and the best results were found when etched for 1 hour at 500C. Etch rates increases with higher temperatures and results in comparatively rougher surface than at lower temperatures. Figure 25 shows the optical profilometer scans of the vertical mirrors. At this roughness level th e theoretical sca ttering loss from these mirrors was approximately 24% when used with a 632.8nm la ser, at an incident angle of 45, and the measured loss was found to be around ~28%. Th is scattering loss was further reduced to 17% with an IR (infrare d) laser of 780nm IR diode laser agai n at an incident angle of 45. The reflectivity of these Si vertical mirrors was improved by coating them with thin film of Au as discussed in next chapter. The improvement in the average sidewall an gles of the vertical structures is shown in Figure 26. The average sidewall angle was measured to be 90.08 with a standard deviation of 0.113. This improvement in verticality comes under the expense of the kind of vertical structures which can be etched using the two step DRIE method, and KOH:IPA polishing, as the vertical surfaces have to be near the (110) planes to expose the (110) planes after polishing. Figure 26 sh ows the variation in sidewall angles across the wafer. Again very uniform sidewall angles were noticed.

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64 Figure 24: Optical Profilometer Scan of the Vertical Surface After O2 Plasma Etching, Which Removes the Polymer From the Sidewall Surface.

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65 Figure 25: Optical Profilometer Scan of the Vertical Mirror After O2 Plasma and Isotropic Etching in KOH:IPA Solution For One Hour, Ra = 38.97nm. 89.91 90.2 90.08 90.21 90.07 90.02 89 89.2 89.4 89.6 89.8 90 90.2 90.4 90.6 90.8 91 123456 Sample numberSide-Wall Angle Figure 26: Sidewall Angles After Two Step DRIE and One Hour KOH:IPA Polishing.

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66 7 METALLIZATION OF VERTICAL MIRRORS WITH TRANSPARENT PACKAGE WINDOW Highly reflective mirrors are required for many optical applications. The vertical mirrors fabricated by processes described in previous chapters have Si surface as the mirror surface. In order to increase the optical reflectivity of the Si vertical mirrors they needed to be coated with meta l. However, the glass lid, as shown in Figure 16 needs to be transparent so that the probing beam can opti cally interact with the packaged devices. Metal was required on top of the package fr ame to allow thermo-compression bonding to surface micromachined chip, or to act as the adhesion layer for indium (In) where hermetic sealing is required. To achieve th is task, a self-masked photolithography step followed by sputtering and liftoff was develo ped. The idea of self-masking lithography for selective lithography and liftoff process is shown in Figure 27 and the process is shown in Figure 28 and described below.

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67 (a) (b) Figure 27: Process For the Se lf-Masking Liftoff Process. (a) Lithography Using Negative PR on the Chip With Flood Exposure From the Back Side, (b) Metallization and Liftoff Leaving Metallized Vertical Mirrors and Transparent Optical Window.

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68 Figure 28: Cross Sectional View of the Self-M asking Liftoff Process. (a) Vertical Mirrors and Package Frame Etched in Si, (b) Nega tive Photoresist Was Spun on the Features and Was Exposed from the Pyrex Side, (c) The Exposed Photoresist Gets Entangled and Remains After Developing, (d) Gold Was Sputtered on the Mirrors and Photoresist Was Liftoff in Acetone, (e) Metallization and Lifto ff Leaving Metallized Vertical Mirrors and Transparent Optical Window. 7.1 Liftoff Using Self -Masking Technique Futurrex negative photoresist NR9 1000PY was spun into the cavity created by prior etches (back side of Si), at 3000rpm and soft baked at 150C for 60 seconds. The resist was flood exposed from the Pyrex side (f ront side of Si) of the bonded structure in EVG 620 mask aligner as shown in Figure 27( a). The photoresist in the windowed area was thus exposed, while the brief exposure and vertical geometry prohibits the exposure of resist on the sidewalls and package frame surfaces. The resist was hard baked on a hot plate at 100C for 60 seconds and developed in Futurrex RD6 developer. The resist remains only on the exposed window after devel oping. Ti/Au layers were then sputtered

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69 onto the chip. Liftoff in acetone was performed to remove the resist and metal from the window region. This leaves the sidewalls and top surface metallized for high optical reflectivity, and Au-Au bonding to active part s respectively. Figure 28 illustrates the process flow to metallize th e vertical mirrors and liftoff the gold from the package window [14]. A thin coating of 500nm has been shown to be sufficient for Au-Au thermo-compression bonding [75] but in our experiments 1 m thick Au coating with 100nm Cr layer was used since it was noti ced that the thermo -compression bonding of small features (50m) was stronger with thicke r Au layer, as was also described in [76]. Figure 29 shows the optical image of the ve rtical mirrors with metal coverage on the mirrors using conventional lithogra phy (Futurrex NR9 PY1000, 3000rpm, 198mJ/cm2 exposure dose and 10 seconds de veloping) and liftoff. As s hown in Figure 29, Au was lifted off from a large portion of the mirror. It was concluded that with normal exposure and developing time the photoresist on the sidewalls was not fully removed during development due to the topography of the stru cture. This results in the removal of the metal from the window and some portion of th e sidewalls after liftoff, resulting in the uncoated mirror surfaces as shown in Figure 29. Hence due to the topography of the struct ure and to obtain uniform metal coating on the sidewalls with transp arent package window a non c onventional lithography was developed. The spin speeds, exposure dose and developing time were changed on two different negative photoresist s (Futurrex NR9 1000PY & NR9 1500PY) to obtain the best metal coverage on the vertical mirrors and package frame with a transparent glass lid after liftoff. With thinner photoresist (PY1000) faster spin speed gave better coverage

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70 while slower spin speed gave better cove rage with thicker phot oresist (PY1500). The exposure dose was changed to just expose the photoresist on the glass window from the backside without exposing the photoresist on the ve rtical mirrors which were self-masked with the vertical Si structur es. Too much or too little dosag e results in undesirable metal coverage on the vertical mirrors or gla ss lid. Longer than normal developing time was used to ensure that all the photoresist fr om the vertical mirrors was removed leaving photoresist just on the glass window. Figure 29: Metal Coverage on the Vertical Mirrors After Sputtering and Liftoff Using Standard Lithography. 7.2 Improving the Metal Coverage Due to the diffraction of the UV (ultraviole t) light the photoresist on the sidewalls gets exposed with increase in the exposure dose. This also resulted in liftoff of the metal covering the vertical mirror re sulting in a profile similar to Figure 29. Thus it was important to control the exposure dose to minimize the diffraction of light.

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71 To further improve the metal coverage care was taken to get rid of any air bubble while dispensing photoresist on the samples. An air bubble was formed due to the surface tension of the photoresist which prevents coating of the photore sist at the intersection of the cross-hair. As a result the metal gets sput tered directly on the Pyrex and could not be liftoff as shown in Figure 30. To overcome this problem micro-pipettes were used instead of conventional dropper which forced the ph otoresist at the in tersection area. 2.0 l photoresist was dispensed at each quadrant of the cross-hair. This resulted in better photoresist coverage and minima l air bubble formation at the cross-hair as shown in Figure 31. It should be noted that a spray coat ing system, if available, could be used for coating the high aspect ratio structures whic h can circumvent the need for using micropipettes. Thus the metal coated vertical mirrors, with transparen t package window were fabricated. These vertical mirrors can then be bonded to other MEMS chips to assemble various devices. Here these mirrors will be bonded to a MEMS torsion mirrors chip to assemble CCRs. The package frame area of th e package lid is bonded to a corresponding area of the MEMS chip as di scussed in Chapter 7.

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72 Figure 30: Metal Coverage on the Vertical Mi rrors With Transparent Package Lid Using NR9-1000PY Photoresist, Spin Speed – 3000 rpm, Exposure Dose – 360mJ/cm2, Developing Time – 3 minutes. Photoresist Wa s Dispensed Using Conventional Dropper. Figure 31: Metal Coverage on the Vertical Mi rrors With Transparent Package Lid Using NR9-1000PY Photoresist, Spin Speed – 3000 rpm, Exposure Dose – 360mJ/cm2, Developing Time – 3 minutes. Photoresist Was Dispensed Using Micro-pipettes.

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73 8 SURFACE MICROMACHINING: MEMS TORSION MIRRORS MEMS fabrication can be classifi ed into two different kinds: bulk micromachining and surface micromachining. In various fabrication schemes it is desirable to perform both surface and bulk mi cromachining, like the fabrication of CCR. Usually these two different schemes are perf ormed on two different wafers/dies and the final dies are mated together to assemb le the final device. In this work bulk micromachining was performed to fabricate the vertical mirrors and the packaging lid as discussed earlier. Surface micromachining was then performed to fabricate torsion mirrors or other electrostatic actuators on separate wafers. Finally the two structures were bonded together at die level to assemble the final device. Though the processes described here can be used to perform wafer level p ackaging, chip level packaging was performed in this work. 8.1 Surface Micromachining The basic difference between bulk micr omachining and surface micromachining is that bulk micromachining is mainly s ubtractive in nature, where the bulk of the substrate is etched, whereas surface micromach ining is mainly additive in nature where various layers are deposited on top of each other followed by selective removal during the processing. Usually structural layers are made of polysilic on, with sacrificial material such as silicon dioxide sandw iched between layers of polys ilicon. Both materials are

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74 commonly deposited using low pressure chemical vapor deposition (LPCVD). The advantage of using surface micromachining is that freestanding and moveable devices can be readily fabricated by stacking multiple layers of materials and removing the sacrificial layer. The processe s are also highly compatible w ith IC processes. The surface micromachined devices suffer from the thin film stresses. Th e film stresses can result in delamination, cracking and/or formation of vo ids in the final device or surface curvature. Nearly all the deposited films have residual stresses, due to mismatch in the thermal expansion coefficient, non unifo rm plastic deformation, lattice mismatch and/or growth processes. To reduce the surface curvature which was caused by the stresses in the films, low stress Si3N4 was used as the structural layer and was sandwiched betwee n thin layers of Au to minimize the stress and to reduce the surface curvature. The process was named NitrideMEMS (NMEMS) and is discussed below. 8.2 Nitride MEMS NitrideMEMS is a single structural laye r, four mask level surface micromachining process. Several unique steps enable its appl ication in optical MEMS devices, and allow packaging of sensors and actuators. The initia l metal layers consist of sputtered Ti/Au, this layer defines the bond pad area and the elec trode areas. The sacrificial material is a high temperature resistant, co-developable polyimide, PIRL III [77]. The structural material is a sandwich of Au/Ti, low stress Si3N4, and Ti/Au. The polyimide sacrificial layer is removed after processing using oxygen plasma to circumvent the stiction problem, which is usually an issue with wet release [78]. Active torsion mirrors were

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75 fabricated using Si3N4 as the structural layer sandwiched between Ti/Au metal films to allow electrostatic actuation of parts, and provide high reflectivity [79, 80]. This active parts die also contains an open area, which is slightly wider than the width of the vertical mirror surface area, and an corresponding area for the Au coated package frame area. A solid model rendering of the layers comprisi ng a torsion mirror is shown in Figure 32. The fabrication process is detailed below. Figure 32: Mask Layers as Applied to Thin Films for NitrideMEMS Process. Dark Area is Silicon Nitride-Passivated Si Wafer. Botto m Metal0 Defines First Ti/Au, Anchor Opens Holes into PIRL III Sacrificial Material, Ho leMetal1 Removes Second Au/Ti Structural Metal Layer. Struct. Patterns the Top Ti/Au, Structural Silicon Nitride, and Au/Ti Structural Layers. 8.3 Fabrication A 500 m, SSP (single side polished) silicon wafer was used as the active device substrate. 3 m thick plasma enhanced chemi cal vapor deposition (PECVD) SiO2 film was deposited on top of Si wafer to preven t leakage current thr ough the Si wafer. 600nm thick low pressure chemical vapor deposition (LPCVD) Si3N4 layer was then deposited

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76 using SiH2Cl2 and NH3 at 850C to passivate the forthcom ing layers from the substrate. A 30nm/300nm titanium/gold layer was next s puttered onto the surface using a multitarget sputtering system. The metal was patter ned using a Metal0 li ght field mask using positive resist (Shipley S1813, 1.6 m thickness, Microposit MF319 developer), and post baked at 130C for 90 seconds. The gold was etched in Transene Gold Etch TFA for approximately 120 seconds or until the exposed gold was removed. The exposed Ti layer was etched using Transene Ti Etch TFTN et chant until removed. This is shown in Figure 33 (a). This metal layer forms the bottom electrodes. Figure 33: Solid Model of the NMEMS Fabr ication Steps for Torsion Mirrors. (a) Deposition of Passivation Dielectric Followe d by Bottom Electrode Metal Deposition and Patterning, (b) Deposition of the Sacrifici al Layer and Patterning of Anchor Holes, (c) Deposition of Ti/Au and Isolat ion Pattern, (d) Low Stress Si3N4 Was Deposited Followed by Ti/Au. The Layers Were Pattern ed Using Structure Mask, (e) Sacrificial Layer Was Removed Using O2 Plasma. The substrate was next primed by spin coating using Brewer APX-K1, and the sacrificial material, PIRL III, was subse quently spin coated to a nominal 3.5 m

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77 thickness, pre baked at 120C for 90 s econds, and post baked on a 250C vacuum hotplate for 15 minutes or in a vacuum oven at 300C for 1 hour. A layer of S1813 was then spin coated onto the PIRL III, and exposed using the Anchor mask. The resist was developed for normal process times, and then over-etched to co-develop the underlying PIRL III layer, until the underlying metal or nitride was fully exposed. The resist was then removed using solvents and brief oxyge n plasma descum. The resulting anchor profile was tapered. The resulting tape red profile enables good conformality of subsequent deposited layers. Th is is shown in Figure 33(b). A 300nm/30nm Au/Ti layer was sputtered ont o the surface. It a dheres well to the underlying metal or creates a w eak bond with nitride; both can be used to our advantage. This layer was patterned using the Ho leMetal1 darkfield mask, (S1813, 1.6 m nominal thickness, 130C post bake) and wet etched us ing the aforementioned metal etchants, as shown in Figure 33(c). This s ubtractive patterning allows el ectrical isolation of portions of this bottom metal portion of the structural element, wh ich was useful for routing, packaging, and electrical switching applications. Next, a 2.0 m low stress Si3N4 structural dielectric layer was deposited by PECVD at 250C (Appendix A). A top metal la yer (Ti/Au10/90nm) was then sputtered onto the unpatterned nitride su rface. The Struct mask wa s patterned (Shipley S1827, 3.3 m nominal thickness, MF-319 developer), and the resist was hard baked. This serves as the mask for the entire Au/Ti/SixNy/Ti/Au structural material stack. Wet etching of the Ti/Au layer was performed, followed by CF4-based nitride reactive ion etching, and wet etching the underlying Au/Ti. Th is is shown in Figure 33(d).

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78 Typically, the wafers are protected with phot oresist and diced at this stage, prior to individual die release, though wafer-level re lease was possible. For release, either of two methods may be used. PIRL III can be removed, even after high temperature processing (to 350C). To rel ease the parts, etching in TMAH-based developer (MF319) is suitable. Etch rates are approximately 5 m/minute at room temperature. Release holes designed into the Struct mask can speed re lease, though the remaining materials do not appear visibly affected by rele ases as long as 24 hours. Long structures typically need a CO2 critical point dry step after rinsing in water/isopropanol to avoid sticking of parts due to surface tension. Stiffer m echanical structures may not require this step. After wet release, a thin scum of resi dual polymer has been noted; this can be removed with a short (~2 minutes) oxygen plasma etch. Stiction is so metime an issue with wet release process. To prevent stiction, dry release was performed in an isotropic oxygen plasma etcher (Tepla M4L). Though longer release times are required and thermal-induced surface roughness has been noted at high RF power. The roughness is seen only in areas not anchored to the substrate. It is hypothesized that the fr ee-standing structures become hotter than the substrate during the release, causing some re-crysta llization of the gold. The process was optimized to decrease the release time and roughness, which increases optical reflectivity. The release parameters are listed in Appendix A. The released torsion mirrors is shown in Figure 33(e). Figure 34 shows the SEM image of the NMEMS die with various features noted on the Figure 32. 100 x 100 m mirrors were fabricated in an array of 5x5 or 8x10 in each of 4 quadrants. Th e space in between the different quads was metallized so that the vertical mirrors can be bonded to the NMEMS chip. The Au coated

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79 package frame area is also designed and fabr icated in the same step. The package lid (vertical mirrors and package frame) can be bonded to the active torsion mirror die by thermo-compression bonding (AuAu or In-Au) using a flip-chip bonder to assemble the package CCR, which will be discussed in the packaging section. Mirrors with different resonant fre quencies were fabricat ed ranging from 20 KHz to 50 KHz, with modulati ng voltage ranging from 6-20VP-P for suitable scan angle. The mirror curvature was measured using Veeco optical profilometer. The optical scan is shown in Figure 35. The mirror curvature wa s measured to be anywhere between 2080mm at different spots of the chips with RMS roughness of ~5nm, as shown in Figure 36. Figure 34: Optical Image of the Active MEMS Device Chip With Torsion Mirrors Shown in the Inset. Torsion Mirrors Au Coated Package Frame Area Opening for Vertical Mirrors

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80 Figure 35: Optical Profilometer Scan of a Si ngle Torsion Mirror to Measure the Mirror Curvature After Release. Figure 36: 2-D Analysis of NMEMS Torsion Mirrors Using V eeco Optical Profilometer.

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818.4 Modeling and Simulation Using Finite Element Analysis (FEA) A complete finite element analysis (FEA) model was created using ANSYS Multiphysics 10.0 software to simulate th e torsion mirror for further performance improvement and design optimization. The model was based on a reduced order modeling approach, ROM144, developed by ANSYS, Inc. First, the micromirror structure was meshed using structural elemen t, SOLID45, as shown as green areas in Figure 37(a); second, th e air region including fringe fi eld areas, were meshed using electrostatic element, SOLID122, as shown as purple in Figure 37(a). Then coupled field simulations were done between electrostatic and structural domain s to calculate mirror deflections under certain driving voltage, as shown in Figure 37(b) for a mirror movement for a 9V driving signal. Figure 37: Finite Element A nalysis (FEA) of Torsion Mirro r. (a) Coupled Field Model of Structural and Electrostatic Domains, (b) Mirror Deflection Under 9V Driving Voltage. In the reduced order mode ling, several master nodes were defined at the key points for the micromirror, such as the ends and the center of the mirror plate and the

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82 torsion bars. Then the modal behaviors were simulated under certain test loads applied onto the mirror plates, such as pressures a nd accelerations. These modal behaviors were then extracted into a circuit model. Then the following simulations can be performed using this equivalent circuit model without going back to use full finite element model. This allows significant savings in simulation times, such that many properties, for example, mirror deflections under swept drivi ng voltages or pressure, pull-in voltage, resonant frequencies, can be calculated with in reasonable time frame. The model also allows pre-stress harmonic analysis to eval uate resonant frequency change due to the applied voltage for spring softening effects, as well as nonlinear transi ent analysis. It is also generated using ANSYS parametric design language (APDL), so that each dimension of the mirror structure can be ch anged parametrically and new performance can be simulated easily. This is especially us eful and efficient for large amount of design optimizations once the reduced orde r model analysis is combined. Various parameters were changed to de termine optimum design of the torsion mirrors. The pull-in voltage, resonant fre quencies and dominant modes of operations were calculated using ANSYS. The spring thic kness and the spring width were varied to see the effect on MEMS structures. Also it was noted that with the change in spring thickness and spring length the dominant mode s in which the mirro rs modulate changes from mode 1 and mode 2 to mode 1 and mode 3, 4. Figure 38 and Figure 39 show the changes in pull-in voltage and resonant fre quency when parameters of the spring were changed. In this instance, spring is define d as the beam running between the two anchors and center width is the width of the part jo ining the mirrors and the spring. Figure 40

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83 shows the harmonic transfer function amplitude for 50V polarization voltage. The peak shifts left and right with ch anges in spring parameters. Figure 38: Changes in Pull-In Voltage and Re sonant Frequency of the Torsion Mirrors With Changes in Spring Thickness. Figure 39: Changes in Pull-In Voltage and Re sonant Frequency of the Torsion Mirrors With Changes in Center Width.

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84 Figure 40: Frequency Response of the Mirrors for 50V Polarization Voltage.

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85 9 PACKAGING AND ASSEMBLY MEMS packaging techniques are borrowed fr om IC industry, but the functionality of MEMS devices differ a lot from the IC devices. MEMS packaging presents various challenges which were never faced by the IC packaging industry due to the diversity of MEMS devices and the requir ement that many of MEMS devices are in continuous and/or intimate contact with their envi ronment. Even though ap plication specific packaging is not an efficient method of sealing MEMS based products, a new and specialized package is designe d nearly for each new MEMS device. Consequently, most manufacturers find that packag ing is the single most expens ive and time-consuming task in a MEMS product development program, and is also often the firs t to influence the system response. Device protection is an important elemen t in MEMS packaging because debris and moisture can adversely affect its functionality. Various MOEMS devices also require an optically transparent window to obtain op tical access to the parts while providing protection from the environment. These ME MS devices use active mechanical and/or optical elements such as optical switches, t iltable mirrors, and various optical sensors. The active structures in these devices must be free to move and an optical access is required for MEMS devices that have mirrors and optical elements. Optical access to non-optically active MEMS devices may also be required for inspection, observation, and

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86 performance characterization of moving elemen ts. The coefficient of thermal expansion (CTE) of the package materials should be equa l to or slightly greater than the CTE of silicon for reliability. Hence to package th e MEMS sensors, a transparent window and electrical connections to the outside world need to be integrated into the design. Processes which can create a package and simultaneously assist in the fabrication of the needed optical surfaces will be beneficial toward meeting th e growing need for low cost packaging solutions. Past works have pres ented various methods and approaches to package an optical device with integrated window for optic al access [81, 82]; however these techniques requires extra complex processes to packag e 3-D optical structures. In many devices hermetic sealing is required, allowing only a negligible amount of gas to be exchanged between the passages in the MEMS body and the atmosphere during the life of the MEMS, in order to prev ent the device from becoming contaminated. Moisture can be readily absorbed by some materials (for example Al) used in MEMS device fabrication. This can cause failure of MEMS devices due to stiction, swelling, stress, and possibly delamination at vari ous stages. To minimize these failure mechanisms, MEMS packages needs to be he rmetically sealed. Also low temperature packaging is desired as high temperature ca n cause thermal stress/mismatch problems. Developing a low temperature packaging sche me, which can be used to hermetically package various devices at die and/or wafer level, will be beneficial for the development of the MEMS industry; such a packaging scheme is discussed in this chapter.

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879.1 MEMS Packaging Techniques: Prior Art MOEMS package should be designed such th at it can provide mechanical support, protection from the environment, optical access to the packaged devices, electrical interconnects and thermal management. MEMS packaging can be largely divided into two different categories, integrated encapsulation and wafer/chip bonding. 9.1.1 Integrated Encapsulation Extra process steps are required for inte grated encapsulation, which requires the deposition, patterning and etch ing of encapsulating film. After the fabrication of MEMS device, and before their release another thick layer of sacrificial layer is deposited and patterned. After that a package cap layer is deposited and patterned to form a package shell enclosing the MEMS devices. Release hol es are patterned on these shells, which are later sealed after the devices a nd the package has been released. Typical examples are an epitaxial silicon cap to seal microstructures [83] and a silicon nitride shell to seal mechanical re sonator for wireless comm unication applications [84]. Integrated encapsulation process is developed while the device wafer is under processing and hence this pro cess is processing dependent. 9.1.2 Wafer Bonding Wafer bonding technique uses a secondary wafer to encapsulate the device wafer after the device wafer was fabricated. Va rious bonding methods li ke anodic bonding, fusion bonding and intermediate la yer bonding (eutectic, glass frit, Au-Au) can be used to encapsulate microstructures by using a second substrate of silicon, glass or other

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88 materials [85, 86, 87, 88, 89, 90, 91]. Surf ace preparation, high temperatures, and/or electric potential are the drawbacks of wafe r bonding process. Localized heating can be used to alleviate some of the drawback s which occur due to the high temperature requirements of bonding process. Figure 41 shows the bonding technique tree. Figure 41: Flow Chart Showing Various Bondi ng Techniques Which Can Be Used for MEMS Packaging. 9.1.2.1 Bonding Without Intermediate Layers This bonding technique doesn't require any intermediate layer for bonding two substrates. Usually surface pre treatment is pe rformed to make the surfaces agitated. For reliable and repeatable bonding, the bonding su rfaces need to be of highest quality, free of defects and contaminations. This technique can be divided into two: 9.1.2.1.1 Anodic Bonding Si and glass wafers are usually bonde d together using anodic bonding. High DC voltage is used to generate large electrostatic forces to pull the wafers together. It is a relatively simple and safe pro cess, which is widely used in microsystems technology. By using anodic bonding, high bond st rengths and hermetic seali ng can be achieved. Other

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89 advantage of anodic bonding is that the bond temperature range from 300-500C, which provides good process temp erature compatibility. For anodic bonding, one of the two surfaces to be bonded must be made of sodium-containing glass which has its thermal expansion coefficient adjusted to match that of silicon, for examples Corning Pyre x # 7740. The wafers to be bonded are stacked together and are heated to a temperature of 300-500C. At this temperature the sodium ions of the glass become mobile. By applyi ng a negative potential (200V-1000V) to the Pyrex the sodium ions drift away from the bonding interface, creating a sodium (Na+) depleted zone, leaving oxygen ions (O2-) near the bond interface. As a result of the strong electrostatic field, the wafers are pressed together at th e atomic level, and by field assisted oxygen diffusion and anodic oxidati on, oxygen bonds are formed between glass and silicon (Equation 9). The bonding setup and formation of bonds are shown in Figure 42. e SiO O Si 4 22 2. Equation 9 (a) (b) Figure 42: (a) Anodic Bonding Setup, (b) Formation of Oxygen Bonds.

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90 Anodic bonding is a very safe and reproducible pr ocess, producing strong, hermetic bonding [92]. For successful bonding usua lly double sided wafers are used, with precautions taken to keep the surfaces clean and particle free. Single crystal and polycrystalline silicon, thermal oxides, C VD oxides, metals and silicon nitride (CVD) layers deposited on silicon wafers can be bonded using this technique [93]: 9.1.2.1.2 Fusion Bonding Unlike anodic bonding, which is field a ssisted, fusion bonding relies on chemical forces. Clean surfaces are br ought together under pressure and high temperatures for fusion bonding [94]. Hydrati on process is used to introduce oxygen-hydrogen (O-H) bonds to the interface. This can be done by soaking the wafers in HNO3 or H2O2-H2SO4. After the surface pretreatment the wafers are stacked together under pressure and are then annealed together at about 1000C to create strong Si-O-Si bonds as a dehydration process as shown in Equation 10. Si O Si O H Si OH OH Si 2) (. Equation 10 9.1.2.2 Intermediate Layer Bonding This is a process where two substrates ar e bought together. Either one or both of them are coated with an intermediate layer. This intermediate layer is sandwiched between the two substrates. The stack is then subjected to pressure, to bring the two surfaces closer and is usually heated to a certain temperature. Upon cool down the substrates gets bonded to each other. There are various types of intermediate layers which can be used to bond two substrates.

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919.1.2.2.1 Eutectic Bonding Eutectic bonding is achieved by the diffusion of atoms of eutectic alloys into the atomic structures of the wafers to be bonde d together. Eutectic bonding uses silicon metal alloy or other alloys, such as Si-Ag, Si-Au, Si-Al etc. to form solid bonding of the wafers. Gold silicon eutectic formation occurs at 363C for 19% silicon as shown in the phase diagram in Figure 43 [95]. Eutectic bonding is performed by placing the Si wafer on top of the wafer with gold on it. Applying the co ntact force and increasing the temperature above the Au-Si eutectic temperature of 363C results in the diffusion of Si into Au, and formation of eutectic compound, at the interf ace and eutectic bonding at cool-down. It is interesting to note that below the eutectic temperature, gold diffuses into the silicon rather than the silicon into the gold and give s rise to silicide formation (SiAu3) [95]. The setup for the eutectic bonding is shown in Figure 44. Figure 43: Binary Phase Diagram of Au-Si Alloy.

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92 Figure 44: Setup for the Wafer to Wafer Eutectic Bonding. 9.1.2.2.2 Adhesive Bonding This method uses an adhesive as an in termediate bonding layer. Several different polymers have been used as intermediate material for adhesive bonding, which includes wax, polyimide, epoxies, photoresists, etc. Adhesive bonding offers some advantages over other bonding as various kinds of substr ates can be bonded together, without any surface pretreatment. It is a low cost met hod and low temperature bonding is possible. Also substrates with various CTE can be bonded together as elas tic polymers can reduce the stress between the bonded substrates. Th is kind of bonding technique does not result in hermetic sealing because of the out gassing of the adhesi ve layers. Also the long term reliability of these kinds of bonds is questionable. 9.1.2.2.3 Glass Frit Bonding This method uses a low melting point gl ass to bond two surfaces together. This glass in the form of paste consists of glass powder, organic binders and solvents. This is a thermo-compression bonding where the stack of wafer is subjected to heat (~450C) under pressure. Prior to bonding a multistep thermal conditioning is necessary to

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93 transform the glass frit paste into a real glass. Hermetic sealing is achieved by using glass frit bonding; however it exhibi ts strength reduction over a pe riod of time due to stress corrosion. 9.2 Assembly of CCR 9.2.1 Au-Au Thermo-Compression Bonding This is the technique where temperature a nd pressure is applied simultaneously to bond two surfaces coated with Au. Thermo -compression bonding can be achieved by various metals but gold is preferred because of its high resistance to oxidation and low modulus. Gold to gold thermo-compression bondi ng is an affective te chnique to achieve low wafer or chip level bonding without the use of electric field. Th e technique is also less dependent on surface cleanliness when co mpared to fusion and anodic bonding. A thin coating of 500nm has been shown to be sufficient for Au-Au thermo-compression bonding [96], but in our experiments 1 m thick Au coating w ith 100nm Cr layer was used since it was noticed that the thermo -compression bonding of small features was stronger with thicker Au layer as was also described in [97]. Au-Au bonding can be reliably achieved at 300C-350C at various bond pressures. 9.2.2 CCR Assembly Using Au-Au Bonding Au-Au thermo-compression bonding was used to assemble the CCR. The metallized vertical mirrors were bonded to the active MEMS die using Au-Au thermocompression bonding, using a flip-chip tool (FineTech Pico5). The bonding was carried out at 320C for 2 minutes with a 40MPa pressure The bonded CCR with transparent

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94 package window for optical access is show n in Figure 45, looking through the package window. The glass lid protects the underlying optical stru ctures from dust and other contaminants. However, at electrical routin g isolation areas topogra phy is formed due to non-planar feature of the package frame ar ea on the active MEMS die, the vertical structures does not completely seal the de vice to protect it from moisture and liquid ingress. Coating the whole assembly with a th in layer of parylene using Labcoater 1 PDS 2010 parylene deposition unit formed a better seal. Specialty Coating System’s MEMS compatible A-174 silane solution in 100% IPA was used as the adhesion promoter. Coated devices were dipped in IPA for more than 2 hours without any leakage. The devices were tested before and after Parylene deposition without any noticeable difference, however the devices failed th e helium leak tests (hermetic tests).

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95 Figure 45: Optical Image, Taken Through the Py rex Package Lid, Consisting of Nitride MEMS Active Torsion Mirrors and Passive Vertical Mirrors. 9.3 Hermetic Sealing Techniques The MEMS packaging processes must fulf ill various stringent requirements. It should not damage the parts which are to be packaged. Low temperature bonding is required to protect the fragile MEMS parts, the bonding process should be compatible with other MEMS processes, and preferably it should use the pre-existing IC packaging tools. Hermetic sealing is required in many MEMS devices. The packaging not only protects the devices from physical damage during normal handling but it also minimizes the exposure of the p ackaged devices to the surrounding like gas, moisture etc. There are various techniques which can be used to achieve hermetic sealing. For example anodic bonding and fusion bonding both can result in he rmetic sealing but th e disadvantages of using them they are high temperature bonding, they require clean surfaces to achieve

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96 good bonding results and surface plan arization is required to ac hieve hermetic seal in case of surfaces with topography. The major disadvantage is that they require high bonding temperatures which can damage the de vices or can cause the thermal stress issues. Micro shells [98] can be used for he rmetic sealing as disc ussed before and the schematic for such packaging scheme is shown in Figure 46. MEMS devices were fabricated using standard surface micromachin ing processes. Before the structures are released, a thick sacrificial layer is deposited covering the structures. Micro shell material of desired thickness is then deposited on top of the second sacrificia l layer. Micro shell layer is then patterned to open etch holes. Fi nally the devices were released to etch away the sacrificial materials. The etch holes were then covered by another thin film deposition step. Hermetic packaging can be achieved by this method; however the thickness of the micro shells is limited by the thin film depos ition step. There is a big concern if the thin micro shells can survive the high pressure plastic molding during the final packaging process.

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97 Figure 46: MEMS Packaging Scheme Using an Integrated Encapsulating Micro Shell. 9.3.1 Low Temperature Hermetic Sealing Methods To overcome the drawbacks which occurs while using global heating or micro shells for packaging, localiz ed heating was developed. Th is can be achieved by various methods like laser welding, micro heaters or nanofoils. 9.3.1.1 Laser Welding Laser welding can be used to locally heat the bonding material which upon cooling solidifies and bond two surfaces. Figur e 47 shows the setup of the laser welding process which can be used for MEMS packaging. Pulsed laser beam was aimed at the bonding area, while the area which is not to be bonded is protected by a mask [99, 100]. The drawbacks of using laser welding method s are that the laser power density has a Gaussian distribution, which results in a circular bonding area. In case of the fine bond areas this might cause bonding i ssues. Also large laser energy can damage the wafers and special laser tools are required to obtain pulsed laser outputs aimed at specific location.

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98 Figure 47: Experimental Set up of Glass-Silicon Bonding Usi ng Indium as Intermediate Layer. Laser is Used to Locally Heat the In. 9.3.1.2 Micro Heaters Localized heating using micro heaters is another method which overcomes the problems which arise from the global heating methods described before [101]. Resistive micro heaters are used to provide localized heating. Current is passed through these heaters to generate heat. To control the bondi ng it is necessary to characterize the heat transfer properties of the microheater materi al. Various kinds of bonds such as eutectic bonds, fusion bonds, solder bonds can be created using the localized heating method. Heating is achieved by using resistive sources such as electrical wiring. In many cases, the electrical wiring is not preferred. 9.3.1.3 Nanostructure Foils These [102] can be used as a local heat source to create hermetic packages at room temperatures. This is a solder based he rmetic seal method. But unlike solder reflow method which requires the use of flux and hi gh temperature heating, nano foils provides flux free soldering process. The multilayer nanof oils consist of thousands of alternating

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99 nanoscale layers comprised of elements with large negative heats of mixing, such as Al and Ni. The foil is sandwiched between free st anding sheets of solder and the assembly positioned between the package housing and lid. A reaction is initiated within the foil with a small thermal or electr ical pulse. Heat generated by the reaction melts the solder on either side of the foil and consequently bonds are substrates. Figure 48 shows the schematic view of packaging ME MS devices using nanofoils. Figure 48: Schematic View of Packaging Us ing Nanofoils for Localized Heating. Again this method is highly dependent on th e heat transfer char acteristics of the nanofoils. Table 3 shows a comparison on various bonding techniques.

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100 Table 3: Comparison of Va rious Bonding Techniques. Bonding Technique Surface Quality Sensitivity Bonding Temperature (C) Hermetic Sealing Need of Planarization Reliability Anodic High 300-500 Yes Yes Good Fusion High 800-1000 Yes Yes Good Eutectic Medium 300-500 Yes No Good Intermediate Layer Low Variable Variable No Variable Encapsulating Micro Shell Low NA Yes No Good Micro Heaters Low Variable Yes No Good Nanofoils Low Variable Yes No Good

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101 10 HERMETIC PACKAGING WITH LATERAL FEED-THROUGHS In various applications device needs to be hermetically sealed to improve the functionality and life time of the device. Op tical MEMS packages often are required to provide both optical and electrical access, he rmeticity, mechanical strength, dimensional stability and long term reliability. Low temperature, zero level, herme tic packaging for MEMS/MOEMS devices using indium/gold as intermediate layers, to assemble and package the CCR is presented here. Indium is a low melting point metal ( 157C) and is soft enough to allow conformal thermo-compression bonding. Due to its soft ness it also absorbs any stress which might arise due to the mismatch of th e CTE of the bonding materials. Corning Pyrex 7740 glass wafer was used to form the protection caps because it can be anodically bonded to silicon wafers and also since it is mechanically robust, chemically stable, and transparent to white light. In addition, the 7740 glass has a similar coefficient of thermal expans ion (CTE) to silicon wafer so that it has better thermal stability in the bonding interface. Hermetic seal can be obtained using various methods as discussed before. But most of them are high temper ature methods which are not suitable for sensitive MEMS devices. The localized heating methods provide an alternativ e but they either require

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102 special tools or are highly dependent of the heat transfer characte ristics of the micro heaters/nanofoils. The packaging scheme described here uses a Pyrex wafer as a handle wafer and as the optically transparent pack age lid. The co-bonded Si wafer was patterned, etched and metallized using the DRIE process described before to fabricate vertical mirrors and package frame. After polishing, metallizati on and liftoff was perfor med on the vertical mirrors to get metallized mirrors and transp arent package lid. The nitride MEMS chip with torsion mirrors have all the metal rou ting to make the conne ctions to the outer world. Au-Au thermo-compression bonding was unsuccessfully tried to form a hermetic seal. The on chip metal feed-throughs result s in topography on the chip which prevents the sealing of the fina l device. Indium metal with low melting point was then used to make the bond between the ve rtical mirrors and the NMEMS chip, forming a hermetic seal. 10.1 Low Temperature Hermetic Bonding Using In-Au Au-Au thermo-compression bonding was successfully performed to assemble the CCR as discussed before. However, due to the lateral interconnects on the device chip in the CCR an indentation was formed between th e isolated metal traces. Because of this indentation, when the packag e lid was bonded to the active device chip using Au-Au bonding, gaps were found near the indented areas. This prevents the devices to be hermetically sealed. Figure 49 shows a SEM im age of a test chip with the dimension of package lid chip bonded to the NMEMS device chip. The electrical routings which are isolated to each other are al so shown in the SEM image.

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103 Figure 49: SEM Image of a Test Sampl e Bonded to the NMEMS Device Chip. Figure 50: Optical Image of the Bond Interface. Figure 50 shows the zoomed in view of the bond interface showing the top package lid frame being bonded to the bond frame area on the NMEMS device chip. The voids which are formed due to the indented bond frame area on the NMEMS chip can be Leak Site Electrical Routing Pads

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104 clearly seen. This is caused because of the is olated lateral electrical routing to modulate the torsion mirrors. Planarization is not po ssible on this chip because of the fragile MEMS structures. Hence Au-In solder bonding was used to cover these voids and get a hermetically sealed package. Low temperature hermetic seal package w ith lateral feed-thr oughs for electrical routing is presented here using In-Au alloy as the bonding material. The bonding was done at 160C-200C and it produces high temper ature bonds (454C) [103]. When In is heated to 157C it melts and dissolves Au laye rs to form a mixture of liquid and solids. The solid-liquid interdiffu sion process continues until Au-In bond is formed upon solidification. Packaging using indium at 200C has been shown befo re [103]. We present a totally packaged MOEMS device at 160C. A ll the processes used are standard IC processes and no special handling process or tool is required. Low temperature, zero level, herme tic packaging for MEMS/MOEMS devices using indium/gold as intermediate layers was successfully performed to assemble and package the CCR in a single bond step. Surf ace micromachined torsion mirrors with lateral electrical feed-throughs constitute one surface of the CCR. They were bonded to metallized package lid, with integrated ver tical mirrors, to assemble and package the CCR at 160C. The integrated optical window facilitates the inspection and optical probing. Packaged devices passed the Mil sta ndard for helium leak detection and showed leak rates of less than 5x10-8 atm cc/s air. This technique is independent of the substrate material. Wafer level packaging can be perf ormed using this tec hnique though we present

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105 flip-chip results obtained on a 5.8mm x 5.8 mm die, and the package volume was 7.8x10-3 CC. 10.2 Principle of In-Au Bonding Figure 51 shows the phase diagram for In -Au alloy [103]. A phase diagram is a temperature composition map which indicates the phases present at a given temperature and composition. The phase diagrams are determined experimentally by recording cooling rates over a range of compositions. These diagrams are used to understand and predict the alloy microstructure obtained at a given composition. Bulk solid-state diffusion between gol d and indium was studied at room temperature [104] to just be low the In melting point. AuIn2 is the first compound to form, and if enough gold is present, AuIn forms ne xt. Room temperature interdiffusion in thin film couples found AuIn2 forming very fast, almost imme diately upon evaporation of Au on the In film. If Au and In films have the stoichiometry to form AuIn2, the compound will from completely and remain stable. For films with higher gold concentrations, AuIn2 will change within 5 days at room temperature to AuIn, whereas still higher gold film thickness will eventually result in and phases. If the temperat ure is raised above the melting point of In, 157C AuIn2 will form within seconds since liquid diffusion is several orders of magnitude highe r than solid-liquid diffusion.

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106 Figure 51: In-Au Phase Diagram. The recommended ratio of thickness for the interdiffusion material and the lower and upper diffusion material is 2:1. 10.3 Bonding Procedure and Results The lower and upper diffusion material is Au and the interdiffusion material is In. 200 Ti and 1 m Au was sputtered on the package lid and liftoff was performed as discussed earlier. The NMEMS chip was patte rned with Shipley 1813 photoresist to open up the package frame area us ing standard lithography. 1 m thick In was e-beam evaporated on top of the NMEMS chip, and was followed by the evaporation of 2000 Au. Indium and gold evaporation is done se quentially under high vacuum to minimize the

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107 oxidation of indium. InAu2 forms almost immediately upon deposition because of the high diffusion rate. Thus deposition of thin layer of gold was necessary to prevent the formation of indium oxide. Only thin layer of Au was necessary to prevent the oxidation of In [103]. Liftoff was then performed to remove the metal from everywhere except from the package frame area. Since the In and Au layers are in a proportion where In is in abundance when compared to Au, interdiffusion occurs when AuIn2 comes in contact with Au layer on the package lid. If enough pressure is applied to allow intimate contact between the die and the substrate at a temperature above 157C, the melting temperature of In, solid-liquid diffusion will occur resulting in bonding of tw o substrates. When In melts, it wets the adjacent Au layers to form the Au-In alloy, and liquid and solid components interdiffuse. When the assembly is held at temperature above 157C, In melts and breaks up the AuIn2 layer to form a mixture of liquid and solid. Th e mixture wets and disso lves the Au on the substrate to form more AuIn2. This solid-liquid interdiffusion continues until the mixture solidifies, followed by solid-state diffusion. The bonding is thus complete and it has a melting temperature much higher than the temperature at which it is produced. O2 plasma release was then performed to release MEMS. When thin Au (~100) was used to passivate the In la yer, it was noticed that the In layer still gets oxidized and gets hillock formation. It was speculated that because of the thermal gradient in the O2 plasma Au and In are getting interdiffused forming hillocks and because of the O2 presence In is getting oxidized. Figure 52 shows the SEM image of the released NMEMS chip with the package frame area coated with In-Au.

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108 Figure 52: SEM Image of the MEMS Chip With Torsion Mirrors and On Chip Lateral Feed-Throughs. In-Au was Evaporated on the Package Frame Bond Area. Figure 53: Solid Model of the Vertical Mirror Chip With Metallized Vertical Mirrors and Package Frame. Figure 53 shows the solid model of the vertical mirror chip with package frame. Thermo-compression bonding was performed to bond the vertical mirror chip to the NMEMS device chip using flip-chip bonder. The bonding setup is shown in Figure 54.

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109 Figure 54: Schematic View of the Au -In Bonding Using Flip-Chip Bonder. Flip-chip bonder was used to pick up th e vertical mirror lid, and the NMEMS device was kept on the bottom chuck. Alignment was performed to align the package frame areas of both the chips. After the ali gnment the arm with the vertical mirror chip was brought down, and the force was applied to bring both the chips in contact to each other. A force of 40N was used for successf ul bonding. Smaller forces were tried with less success. The temperature of the assembly was raised to 160C and was kept at this temperature for 1 hour. Various bonding time and temperatures we re tried to compare the bonding. The bonding results are shown in Table 4 and the bonding interface is shown in Figure 55. As can be seen from the SEM image in Figure 55 the trenches are filled and there is hardly any notable interface to see where Au and In bonded. This shows that the interdiffusion had taken place successfully and there are no voids at the bonding interface and no apparent leakage point s between the isolated metal electrodes. Figure 55.

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110 Figure 55: Bonding Interface at the Metal Feed -Throughs. All the void sites were filled with conformal coating of Au -In at the bonding interface. Figure 55: Bonding Interface at the Metal Feed-Throughs. All the Void Sites were Filled with Conformal Coating of Au-In at the Bonding Interface. Top Package Lid 1 Micron Au 1 Micron In Patterned Au and Si3N4 Underlying Metal Traces Insulating Layers Si Wafer

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111 Table 4: Hermetic Sealing Results From Sam ples Bonded at Different Temperatures and Different Times. Bonding Force of 40N Was Used on All the Samples. Bonding Temperature (C) Bonding Time (Minutes) Bond Strength He Leak Rates (Atm cc/s air) Gross Leak Test 160 15 Not Bonded X X 160 30 Good 3.0x10-8 Failed 160 60 Good 5.4x10-8 Passed 160 120 Good 3.8 x10-8 Passes 180 15 Not Bonded X X 180 30 Good 7.2 x10-8 Passed 180 60 Good 3.2 x10-8 Passed 180 120 Good 2.8 x10-8 Passed 200 15 Not Bonded X X 200 30 Good 3.6 x10-8 Failed 200 60 Good 4.8 x10-8 Passed

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112 11 TESTING OF THE CCR For the testing of the CCR and to read the physical values of the sensor data three different components were required. First is the microsensor system which contains the microprocessors and drive electronics to modulate the CCR mirrors according to the sensor data and the second component is th e transceiver which will transmit the laser beam to the CCR and will detect the retrorefle cted beam using an optical detector. The optical signal was then electrical processed and was serially transmitted to a computer where a LabVIEW program was used to display the physical values of the sensor data to the computer. 11.1 Microsensor System Figure 56: System Level Bl ock Diagram for Passive Optical Digital Communication.

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113 Figure 56 shows the system level block diagram for passive optical digital communicator (PODC) [105]. The operation of the unit was controlled by a low power, CMOS 8-bit microprocessor, Tiny12, fr om Atmel. Tiny12 is based on AVR RISC architecture with 1K bytes flash memory and 64 bytes EEPROM that can be used for programming of control commands and data processing. The operation voltage is in the range of 1.8V~5.5V, suitable for battery ope ration, with operati on frequency up to 1.2 MHz. The power consumption of the micropro cessor is about 2.2 mA when it is active and less than 1 A when it is set at sleep mode. A surface mount temperature and humidity sensor, SHT11, from Sensirion was used for testing. The sensor has a capacitive polymer sensing element for relative humidity and a bandgap temperature sensor. Both are seamlessly coupled to a 14-bit analog to digital convert er and a serial interface circuit on the same chip, allowing easy data processing, superior signal quality, a fast response time and insensitivity to external disturbances. Other sensors, such as bio-chem ical sensors, can be potentially integrated into the system for further enhanc ing the functionalities as needed. The power of the unit was provided by two flat, 3V, flexible polymer batteries (Model FP-252903M002), connected in parallel, fr om Solicore, Inc. The size of each battery was about 29mmx25mm. As can be seen, the overall size of the sensor system is determined by the size of these batteries. Th e battery has a thickne ss of only about 0.37 mm, allowing very low overall profile of the unit to about 6 mm. The normal capacity of each battery is 10 mAh. The sensor unit has both a miniature mechan ical switch for local actuation, and an optical switch for re mote actuation. Once actuated, the Tiny12

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114 microprocessor sends the comma nd to SHT11 to take temperat ure and humidity data in every second, then send the digital data to drive optical MEMS micromirrors of the CCR to realize passive optical di gital communications (PODC). A voltage doubler (not shown in the figure) was used to increase the drive voltage from 3V from battery to about 9V, which is required for the el ectrostatic operation of CCR. Figure 57: Form Factor of the Packaged CCR 7.2mm7.2mm1.5mm. Figure 57 shows the form f actor of the assembled CCR. The total dimension of the CCR was 7.2mmx7.2mmx1.0mm. The CCR was directly mounted to the flexible circuit board using epoxy. Initially anisot ropic conductive film (ACF) bonding was used for mounting the CCR to the flexi circuit boa rd. But shorting was noticed as the gap isolating the bond pads on the CCR chip was of the same size as th e conductor balls in the ACF (30 m). Hence epoxy bonding was used to bond the CCR to the flexi board.

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115 Figure 58: Fully Integrated PODC Microsensor Unit. (a) Front Side, (b) Back Side. Figure 58 shows the optical images of fu lly integrated PODC microsensor unit. Figure 58(a) shows the front side of the unit with mechanical and optical switches, CCR and a LED which indicates if the unit is ON or OFF. Figure 58(b) show s the back side of the unit with sensor and microprocessor along with the pogo pins for programming access. These pogo pins can also be used to re ad the data the sensor is sending to the CCR for debugging purposes. The overall power consumption of the sens or node was about 1.4 mA. This gives about 14 hours of continuous operation for a two battery unit, assuming a roughly 50% sleeping time for the microprocessor. The ba tteries can also be replaced easily. The current drawn when the unit is off is only about 2 A, giving about 10,000 hours of “shelf life” if there is no “wakeup” from sleep mode. Such a sensor node would have very critical applications for remote sensing as an alternative to RF wireless se nsing systems, as well as ta gging, tracking, and locating applications, when small size, light weight lowpower consumpti on, and more stealthy operations are needed.

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11611.2 Transceiver Figure 59: Block Diagram of the Transceiver Unit. Figure 59 shows the detailed diagram of th e transceiver used. The transceiver unit consisted of a 780nm diode laser and a photomultiplier tube (PMT) as the optical detector. The assembly consists of a 780nm di ode laser, a reflective mirror fabricated on a glass wafer, held at 45 to the outgoing beam and having a small hole for the outgoing beam to pass through. The laser beam from the diode laser was shot at the CCR on the microsensor board through the small hole an d the ambient light limiter barrel. The incident light was then reflected back fr om the CCR which was being modulated using the SHT11 data. Hence the sensor data was imparted to th e probing beam. Upon retroreflection by the remote CCR modulat or, the modulated light beam enters a receiver’s barrel, reflects off the 45 mirror, passes through an optical bandpass filter and was focused by a thin fresnel lens to a sma ll spot on the surface PM T. A spatial filter mask was embedded onto the PMT glass su rface to block off-axis stray light. The combination of spatial and optical filters enabled operation of the sensitive PMT in

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117 ambient light. For use with a near-IR laser, a spotting camera and LCD display were included on the top of the interrogator to allow the user to target the CCR. The PMT output was amplified and electr onically filtered to block signa ls outside of the 25 KHz carrier frequency of the AM-modulated digita l data produced by the CCR. The electronic signal passes through a digital AM demodulator (envelope de tector and comparator) and level shifter to output RS-232 form atted data to a user-supplied PC. Figure 60 shows the mechanical drawing of the transceiver unit and Figure 61 shows the optical image of the actual transceiver. Figure 60: Mechanical Drawi ng for the CCR Transceiver.

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118 Figure 61: Optical Image of the Actual Transceiver. 11.3 Sensor Data Using LabVIEW This electronically amplified signal was transferred to the computer using RS232 and LabVIEW program was used to display th e physical values of the temperature and humidity sensor on the computer screen. Figure 62 shows the block diagram of the LabVIEW program. Visa serial port VI (virtual instrument) was used for serial interface with RS232. COM1 port was selected for serial interface and the baud rate and the st art stop bits were specified in the Visa sub VI. Property node was used to specify a timeout of to prevent the timeout error when no data is transmitted. Visa read sub VI was then used to read the first byte and compare it with ASCII character H. H indicates the star t of the sensor data bytes. A case structure was used. If the first byte is H then the program enters true case.

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119 Figure 62: LabVIEW Block Diagr am for RS232 Interface. Figure 62: LabVIEW Block Diagram for RS232 Interface.

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120 Figure 63: LabVIEW Front Panel Showing the Temperature and Humidity Reading. Figure 63: LabVIEW Front Panel showi ng the Temperature and Humidity Reading.

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121 A while loop was created inside the case stru cture, and as long as the first byte is H it reads the next 3 bytes. Type casting was th en used to convert the digital data to numeric values. The data was sent out from the PODC boa rd once per second. It was programmed so that it sends out 0 as the start bit and 1 as the stop bit. The sequence of data sent is as follows xxxxxxxx – binary humidity LSB to MSB yyyyyyyy binary temp. data (low byte) bit 0 to bit 7 zzzzzzzz binary temp. da ta (high byte) 8 to 11 the serial data looks like ………0 00010010 10 xxxxxxxx 10 yyyyyyyy 10 zzzzzzzz 1…….. where 00010010 represents ASC II character H which repres ents the start of the data strings. Hence the second byte was converted to th e numeric data and it represents the sensor data for humidity. The next two bytes reads the temperature data. Join number function was then used to combine the numeric al values of both th e temperature bytes. The raw data of the sensor was then disp layed in the front panel as shown in The output from the cast type function is the raw sensor data. Following formulas were used to convert that value to ph ysical humidity and temperature values. For relative humidity: 2 410 2 7 648 0 4RH RH linearSO SO RH Equation 11 where SORH is the raw sensor data and the ab solute temperature value is given by

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122 TSO e Temperatur 01 0 40, Equation 12 where SOT is the raw sensor data for temperature. These humidity and temperature values were generated using the above formulas and are then displayed both as numeric valu es and also on the humidity and temperature indicators. Temperature values can be changed from Celsius to Fahrenheit. White characters to a file sub VI were al so used to save the sensor reading to a text file which can be opened in the excel page to monitor the changes in the sensor readings over a period of time. Occasionally the LabVIEW program gives a framing error when bits are missed from the first byte data. The LabVIEW program looks for an H after the start bit '0' is read. If any of the bits are mi ssed the framing error occurs. 11.4 Test Setup and Results Initially the CCR was tested with dummy da ta generated using a signal generator. The torsion mirrors were modulated with an amplitude-modulated signal of 20V peak to peak. 180 out of phase voltage was applied to each side of the torsion mirror electrodes on the active MEMS chip. 780nm wavelength diode laser was us ed to incident light on the packaged CCR and the reflected signal wa s measured using a photomultiplier tube. Figure 64 shows the volt age signal applied to one side of the torsi on mirrors and the data received by the photomultiplier tube. Data was transmitted at 9600 baud with a 50 KHz carrier frequency. Figure 64 shows the oscillo scope data. Two channels are shown where channel 1 shows the signal from the sensors an d channel 2 shows the retroreflected signal as detected using PMT.

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123 Figure 64: The Packaged CCR Was Tested by Modulating the Torsion Mirrors With an Amplitude Modulated Signal. The Retrore flected Signal Was Detected Using a PhotoMultiplier Tube (PMT). Channel 1 Show the AM Modula ted Signal Applied to One Side of the Torsion Mirrors, While the Channel 2 Shows the Retroreflected Data Received by the PMT. The packaged CCR (final PODC unit) was tested for wireless communication to a distance of up to 15 meters. The test setup for CCR testing is show n in Figure 65. The probing beam from the receiver was incide nt onto the CCR. The CCR mirrors were modulated using the sensor da ta and the data was transfe rred to the probing beam. The PMT receives the sensor data and the optical data was then processed electrically before being transferred to the co mputer via RS232. LabVIEW pr ogram was then used to convert this data to the temperature and humid ity values and display it on the computer.

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124 Figure 65: The Test Setup For Reading the Sensor Data With the Use of a CCR is Shown. Figure 65: The Test Setup for Reading the Se nsor Data With the Use of a CCR is Shown.

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125 Figure 66 shows the optical data from the CCR receiver before any digital enhancement with a carrier signal frequenc y of 30 KHz and data rate of 2400bps. Figure 66: The Oscilloscope Data Shows the Digital Output From the CCR Unit. The Inset Image Shows the Detailed View of the High Frequency Carrier Signal and Low Frequency Enveloped Data Signal. ASCII character H was used as the start byt e for the data stream. This is shown as the pink trace in Figure 67. The ASCII ch aracter H was manually generated using Hyperterminal to use as a reference. Channe l 2 shows the unrectified data and channel 1 show the rectified and enveloped data at the transceiver unit.

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126 RS232 communication was used to transmit the output of the receiver to the computer. LabVIEW program was then used to convert the digital da ta into the sensor values of temperature and humidity, which we re then displayed on th e computer screen. Figure 67: The ASCII Character H Was Manual ly Generated Using HyperTerminal to Compare With the Transmitted Data. This is Shown in Pink Trace. Channel 2 (blue) Shows the Digitally Am plified Data and Channel 1 (ye llow) Shows the Final Output From the Receiver. Figure 68 shows the digital data which was transmitted from the PODC unit to the transceiver. The pogo pins were used to get th is data out of the sensor unit. The figure shows the ASCII character H as the start of the data string. The next byte shows the raw data of the humidity and the next two bytes co mbine together to give the raw data for the temperature. The raw data is also shown in the figure. The start a nd stop bits are also shown in the figure.

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127 This data was then sent out from the PODC board once per second, and was received by the transceiver unit at the remote location. The optical data was detected by the PMT as discussed before and was am plified and rectified electronically. Figure 68: Sensor Data as Transmitted From the PODC Unit. Figure 69 shows the digital data from the os cilloscope received at the transceiver end. The respective decimal value is also s hown. Channel 1 (yellow trace) shows the pre rectified data and channel 2 (blue trace) show s the rectified and e nveloped data. The data shown in Figure 68 and in Figure 69 we re collected at different times and hence there is slight variation in the temperature bits. The humidi ty reading is the same. These raw data also match the values shown in th e front panel of LabVIE W as shown in Figure 63. Table 5 summarizes the raw data and physical data as read at different points during the testing.

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128 The humidity was changed by blowing on the sensor and the cha nge in humidity over time was recorded. The humidity changed from 16% to 70% and the temperature reading changed from 38.41 to 38.08. Figure 69: Digital Data Received by the Receiver. The Binary and Decimal Data is Shown in the Figure. Table 5: Comparing the Raw and Physical Sensor Data at Va rious Levels of Testing. Measurement point Raw humidity reading Raw temperature reading Physical humidity reading Physical temperature reading PODC microsensor unit 32 224 16.72% 37.76 C Transceiver unit 32 192 16.71% 38.08 C LabVIEW 32 159 16% 38.41 C

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129 12 RESULTS AND DISCUSSIONS 12.1 Two Step DRIE and Sidewall Improvement MEMS CCRs were fabricated, packaged and tested using different techniques. Techniques were developed to reduce the lo ading effect and aspect ratio dependence during the DRIE process. Sidewall angle of 89. 8 or better for through wafer etches were achieved. Results were presented for etches as deep as 550 m. Excellent uniformity of etch rate and sidewall profile was noticed on a variety of different structures when the described DRIE approach was used. The dens ity of the areas, designed to be removed, varied across the wafer without any noticeable change in the etch rate of surface profile. This was achieved by performing the DRIE on thin 50 m channels, which kept the process parameters constant across different features. The process also showed minimal profile change with change in plasma conditions. Appendix B shows that if the CCR is asse mbled with mirrors which are 0.2 off the ideal dihedral angle the distance between the reflected light and the transmitted light will be 5.7cm when the distance between the detector and the receiver is 10m. A fresnel lens of this diameter can be used to focus the reflected light to the detector aperture. However this angle of 89.8 was further improved to 90.08 by using KOH:IPA polishing on the DRIE surfaces. This polishing also improves the sidewall roughness from more than 122nm to less than 40nm, which significant ly reduces the scatte ring losses from the

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130 mirrors. Though the improvement in the sidewall angle looks small (0.12) its significance can be appreciated when we compare the calculated distance between the reflected light beams before and after polishing. When the offset angle from the dihedral angle is 0.12, the distance between the probi ng beam and the reflected light is 2.25cm when the distance between the reflector a nd receiver is 10m. Th e prototype receiver which was discussed in the previous chapter ha d the receiver aperture of 5cm, which was big enough to collect the reflected light. Etch rates of approximately 2.6 m/min were recorded using this two step DRIE method. There is a trade off be tween etch rates and verticalit y, depending on the width of the uniform width trench pattern. Increase in th e width will result in faster etches but the verticality might be compromised. Decrease in the width might result in better verticality but the etch rates will decrease. 50 m width was chosen, but optimization may need to be done to find a sweet spot between these two parameters. However the optimization would not be needed for different structures but only for a desired channel width. A drawback of this method is that two lithography masks were used instead of a single mask as in conventiona l DRIE process. This increa ses the design and lithography cost but nevertheless, the cost reduction in process gas cons umption, and etch uniformity is more lucrative than lithogr aphy cost. Newer ICP etch equipments claim to achieve 90 sidewall profile [106] with an etch rate of 10 m/min. However optimization of etch recipe is required for different structur es. Moreover sidewall roughness obtained by these tools is not suitable for optical applications. These tools might not be of interest for the researchers who already have a DRIE tool. A process which should work on most of the

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131 DRIE tools with any kind of etch pattern and density was de veloped. No optimization is required for different shape stru ctures. It is su ggested to use the described method of using uniform width trenches to further reduce the loading effect, which will result in more uniform etches and uniform sidewall an gle all across the wafer even with newer DRIE tools. 12.2 Low Temperature Hermetic Packaging Scheme In-situ development of package frame was al so presented. The etching of vertical mirrors on an anodically bonded Si/Pyrex wafe r pair resulted in package frame (Si + Pyrex) and package lid (Pyrex ). Novel self-patterning li thography using flood exposure was presented to metallized the vertical mirrors and package frame while leaving the package lid transparent for optical probing. Spin on photoresist resulted in non uniform coating on the DRIE structures due to the topography. Micro pi pettes were hence used to prevent this non uniformity and to prevent fo rmation of bubbles at the interface of two vertical mirrors. A spray coating system for phot oresist, if available, will circumvent the need for this modified coating process and w ill result in faster turn around of wafers. Low temperature hermetic sealing t echnique was also developed. MOEMS devices were hermetically sealed at the temperatures as low as 160C using In-Au bonding. After bonding the In-Au alloy was formed which is known to have a melting point of more than 545C. The bonded devices were hermetically sealed and passed the MIL-STD-883G which specifies the leak rates of 5x10-8 atm cc/s air for the package volume of 7.8x10-3 CC.

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13212.3 Surface Micromachining and Testing Surface micromachined active MEMS structur es were fabricated using nitride as the structural layer. The nitride structural layer was sandwiched between metal layers to form mirrors and electrodes. The sandwiche d structure reduces the mirror curvature which is caused by thin film stresses an d it also allow for bonding layer for final packaging. The NMEMS mirrors we re modulated at as low as 6Vpp 20Vpp and had resonant frequencies ranging from 30 KHz to 50 KHz. Different runs were performed by varying the thickness of structural nitride and sacrificial polyimide to vary the operating voltage and resonant frequency. A PODC microsensor system with CCR was developed. The sensor system has very low power consumption (1.4 mA), a light weight (8 g), and a small form factor (30mm30mm6mm). The microsensor system has a temperature and humidity sensor for sensing purpose, a Tiny12 microprocessor for signal processing, and an optical MEMS device (active CCR) for remote fr ee space optical communication. Such a microsensor system will find many applications in remote sensing, as well as tagging, tracking, and locating (TTL). A flexible circuit board has been design and a folded packaging scheme has been utilized to minimize the overall form factor Two flat, flexible polymer batteries are incorporated to minimize the vertical profile to a few millimeters. The entire assembly of the microsensor system was performed and th e optical characterizat ion of the CCR and the electrical characterization of the sensor system were successfully demonstrated.

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133 A prototype transceiver wa s developed which was used to probe the PODC unit and remotely sense the optical data as transmitted by the PODC sensor unit. Simpler setup was used to split the incoming beam and the outgoing beam. A PMT was used to detect the faintest of optical signal and the signal was further enhanced electronically to transmit it to a computer via serial interf ace. LabVIEW program was also developed to display the physical values of the sensor data at the computer placed at the central station. 12.4 Investigation for Improving the Range The operating range of the above de scribed CCR was limited by the signal available to the receiver. This signal depends on the quality of the reflector and in the case of the CCR it depends on the quality of the mirrors which make the CCR, and how well the CCR can retro reflect the incident light. The CCR assembled using the vertical mirrors and NMEMS parts have few limitations in terms of the sidewall roughness of the mirrors, and the surface curvature of the NMEMS mirrors. As mentioned before the vertical mirrors obtained by DRIE and KOH:IPA polishing suffer from roughness and hence the incident light gets scattered resulting in scatte ring losses. The maximum range over with a communication link works is given by [107] 4 2 min 2 2 max4 S f A P R Equation 13 where maxR = maximum range of detection P = incident power

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134 = scatter cross section of CCR which is defined as 4 times the ratio of power density per unit solid angle scattered back towards the transmitter, to the power density (power per unit ar ea of the incident light) A = aperture area of the transmitter f = dimensionless quantity which determines the gain of the transmitter in a given direction Smin = minimum detectable signal which depe nds on the aperture of the receiver = wavelength of the light used. As the scattering from the CCR increases th e scatter cross section decreases since the power density per unit solid angle going ba ck to the transmitter decreases. It can also be seen from Figure 20 that while the scat tering loss from a mirror with 40nm roughness is ~38% and it will decrease to <10% fo r a mirror with RMS roughness < 20nm. The CCR presented here works for 10-15 meters but longer range communication is not possible using this CCR and receiver. Hence for longer range communications there is a need to fabricate vertical structures with better mirror finish, and MEMS mirrors with less stress to reduce the mirror curvature. Experiments were conducted using (110) Si wafer to fabricate the mirrors using DRIE and KOH polishing or just KOH etching, and silicon on insulator (SOI) wafer was used to fabricate stress free MEMS mirrors. 12.4.1 Future Work: Medium Range Passi ve Optical Digital Communicator (MRPODC) In applications where 15-50 meter ra nge communication wa s desired MRPODC was designed and fabricated. Shorter range communication might also be possible with

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135 this system, probably with an attenuator in fr ont of the PMT (to prevent its damage), and if enough light is scattered to reach the detector. Vertical mirrors were etched in (110 ) Si wafer using KOH etching and MEMS mirrors were fabricated on silicon on insulator (SOI) wafer. The KOH etching gives atomically smooth sidewalls and mirrors fabr icated on SOI wafer results in stress free mirrors due to the use of single crystal Si as the device layer. Vertical mirrors in the shape of a cross cannot be etched on a (110) Si wafer, so two orthogonal mirrors were fabricated separately and were bonded to the SO I chip in different st eps unlike single step assembly/packaging as discussed before. One se t of structures consists of long vertical mirrors, with a gap in the center, without any package frame and the other set of structures consist of package frame and vert ical mirrors. The process is illustrated in Figure 70.

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136 Figure 70: Solid Model of the Process Desc ribing the Assembly of CCR by Using Vertical Mirrors Etching on (110) Si Wafer. (a) MEMS Mirrors on SOI Wafer With Bonding Areas For the Vertical Mirrors, (b ) First Bonding Using the Vertical Mirrors With a Diced Streak and No Package Frame, (c) Laser Liftoff Was Performed to Remove the Handle Wafer, (d) Vertical Mirrors With Package Frame Was Then Aligned and Bonded to the Assembly, (e) Herme tically Packaged and Assembled CCR.

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137 Figure 70 shows the CoventorWare solid mo dels describing the procedures used to assemble the CCR using the KOH etched mirrors on (110) Si wafer. MEMS mirrors were fabricated using SOI wafers whic h form the base for further bonding. The advantage of using SOI wafer is that the feat ures have minimum stre ss as it uses single crystalline Si as the structure material. This is shown in Figure 70(a). KOH etching was performed on (110) Si wafer to get vertical mi rrors. Two different sets of vertical mirrors were fabricated; with and w ithout package frame area. The mirrors without the package frame area were then diced in the center to make the recess for the final assembly. The mirrors were then metallized and bonded to the SOI chip as show n in Figure 70(b). The SOI devices were then prot ected using photoresist and la ser micromachining was then performed to liftoff the handle Pyrex chip from the top. This is necessary for the final bonding. This is shown in Figure 70(c). The ot her set of vertical mirrors with package frame were then flip-chip bonded to the asse mbly to package the final device, as in Figure 70(d). Au-Au thermo-compression bondin g was again used for bonding, as shown in Figure 70(e). This final bonding results in hermetic packaging as there is no indentation on the SOI chip for electrical routing. To etch the vertical mirrors, a 550m thick double side polished silicon wafer with 100nm of LPCVD-deposited Si3N4 was first anodically bonded to a Pyrex glass hold wafer. The mask structures were aligned to a (111) crystal plane us ing fan out structure mask and etching was then performed us ing 30% w/w KOH solution at 85C for 4.5 hours to etch through the wafer. The vertical mirrors were then sputter coated with gold (100nm Cr, 1000nm Au) using a back side expose d self-patterning lifto ff process [15] to

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138 increase reflectivity and allow thermo-c ompression bonding. Thermo-compression bonding (FineTech Pico5, 320C, 41 MPa, 2 mi nutes) was performed, initially using structures without a package frame, to bond the vertical mirrors to the unreleased SOI chip. After the first bonding of one set of vertical mirro rs, the handle Pyrex lid was removed using laser micromachining. A 248nm laser with 30mJ/pulse, 162 m spot size and fluence of 1.2m/cm2 was shot at every 5 m during the linear move, de-bonding the Pyrex chip from the device chip. Duri ng this process the underlying active MEMS devices was protected from laser ablation de bris using photoresist. After removing the protective photoresist, SOI chips were rel eased in HF. A second thermo-compression bonding of a combined orthogonal vertical mi rror and package frame was performed on the same chip to finish the assembly as s hown in Figure 72. The gl ass wafer and package frame serve to protect the MEMS device and a llow optical probing of th e internal parts. Figure 71 shows the optical image of the ME MS chips after laser liftoff process. In Figure 71(a) the MEMS mirrors were not protected using photores ist and the debris can be seen on the active parts where as in Figure 71(b) the MEMS mirrors were protected using photoresist and after removi ng the photoresist no debris were found on the mirrors.

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139 Figure 71: Optical Image of the Assemble d Device. (a) MEMS Devices Were Not Protected With Photoresist During Laser Li ftoff, (b) MEMS Devices Were Protected Using Photoresist During Laser Liftoff. Figure 72: Surface Deformation After Lase r Micromachining. Th e Inset Image Shows Where the Laser Beam Hits to Release the Pyrex From Si3N4. Figure 73 shows the AFM scan of one of the mirror surface. The scanning was performed on an area of 40 mx40 m. The average roughness was measured to be ~5.86nm and varied from ~6nm to ~12nm at various spots of the mirror. Optical profilometer was also used to measure th e roughness and the measured roughness was 46nm, as shown in Figure 74.

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140 Figure 73: AFM Scan on the KOH Etched Mi rror. Etching Was Performed Using 30% KOH at 85C for 4.5 Hours. Dicing was then performed to separate diffe rent chips. On the mirrors without the package frame dicing was also performe d at the center using a blade of 350 m width. Dicing was performed so that it dices through the Si but only partially through the Pyrex. The mirrors were then metallized and bonded to the SOI chip as described before. Novel use of laser micromachining to liftoff the handle wafer was also demonstrated. It is a quick release process without any wet chemistry. This process is compatible with other pro cesses and once the underlying devices are protected the process is very clean to carry out.

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141 Figure 74: Veeco Optical Profilometer Scan of KOH Etched (110) Silicon Wafer. 12.4.1.1 Silicon-On-Insulator (SOI) SOI wafer consists of a stack of single crystal Si (SCS) which acts as the handle wafer, thin oxide layer which acts as the sacr ificial layer and a thin SCS layer which acts as the device layer. SOI wafers can be us ed to fabricate MEMS devices with fewer processing steps and also provides stre ss free structural device layer. SOI wafer with 3 m thick device Si 2 m thick buried oxide and 500 m thick handle wafer was used to fabricate MEMS devi ces. The structural layer of the wafer was patterned using the structure mask. This mask defines the MEMS stru ctures, anchors and routing of electrodes, and release holes on th e device silicon. Anchor s were defined with larger areas so that during the release the ox ide under the device laye r gets etched but not from under the anchor area. Once the photores ist is patterned DRIE was performed to

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142 etch the exposed Si using phot oresist as the masking layer. Only 14 Bosch cycles were required to etch 2.8 m (measured thickness of device Si) of device Si. Next the exposed O2 is etched using RIE etching. 60 minut es of RIE was performed to etch 2 m thick buried oxide. After the O2 etch, the photoresist was rem oved using acetone/methanol and long descum process. Metal (Cr/Au, 20nm/300nm) was then deposit ed to define the electrical routing and it was also deposited on top of mirrors to improve the reflectivity of the MEMS mirrors. The metals were then et ched in Transene etchants. After the metal is patterned, the wafer was coated with photoresist and diced to get individual chips. The chips were then cleaned in acetone/methanol to remove the dicing debris and photoresist. The parts were released in 49% HF. It was experimentally found out that the release for 3 minutes and 15 seconds gives the best release. After the HF release the chips were transferred to DI wafer container. The DI wafer was continuously pored in the beaker to keep th e DI wafer running and to completely remove the HF from the SOI chip. The chip was then transferred to two beakers containing IPA. After this the chips were dried in a v acuum oven at 80C for 10 minutes. Figure 75 shows the 3-D scan of the released SOI chip and Figure 76 shows the 2D scan of the same SOI chip. It shows the surface curvature of 54mm which is much better than the average curvature of 19mm which was obtained from NMEMS mirrors.

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143 Figure 75: Optical Scan of the Released SOI Chip. Figure 76: Optical Scan of the Released SOI Chip Showing the Mirror Curvature.

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144 12.5 Conclusions A working passive optical digital communicator (PODC) was demonstrated in this dissertation. It was demonstrated to se nd the sensor data to a remote location and it was successfully verified that the data read by the detector unit, at the remote location, is the same data as it is being sent out by the PODC sensor. Various new techniques were developed during this wo rk. Vertical etching of 550 m deep mirrors with sidewall angles of 90.08 and sidewa ll roughness of ~38nm was successfully demonstrated. Self-patterning liftoff process was also demonstrated which helps in designing packages for MOEM S/MEMS devices with less process steps. Versatile hermetic sealing method at 160C wa s also successfully demonstrated and the devices successfully passed the military standards. Zero level hermetic packaging techniques for MEMS devices were developed and demonstrated. Techniques to reduce the overall form factor of the device were also demonstrated using a folding technique using flexible ci rcuit board. Die level bonding of parts to assemble the application specific integrated circuit (ASIC) was also developed to reduce the overall form factor of the board. New liftoff method to release the handle wa fer from the device wafer was also developed using laser micromachining. Unlike other wet release methods this method is very quick, does liftoff in few seconds, and al so prevents the potential damage to the fragile parts from wet etchants.

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145 REFERENCES 1. K. E. Peterson, "Silicon as a mechanical material," Proc. IEEE, vol. 70, pp. 420-457, 1982. 2. K. S. J. Pister, M. W. Judy, S. R. Burget t and R. S. Fearing, "Microfabricated hinges," Sensors and Actuators-A: Physical, vol. 33, pp. 249-256, 1992. 3. C. R. King, L. Y. Lin and M. C. Wu, Monolithically integrated refractive microlens standing perpendicular to the substrate," Proc. SPIE, vol. 2687, pp. 123-130, 1996. 4. S. Spiesshoefer, Z. Rahman, G. Vangara, S. Polamreddy, S. Burkett and L. Schaper, “Process integration for through-silicon vias,” Journal of Vacuum Science Technology A vol. 4, issue 23, pp. 824-830, 2005. 5. Y. Uenishi, M. Tsugai and M. Mehregany, "Micro-opto-mechanical devices fabricated by anisotropic etching of (110) silicon," Journal of Micromechanics and Microengineering vol. 5, pp. 305-312, 1995. 6. I. Zubel and M. Kramkowska, "The eff ect of isopropyl alcohol on etching rate and roughness of (100) Si surface etch ed in KOH and TMAH solutions," Sensors and Actuators-A: Physical, vol. 93, pp. 138-147, 2001. 7. P. Krause and E. Obermeier, "Etch rate and surface roughness of deep narrow Ugrooves in (110)-oriented silicon," Journal of Micromechani cs and Microengineering vol. 5, pp. 112-114, 1995.

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146 8. D. R. Ciarlo, "A latching accelerometer fa bricated by the anisotropic etching of (110) oriented silicon wafers," Journal of Micromechan ics and Microengineering vol. 2, pp. 10-13, 1992. 9. S. H. Kim, S. H. Lee, H. T. Lim and Y. K. Kim, "(110) silicon etching for high aspect ratio comb structures," Proc. IEEE on Emerging Technologies and Factory Automation, pp. 248-252, 1995. 10. H. Guckel, "High-Aspect-Ratio micr omachining via deep X-ray lithography," Proc. IEEE, vol. 86, pp. 1586-1593, 1998. 11. C. K. Wong, J. Wei, G. J. Qi, Z. F. Wa ng, F. Y. Jin and C. P. Lim, "A wafer level packaging for pressure sensors MEMS," Micro System Technologies, pp. 123-130, 2003. 12. Y. L. Ramsey and D. Andrew, “Packagi ng micromechanical devices,” U.S. Patent 6,603,182, 2003. 13. K. A. Peterson and R. D. Watson, “Sealed symmetric multilayered microelectronic device package with integral windo ws,” U.S Patent 6,489,670, 2002. 14. R. Agarwal, S. Samson and S. Bhansali, “F abrication of vertical mirrors using plasma etch and KOH:IPA polishing,” Journal of Micromechanics and Microengineering, vol. 17, pp. 26-35, 2007. 15. R. Agarwal, S. Samson, S. Kedia and S.Bh ansali, “Fabrication of integrated vertical mirror surfaces and transparent window for packaging MEMS devices,” Journal of Microelectromechanical systems vol. 16, issue 1, pp. 122-129, 2007.

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147 16. S. Samson, R. Agarwal, S. Kedia, W. Wang, S. Onishi and J. Bumgarner, “Fabrication processes for packaged optical MEMS devices,” Proc. ICMENS Canada, pp. 113-118, 2005. 17. H. Stockman, “Communication by means of reflected power,” Proc. I.R.E pp. 11961204, 1948. 18. J. M. Kahn and J. R. Berry, “W ireless infrared communication,” Proc. IEEE vol. 85, issue 2, pp. 265-298, 1997. 19. A. Makynen, J. T. Kostamovaara and R. A. Myllyla, “Displacement sensing resolution of position-sensitive detectors in atmospheric turbulence using retroreflected beam,” IEEE Transactions on Instrumentation and Measurement vol. 46, issue 5, pp. 1133-1136,1997. 20. D. P. McElroy, H. Sung-Cheng and E. J. Hoffman, “The use of retro-reflective tape for improving spatial resolution of scintillation detectors,” IEEE Transactions on Nuclear Science, vol. 49, issue 1, part 1, pp. 165-171, 2002. 21. R. J. McClure and F. J. Jeffers, “X-ray phosphor imaging screen and method of making same,” US patent 4,992,699, 1991. 22. M. Achour, “Free-Space optical comm unication by retro-modulation: concept, technologies and challenges,” Proc. of SPIE vol. 5614, pp. 52-63, 2004. 23. W. S. Rabinovich, G. C. Gilbreath, C. B ovais, K. Cochrell, H. R. Burris, M. Ferraro, M. Vilcheck, R. Mahon, K. Goins, I. Sokolsky, J. Vasquez, T. Meehan, R. Barbehehn, D. S. Katzer and K. Ikossi-Ansatasiou, “Infrared data link using a multiple quantum well

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148 modulating retro-reflector on a small rotary-wing UAV,” Proc. IEEE, Aerospace Conference vol. 3, pp. 93-100, 2000. 24. J. Thornton and D. J. Edwards, “Modul ating retro-reflector as a passive radar transponder,” Electronics Letters vol. 34, issue 19, pp. 1880-1881, 1998. 25. T. Tsumura, H. Okubo, N. Komatsu a nd N. Aoki, “Optical two-way communication system for vehicles using lasers and corner cubes,” Proc. Vehicle Navigation and Information Systems pp. 535-538, 1995. 26. P. B. Chu, “Optical co mmunication with micromachined corner cube reflectors,” Ph.D. dissertation, University of California, Los Angeles, 1998. 27. R. Agarwal, "A novel normal-to-pl ane space efficient micro corner cube retroreflector with improved fill factor," Master's thesis, University of South Florida, 2003. 28. V. Handerek and L. Laycock, “Feasibility of retroreflective free-space optical communication using retror eflectors with very wide field of view,” Proc. of SPIE vol. 5614, pp. 1-9, 2004. 29. X. Zhu, V. S. Hsu and K. S. J. Pister, “Optical modeling of ME MS corner cube retroreflectors with misalignment and nonflatness,” IEEE Journal of Selected Topics in Quantum Electron, vol. 8, pp. 26-32, 2002. 30. P. B. Chu, N. R. Lo, E. C. Berg and K. S. J. Pister, “Op tical communication using micro corner cube reflectors,” Proc. IEEE, Micro Elect ro Mechanical Systems pp. 350355, 1997.

PAGE 168

149 31. D. S. Gunawan, Lin-Yuan Lin and K. S. J. Pister, “Micromachined corner cube reflectors as a communication link,” Sensors and Actuators-A: Physical vol. 46, pp. 580583, 1995. 32. V. S. Hsu, J. M. Kahn and K. S. J. Pi ster, “MEMS Corner Cube Retroreflectors for free space optical communications,” Master’s th esis, University of California, Berkeley, 1999. 33. K. S. J. Pister, M. W. Judy, S. R. Bu rgett and R. S. Fearing, “Microfabricated hinges,” Sensors and Actuators-A: Physical vol. 33, pp. 249-256, 1992. 34. A. Friedberger and R. S. Muller, “Improved surface-micromachines hinges for foldout structures,” Journal of Microelect romechanical Systems vol. 7, pp. 15-19, 1998. 35. J. Reid, V. Bright and T. Butler, “Aut omated assembly of flip-up micromirrors,” Sensors and Actuators-A: Physical vol. 66, pp. 292-298, 1998. 36. L. Zhou, J. Kahn and K. Pister, “Cor ner-cube retroreflector based on structureassisted assembly for free-space optical communication,” Journal of Microelectromechanical Systems vol. 12, pp. 233-242, 2003. 37. D. Pedersen and O. Solgaard, “Free space communication link using a grating light modulator,” Sensors and Actuators-A: Physical, vol. 83, pp. 6-10, 2000. 38. Y. K. Hong, R. R. A. Syms, K. S. J. Pi ster and L. X. Zhou, “Design, Fabrication and Test of Self-Assembled Optical Corner Cube Reflectors,” Journal of Mircomechanics and Microengineering, vol. 15, pp. 663-672, 2005.

PAGE 169

150 39. R. Agarwal, S. Samson, S. Onishi and S. Bhansali, “Corner C ube Retroreflectors,” US Patent 7,201,485, 2007. 40. H. Jansen, M. de Boer, R. Wiegerink, N. Tas, E. Smulders, C. Nuagu and M. Elwenspoek, "RIE lag in high aspect ratio trench etching of silicon," Microelectron. Eng vol. 35, pp. 45-50, 1997. 41. A. A. Ayon, R. Braff, C. C. Lin, H. H. Sawin and A. M. Schmidt, "Characterization of a time multiplexed inductively coupled plasma etcher," Journal of electrochemical society, vol. 146, pp. 339-349, 1999. 42. S. Jensen and O. Hansen, "Characteriz ation of the microloading effect in deep reactive ion etching of silicon," Proc. SPIE on Micromachi ning and Microfabrication, vol. 5342, pp. 111-118, 2004. 43. H. Jansen, B. M. Gardeniers, M. Elwenspoek and J. Fluitman, "A survey on the reactive ion etching of si licon in microtechnology," Journal of Micromechanics and Microengineering, vol. 6, pp. 14-28, 1996. 44. H. Jansen, M. Boer, R. Legtenberg and M. Elwenspoek, "The black silicon method: a universal method for determining the paramete r setting of a fluorin e-based reactive ion etcher in deep silicon trench etching with pr ofile control," Journal of Micromechanics and Microengineering, vol. 5, pp. 115-120, 1995. 45. A. Bertz and T. Warner, "The formation of very flat silicon side walls by dry etching," Journal of Micromechan ics and Microengineering, vol. 4, pp. 23-27, 1994.

PAGE 170

151 46. T. Ikehara and R. Maeda, "Fabrication of an accurately vertical sidewall for optical switch applications using deep RI E and photoresist spray coating," Journal of Microsystem Technology, vol. 12, pp. 98-103, 2005. 47. J. Hsieh and W. Fang, "A boron etch-stop assisted lateral silicon etching process for improved high-aspect-ratio silicon mi cromachining and its applications," Journal of Micromechanics and Microengineering, vol. 12, pp. 574-581, 2002. 48. Y. Mita, M. Kubota, T. Harada, F. Marty, B, Saadany, T. Bourouina and T. Shibata, "Contour lithography methods for DRIE fa brication of nanometer-millimetre-scale coexisting Microsystems," Journal of Micromechanics and Microengineering, vol. 16, pp. S135-S141, 2006. 49. T. Suligoj, K. L. Wang and P. Biljanovic, "Minimization of sidewall roughness in Si pillar-like structure by p hotolithography optimization," IEEE Electrotechnical conference, pp. 458-462, 2002. 50. W. H. Juan and S. W. Pang, "Contro lling sidewall smoothness for micromachined Si mirrors and lenses," Journal of Vacuum Science Technology vol. 14, issue 6, pp. 40804084, 1996. 51. B. Volland, F. Shi, P. Hudek, H. Heerlein and I. W. Rangelow, "Dry etching with gas chopping without rippled sidewalls," Journal of Vacuum Science Technology vol. 17, issue 6, pp. 2768-2771, 1999.

PAGE 171

152 52. W. H. Juan, Y. H. Kao and S. W. Pang, "High reflectivity micromirrors fabricated by coating high aspect ratio Si sidewalls," Journal of Vacuum Science Technology vol. 15, issue 6, pp. 2661-2665, 1997. 53. W. H. Juan and S. W. Pang, "High-aspect ratio Si vertical micromirror arrays for optical switching," Journal of Microelectromechanical Systems, vol. 7, pp. 207-213, 1998. 54. M. Sasaki, T. Fujii, Y. Li and K. Ha ne, "Anisotropic Si etching technique for optically smooth surfaces," Transducers’01, pp. 604-607, 2001. 55. C. Mihalcea, S. Khumpuang and M. Ku wahara, "Ultra-fast Anisotropic silicon etching with resulting mirror su rfaces in ammonia solutions," Transducers’01, pp. 608611, 2001. 56. P. Helin, M. Mita, T. Bourouina, G. Reyne and H. Fujita, "Self-aligned micromachining process for large-scale, free-space optical cross-connects," Journal of Lightwave Technology, vol. 18, pp. 1785-1791, 2000. 57. C. Marxer, M. A. Gretillat, N. F. De Rooij, R. Battig, O. Anthamatten, B. Valk and P. Vogel, "Vertical mirrors fabricated by r eactive ion etching for fiber optical switching applications," Proc. IEEE, Tenth Annual International Workshop, pp. 49-54, 1997. 58. Y. Lv, J. Ma, J. Zou and X. Wang, "Res earch of anisotropic etching in KOH water solution with isopropyl alcohol," International Conference on Communication, Circuits and Systems vol. 2, pp. 1779-1783, 2002.

PAGE 172

153 59. D. Nilsson, S. Jensen and A. Menon, "Fabrication of silicon molds for polymer optics," Journal of Micromechani cs and Microengineering, vol. 13, pp. S57-S61, 2003. 60. W. H. Juan and S. W. Pang, "Released Si microstructures fabricated by deep etching and shallow diffusion," Journal of Microelectromechanical Syst ems, vol. 5, no. 1, pp. 18-23, 1996. 61. S. Sugiyama, M. Takigawa, and I. Igarashi "Integrated piezoresistive pressure sensor with both voltage and frequency output," Sensors and Actuat ors-A: Physical vol. 4, pp. 113-120, 1983. 62. E. A. Sani, R. S. Huang and C. Y. Kwok, "A novel optical accelerometer," IEEE Electronic Device Letter vol. 16, pp. 166-169, 1995. 63. W. C. Lin and L. J. Yang, "A liquid-ba sed gravity-driven etchin g-stop technique and its application to wafer level cantilever thickness control of AFM probes," Journal of Microelectronics and Microengineering, vol. 15, pp. 1049-1054, 2005. 64. H. Seidel, L. Csepegi, A. Heuberger a nd H. Baumgartel, "Ani sotropic etching of crystalline silicon in alkaline solutions; I orientation dependence and behavior of passivation layers, Journal of Electrochemical Society, vol. 137, pp. 3612-3622, 1990. 65. C. Moldovan, R. Iosub, D. Dascalu and G. Nechifor, "Anisotropic etching of silicon in complexant redox alkaline system," Sensors and Actuators-B: Chemical vol. 58, pp. 438-449, 1999. 66. H. G. Linde and L. W. Austin, "Catalyt ic control of anisot ropic silicon etching," Sensors and Actuators-A: Physical vol. 49, pp. 181-185, 1995.

PAGE 173

154 67. J. B. Prince, "Semiconductor Silicon," Electrochemical Socie ty softbound Proc. series, Princeton NJ, pp. 339-357, 1973. 68. I. Zubel, I. Barycka, K. Kotowska a nd M. Kramkowska, "Silicon anisotropic etching in alkaline solutions IV: the effect of organi c and inorganic agents on silicon anisotropic etching process," Sensors and Actuators-A: Physical vol. 87, pp. 1-9, 2000. 69. P. S. Reddy and J. R. Jessing, "Patte rn alignment effects in through-wafer bulk micromachining of (100) silicon," IEEE Workshop on Microelectronics and Electron devices, pp. 89-92, 2004. 70. G. Ensell, "Alignment of mask patterns to crystal orientation," Sensors and Actuators-A: Physical vol. 53, pp. 345-348, 1996. 71. B. Puers and W. Sansen, "Compens ation structures for convex corner micromachining in silicon," Sensors and Actuators-A: Physical vol. 21, pp. 1036-1041, 1990. 72. M. Bao, C. Burrer, J. Esteve, J. Bause lls and S. Marco, "Etching front control of <110> strips for corner compensation," Sensors and Actuators-A: Physical vol. 37, pp. 727-732, 1993. 73. N. Soin and B. Y. Majlis, "Realization of perfect silicon corrugated diaphragm using KOH etching," Proc. IEEE, International Confer ence on Semiconductor Electronics, pp. 400-4006, 2004.

PAGE 174

155 74. H. Namatsu, M. Nagase, T. Yamaguchi, K. Yamazaki and K. Kurihara, “Influence of edge roughness in resist pa tterns on etched patterns”, Journal of Vacuum Science Technology B, vol. 16, issue. 6, pp. 3315-3321, 1998. 75. G. S. Matuasevic, C. Y. Wang and C. C. Lee, “Void free bonding of large silicon dice using gold-tin alloys,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology vol. 13, no. 4, pp. 1128-1134, 1990. 76. S. M. L. Nai J. Wei, P. C. Lim and C. K. Wong, “Silicon-to-silicon wafer bonding with gold as intermediate layer,” Electronics Packaging T echnology, 5th Conference pp. 119-124, 2003. 77. Brewer Science 2401 Brewer Drive; Ro lla, Missouri, USA 65401. 78. X. Zhu, "Mololayer surface coatings solve stiction and drift problems in MEMS," Proc. IEEE, MEMS, NANO and Smart Systems, vol. 20, issue 23, pp. 128-130, 2003. 79. S. Samson, R. Agarwal, S. Kedia, W. Wang, S. Onishi and J. Bumgarner, “Fabrication processes for packaged optical MEMS devices,” Proc. ICMENS Canada, pp. 113-118, 2005. 80. R. Agarwal, S. Samson, S. Kedia and S. Bhansali, “Fabrication and Testing of Packaged Corner Cube Retroreflectors,” Proc. SPIE, Optics in the Southeast, Georgia, 2005. 81. Y. L. Ramsey and D. Andrew, “Packagi ng micromechanical devices,” U.S. Patent 6,603,182, 2003.

PAGE 175

156 82. K. A. Peterson and R. D. Watson, “Sealed symmetric multilayered microelectronic device package with integral windo ws,” U.S Patent 6,489,670, 2002. 83. K. Ikeda, H. Kuwayama, T. Kobayashi, T. Watanabe, T. Nishikawa, T.Yoshida and K. Harada, "Silicon Pressure Sensor Integrates Resonant Strain-Gauge on Diaphragm," Sensors and Actuators-A: Physical vol. 21, pp. 146-150, 1990. 84. L. W. Lin, R. T. Howe and A. P. Pisano, "Microelectromechanical filters for signal processing," Journal of Microelect romechanical Systems vol. 7, pp. 286-294, 1998. 85. B. Ziaie, J. A. VonArx, M. R. Dokmeci and K. Najafi, "A hermetic glass silicon micropackage with high-density on-chip feed-throughs for sensors and actuators," Journal of Microelect romechanical Systems vol. 5, pp. 166-179, 1996. 86. Y. S. Choi, J. S. Park, H. D. Park, Y. H. Song, J. S. Jung and S. G. Kang, "Effects of temperatures on microstructures and bonding strengths of Si-Si bonding using bisbenzocyclobutene," Sensors and Actuators-A: Physical vol. 108, pp. 201-205, 2003. 87. R. de Reus, C. Christensen, S. Weichel, S. Bouwstra, J. Janting, G. F. Eriksen, K. Dyrbye, T. R. Brown, J. P. Krog, O. S. Jens en and P. Gravesen, "Reliability of industrial packaging for microsystems," Microelectronics Reliability, vol. 38, pp. 1251-1260, 1998. 88. J. T. Huang and H. A. Yang, "Impr ovement of bonding time and quality of anodic bonding using the spiral arrangemen t of multiple point electrodes," Sensors and Actuators-A: Physical, vol. 102, pp. 1-5, 2002. 89. C. Lee, W. F. Huang and J. S. Shie "Wafer bonding by low-temperature soldering," Sensors and Actuators-A: Physical vol. 85, pp. 330-334, 2000.

PAGE 176

157 90. P. Lindner, V. Dragoi, S. Farrens, T. Glinsner and P. Hangweier, "Advanced techniques for 3-D devices in wafer-bonding processes," Solid State Technology, vol. 47, pp. 55, 2004. 91. M. A. Schmidt, "Wafer-to-wafer bonding for microstructure formation," Proc. of the IEEE Transactions on Advanced Packaging, vol. 86, pp. 1575-1585, 1998. 92. H. Henmi, S. Shoji, Y. Shoji, K. Yoshimi and M. Esashi, "Vacuum Packaging for Microsensors by Glass Silicon Anodic Bonding," Sensors and Actuators-A: Physical vol. 43, pp. 243-248, 1994. 93. Suss report, "Wafer bonding in industrial MEMS processing," issue 1, pp 4-9, 2006. 94. A. P. London, A. A. Ayon, A. H. Epstein, S. M. Spearing, T. Harrison, Y. Peles and J. L. Kerrebrock, "Microfabrication of a high pressure bipropella nt rocket engine," Sensors and Actuators-A: Physical vol. 92, pp. 351-357, 2001. 95. P. H. Chang, "TEM of gold-silicon inter actions on the back side of silicon wafer," Journal of Applied Physics, vol. 63, pp. 1473-1477, 1988. 96. G. S. Matijasevic, C. Y. Wang and C. C. Lee, “Void free bonding of large silicon dice using gold-tin alloys,” IEEE Transactions on Components, Hybrids, and Manufacturing Technology vol.13, issue 4, pp. 1128-1134, 1990. 97. S. M. L. Nai, J. Wei, P. C. Lim a nd C. K. Wong, "Silicon-to-silicon wafer bonding with gold as intermediate layer," Electronics Packaging Technology, pp. 119-124, 2003. 98. L. W. Lin, R. T. Howe and A. P. Pisano, "Microelectromechanical filters for signal processing," Journal of Microelect romechanical Systems vol. 7, pp. 286-294, 1998.

PAGE 177

158 99. A. Scatamacchia, “Laser welding for hermetic sealing of large MIC package,” Electronic Manufacturing Technology Sympos ium, IEMT Conference, 8th IEEE/CHMT International pp. 493-502, 1990. 100. C. Luo and L. Lin, "The applicatio n of nanosecond-pulsed la ser welding technology in MEMS packaging with a shadow mask," Sensors and Actuators-A: Physical vol. 97, pp. 398-404, 2002. 101. L. Lin, “MEMS post-packaging by localized heating and bonding,” IEEE transaction on Advanced Packaging vol. 23, no. 4, pp. 608-616, 2002. 102. J. Wang, E. Besnoin, A. Duckham, S. J. Spey, M. E. Reiss, O. M. Knio, M. Powers M. Whitener and T. P. Weihs, “Room-temper ature soldering with nanostructured foils”, Applied Physics Letters vol. 83, pp. 3987-3989, 2003. 103. C. C. Lee, C. Y. Wang and G. Mat ijasevic, "Au-In bonding below the eutectic temperature," I EEE transactions on Components, Hybrids and Manufacturing Technology vol. 16, no. 3, pp. 311-316, 1993. 104. Z. Marinkovic and V. Simic, "Cond itions for compound formation in Au/metal couples at room temperature," Journal of Less-Common Metals vol. 115, pp. 225-234, 1986. 105. W. Wang, S. Samson, R. Agarwal, J. Bu mgarner, R. Hazen, S. Kedia, G. Gonzalez, L. Langebrake, C. Munoz and E. Kaltenbacher ""Small form factor microsensor system using optical MEMS for passive opti cal digital communications (PODC)," Proc. SPIE on Micro (MEMS) and Nanotechnolog ies for Defense and Security vol. 65560N, May 2007.

PAGE 178

159 106. T. Pandhumsoporn L. Wang M. Feldbaum and P. Gadgil, "High-etch-rate deep anisotropic plasma etching of silicon for MEMS fabrication," Proc. SPIE on Smart Structures and Materials vol. 3328, pp. 93-101, 1998. 107. L. N. Ridenour, "Radar System Engin eering," Boston Technical Publishers, Inc. 1964.

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160 APPENDICES

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161Appendix A: Process Recipes Anodic Bonding Anodic bonding was used to bond one side of DSP Si wafer to Pyrex. The bonding parameters are shown in Table 6. Anodic bonding was performed on the indented side of Si. The ot her side of Si was patterned and DRIE was performed from this side. It was noticed that during the anodi c bonding this side, wher e the DRIE is to be performed, gets dirty as it comes in direct contact with the bonding chuck. To prevent this contamination and scratching of su rface a space SSP Si wafer was used. The rough side of this space wafer touches and bonding chuck and the polished side touches the DSP Si wafer. The indented side of this DSP wafer was then anodically bonded.

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162Appendix A: (Continued) Table 6: Parameters and Process Flow For Anodic Bonding. Step Command Parameter 1 Parameter 2 1 Pump ON High Vacuum 2 Wait Pressure 1x10-2 mbar 3 Pump OFF 4 Purge ON 5 Wait Time 0:00:30 6 Purge OFF 7 Piston Down 500 N 8 Heating 400C 0:00:00 9 Set Temp. Top 400C 10 Wait Temp Top 400C 11 Wait Temp Bottom 400C 12 Pump ON High Vacuum 13 Wait Pressure 1x10-3 mbar 14 Voltage ON Internal Negative 1000 15 Wait Time 0:10:00 16 Voltage OFF 17 Piston UP 18 Cooling 60C 0:00:00 19 Pump OFF 20 Purge ON 21 Wait Time 0:00:30 22 Purge OFF 23 Wait Temp Bottom 60C

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163Appendix A: (Continued) Oxygen Plasma Ashing Oxygen plasma ashing was used during various processing steps in this dissertation. Different recipes were used to etch polymer from the DRIEed sidewalls, to etch photoresist so th at the sidewalls of the photoresis ts are much smoother for further processing, and to clean off the remaining photoresists from the wafer after acetone/methanol cleaning. Table 7 shows th e different recipes which were used. Table 7: Various Oxygen Plasma Recipes Which Were Used. Purpose O2 Flow (sccm) Ar Flow (sccm) CF4 Flow (sccm) R.F. Power Time Cleaning Wafers 300 0 0 400 10 Smoothening Photoresist Sidewalls 260 0 0 200 7 Etching DRIE Polymers 400 0 0 400 60 NMEMS Release 500 0 0 300 180

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164Appendix A: (Continued) PECVD Recipe to deposit SiO2 Table 8: PECVD Recipe for SiO2 Deposition. LPCVD Recipe to deposit low stress Si3N4 Table 9: LPCVD Recipe for Si3N4 Deposition. Si3N4 Reactive Ion Etching The process parameters used for Si3N4 are listed below. Photoresist was used as masking layer. Command Parameter Pump Lovac Pressure 900mTorr SiH4 Flow Rate 160 sccm N2O Flow Rate 900 sccm NH3 Flow Rate 0 N2 Flow Rate 240 He Flow Rate 0 SF6 Flow Rate 0 RF1 25 Deposition Rate 47nm/min Command Parameter Growth Pressure 173 Torr Temperature 840 C NH3 Flow Rate 20 sccm DCS Flow Rate 100 sccm Purge Gas N2 RF1 25 Deposition Rate 4.83nm/min

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165Appendix A: (Continued) Table 10: RIE Etch Recipe for Si3N4. Command Parameter CHF3 flow rate 45 sccm O2 5 sccm Temp 24 Pressure 40 mTorr RF Power 200 DC 442 Etch Rate 6nm / min Fabricating Vertical DRIE Mirrors 1. Get 550 m thick, (100) 4" DSP Si wafer (from wafer world). 2. Deposit 90nm thick Si3N4 using LPCVD. 3. Spin Futurrex PY2000 positive photoresist on one side of the wafer at 3000rpm for 40 seconds using a delta spin coating system. 4. Soft bake the photoresist at 120C fo r 60 seconds on a vacuum hot plate. 5. Expose the wafer with the fan out ma sk for 3.4 seconds. Align the wafer so that the wafer flat aligns to a re ctangle on the mask. This is to ensure that the features of the mask are r oughly aligned in the <110> direction. 6. Develop the photoresist in RD 6 developer for 40 seconds 7. Inspect the wafer for critical dimensions. 8. RIE etch the Si3N4. 9. Strip photoresist in acetone/methanol. 10. Rinse the wafer in DI wafer and blow dry the wafer. 11. Perform KOH etching (30% w/ w KOH at 80C) for 1 hour.

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166Appendix A: (Continued) 12. Inspect the wafer using SEM images to determine the rectangle with least undercutting. This rectangle determin es the crystal <110> direction. 13. Again spin Futurrex PY2000 positive phot oresist on one side of the wafer at 3000rpm for 40 seconds using a delta spin coating system. 14. Soft bake the photoresist at 120C fo r 60 seconds on a vacuum hot plate. 15. Expose the wafer with the indentati on mask in a mask aligner for 3.5 seconds. 16. Develop the photoresist in RD 6 developer for 40 seconds. 17. Inspect the wafer under the optical microscope. If everything looks fine proceed to the next step otherw ise strip off the photoresist using acetone/methanol and repeat steps 3-17. 18. Etch the exposed Si3N4 in RIE using CHF3 and O2 plasma. 19. Strip off the photoresist using acetone/methanol. 20. Even after wet cleaning there are small traces of PR left on the wafers. To clean this wafer, O2 plasma (cleaning wafer) is performed. 21. Bond the wafer to a Pyrex wafer using anodic bonding. A spacer wafer is preferred to protect the other side. 22. The back side of the wafer was then patterned using the KOH:IPA mask to pattern the Si3N4. 23. Etch the exposed Si3N4 using RIE. 24. Strip the photoresist using acetone/methanol and descum process.

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167Appendix A: (Continued) 25. Sputter coat the back side of the wafer with 1000 thick Al. 26. Spin 1813 on top of Al. 27. Soft bake at 90C for 60 seconds. 28. Expose the photoresist with DRIE mask. 29. Hard bake the photoresist at 120C for 4 minutes. 30. Plasma clean the photoresist in O2 plasma to smoothen the photoresist edges. 31. Etch off the exposed Al by etching it in Al etchant for 3 minutes at room temperature. 32. Strip off the photoresist. 33. Perform DRIE for 700 cycles or until you can see the light go through the trenches when you take the wafe r out of the DRIE chamber. KOH:IPA Polishing and Metallization 1. After DRIE, flip the wafer upside down to remove the unwanted Si parts. 2. Few Si parts get electrostatically st uck to the Pyrex and can be easily removed by putting the wafer in IPA. 3. Strip off the Al using Tran sene Al etchant. After DRIE Al film takes much longer to etch. Just keep an eye and as soon as you see the entire Al being removed take out the wafer, rinse it and blow/spin dry it.

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168Appendix A: (Continued) 4. Dice the wafer using a dicing machin e so that you have 5.8mmx5.8mm dies. Thermocarbon blades, model # 2.187-6A-30RU-3, were used for dicing. Spindle speed of 15KRPM, cut speed of 0.8 mm/sec and feed speed of 0.8 mm/sec were used for dicing. 5. Strip off the photoresist. 6. Mix KOH:IPA in the ratio of 3M:2M in a Pyrex beaker. The solution is made by mixing KOH:IPA:H2O::116:62:224 in the given ratio. 7. Heat the solution to 50C on a hot plate. 8. Put a magnetic stirrer in the beaker, rotating at ~200rpm. 9. Put the chips to be polished in the beaker for 1 hour. 10. Remove the chips and rinse it thoroughly in DI water. 11. Blow dry and inspect the chip under the microscope at an angle to see the sidewalls of the vertical mirrors. 12. Black particles were noticed on the polished sidewalls after the KOH:IPA polishing. They were identified as iron particles with the help of EDAX. These particles were etched away by iron oxide etchant in 60 seconds. 13. Using a micro-pipette take 2 l of futurrex negative PR (NR9 1000PY). Pour this PR on one edge of the ve rtical mirrors (at the cross section point). Care should be taken not to scratch the mirror surface with the pipette. Repeat this on all the 4 corner s of the cross-hair. If done correctly one should not see any PR rings around the cross-hair areas.

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169Appendix A: (Continued) 14. Let the chip sit like this for 5 minutes. Spin the chip at 3000rpm for 40 seconds. 15. Let it again sit for 5 minutes. 16. Soft bake the photoresist at 150C for 60 seconds. 17. It was noticed that during spinning some of the PR flows around the corner to the Pyrex, which is on the b ack side of Si. After soft bake clean the Pyrex side of the chip. To do th is use acetone soaked kimwipes and with the help of a pair of tweezers gently rub the chip along the wipe. This cleans the Pyrex side and the same procedure is repeated with methanol soaked wipe to get rid of any acetone residue. 18. After cleaning place the chips on top of a Si wafer with Pyrex side on the top. Flood exposure is then perf ormed in the mask aligner. 19. Post bake the photoresist on a hot plate at 100C for 60 seconds 20. Develop the photoresist in RD 6 developer for 180 seconds 21. After developing one should see PR ju st on the Pyrex window and there shouldn't be any PR left either on th e package frame or the sidewalls of the vertical mirrors. 22. Metallize the chips in a sputtering m achine. Carbon conductive tape is used to hold multiple chips onto a Si wafer. One can also use photoresist for mounting the chips. 23. Sputter coat 200nm/1 m Ti/Au on the chips.

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170Appendix A: (Continued) 24. After sputtering the wafer, dissolve the adhesive tape in acetone to remove the chips. 25. Using a micro-probe release holes are manually created in the Au film. To do this the micro probe is used to remove Au from the bottom of the package frame area. It is not an activ e area for light to enter the CCR area hence doesn't damage the package lid/frame. 26. After 45-60 minutes the released film of Au is removed with the help of fine tweezers. 27. Small photoresist residue remaining on top of the package window is cleaned using descum recipe in plasma asher. KOH Etching on (110) Si Wa fer and assembly of CCR 1. Start with a 550 m thick (110) 4" DSP Si wafer. 2. Deposited 90nm thick Si3N4 using LPCVD. 3. Bond one side of the Si wafer to a Pyrex wafer using anodic bonding in a wafer to wafer bonder. Use a spacer wafer to protect the front side of the Si wafer from getting scratched 4. Spin Shipley 1813 photoresist on the Si. 5. The fan out mask is mechanically ali gned to the (111) wafer flat, and the wafer is exposed in the mask aligner. 6. Developed the photoresist in MF319 developer.

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171Appendix A: (Continued) 7. Perform a 3 minutes descum to remove any residual photoresist from the developed areas. 8. Etch the exposed Si3N4 for 15 minutes using RIE. 9. After RIE perform an acetone/metha nol clean and follow it by a short descum to clean the wafer. 10. KOH etch the wafer using 30% w/w KOH at 85C for 1 hour. 11. DI rinsed and blow dry the wafer in N2. 12. SEM images are used to determine th e rectangles with least undercutting from the fan out structures. This determines the ( 111) crystal flat. 13. The KOH etch mask is then aligned to the (111) crystal flat and the wafer is patterned using the KOH etch mask. 14. After the short descum again etch the exposed Si3N4 using RIE. 15. Clean the wafer again to get rid of any photoresist from the wafer. 16. KOH etch eth wafer for 5 hours in a 30% w/w KOH bath. Use a magnetic stirrer at 300rpm to remove the H2 bubbles from the etch sites. 17. Stop the etching when the wafer looks vi sually clear indica ting that all the Si from the window is removed. 18. Some black residue remains on the (111) surface and EDAX analysis shows that it was iron. 19. Use an Iron oxide etchant for one minute to remove this residue. 20. DI rinse the blow dry the wafer.

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172Appendix A: (Continued) 21. Spin Shipley 1813 on the wafer to prot ect the structures from dicing debris. 22. Using the dicing machine dice the wa fer to get required size chips. Separate the chips with package lids and the chips without the package lids. 6 mil (152.4 m) thick blade is used for this purpose. Dice the chips with the package frame to a size of 5.8mmx5.8mm. On the chips without the package frame separate the mirr ors to get a single mirror of 3.1mm length. Perform this dicing so that the dicing blade cuts through the Si and bonded Pyrex. Make a second cut usi ng 12 mil thick blades along the center of the long mirrors to make a gap between them. This form a 13.1 mil gap. Perform this dicing performed so that the blade cut through the Si and only partially th rough the Pyrex. 23. Clean the chips using acetone/m ethanol and blow dry them. 24. Metallized the vertical mirrors using the same liftoff process as described before. 25. Bond the chips without the package frame to the unreleased SOI chip using Au-Au thermo-compression bonding. 26. Liftoff the co-bonded Pyrex using la ser micromachining. During this process protect the underlying st ructures using photoresist. 27. After liftoff strip the photore sist using acetone/methanol.

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173Appendix A: (Continued) 28. Release the SOI wafer using HF wet re lease. To avoid stiction after the release, place the chips in IPA soluti on for 5 minutes and then dry them in a vacuum oven at 80C for 10 minutes. 29. After the release, perform the second bonding using the chips with package frame.

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174Appendix A: (Continued) Make and model of various tools used in this work Table 11: List of Tools, Thei r Manufacturer and Model Numbers. Purpose Manufacturer Model Thin film sputtering (Ti/Cr/Au) AJA ATC1800 Thin film LPCVD (Si3N4) Tystar Tystar 4600 Thin film evaporation (Au/In) AJA PVDX-1800 Series DRIE Unaxis SLR-7701-10R-B BOSCH DRIE System RIE Unaxis 790-10-RIE System PECVD Unaxis Plasma release/clean/descum Tepla PVA tepla M4L Plasma Processing System Laser micromachining JPSA JPSA IX-500 Excimer Laser Micromachining System Flip-chip bonding Finetech Pico5 Optical Microscope Nikon Nikon Eclipse L150 Optical Microscope Stereo zoom microscope Nikon SNZ800 Shear strength testing Roy ce Royce Instrument DSW-001 Wire bonding K&S K&S 4524D Ball Bonder Wafer bonder EVG EV501 Dicing saw K&S 982-10 plus Thin film measurement Filmetrics F20 Surface profilometer Tencor S-10 Surface Profiler Mask aligner EVG 620 Spinner Delta 2OT2 MEMS motion analyzer Umech Technologies MMA SEM Hitachi S4800 SEM JEOL JSM-5910LV Optical profilometer Veeco NT3300 Atomic force microscopy Veeco DI-3100 SPM/AFM Focused ion beam FEI DB235

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175Appendix B: Power and Range Calculations Calculating capacitance in NMEMS parts To determine the power consumption in NMEMS mirrors it was important to determine how much current the mirrors were drawing from the portable battery. Since the torsion mirrors can be considered as pa rallel plate capacitors, the capacitance was calculated as follows: F m m m F d A C14 2 18 110 9513 2 3 100 100 10 854 8 Equation 14 where is the permittivity of air. Since the metal on the bottom of Si3N4 was used as the top electrode the permittivity of Si3N4 is not used. A is the plate area of the capacitor and d is the gap between the capacitor plates. Total C F C CT13 110 37 7 25 Current dt dv dt dv c dt dq i 10 37 713 Equation 15 Since the mirrors are modulat ed using an AM modulated square wave signal with 50Khz carrier wave, with 20V P-P signal, it is justified to say that the 20V change in voltage level is achieved in a time interval of reaches 20V in a time interval of 10 s.

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176Appendix B: (Continued) Figure 77: Waveform Showi ng the Signal Used to M odulate the NMEMS Mirrors. Therefore we have A i4756 1 10 10 20 10 37 76 13 Therefore the current required to modulate a quad of CCR contai ning 25 mirrors should be approximately 1.4756 A. PowerW i v p512 29 10 4756 1 206 Equation 16 since the bit rate of the signal was 9600bps the energy required per bit of data transferred can be given by bit nJ bits W / 07 3 sec / 9600 10 512 296 However the actual current drawn by a quad of 25 mirrors was 100 times larger than the calculated current. It was conclude d that the routing pads which connect the

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177Appendix B: (Continued) mirrors to the bond pads also act as parasitic capacitors via the Si s ubstrate and draw a lot of current. Table 12: Table Showing the Area of the Input Traces and Bond Pads. Electrode Area ( m) Input trace to +/supply 152500 Input trace to ground 80000 Bond pad area for ground 1420342 Bond pad area for +/supply 1212443 Capacitance due to the electrical traces can be calculated using the formula given in Equation 14. F m m m F d A Cr 10 2 18 0 210 770 2 3 0 ) 1412443 152500 ( ) 6 10 854 8 ( F m m m F d A Cr 10 2 18 0 310 656 2 3 0 ) 1420342 80000 ( ) 6 10 854 8 ( These capacitors are in parallel and the total capacitor is given by F C C C10 3 210 355 1 1 1 1 A i271 10 10 20 10 355 16 10 and mW p 42 5 10 271 206 which is about the measured power drawn by the devices. To improve upon this power consumption 3 m thick SiO2 was also deposited under the Si3N4 layer to make a

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178Appendix B: (Continued) thicker dielectric layer on top of the wafer. It is also suggest ed in future designs to reduce the size of the input traces and bond pad area s to reduce this para sitic capacitance. Beam deviation with mirror misalignment If is the deviation of the dihedral angle from 90 the reflected beam gets split into two. The angle between the cent ers of these two beams is given by: n 3 6 4, Equation 17 where n is the refractive index of the material filling the CCR and is the deviation from the dihedral angle. For a CCR assembled as di scussed in this work, n =1. If the CCR works on the total internal reflection principle the n will vary accordingly. Therefore we get 266 3. If the deviation of one of the mirror from the dihedral angle of 90 is 0.1 radians) then we get 3.266x0.1 = 0.3266 radians. Transreceiver Reflector d x Transreceiver Reflector d x Figure 78: Calculating the Dist ance Between the Reflected Be ams With the Deviation of the Orthogonal Mirrors From the Dihedral Angle.

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179Appendix B: (Continued) As illustrated in Figure 78 if the distance d, between the reflector and the receiver, is 10m the distance between the two reflected beams will be given by d x / 2 2 tan By putting in the values we get m x 29 3 Thus the reflected beams will be 1.645 me ters away from the transmitted beam if the two mirrors are misaligned by 0.1 radi ans. Table 13 shows the list of angular deviation and distance between the reflected be ams with changes in the deviation of the mirrors from the dihedral angle. Table 13: Calculating the Distance Between th e Reflected Beams With the Deviation of the Orthogonal Mirrors From the Dihedral Angle. Deviation of one of the CCR mirrors (degrees) Angular deviation between reflected beams (degrees) Distance between the reflected beams and transmitted beam (cm), 10m from the reflector. 0.05 0.1633 1.425 0.08 0.2612 2.281 0.1 0.3266 2.851 0.2 0.6532 5.702 0.5 1.633 1.425 1 3.266 28.520 10 32.66 293.11

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180Appendix B: (Continued) Figure 79: Graph Showing the Change in Distance Between the Reflected Light W ith Deviation From Dihedral Angle.

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ABOUT THE AUTHOR Rahul Agarwal received the B.E. degree in Electronics Engineering from Nagpur University, Nagpur, India, in 2001 and the M.S. degree in Electrical Engineering from the University of South Florida, Tampa, in 2003 and Ph.D. in 2007. His research interests include MEMS design and fabrication, various bonding techniques, and MEMS packaging.