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Adhesion comparison of low dielectric constant thin films using four point bend and nanoscratch testing
h [electronic resource] /
by Daniel Vilceus.
[Tampa, Fla] :
b University of South Florida,
Title from PDF of title page.
Document formatted into pages; contains 76 pages.
Thesis (M.S.)--University of South Florida, 2008.
Includes bibliographical references.
Text (Electronic thesis) in PDF format.
ABSTRACT: As the semiconductor technology moves further into scaled down device structures, modern day complexities in the fabrication processes become more prevalent. This thesis focuses on the issues associated with mechaincal and adhesion failure in low dielectric constant (low-k) thin films. In this thesis the four point bend test and nanoscratch test method was used for evaluating adhesion of boro-phosphate-silicate glass (BPSG) and tetraethylorthosilicate (TEOS) low-k thin films to silicon subtrates. Nanoindation tests were also performed on the low-k films to evaluate material properties such as hardness and elastic modulus. The sample preparation and testing set up for the four point bend test and nanoscratch test were observed to be greatly disparate. Nanoscratch and nanoindentation sample preparation and sample testing were able to be carried out much quicker than in four point bending. It was observed that nanoscratch testing holds an immense potential for reducing the time needed to evaluate thin film adhesion then in FPB testing. Nanoindentation performed on the BPSG and TEOS dielectric thin films showed uniform mechinacal properties throughout the surface of the films. The adhesion energy for BPSG and TEOS using FPB testing ranged from 29.5390 J/m¨§ 3.0379 J/m¨§. While the adhesion energy for BPSG and TEOS using nanoscratch testing ranged from 0.0012 J/m¨§ 0.0028 J/m¨§. It was observed that the difference in adhesion energy for FPB and nanoscratch testing was due to differing failures modes.
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Advisor: Ashok Kumar, Ph.D.
x Mechanical Engineering
t USF Electronic Theses and Dissertations.
Adhesion Comparison of Low Dielectric Constant Thin Films Using Four Point Bend and Nanoscratch Testing by Daniel Vilceus A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Mechanical Engineering Department of Mechanical Engineering College of Engineering University of South Florida Major Professor: Ashok Kumar, Ph.D. Frank Pyrtle, Ph.D. Muhammad Rahman, Ph.D. Date of Approval: May 29, 2008 Keywords: epoxy, fracture, hardness, modulus, notch silicon Copyright 2008 Daniel Vilceus
DEDICATION I dedicate this thesis to the Lord and my family, e specially my loving parents Joseph M. and Marie C. Vilceus. I owe every achievement of m y life to my parents, brothers and sister. I am extremely grateful for the continuous mentoring, encouragement and love they have provided throughout my life.
ACKNOWLEDGMENTS I would like to thank Dr. Kumar for being my advis or and for taking me in for the research experience for undergraduates (REU) studen t program. I would also like to thank Dr. Pyrtle and Dr. Rahman for being in my com mittee. I want to recognize Dr. Makoto Hirai and the Nanomaterials & Nanomanufactur ing Research Center (NNRC) staff for their guidance and assistance in using va rious NNRC imaging equipment. I will never forget the support of my colleagues in Dr. Ku mars group, especially Michael, Jessica, Harish, Raghu and Zantye. I also have to thank the mechanical engineering staff, especially Sue and Shirley for their support. I wo uld like to thank Dr. Rahman again for recommending to McNair Scholar program here at USF. The McNair Scholar program has impacted my life aspirations in ways that canno t be repaid. I would like to give a big thank you to Dr. Joan Holmes, my McNair Scholar coo rdinator. I am also grateful to have had Rosalynne Miller and Bernard Batson as my McNair Scholar advisors. I want to thank my parents and family again for their endl ess support and patience. Thank you to everyone I may have forgotten!
i TABLE OF CONTENTS LIST OF TABLES iv LIST OF FIGURES v ABSTRACT ix CHAPTER 1: INTRODUCTION 1 1.1 Manufacturing goals of integrated circuits 1 1.2 Multilayer structures 2 1.3 Chemical mechanical planarization (CMP) 3 1.4 Failure and reliability issues in MLM structure fabrication during CMP 4 1.5 The role of low dielectric constant thin films in integrated circuits 4 1.6 Candidate low-k thin films 7 1.7 Review of adhesion energy for thin films 8 1.8 Thesis motivation and objectives 9 CHAPTER 2: EVALUATION OF MECHANICAL PROPERTIES FOR LOW DIELECTRIC CONSTANT THIN FILMS USING NANOINDENTATIO N TESTING 10 2.1 Introduction to nanoindentation testing 10 2.2 Theoretical development of the nanoindentation test 12
ii 2.3 MTS Nano Indenter XP 15 2.4 Nanoindentation sample preparation 17 2.5 Results and discussions of low-k thin film nano indentation tests 19 CHAPTER 3: EVALUATION OF ADHESION ENERGY FOR LOW DIELECTRIC CONSTANT THIN FILMS USING FOUR POINT BEN D TESTING 26 3.1 Introduction to four point bend testing 26 3.2 Theoretical development for adhesion energy of four point bend testing 27 3.3 DTS Delaminator test system 30 3.4 FPB sample preparation 32 3.5 FPB wafer bonding 33 3.6 FPB wafer epoxy curing 37 3.7 FPB sample wafer dicing 38 3.8 Notching of the FPB sample 39 3.9 FPB testing using the DTS Delaminator test syst em 40 3.10 FPB sample preload and loading test 41 3.11 Notch crack propagation 42 3.12 Interfacial delamination 42 3.13 Results and discussions of adhesion energy usi ng four point bend tests 43
iii CHAPTER 4: EVALUATION OF ADHESION ENERGY FOR LOW DIELECTRIC CONSTANT THIN FILMS USING NANOSCRATCH TESTING 57 4.1 Introduction of scratch testing 57 4.2 Theoretical adhesion energy for nanoscratch tes ting 59 4.3 CETR Universal Tribometer system 60 4.4 Nanoscratch sample preparation and test paramet ers 62 4.5 Results and discussions of low-k thin film nano scratch test results 64 4.6 Nanoscratch test error propagation 70 CHAPTER 5: THESIS CONCLUSION 72 5.1 Thesis summary 72 5.2 Future work 74 REFERENCES 75
iv LIST OF TABLES Table 1.1 MLM fabrication projections (Hendricks, 1 999) 7 Table 2.1 BPSG low-k material properties 21 Table 2.2 TEOS low-k material properties 22 Table 2.3 Fused silica material properties 25 Table 3.1 BPSG delamination 53 Table 3.2 TEOS delamination 56 Table 4.1 Nanoscratch test (NSCT) parameters 63 Table 4.2 Nanoscratch test critical load and adhesi on energy for BPSG and TEOS low-k thin film 70
v LIST OF FIGURES Figure 1.1 Transistors per chip area vs. years of e lectronic advances (Moore, 2003) 1 Figure 1.2 Schematic of an MLM structure (Lee, 2003 ) 2 Figure 1.3 Schematic of wafer planarization by CMP process (Zantye, 2005) 3 Figure 1.4 Delaminated dielectric capping layers CM P (Zantye, 2005) 4 Figure 1.5 IC device speed equation (Bohr, 1995) 5 Figure 1.6 Hardness vs. dielectric constant (Ryan, 2005) 6 Figure 1.7 BPSG and TEOS low-k wafers, respectively 8 Figure 2.1 SEM of a diamond Berkovich nanoindenter tip 11 Figure 2.2 Loading and unloading nanoindentation on a material 12 Figure 2.3 40X surface view of fused silica indenta tion impressions 13 Figure 2.4 Loading and unloading nanoindentation cu rve (Crawford, 2006) 13 Figure 2.5 MTS Nano Indenter XP 16 Figure 2.6 Schematic of the CSM loading cycle (Li, 2002) 17 Figure 2.7 Sample mounted on disk 17 Figure 2.8 Sample tray 18 Figure 2.9 Sample tray inserted into MTS Nano Inden ter XP 18 Figure 2.10 BPSG25 sample elastic modulus test 19
vi Figure 2.11 BPSG25 sample hardness test 20 Figure 2.12 BPSG25 sample loading and unloading tes t 20 Figure 2.13 BPSG and TEOS modulus values 22 Figure 2.14 BPSG and TEOS hardness values 23 Figure 2.15 Fused silica sample modulus curve 24 Figure 2.16 Fused silica sample hardness curve 24 Figure 2.17 Fused silica sample loading and unloadi ng curve 25 Figure 3.1 Four point bend test on a ceramic sample 26 Figure 3.2 Three point bend and four point bend mom ent diagrams 27 Figure 3.3 A schematic of a FPB sample (Zhenyu, 20 05) 30 Figure 3.4 DTS Delaminator test system 31 Figure 3.5 DTS Delaminator test system frame (DTS, 2004) 32 Figure 3.6 50 mm X 50 mm diced silicon sample (left ) and low-k sample (right) 32 Figure 3.7 EPO-Tek 375 resin (left) and hardener (r ight) 33 Figure 3.8 EPO-Tek 375 epoxy applied on Si wafer us ing a razor tip 33 Figure 3.9 EPO-Tek 375 epoxy applied on Si wafer us ing a pipette nozzle 34 Figure 3.10 EPO-Tek 375 epoxy on Si wafer 34 Figure 3.11 FPB sample clamping setup 35 Figure 3.12 FPB sample clamping 35 Figure 3.13 Schematic of FPB sample clamping 36 Figure 3.14 FPB sample hydraulic clamping setup 36 Figure 3.15 FPB sample hydraulic clamping with wood en blocks 37
vii Figure 3.16 Lindberg/Blue tube furnace 37 Figure 3.17 Thermolyne 4800 furnace 38 Figure 3.18 MA 1006 Dicing Saw available at the NNR C 39 Figure 3.19 Diced and notched FPB sample 39 Figure 3.20 Notch cut (DTS, 2004) 40 Figure 3.21 FPB sample set up (DTS, 2004) 40 Figure 3.22 FPB sample loading 41 Figure 3.23 FPB sample notch crack 42 Figure 3.24 Interfacial delamination 43 Figure 3.25 Load vs. displacement curve for notch d epth below 85% 44 Figure 3.26 Load vs. displacement curve (actuator s peed greater than 2 um/sec) 45 Figure 3.27 Load vs. displacement curve (actuator s peed decreased after notch crack) 46 Figure 3.28 FPB partial delamination load vs. displ acement curve 47 Figure 3.29 BPSG sample partial delamination 47 Figure 3.30 TEOS sample partial delamination 47 Figure 3.31 BPSG22-4 delamination curve 48 Figure 3.32 BPSG22-4 delamination 49 Figure 3.33 BPSG22-4 50X view of delamination 49 Figure 3.34 Raman spectroscopy calibration Si wafer 50 Figure 3.35 BPSG22-4 Raman spectroscopy of delamina tion 51 Figure 3.36 BPSG adhesion energy 52
viii Figure 3.37 TEOS5-8 delamination curve 54 Figure 3.38 TEOS5-8 delaminated sample 54 Figure 3.39 TEOS5-8 50X view of delamination 55 Figure 3.40 TEOS adhesion energy 56 Figure 4.1 Configuration of a scratch test (Fischer -Cripps, 2002) 57 Figure 4.2 Scratch test on a multilayer thin film ( Fischer-Cripps, 2002) 58 Figure 4.3 Coefficient of friction vs. scratch leng th (Fischer-Cripps, 2002) 59 Figure 4.4 CETR Universal Tribometer 60 Figure 4.5 Scratch tip and AE sensor head 61 Figure 4.6 Face forward nanoscratch tip orientation 62 Figure 4.7 Nanoscratch sample setup 62 Figure 4.8 In-situ nanoscratch recording 64 Figure 4.9 In-situ of the BPSG1 low-k film using NS CT2 65 Figure 4.10 SEM of BPSG1 low-k film surface chippin g 66 Figure 4.11 SEM of initial delamination of BPSG1 lo w-k film 66 Figure 4.12 SEM of complete delamination of BPSG1 l ow-k film 67 Figure 4.13 In-situ of the BPSG1 low-k film using N SCT4 68 Figure 4.14 Nanoscratch test critical load for BPSG and TEOS low-k thin film 69 Figure 4.15 Nanoscratch test adhesion energy for BP SG and TEOS low-k thin film 69
ix ADHESION COMPARISON OF LOW DIELECTRIC CONSTANT THIN FILMS USING FOUR POINT BEND AND NANOSCRATCH TESTING Daniel Vilceus ABSTRACT As the semiconductor technology moves further into scaled down device structures, modern day complexities in the fabricat ion processes become more prevalent. This thesis focuses on the issues associated with m echaincal and adhesion failure in low dielectric constant (low-k) thin films. In this t hesis the four point bend test and nanoscratch test method was used for evaluating adh esion of boro-phosphate-silicate glass (BPSG) and tetraethylorthosilicate (TEOS) low -k thin films to silicon subtrates. Nanoindation tests were also performed on the low-k films to evaluate material properties such as hardness and elastic modulus. The sample p reparation and testing set up for the four point bend test and nanoscratch test were obse rved to be greatly disparate. Nanoscratch and nanoindentation sample preparation and sample testing were able to be carried out much quicker than in four point bending It was observed that nanoscratch testing holds an immense potential for reducing the time needed to evaluate thin film adhesion then in FPB testing.
x Nanoindentation performed on the BPSG and TEOS die lectric thin films showed uniform mechinacal properties throughout the surfac e of the films. The adhesion energy for BPSG and TEOS using FPB testing ranged from 29. 5390 J/m2 3.0379 J/m2. While the adhesion energy for BPSG and TEOS using nanoscr atch testing ranged from 0.0012 J/m2 0.0028 J/m2. It was observed that the difference in adhesion energy for FPB and nanoscratch testing was due to differing failures m odes.
1 CHAPTER 1: INTRODUCTION 1.1 Manufacturing goals of integrated circuits In 1975 Gordon Moore stated that the projected num ber of transistors that can be fabricated on a very large scale integrated (VLSI) chip would double every 18 months (Moore, 1975). His projection is now known is Moor es Law. Figure 1.1 below shows the projected trend of transistor increase per chip area through 2010. Figure 1.1 Transistors per chip area vs. years of e lectronic advances (Moore, 2003)
2 The main focus of the semiconductor industry is to continue to meet the projected transistor growth described in Moores Law until Mo ores Law cannot be sustained and meets a physical fundamental barrier. 1.2 Multilayer structures One method of packing more transistors per area in a chip is to stack planes of transistors on top of each other. The transistor s tack illustrated in Figure 1.2 is a multilayer metallization (MLM) structure. In MLM s tructures each plane of transistors is isolated by a dielectric capping layer that prevent s electrical signal propagation between neighboring planes. The planes in MLM structures a re connected to each other by wiring that goes through wholes in the dielectric capping layer. Figure 1.2 Schematic of an MLM structure (Lee, 2003 )
3 1.3 Chemical mechanical planarization (CMP) Chemical mechanical planarization (CMP) is the met hod that is universally accepted to planarize surfaces during fabrication o f MLM structures. Compared to conventional planarization technologies such as bia s sputtering and dry etching processes, CMP offers more versatility, simplicity and better global planarization. Figure 1.3 shows how surfaces are planarized using the CMP process. During the CMP process, the surface to be planarized is held at pressure ag ainst a rotating polishing pad soaked by abrasive based slurry. Figure 1.3 Schematic of wafer planarization by CMP process (Zantye, 2005)
4 1.4 Failure and reliability issues in MLM structure fabrication during CMP During the CMP process, MLM structures experience a multitude of forces as each transistor plane and dielectric capping layer is planarized. These forces are often the cause of device failure through delamination of the dielectric capping layer. Figure 1.4 below shows the delamination of dielectric capping layers during CMP. Figure 1.4 Delaminated dielectric capping layers CM P (Zantye, 2005) 1.5 The role of low dielectric constant thin films in integrated circuits A dielectric material is a substance that is a poo r conductor of electricity but is able to hold an electrostatic field. The dielectri c constant (k) of a material measures ability of that material to hold an electrostatic f ield. Ideally the lowest dielectric constant of a material is given a value of 1. As seen in fi gure 1.5 the device speed is inversely proportional the k value of MLM structure capping l ayers.
5 Figure 1.5 IC device speed equation (Bohr, 1995) Low dielectric constant (low-k) films play a numbe r of roles in the IC (integrated circuits) industry. Their functionality can range from radiation resistance, masking for diffusion, diffusion from doped oxides, protecting of doped films to prevent dopant loss, mechanical or chemical protection, to electronic in sulation. Due to its ease of preparation and extensively well characterized properties, the most commonly used dielectric is silicon dioxide (SiO2) (Zaininger, 1969). Nevertheless the k value of SiO2 is not low enough to meet the demands of future IC devices. T his has prompted the development of alternative low-k materials. The production of alt ernative low-k materials aim to decrease the dielectric constant value thereby incr easing the materials semi-conductive insulation potential. However as materials with l ower k values are created, the mechanical properties for these materials began to degrade as shown in figure 1.6.
6 Figure 1.6 Hardness vs. dielectric constant (Ryan, 2005) To meet industry goals for applications in the mon olithic semiconductor technology, the production of new materials with lo w-k values is urgently needed. As seen in table 1.1 IC device stacking planes, device frequency and plane to plane interconnects are projected to increase through 201 0, while the feature size and k values of capping layers in MLM structures are projected t o decrease. To meet these MLM structure fabrication goals, capping layers must ha ve good adherence to semi-conductive surfaces and retain good mechanical properties for structural rigidity during device fabrication.
7 Table 1.1 MLM fabrication projections (Hendricks, 1 999) Year 1996 1999 2002 2005 2010 Feature size (m) 0.35 0.25 0.18 0.13 0.1 Metal levels 4-5 5 5-6 6-7 7-8 Device frequency (MHz) 200 350 500 750 1000 Interconnect length (meters/chip) 380 840 2100 4100 6300 Dielectric constant (k) 4 2.9 2.3 <2 2~1 1.6 Candidate low-k thin films In this thesis the adhesion of boro-phosphatesili cate glass (BPSG) and the adhesion of tetraethylorthosilicate (TEOS) to silic on (Si) substrates were evaluated. BPSG low-k films are produced by doping SiO2 with boron and phosphorous. BPSG is often used as a capping layer because it reduces of sodium contaminates during IC devices fabrication (Walder, 2004). TEOS is used a s a low-k material for interconnect technologies because it provides reduced dynamic po wer dissipation and signal propagation delay (Loke, 1998). Both BPSG and TEOS are deposited by chemical vapor deposition (CVD) process and are known for their sm ooth topographies as seen in figure 1.7. The BPSG and TEOS low-k films used in this th esis were provided by Syntax Company.
8 Figure 1.7 BPSG and TEOS low-k wafers, respectively 1.7 Review of adhesion energy for thin films As previously mentioned, during the fabrication of MLM structures by CMP process many force are induced on the structure. Th ese forces cause interfacial delamination separating the low-k film thins film f rom the adjacent substrate. The adhesion energy between two materials is can be cha racterized by the work required to separate the materials from each other. Adhesion e nergy has also been referred to as interfacial fracture toughness (Zhang, 2004). In o rder to measure interfacial fracture toughness, the work of adhesion (adhesion energy) a s the film is removed from the substrate needs to be analyzed. Traditionally adhe sion of thin films has been measured through rudimentary methodologies. One method of measuring the adhesion of a thin fil m is the tape test. In the tape test adhesive tape is put on a film surface and is pulled off. The adhesion of the film to the underlying surface is deemed good if the film r emains on the substrate. On the other hand, adhesion is deemed bad if the film is removed from the surface while the tape is
9 ripped away. In addition to tape test, the stud te st has been another crude method of measuring adhesion strength. In the stud pull test the film surface has a stud glued onto it. Adhesion is then measured by the force needed to pull the stud and the film from the underlying substrate. The manner at which these te sts measure adhesion often introduce counter productive plastic deformations in the film s from the bending, stretching, and tearing associated with the sample preparation. Th us difficulties in interpreting the adhesion results for the tape and stud pull test ma ke them undesirable methods for characterizing or scientifically analyzing adhesion 1.8 Thesis motivation and objectives As semiconductor technology moves further into sca led down device structures, measuring the adhesion of low-k thin films to subst rates becomes increasingly important. The motivation behind this thesis was to measure th e adhesion energy of low-k capping layers by using four point bend (FPB) and nanoscrat ch testing methods. The objectives of this thesis were to evaluate the material proper ties of the BPSG and TEOS low-k thin films and optimize the parameters that promote thin film delamination in order to measure the adhesion energy for the FPB and nanoscr atch testing methods.
10 CHAPTER 2: EVALUATION OF MECHANICAL PROPERTIES FOR LOW DIELECTRIC CONSTANT THIN FILMS USING NANOINDENTATIO N TESTING 2.1 Introduction to nanoindentation testing The process of indenting can be defined as a metho d by which a material whose mechanical properties (hardness and elastic modulus ) are well known touches another material for which the mechanical properties are un known or not well defined (FischerCripps, 2002). The method of indentation has origi ns from the 19th century. In 1822 Mohs hardness scale categorized materials by their ability to leave a permanent scratch on another material. Moh assigned diamond the high est score of 10 on his scale. It was from Mohs method of material hardness characteriza tion that well known methods like the Brinell, Knoop, Vickers, and Rockwell came abou t. Nanoindentation essentially follows the same principle. However nanoindentatio n differs from these methods in one important area. While indentation tests like Brine ll, Knoop, Vickers, and Rockwell measure the residual impression left on the materia l with macroscopic tools. In nanoindentation it becomes difficult for measuremen ts to be performed with conventional equipment, due to the small material thicknesses in volved. Nanoindentation test results are produced partially by recording the penetration depth of a hard material like the diamond tip (Berkovich tip) illustrated in figure 2 .1.
11 Figure 2.1 SEM of a diamond Berkovich nanoindenter tip The knowledge of the penetration depth coupled wit h the known geometry of the indenter provides an indirect measurement of the me chanical properties of the indented material. Nanoindentation testing for thin films h as been in development over the past two decades for the purpose of analyzing the physic al properties of micron and submicron scale materials. In this thesis the term thin film denotes thicknesses of about 1000 nm 10 nm. Current nanoindentation systems c an position indents within 1 um each other. Newer systems have been integrated wit h optical systems which enable the user explore the topography of the thin film surfac e before and after indentations are
12 performed. Nanoindentation testing is the leading choice for analyzing the hardness and or elastic properties of a material because of its ease in regards to sample preparation. 2.2 Theoretical development of the nanoindentation test In nanoindentation experiments for the nanometer s cale, the indenters are generally made from diamond which can have an axsym metric or symmetric pyramidal geometry with a very small radius of curvature at t he apex. As seen figure 2.2 during a nanoindentation test, the indenter tip is increment ally pushed into the thin film material of interest at a constant speed. The force (P) acting on the tip is measured as the tip is driven into the thin film. Once the tip has reache d a specified penetration depth, the tip is then incrementally retracted to its original positi on above the thin film. From this loading and unloading of the indenter tip the mechanical pr operties such as hardness and elastic modulus are determined. Figure 2.2 Loading and unloading nanoindentation on a material
13 As the tip is pushed into the material of interest it will plastically deform the material leaving an impression like the ones in dep icted in figure 2.3. Figure 2.3 40X surface view of fused silica indenta tion impressions The load vs. indenter penetration depth curve in f igure 2.4 shows the hysteresis between the load and unloading curve that denote th e plastic deformation experienced by the indented material. Figure 2.4 Loading and unloading nanoindentation cu rve (Crawford, 2006)
14 An important parameter to obtaining the mechanical properties in materials using nanoindentation is the projected contact indenter t ip area which varies with the indentation depth. The most agreed upon method for nanoindentation was developed by Oliver and Pharr (Oliver, 1992). The load P from t he load vs. depth penetration curve is fitted by parameters B and m in equation 2.1. Equa tion 2.1 takes into account the resulting depth penetration (h), and final displace ment (hf) after and tip has completely been unloaded from the test sample (MTS, 2001) ( ) m fh h B P = (2.1) The slope of the unloading curve from the load vs. penetration depth graph is obtained by differentiating equation 2.1 and evalua ting it at the maximum penetration depth (MTS, 2001 and Oliver, 1992) ( ) dh dP h h h h Bm Smax 1 m f= = =(2.2) The equation for determining the depth at which th e indenter tip is in contact (hc) with the thin film is S P h hc= (2.3) where is a constant which corresponds to the geometry of the indenter being used (Oliver, 1992). For the Berkovich tip =0.75 (Fischer-Cripps, 2002). Lastly, with the geometry of the indenter tip known (provided by the manufacture), the projected area A is a function of the contact depth (Oliver, 1992) ( ) ch f A= (2.4)
15 The hardness (H) of a material measures the materi als resistance to penetration by a hard object (Kalpakjian, 2003) A P H= (2.5) where P is load applied on the test surface and A i s the projected contact area at the load. The thin film elastic modulus (Ef) is determined by the combination of the film modu lus and indenter modulus (Ei), called the reduced modulus (Erif) (Oliver, 1992) ( ) A 2 S Erif = (2.6) where dP/dh is the contact stiffness (S). The geom etry correction factor, beta () is 1.034 for the commonly used Berkovich indenter (Fis cher-Cripps, 2002). The elastic modulus for the thin film is determined using the e quation (Oliver, 1992) ( ) ( ) i 2 i f 2 f rifE1 E1 E 1+ = (2.7) where f and i are the Poisson ratio of the film and indenter, re spectively. 2.3 MTS Nano Indenter XP In this thesis the MTS Nano Indenter XP at USFs advance materials lab was used to indent the BPSG and TEOS low-k thin films f or hardness and elastic modulus data. The MTS indenter in figure 2.5 has a maximum applied load of 500 mN, an indenter load resolution of 50 nN, and a displaceme nt resolution of 0.02 nm. The MTS indenter uses Testworks 4 interface software to ana lyze the collected indentation data.
16 Figure 2.5 MTS Nano Indenter XP All indentations done in this thesis used the cont inuous stiffness measurement (CSM) option. As seen in figure 2.6 the CSM option differs from traditional nanoindentation in that the resultant data is deriv ed from partially unloading the indenter at each load increment and not just at the maximum depth penetration. The advantage of using the CSM option is that it provides viscoelast ic behavior of materials which provides information about the storage or loss of t he test sample moduli (Li, 2002). The CSM option also provides less sensitivity to therma l drift to allow accurate observation of small volume deformation. Indenter
17 Figure 2.6 Schematic of the CSM loading cycle (Li, 2002) 2.4 Nanoindentation sample preparation From start to finish sample preparation for nanoin dentation test can range from 1 10 minutes. First the test sample is mounted o n a flattened disk, as seen in figure 2.7. A small amount of adhesive glue (cyanoacrylate also known as Super glue) can be applied between the disk and the bottom of the test sample. Figure 2.7 Sample mounted on disk
18 Next the disk is placed on a sample tray like the one depicted in figure 2.8, and then leveled off to insure all the test samples do not exceed a predetermined indenter tip height. Figure 2.8 Sample tray Next the sample tray is inserted into the MTS Nano Indenter XP for material testing as shown in figure 2.9. Figure 2.9 Sample tray inserted into MTS Nano Inden ter XP
19 2.5 Results and discussions of low-k thin film nano indentation tests In this thesis the mechanical properties of 9 sili con (Si) wafers with low-k thin films deposited on them were tested using nanoinden tation. Although 15 random indents were performed on each low-k thin film, figures 2.1 0, 2.11 and 2.12 show the profile curves of the BPSG low-k thin film wafer 25, which resembled the modulus, hardness, and load curves profiles for the all thin films tes ted. Due to insufficient indenter contact area with the low-k thin films, as a rule of thumb the first 20 to 30 nm of the indentations were disregarded (FischerCripps, 2002). This lack of indenter contact area explains the non uniform mechanical properties exhibited at the beginning of figures 2.10 and 2.11. 0 20 40 60 80 100 020406080100120140 Displacement into surface (nm)Modulus (GPa) BPSG25 Figure 2.10 BPSG25 sample elastic modulus test In figure 2.11 the hardness of the BPSG25 film beg ins to stabilize after 40 nm indenter depth. This steady hardness value indicat es that the material is uniform and does not change in material throughout the thickness of the film. In figure 2.12, the plastic deformation that occurred in BPSG25 film can be see n by the difference in the loading
20 and unloading of the indenter. It can be observed that the BPSG film was plastically deformed to a depth of 80 nm. 0 1 2 3 4 5 6 7 020406080100120140 Displacement into surface (nm)Hardness (GPa) BPSG25 Figure 2.11 BPSG25 sample hardness test 0 0.5 1 1.5 2 020406080100120140 Displacement into surface (nm)Load on sample (mN) BPSG25 Figure 2.12 BPSG25 sample loading and unloading tes t
21 Table 2.1 shows the average value for the mechanic al properties of BPSG wafer 1, 21, 22, 23, 24, and 25. The indentation uncerta inties for the elastic modulus and hardness of all BPSG and TEOS films were calculated by the Testworks 4 software in the MTS Nano Indenter XP. Also the BPSG and TEOS mech anical properties were calculated at 10% depth of the thin film thickness to avoid Si substrate effects that may alter the material property values (Oliver, 1992). Table 2.2 shows the average value for the mechanical properties of TEOS wafer 3, 5, 7. Table 2.1 BPSG low-k material properties Low-k thin film wafer Film thickness (nm) Elastic modulus (GPa) Hardness (GPa) Penetration depth (nm) BPSG1 435 61.300 0.615 4.940 0.192 131 BPSG21 433 64.109 0.859 4.528 0.166 130 BPSG22 430 62.955 0.371 4.734 0.219 129 BPSG23 426 65.045 0.267 4.631 0.490 128 BPSG24 433 63.798 0.429 4.845 0.185 130 BPSG25 623 64.319 0.493 4.327 0.795 130
22 Table 2.2 TEOS low-k material properties Low-k thin film Film thickness (um) Elastic modulus (GPa) Hardness (GPa) Penetration depth (nm) TEOS3 1.1 82.933 3.373 13.171 0.205 110 TEOS5 1.1 79.198 7.534 13.878 1.372 110 TEOS7 1.1 81.713 5.453 12.021 0.785 110 Depicted in figure 2.13 and figure 2.14 are the mo dulus and hardness values for both BPSG and TEOS film samples, respectively. The se bar graphs show that the mechanical properties of the low-k thin films used in this thesis did not change, and thus were uniform throughout the surface of the wafer. 0 20 40 60 80 100 Modulus (GPa) BPSG and TEOS low-k BPSG1 BPSG21 BPSG22 BPSG23 BPSG24 BPSG25 TEOS3 TEOS5 TEOS7 Figure 2.13 BPSG and TEOS modulus values
23 0 3 6 9 12 15 Hardness (GPa) BPSG and TEOS low-k BPSG1 BPSG21 BPSG22 BPSG23 BPSG24 BPSG25 TEOS3 TEOS5 TEOS7 Figure 2.14 BPSG and TEOS hardness values Before and after performing indentation tests for both the BPSG and TEOS test samples, indentations were also performed on fused silica for indenter tip calibration purposes. The calculation depth of 150 nm was used for calculating the fused silica material properties. Figures 2.15, 2.16, and 2.17 show the modulus, hardness, and load curves of the fused silica sample after all nanoind entation test were completed. Table 2.3 shows that the fused silica properties were within the correct range of 8.5 10.5 GPa and 69 74 GPa for the hardness and elastic modulus, r espectively. The fused silica calibration test also show that since the fused sil ica properties were correct, the tip was not damaged during the indentations of the BPSG and TEOS films.
24 0 50 100 150 200 050100150200250300 Displacement into surface (nm)Modulus (GPa) Fused silica Figure 2.15 Fused silica sample modulus curve 0 2 4 6 8 10 12 14 050100150200250300 Displacement into surface (nm)Hardness (GPa) Fused silica Figure 2.16 Fused silica sample hardness curve
25 0 2 4 6 8 10 12 050100150200250300 Displacement into surface (nm)Load on sample (mN) Fused silica Figure 2.17 Fused silica sample loading and unloadi ng curve Table 2.3 Fused silica material properties Fused silica Elastic modulus (GPa) Hardness (GPa) Penetration depth (nm) 72.016 0.082 10.039 0.665 280
26 CHAPTER 3: EVALUATION OF ADHESION ENERGY FOR LOW DIELECTRIC CONSTANT THIN FILMS USING FOUR POINT BEN D TESTING 3.1 Introduction to four point bend testing Three point bend and four point bend (FPB) testing has traditionally been used to analysis the fracture toughness of bulk materials. Depicted in figure 3.1 is a ceramic sample that has fractured under an increasing load during a four point bend test. Figure 3.1 Four point bend test on a ceramic sample The orientation and number of load points differen tiate the three point bend from four point bend test. As seen figure 3.2 the three point bend test applies a maximum
27 bending moment at the center load point of the test sample. However the four point bend load points permit the test sample to experience a maximum bending moment at larger surface area between the inner load pins. This all ows defects or weak points that may lead to fracture to be analyzed. The four point be nd test has in the past several years been adapted as an alternative method to investigating a nd measuring thin film adhesion energy. Figure 3.2 Three point bend and four point bend mom ent diagrams 3.2 Theoretical development for adhesion energy of four point bend testing In FPB testing, the governing equation for determi ning the adhesion energy begins with the fundamental concept of internal wor k. This internal work is often called strain energy (U) (Gere, 2001) x P dx P Ux0D = = (3.1) where P is any value for a force between zero and t he maximum value P which corresponds to the elongation of a bar over a dista nce x D In geometric terms, the work
28 done by the load P is equal to the area under a loa d vs. displacement curve. The SI unit for strain energy is the joule (J), which is equal to 1 Newton meter (1 J = 1 Nm) (Gere, 2001). As an actuator presses on the test sample the maxi mum bending moment occurs in the region between the inner pins. The equation for bending moment in this region is PL M = (3.2) where P equals the force applied on each pin and L is the distance between the outer and inner pin. However the force P from the actuator i s divided equally between the two pins on either side of the sample being tested. Thus P= P/2 at each of the pin positions making equation 3.2 become 2 PL M = (3.3) The angle of rotation of a beam axis is S rfsI E ML = (3.4) where is defined as the angle of the arc length that the test sample produces while being bent by the actuator load (Gere, 2001). Erfs is the reduced elastic modulus for the test sample (Ugural, 2003) ( ) ( ) S 2 S F 2 F rfsE 1 E 1 E 1 + = (3.5) where Ef is the thin film modulus, Es is the substrate modulus, F is the Poisson ratio of the thin film, andS is the Poisson ratio of the substrate. In this th esis it is assumed that since there is such a great disparity in thickness between the substrate
29 (approximatelym 10 1.453 - ) and the thin film (approximatelym 10 4259 - ), the effect of low-k film on the test sample bending is negligible Thus the material properties of the thin film in regards to the reduced modulus are ass umed zero, and the reduced modulus of the FPB test sample is now ( ) S 2 S rfsE1 E 1 = (3.6) The moment of inertia (IS) for the FPB test sample is 12 H B I3 S= (3.7) where B is the width of the test sample and H=H1+H2 is the height of the total thickness of the test sample Si substrate as seen in figure 3 .3 (Gere, 2001). Combining the angle of rotation of a beam axis (eq uation 3.4) and bending moment (equation 3.3) on the sample we obtain the e quation for strain energy of the test sample (Ugural, 2003) 3 rfs 3 2BH 2E L 3P 2 MU= = (3.8) To obtain the equation for adhesion energy, the re duced modulus (equation 3.6) is applied to the strain energy (equation 3.8). The st rain energy is then divided by area of the width (B) and length (L) of the sample. The eq uation for the adhesion energy of the interfacial delamination is then () ( ) 3 2 S 2 c 2 2H B 2E L P1 3 C G= (3.9) where cP is the critical load or load at the plateau regio n when delamination occurs, C is a non dimensional parameter for the substrate heigh t and material properties (Zhenghao,
30 2005). Since the top and bottom substrate height a nd materials properties are the same, C=42/48. The final equation for adhesion energy wi th SI units of (J/m2) is (DTS, 2004) ( ) 3 2 S 2 c 2 2H B 16E L P1 21 G= (3.10) Figure 3.3 A schematic of a FPB sample (Zhenyu, 20 05) 3.3 DTS Delaminator test system In this thesis the DTS Delaminator test system at U SFs advance materials lab was used to evaluate the BPSG and TEOS low-k film a dhesion energy. As seen in figure 3.4 the system is comprised of three main component s: the computer system with DTS Delaminator software, the four point delaminator te ster, and data acquisition box.
31 Figure 3.4 DTS Delaminator test system The four point delaminator tester is sustainable f or stability because it is encompassed around a mechanically stiff frame. The system provides ultra-high resolution for the linear actuator with a range of 50 mm with sub-micron resolution (DTS, 2004). The ultra-high resolution allows the actuator to be able to control increment motion as small as 50 nm. The load cell featured in figure 3.5 is built for maximum load of 180 N. The system is also rated fo r a temperature range of -20 85 degrees centigrade (DTS, 2004).
32 Figure 3.5 DTS Delaminator test system frame (DTS, 2004) 3.4 FPB sample preparation FPB test sample preparation can range from 1 day t o 1 week. First two square wafers are scribed into 50 mm X 50 mm pieces. As s een in figure 3.6 one wafer is a blank silicon (Si) wafer and the other wafer contai ns the target film (TEOS or BPSG). Figure 3.6 50 mm X 50 mm diced silicon sample (left ) and low-k sample (right)
33 3.5 FPB wafer bonding For bonding the two squares EPO-Tek 375 epoxy is p repared using the resin and harder in figure 3.7. The epoxy mix is composed of a 10:1 ratio of resin and hardener, respectively. Figure 3.7 EPO-Tek 375 resin (left) and hardener (r ight) After the epoxy is prepared, it is then applied to the surface of wafer not containing the film of interest using a razor tip. However, as seen in figure 3.8 this method of applying epoxy results in a non uniform c oating with a thickness over 1 um. Figure 3.8 EPO-Tek 375 epoxy applied on Si wafer us ing a razor tip
34 A different method of applying the epoxy mix on th e Si wafer is illustrated in figure 3.9. Figure 3.10 shows the uniform layer th at can be put on the silicon wafer by using a disposable pipette nozzle to apply the epox y. Figure 3.9 EPO-Tek 375 epoxy applied on Si wafer us ing a pipette nozzle Figure 3.10 EPO-Tek 375 epoxy on Si wafer
35 The silicon wafer with the target film (BPSG or TE OS) is then sandwiched together with the blank Si wafer coated with the ep oxy. To remove any air between the FPB sample the pressing set up seen in figure 3.11 is used to apply a distributed force on the sample. Figure 3.12 and 3.13 shows how the two paper clamps are used to sandwich the samples to minimize the epoxy thickness and rem ove any trapped air between the FPB samples. Figure 3.11 FPB sample clamping setup Figure 3.12 FPB sample clamping
36 Figure 3.13 Schematic of FPB sample clamping Nevertheless, using paper clamps was found to be i neffective in reducing the epoxy thickness and removing trapped air between th e FPB samples. Figure 3.14 FPB sample hydraulic clamping setup Seen in figure 3.15 is a new pressing method that was implemented. This method involves placing the test sample between two wooden blocks then applying pressure on the blocks with a hydraulic press.
37 Figure 3.15 FPB sample hydraulic clamping with wood en blocks 3.6 FPB wafer epoxy curing To cure the epoxy in the samples, the FPB sample a re placed in a furnace and heated to 100 degrees centigrade for 1 hour. Figur e 3.16 shows the Lindberg/Blue tube furnace used to cure the epoxy in the samples. Figure 3.16 Lindberg/Blue tube furnace
38 The disadvantage with curing FPB samples with the Lindberg/Blue tube furnace is that the cool down time takes 5 hours and only 1 sample could be placed in the furnace at a time when using the Lindberg/Blue furnace. Th e Lindberg/Blue tube furnace was replaced with the Thermolyne 4800 furnace in figure 3.17, which allowed multiple samples to be cured simultaneously. However, the c ool down time when using this furnace was 3 hours. Figure 3.17 Thermolyne 4800 furnace 3.7 FPB sample wafer dicing After the curing process is complete the test samp le is then diced into 50 mm X 7 mm rectangular samples using the MA 1006 Dicing Saw at USFs Nanomaterials & Nanomanufacturing Research Center (NNRC). Each tes t sample prior to dicing is placed on a protective blue tape which holds the sample st eady while dicing is performed.
39 Figure 3.18 MA 1006 Dicing Saw available at the NNR C 3.8 Notching of the FPB sample To assist in inducing an interfacial delamination, a notch is cut at 85% of the thickness of the blank Si wafer (top substrate) usi ng a 100 um diamond resin blade saw. This notch is illustrated in figures 3.19 and 3.20. In this thesis the thickness of the Si wafers used was 0.74 mm. Figure 3.19 Diced and notched FPB sample
40 Figure 3.20 Notch cut (DTS, 2004) 3.9 FPB testing using the DTS Delaminator test syst em Illustrated in figure 3.21 is the orientation of t he FPB test sample before FPB testing begins. As seen in this figure, the two ou ter metal dowel pins are placed at the 35 mm markers facing the notched side of the test samp le. The test sample is then placed on the set screws to reduce any frictional affects tha t could lead to reduced accuracy of the adhesion measurement. Next, the two inner dowel pi ns are placed on the non notched side of the test sample at the 27mm markers. Figure 3.21 FPB sample set up (DTS, 2004)
41 3.10 FPB sample preload and loading test Before the four point bend test begins, a preload of 0.1 N is applied onto the sample by the actuator to ensure that the sample is securely in contact with the load pins. Once the preload force is reached, the actuator the n begins to displace at a specified constant velocity to start the FPB test. The shade d pink region in figure 3.22 shows that the force experienced by the sample increases linea rly as the actuator displacement increases. The figure 3.22 also illustrates that t he notch cut in the FPB sample is unaffected during this point of the delamination te st. Figure 3.22 FPB sample loading
42 3.11 Notch crack propagation As the sample is continually loaded a notch crack begins to emerge from the notch cut and propagates downward towards the inter facial surface where it arrests (Zhenyu, 2005). The small abrupt load drop in the pink shaded region in figure 3.23 marks the strain release in the sample from the not ch crack. Figure 3.23 FPB sample notch crack 3.12 Interfacial delamination Once the notch crack is achieved, strain energy in the sample continues to build until a critical load is reached. As seen in the p ink shaded region in figure 3.24, the abrupt load drop marks where interfacial delaminati on in the FPB sample begins. The interfacial delamination then begins to propagate h orizontally along the interfacial layer from the arrested notch crack location. As the del amination propagates, the required
43 force needed to maintain delamination remains uncha nged. This plateau region of constant load is used to obtain adhesion energy of thin films. Figure 3.24 Interfacial delamination 3.13 Results and discussions of adhesion energy usi ng four point bend tests The parameters for the FPB test were optimized to improve delamination in the FPB samples. Initially notch cuts on the FPB sampl es were cut to 75% 50% of the thickness of the top Si wafer. Figure 3.25 shows l oad vs. actuator displacement profile of FPB samples that had the notch cut less than 85% of the top Si wafer. It was observed that all of the samples that had notches cut less 8 5 % of top Si wafer did not delaminate. It was also observed that the propagation of the no tch crack to the interfacial surface did not occur in any of these samples. Figure 3.25 als o illustrates that these samples fractured without delaminating because the shallow notch cuts allowed too much strain
44 energy build up in the sample. In this thesis all FPB sample notch cuts were cut at 85% depth of the top Si wafer. This notch cut criterio n proved to be a very crucial parameter in achieving delamination in the samples. 0 20 40 60 80 100 020406080100120140160 Displacement (um)Load (N) Figure 3.25 Load vs. displacement curve for notch d epth below 85% Figure 3.26 shows load vs. actuator displacement p rofile of FPB samples that experienced an actuator displacement speed greater than 1.5 um/s. It was observed that the strain energy in the samples built up too quick ly causing the sample to fracture prematurely with no notch crack propagation. In th is thesis the FPB actuator displacement speed press of 0.8 um/sec 1 um/sec w as used successfully achieve delamination in both the TEOS and BPSG samples. The load vs. actuator curve in figure 3.26 also re sembles the load vs. actuator profile of FPB samples when the inner metal dowel p in spacing was less than 27 mm
45 apart. It was observed that a larger bending momen t was applied to the FPB sample during the actuator displacement. This large bendi ng moment rapidly applied strain in the sample causing the sample to fracture premature ly with no notch crack propagation. In this thesis the inner and outer metal dowel pin spacing for all FPB tests were 27 mm and 35 mm, respectively. 0 3 6 9 12 15 0369121518212427303336 Displacement (um)Load (N) Figure 3.26 Load vs. displacement curve (actuator s peed greater than 2 um/sec) Figure 3.26 shows the load vs. actuator curve prof ile for FPB samples when the actuator displacement speed was slowed below 0.7 um /s once a notch crack occurred. However this reduction in actuator pressing caused the sample to fracture near the load cell maximum value of 180 N. This phenomenon is a result of the actuator displacement lagging behind the interfacial delamination which p revented interfacial delamination at a steady load.
46 0 5 10 15 20 25 30 35 40 45 020406080100 Displacement (um)Load (N) Figure 3.27 Load vs. displacement curve (actuator s peed decreased after notch crack) Figure 3.28 shows the load vs. actuator curve prof ile of partially delaminated FPB samples. It was observed that partial delamination like the ones depicted in figures 3.29 and 3.30 resulted from a combination of applying a non uniform thick epoxy layer greater than 1 um and insufficient sample clamping pressure to remove trapped air during the FPB sample preparation.
47 0 5 10 15 20 25 30 020406080100 Displacement (um)Load (N) Figure 3.28 FPB partial delamination load vs. displ acement curve Figure 3.29 BPSG sample partial delamination Figure 3.30 TEOS sample partial delamination
48 In this thesis 67 BPSG and 37 TEOS FPB samples wer e tested after the parameters for the FPB test were optimized to achie ve delamination. Figure 3.31 shows the load vs. actuator curve profile of the delamina ted sample for the BPSG wafer 22 sample test number 4 (BPSG22-4). The curve in figu re 3.31 exhibits an ideal load vs. actuator displacement curve because it has linear l oading, notch crack propagation at 29 N, and finally an abrupt load drop followed by a de lamination plateau load of 61 N. 0 10 20 30 40 50 60 70 020406080100120 Displacement (um)Load (N) BPSG22-4 Figure 3.31 BPSG22-4 delamination curve In figure 3.32 it can be seen that the Si surface is exposed from to the delaminated BPSG film. Figure 3.33 shows a magnified view of t he BPSG22-4 sample surface revealing that the film was delaminated from the Si surface.
49 Figure 3.32 BPSG22-4 delamination Figure 3.33 BPSG22-4 50X view of delamination
50 In this thesis Raman spectroscopy was performed on the all delaminated FPB test samples to verify that the low-k was completely del aminated from the surface exposing the underlying Si wafer surface. Depicted in figur e 3.34 is a scan of standard Si calibration sample, where the peaks of 518 cm-1 5 21 cm-1 correspond to the material characterization of Si. Figure 3.35 depicts a scan of the BPSG22-4 delaminated surface. It can be observed that the peaks for figures 3.34 and 3.35 are identical, thus validating that the low-k film was completely delaminated from the underlying Si substrate. Figure 3.34 Raman spectroscopy calibration Si wafer
51 Figure 3.35 BPSG22-4 Raman spectroscopy of delamina tion In this thesis only 10 of the 67 BPSG FPB samples tested were observed to delaminate. The average adhesion energy with the c orresponding average plateau load of the delaminated BPSG samples is shown in figure 3.3 6. It can be seen in figure 3.36 that BPSG1-4, BPSG21-1, BPSG21-3, BPSG21-6, and BPSG21-7 all exhibited low adhesion energy values. It was observed that these low adhe sion values were a result of partial delamination stemming from weak epoxy adhesion to t he low-k BPSG film. However it can be seen that the BPSG samples that delaminated had consistent adhesion energy values.
52 0 5 10 15 20 25 30 Adhesion energy (J/m^2) BPSG BPSG1-4 BPSG1-7 BPSG21-1 BPSG21-3 BPSG21-6 BPSG21-7 BPSG22-3 BPSG23-1 BPSG24-1 BPSG24-6 Figure 3.36 BPSG adhesion energy The average adhesion energy value with the corresp onding average plateau load of the delaminated BPSG samples is shown in table 3 .1. The uncertainties in table 3.1 were calculated by the DTS Delaminator software.
53 Table 3.1 BPSG delamination Low-k thin film Plateau load (N) Adhesion energy (J/m^2) BPSG1-4 42.5703 1.5831 12.1828 0.3092 BPSG1-7 65.8295 3.9541 29.5390 0.5490 BPSG21-1 25.1499 2.9583 3.7103 0.1388 BPSG21-3 22.6832 1.4198 3.0379 0.8004 BPSG21-6 28.7871 1.1170 5.0750 0.2744 BPSG21-7 25.7207 1.6649 3.9059 0.8076 BPSG22-3 63.6350 4.0507 23.9983 0.5077 BPSG23-1 62.7778 1.9729 23.1405 0.5043 BPSG24-1 61.5126 3.9421 22.3722 0.4710 BPSG24-6 61.4900 4.8933 22.3702 0.4065 Figure 3.36 shows the load vs. actuator curve prof ile of delaminated sample for TEOS wafer 5, sample test number 8 (TEOS5-8). It c an be observed that the delamination plateau load length appears short. Th e reduced plateau load length is due to premature fracture that occurred in the sample. In figure 3.37 it can be seen that the Si surface is exposed from the delaminated TEOS film. Figure 3.38 shows a magnified view of the TEOS5-8 sample surface revealing that t he film was delaminated from the underlying Si substrate.
54 0 10 20 30 40 50 60 70 0102030405060708090100110 Displacement (um)Load (N) TEOS5-8 Figure 3.37 TEOS5-8 delamination curve Figure 3.38 TEOS5-8 delaminated sample
55 Figure 3.39 TEOS5-8 50X view of delamination In this thesis only 3 of the 37 TEOS FPB samples t ested were observed to delaminate. The average adhesion energy with the c orresponding average plateau load of the delaminated TEOS samples is shown in table 3.2. The uncertainties in table 3.2 were calculated by the DTS Delaminator system software.
56 13 14 15 16 17 18 Adhesion energy (J/m^2) TEOS TEOS3-2 TEOS5-5 TEOS5-8 Figure 3.40 TEOS adhesion energy Table 3.2 TEOS delamination Low-k thin film Plateau load (N) Adhesion energy (J/m^2) TEOS3-2 47.3926 6.7239 15.0035 0.4320 TEOS5-5 51.0301 3.8358 17.7830 0.5585 TEOS5-8 50.9668 3.8474 17.4128 0.5672
57 CHAPTER 4: EVALUATION OF ADHESION ENERGY FOR LOW DIELECTRIC CONSTANT THIN FILMS USING NANOSCRATCH TE STING 4.1 Introduction of scratch testing Typically scratch testing involves applying an inc reasingly downward moving load across a materials surface until fracture occ urs. Figure 4.1 illustrates a scratch test for measuring the scratch hardness, where FT, FN, and FL are the measured lateral, tangential, and normal forces, respectively. Scrat ch hardness is defined as the track width of the scratched surface divided by the diameter of the scratch tip (Fischer-Cripps, 2002). Figure 4.1 Configuration of a scratch test (Fischer -Cripps, 2002) Scratch testing for measuring thin film adhesion i s defined as the ability of a thin film to absorb energy until fracturing occurs in th e form of delamination (Fischer-Cripps, 2002). The physical meanings of the results from s cratch testing have long been
58 interpreted differently because different modes of fracture occur for varying indenter shapes and scratch velocities. As scratch testing technologies continue to advanc e, the critical load for measuring of film fracture have begun to be measure d by optical microscopy, acoustic emission (AE), and coefficient of friction (COF) fo rce sensors. It is generally beneficial to use acoustic emissions and analysis of the coeff icient of friction in conjunction to the optical microscopy if a scratch test system has the m available. Figure 4.2 below shows the optical scratch test results of a multilayered Al/TiN/SiO 28 um thick film on a Si substrate. Figure 4.2 Scratch test on a multilayer thin film ( Fischer-Cripps, 2002) The coefficient of friction vs. scratch length gra ph in figure 4.3 corresponds with the scratch test results of the multilayered Al/TiN /SiO thin film in figure 4.2. The encircled area indicates a sudden change in the COF showing when film fracture occurs.
59 Figure 4.3 Coefficient of friction vs. scratch leng th (Fischer-Cripps, 2002) 4.2 Theoretical adhesion energy for nanoscratch tes ting The critical resultant tangential and normal force needed to cause film delamination during a scratch test can be expressed in terms of work of adhesion. This work of adhesion is the work done to overcome the i nterfacial adhesion energy in order for film delamination to occur (Benjamin, 1960) 2 1h 2EW 2 A Pcr = (4.1) where Pcr is the resultant tangential and normal cr itical force. Rearranging equation 4.1, the critical load equation the work or adhesion ene rgy with SI units of (J/m2) is expressed as 2 2A E h Pcr 2 W = (4.2) where h is the depth of the indenter in the thin fi lm, E is the modulus of the thin film form the nanoindentation tests, and A is the projec ted area of the tip in contact with the film. The area A for a Berkovich indenter is (Fisc her-Cripps, 2002) 2h 24.56 A = (4.3)
60 4.3 CETR Universal Tribometer system In this thesis all nanoscratch tests were performe d with the CETR Universal Tribometer at USFs advance materials lab. As seen in figure 4.4 the CETR Universal Tribometer carries acoustic emission (AE), tangenti al (Fz), and normal force (Fx) sensors that can detect the coefficient of friction during scratch tests. The CETR Universal Tribometer is also equipped with a FM-0.5 model sen sor. The FM-0.5 model sensor is capable of dictating loads from 0.05 mN (5 g) 5 N (500 g). The acoustic emission sensor provides an in-situ measurement of the inden ter to indicate specific events in which the indenter head experiences abrupt changes during the load application. Figure 4.4 CETR Universal Tribometer
61 Figure 4.5 provides a clear view of the Berkovich tip and AE sensor attached to the nanoscratch tip housing. It should be noted th e CETR Universal Tribometer software denotes the tangential (Fz) as negative, while this thesis denotes down forces as positive. Figure 4.5 Scratch tip and AE sensor head Due to the high cost of Berkovich indenter tips, t he edge forward orientation was used for all scratch tests in this thesis. The edg e forward tip orients the vertices of the tip parallel to the direction of the scratch path. Fig ure 4.6 is an illustration of the face forward orientation, which orients the tip face par allel to the direction of the scratch path. Studies have shown that scratch tests performed wit h a face forward orientation significantly decreased the life of the indenter an d increase the risk damaging to the tip geometry (McAdams, 2006).
62 Figure 4.6 Face forward nanoscratch tip orientation 4.4 Nanoscratch sample preparation and test paramet ers Sample preparation for nanoscratch testing is as s imple as sample preparation for nanoindentation. First the nanoscratch test sample is prepared by scribing the low-k wafer into 30 mm X 42 mm rectangles. The sample is then individually adhered in place on the CETR Universal Tribometer steel stage and th en tested as seen in figure 4.7. Figure 4.7 Nanoscratch sample setup
63 All nanoscratch tests performed in this thesis sta rted with a 5 g (0.05 N) tip normal load and ended with a 105 g (1.05 N) tip nor mal load. Each scratch test length was kept constant at 37 mm. The nanoscratch test p arameters in this thesis were governed by scratch length, initial tip normal load (Fzi), final tip normal load (Fzf), and tip load rate. For example as seen in table 4.1, w ith a the tip load rate of 0.01 N/s, nanoscratch test parameter 1 (NSCT1) needs a tip ve locity of 0.352 mm/s to perform a 37 mm long scratch test which lasts 105 seconds; NSCT 2, 3, 4 and were all determined this way. The table 4.1 below shows the variation in ti p load rate, scratch tip velocity, and scratch test duration that was tested on each low-k film. Table 4.1 Nanoscratch test (NSCT) parameters Scratch test Scratch length (mm) Fzi (N) Fzf (N) Tip load rate (N/s) Tip velocity (mm/s) Scratch duration (s) NSCT1 37 0.05 1.05 0.01 0.352 105 NSCT2 37 0.05 1.05 0.02 0.705 52.5 NSCT3 37 0.05 1.05 0.03 1.057 35 NSCT4 37 0.05 1.05 0.0555 2 18 Figure 4.8 below shows the Fx and Fz in-situ recor ding of a scratch test for NSCT1. The figure illustrates the 5 g Fz load (blu e curve) and 0 g Fx load that is applied to the film for 5 seconds before the scratch test b egins. This is done to ensure that the tip load is steady before scratching commences. Once t he scratch test begins it can be seen
64 that the Fz increases to 105 g as the tip moves acr oss the film surface. As a result of the Fz, the Fx experiences a frictional force which inc reases throughout the scratch test. Figure 4.8 In-situ nanoscratch recording 4.5 Results and discussions of low-k thin film nano scratch test results Figure 4.9 shows the in-situ COF (red curve), AE ( brown curve), Fx (blue curve), and Fz (blue curve) measurements for the BPSG low-k sample using nanoscratch test parameter 2 (NSCT2). The change in the AE signal c urve in the shaded green region in figure 4.9 marks the instant that the surface of th e BPSG film begins to be chipped off by the indenter at 12 14 seconds during the nanoscra tch test. Figure 4.10 shows the SEM
65 (scanning electron microscope) of BPSG1 low-k film surface chipping which correspond with the shaded green region in figure 4.9. The next AE signal change in the shaded red region in figure 4.9 marks the instant that delamination occurs in BPSG1 low-k film by the indenter at 20 22 seconds during the nanoscratch test. Figure 4.11 shows the SEM of the BPSG1 low-k film delamination which correspond with the shaded red region in figu re 4.9. Further along the nanoscratch test as the load app roaches the maximum Fz value of 105 g, the shaded blue region in figure 4.9 mark s the instant that the BPSG1 low-k film experiences complete delamination by the inden ter at 25 49 seconds during the nanoscratch test. Figure 4.12 shows the SEM of exp osed Si surface as a result of the BPSG1 low-k film experiencing complete delamination corresponding to the shaded blue region in figure 4.9. Figure 4.9 In-situ of the BPSG1 low-k film using NS CT2
66 Figure 4.10 SEM of BPSG1 low-k film surface chippin g Figure 4.11 SEM of initial delamination of BPSG1 lo w-k film
67 Figure 4.12 SEM of complete delamination of BPSG1 l ow-k film Figure 4.13 depicts the in-situ COF (red curve), A E (brown curve), Fx (blue curve), and Fz (blue curve) measurements of the BPS G1 low-k sample using nanoscratch test parameter 4 (NSCT4). It can be seen that the AE signal was undisturbed during the nanoscratch test. Figure 4.13 also shows no clear COF, Fx, or Fz signal changes that mark the instances that the low-k film experiences surface chipping, delamination or complete delamination. In this thesis it was observed that the NSCT2 was the only nanoscratch test parameter that consistently showed a clear COF, AE, Fx, and Fz signal change identifying instances when the BPSG and TEOS low-k thin films experienced surface chipping, delamination and complete delamination fr om the Si substrate. For this reason all adhesion energy measurements for nanoscratch te sting where calculated from the Fx and Fz critical resultant loads obtained using NSCT 2.
68 Figure 4.13 In-situ of the BPSG1 low-k film using N SCT4 Figures 4.14 and 4.15 show the nanoscratch test cr itical load and adhesion energy obtained using NSCT2 for the BPSG and TEOS low-k th in films. Figure 4.14 illustrates the consistent critical measurements obtained from the scratch test for the BPSG and TEOS. It can be observed that the adhesion energy of both the BPSG and TEOS did not change much. The consistency observed of the criti cal and adhesion energy for both the BPSG and TEOS is a result of the uniform material p roperties of the films and clarity of signal changes with using NSCT2 parameter for scrat ch tests.
69 0.00 0.20 0.40 0.60 0.80 Critical load (N) NSCT-2 BPSG1 BPSG21 BPSG22 BPSG23 BPSG24 BPSG25 TEOS3 TEOS5 TEOS7 Figure 4.14 Nanoscratch test critical load for BPSG and TEOS low-k thin film 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 Adhesion energy (J/m^2) NSCT-2 BPSG1 BPSG21 BPSG22 BPSG23 BPSG24 BPSG25 TEOS3 TEOS5 TEOS7 Figure 4.15 Nanoscratch test adhesion energy for BP SG and TEOS low-k thin film
70 The uncertainty values in table 4.2 were not provi ded by the CETR Universal Tribometer system, these values were calculated usi ng the error propagation calculations discussed in section 4.6. Table 4.2 Nanoscratch test critical load and adhesi on energy for BPSG and TEOS low-k thin film Low-k thin film Pcr (N) W (J/m^2) BPSG1 NSCT2 0.4258 0.0003 0.0028 0.0006 BPSG21 NSCT2 0.4383 0.0003 0.0024 0.0005 BPSG22 NSCT2 0.4479 0.0003 0.0021 0.0004 BPSG23 NSCT2 0.4659 0.0003 0.0021 0.0004 BPSG24 NSCT2 0.4889 0.0003 0.0019 0.0001 BPSG25 NSCT2 0.4658 0.0003 0.0016 0.0003 TEOS3 NSCT2 0.7262 0.0004 0.0012 0.0001 TEOS5 NSCT2 0.6427 0.0004 0.0013 0.0002 TEOS7 NSCT2 0.6804 0.0004 0.0012 0.0001 4.6 Nanoscratch test error propagation Error propagation for nanoscratch test results was performed to determine the resultant critical load and work of adhesion error. Using the error propagation equation (Dally, 1993) + + + =n n 2 2 2 2 1 1dx x y dx x y dx x y dy (4.4)
71 ()() 2 2Fz Fx Pcr + = (4.5) 2 2dFz Fz Fr dFx Fx Fr dFr + = (4.6) () ()() () ()() 2 2 1 2 2 2 2 1 2 2Fz Fz 2 Fz Fx 2 1Fx Fx 2 Fz Fx 2 1 dFr + + + =(4.7) where Fx and Fz equal 0.00001 N. The work of adhesion error propagation is 2 2 crA E h P 2 W = (4.8) 2 2 2dh h W dE E W dPcr Pcr W dW + + = (4.9) 2 1 4 2 2 cr 2 3 2 2 2 cr 2 3 2 cr h h E (24.56) P 6 E h E (24.56) P 2 Pcr h E (24.56) P 4 dW n n + + = (4.10) where N 0.000355Pcr = ,Pa 10 0.1 E9 =
72 CHAPTER 5: THESIS CONCLUSION 5.1 Thesis summary In this thesis the methodology behind indentation and nanoindentation for small scaled material was explained. Nanoindentation was used to evaluate the material properties of boro-phosphate-silicate glass (BPSG) and tetraethylorthosilicate (TEOS) low-k dielectric thins films deposited on Si substr ates by chemical vapor deposition (CVD). The low-k material hardness and elastic mod ulus results obtained from the MTS Nano Indenter XP showed that the films mechinacal properties were uniform throughout each dielectric wafer. The material pro perties obtained from nanoindentation tests were later used in determine the adhesion ene rgy for nanoscratch testing performed on the low-k films. Using the DTS Delaminator test system, four point bend (FPB) tests were performed to evaluate the adhesion energy for both BPSG and TEOS low-k films. The sample preparation procedures were optimized to pro mote interfacial delamination in FPB samples. New methods for epoxy application, FP B sample bonding, epoxy curing, and sample testing were observed reduce sample frac ture and improve interfacial film delamination for the evaluation of low-k adhesion e nergy. A notch cut depth of 85 % of the top Si substrate also proved to be a very cruci al parameter in achieving delamination in the samples. The adhesion results for both BPSG and TEOS were found to be
73 consistent for FPB samples that completely delamina ted. However some samples experienced partial delamination caused by difficul ties in applying a uniform thin layer of epoxy during in sample preparation. The CETR Universal Tribometer was used for scratch testing because it carries acoustic emission (AE), tangential (Fz), and normal force (Fx) sensors that can detect the coefficient of friction during scratch tests. The edge forward tip orientation was selected to prevent tip damage during scratch testing. In a ddition, the nanoscratch testing parameter 2 (NSCT2) was observed to provide the bes t AE signal changes that corresponded with film delamination. The nanoscrat ch test results showed consistent adhesion energy measurements for the BPSG and TEOS films. The adhesion energy for BPSG and TEOS low-k thin f ilms using FPB testing ranged from 29.5390 J/m2 3.0379 J/m2. However adhesion energy for BPSG and TEOS low-k thin films using nanoscratch testing ranged f rom 0.0012 J/m2 0.0028 J/m2. This large disparity between FPB and nanoscratch test ad hesion energy is due to the different failure modes by which delamination occurs in each test. As previously stated in section 1.7 in chapter 1 the interfacial fracture toughness (adhesion energy) between two materials is the work required to separate the mate rials from each other. During four point bending, the film to absorbed large bending f orces which ultimately led to interfacial delamination. While in nanoscratch tes ting, the film only absorbed small a downward and shearing force causing chipping and bu ckling of the film which ultimately led to delamination.
74 5.2 Future work In this thesis many FPB testing parameters and samp le preparation procedures were optimized in order that achieve interfacial de lamination. However even with these optimizations many samples experienced partial dela mination and premature sample facture which made evaluating adhesion energy diffi cult. Improving the method of applying a uniformly thin epoxy layer may reduce th e number partial delamination occurring in FPB samples. Along with improving epo xy application techniques, revising the clamping method for bonding the FPB sample shou ld to be looked further. A rolling force applied to the sample may help reduce the amo unt of trapped air in the samples. One proposed method would be to put FPB sample into a vacuum after applying the epoxy. This would form very thin epoxy layer while completely removing any trapped air in the FPB sample. Investigating the effects of notch cut depths of 9 0% to 95% were not looked at for fear that the dicing blade would cut into the inter facial layer. However if notch cut depths of 90% to 95% can be achieved in the FPB sam ples, it may greatly reduce the number of fractured samples by minimizing the abrup t strain release which occurs just before interfacial delamination. Lastly, the effec ts of micro cracks in regards to premature FPB sample fracture should be considered to reduce early sample fracturing.
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