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Copper doped window layer for CdSe solar cells


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Copper doped window layer for CdSe solar cells
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Chanda, Sheetal Kumar
University of South Florida
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Tampa, Fla
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Subjects / Keywords:
Cadmium selenide
Zinc teluride
Copper doping
Tech glass
Tunneling contact
Dissertations, Academic -- Electrical Engineering -- Masters -- USF   ( lcsh )
non-fiction   ( marcgt )


ABSTRACT: CdSe solar cells with ZnTe as the window layer deposited by CSS process have shown Vsubscriptoc's around 630mV. However the currents were very low and also the voltages were not meeting the desired objectives. To improve the performance the contact energy at the ZnTe/Cu interface should be minimized by doping the window layer. Thermal evaporation was used to deposit ZnTe to have more control over the composition of the film. Initial experiments were done by depositing Cu doped ZnTe films on plain glass by co-evaporating both ZnTe and Cu. The conductivity was in the order of 10e3 which shows copper present in the film in the order of 1e22 S/cm³. This accomplishes a tunneling contact with the top electrode. Using the ZnTe:Cu contacts in complete devices resulted in disappointing voltages and currents. Efforts were made to deal with the poor performance of the cells. Devices were made on different types of TCO coated glass substrates but, were resulting in the same numbers which shows the type of TCO has an insignificant effect on the performance. The Cu doping has been helping in raising the Vsubscriptocs but at the same time marred the currents whose effect has been unexplainable. Further experiments have been made changing the ZnTe thickness and concentration of Cu doping. Experiments were done increasing the substrate temperature as high as 500C during ZnTe deposition and a Se flux has been introduced so as to compensate the loss of Se from CdSe at such high substrate temperature. But these experiments resulted in dismal performance indicating the domination of defects in the undoped ZnTe layer.
Thesis (M.S.E.E.)--University of South Florida, 2008.
Includes bibliographical references.
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by Sheetal Kumar Chanda.
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Copper Doped Window Layer for CdSe Solar Cells by Sheetal Kumar Chanda A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Electrical Engineering Department of Electrical Engineering College of Engineering University of South Florida Major Professor: Don Morel, Ph.D. Christos Ferekides, Ph.D. Sanjuktha Bhanja, Ph.D. Date of Approval: November 3, 2008 Keywords: cadmium selenide, zinc teluride, copper d oping, tech glass, tunneling contact Copyright 2008 Sheetal Kumar Chanda


DEDICATION To everyone who helped me in my endeavor


ACKNOWLEDGEMENTS I am deeply indebted to Dr. Don Morel, my Major Pro fessor. He guided me and motivated me throughout this project, but his teach ings went much beyond that. He was instrumental in turning my dream into reality. I wo uld also like to thank Dr. Chris Ferekides and Dr. Bhanja for accepting my invitatio n to be in my committee. Special thanks to Stephen Bates and Hehong Zhao for helping me every step of the way. I am also thankful to Mike Konrad from Ele ctrical Engineering department for his timely help in fixing all equipment. I am very thankful for the encouragement given by Ranjit, Vijay, Vamsi, Pawan, Ramkey and other fr iends. I am grateful to my colleagues Deidra, Farah, Vassilis, Ryan and others who were always there to help me and made working in the lab a wonderful experience. I would also like to thank my friends at USF who were always there to support me and made my life at USF a memorable one. I am what I am, because of my parents, my brother, my fianc and because of my friends throughout the years. Sincere thanks to eac h and every one of them who I have come across in my life till now as they have direct ly or indirectly helped me in reaching my goal.


i TABLE OF CONTENTS LIST OF TABLES iii LIST OF FIGURES iv ABSTRACT vi CHAPTER I INTRODUCTION 1 1.1 Need for Solar Energy 1 1.2 History of Solar Cells 2 1.3 Economics of Photovoltaics 5 1.4 Benefits of Solar Energy 8 1.5 Thin Film Photovoltaics 9 CHAPTER II PHOTOVOLTAIC DEVICE PHYSICS 1 2 2.1 Introduction 12 2.2 Photovoltaic Effect 16 2.3 P-N Junction 16 2.4 PN Heterojunction 21 2.5 Solar Cell Parameters 24 2.6 Tandem Solar Cells 30 2.6.1 CdSe-CIGS Tandem Cells 32 2.6.2 CIGS Solar Cell 32 2.6.3 CdSe/ZnSe Solar Cell 33 2.6.4 CdSe/ZnTe Solar Cell 36 CHAPTER III DEVICE FABRICATION AND MEASUREMENTS 37 3.1 Introduction 37 3.2 Processing of CdSe Solar Cells 37 3.2.1 Substrate 37 3.2.2 Cleaning Procedure 37 3.2.3 Back Contact 38 Fluorine Doped Tin Oxide 39 Tech Glass 40 3.2.4 Absorber Layer 42 Preparation of CdSe Source 42 Deposition Procedure for CdSe 42


ii 3.2.5 Window Layer 44 Deposition Procedure for ZnSe 44 Deposition Procedure for ZnTe 44 Deposition Procedure for Cu Doped Window Layer 45 3.2.6 Front Contact 45 3.3 Device Characterization 46 CHAPTER IV RESULTS AND DISCUSSIONS 49 4.1 Results 49 4.1.1 Optimization of CdSe as Absorber Layer 49 4.1.2 CdSe/ZnSe Solar Cells 5 1 4.1.3 CdSe/ZnTe Solar Cells 5 2 4.1.4 Effect of TCO on Device Performance 53 4.1.5 Copper Doping of ZnTe 54 4.1.6 CdSe/ZnTexSe1-x Solar Cells 59 CHAPTER V CONCLUSIONS 60 REFERENCES 62


iii LIST OF TABLES Table 4.1 Voltages for CdSe/ZnTe Solar Cells at Di fferent Substrate 53 Temperatures.


iv LIST OF FIGURES Figure 1.1 Economy of Scale 6 Figure 1.2 PV Roadmap Developed by the Industry 6 Figure 1.3 World PV Module Production 7 Figure 2.1 Energy Band Diagram for Electrons in a Semiconductor 14 Figure 2.2 Cross Section of a P-N Junction 17 Figure 2.3 Energy Band Diagram of P-N Junction Bef ore and After Merging the N-Type and P-Type Regions 18 Figure 2.4 Energy Band Diagram of P-N Junction in Thermal Equilibrium 20 Figure 2.5 Energy Band Diagram of P-N Junction und er Reverse and Forward Bias 21 Figure 2.6 Flatband Energy Diagram of P-N Heteroju nction 22 Figure 2.7 I-V Curve of a Solar Cell and its Elect rical Circuit Diagram 24 Figure 2.8 Illuminated I-V Sweep Curve 25 Figure 2.9 Maximum Power for an I-V Sweep 26 Figure 2.10 Fill Factor from the I-V Sweep 26 Figure 2.11 Simplified Equivalent Circuit Model fo r a Photovoltaic Cell 28 Figure 2.12 Effect of Series and Shunt Resistances 28 Figure 2.13 Shunt and Series Resistances from the I-V Curve 29 Figure 2.14 I-V Curve of Solar Cell without Light Excitation 30 Figure 2.15 Schematic of Tandem Solar Cell 31


v Figure 2.16 Structure of CdSe-CIGS Tandem Solar Cel l 32 Figure 2.17 Structure of CIGS Solar Cell 33 Figure 2.18 Structure of CdSe/ZnSe Solar Cell 34 Figure 2.19 Band Alignments of CdSe and Transparent Contacts 35 Figure 3.1 Schematic of MOCVD Reactor 40 Figure 3.2 Structural Model for Tech 20 Glass 41 Figure 3.3 Schematic of CSS Chamber 4 3 Figure 3.4 Schematic of ZnSe Evaporation Chamber 47 Figure 3.5 Schematic of Cu Evaporation Chamber 48 Figure 4.1 Dark and Light IV Curves with CdSe Glass Source 50 Figure 4.2 Spectral Response of CdSe/ZnSe Solar Ce ll 51 Figure 4.3 Dark and Light Curves for CdSe/ZnSe Sola r Cell 52 Figure 4.4 Plot of Dot to Dot Resistance Measuremen ts 55 Figure 4.5 (a) Dark IV Curves for Cu Doped CdSe/Zn Te Solar Cell 55 Figure 4.5 (b) Light IV Curves for Cu Doped CdSe/Zn Te Solar Cell 56 Figure 4.6 Dark IV Curves for 100nm Undoped and Cu Doped CdSe/ZnTe Solar Cell 57 Figure 4.7 QE Response for 100nm Cu Doped CdSe/ZnT e Solar Cell 57 Figure 4.8 QE Response of Undopedx2 Thickness/Dope d CdSe/ZnTe Solar Cell 58


vi Copper Doped Window Layer for CdSe Solar Cells Sheetal Kumar Chanda ABSTRACT CdSe solar cells with ZnTe as the window layer depo sited by CSS process have shown Voc’s around 630mV. However the currents were very low and also the voltages were not meeting the desired objectives. To improve the performance the contact energy at the ZnTe/Cu interface should be minimized by dop ing the window layer. Thermal evaporation was used to deposit ZnTe to hav e more control over the composition of the film. Initial experiments were d one by depositing Cu doped ZnTe films on plain glass by co-evaporating both ZnTe an d Cu. The conductivity was in the order of 10e3 which shows copper present in the fil m in the order of 1e22 S/cm3. This accomplishes a tunneling contact with the top elect rode. Using the ZnTe:Cu contacts in complete devices resulted in disappointing voltages and currents. Efforts were made to deal with the poor performanc e of the cells. Devices were made on different types of TCO coated glass substra tes but, were resulting in the same numbers which shows the type of TCO has an insignif icant effect on the performance. The Cu doping has been helping in raising the Vocs but at the same time marred the currents whose effect has been unexplainable. Furth er experiments have been made changing the ZnTe thickness and concentration of Cu doping.


vii Experiments were done increasing the substrate temp erature as high as 5000C during ZnTe deposition and a Se flux has been intro duced so as to compensate the loss of Se from CdSe at such high substrate temperature. Bu t these experiments resulted in dismal performance indicating the domination of def ects in the undoped ZnTe layer.


1 CHAPTER I INTRODUCTION 1.1 Need for Solar Energy Solar energy from the sun is free and inexhaustible This enormous, reliable and clean energy resource represents a viable alternati ve to the fossil fuels that are currently polluting our air and water, threatening public hea lth, and contributing to global warming. The amount of energy that falls on the Ear th’s surface from the sun is so enormous that all the energy stored in Earth's rese rves of oil, coal, and natural gas is matched from just 20 days of sunshine. The sun's en ergy contains about 1,300 watts per square meter outside the Earth’s atmosphere. About one-third of this light is reflected back into space, and some is absorbed by the atmosp here itself [1]. Over the next 50 years mankind has to face two big challenges of meeting the global energy demand and limiting the effects of gl obal warming. The demand for energy is growing as the economies around the world are de veloping rapidly with constantly growing population. With supplies of fossil fuels d iminishing daily, solar energy can be one solution to this problem. It is estimated that by 2100, solar energy will account for 80% of the total energy produced around the world [ 1]. Global warming is a danger unlike anything we have faced ever before. Turning to alternative energy sources, like solar, is one way to help.


2 1.2 History of Solar Cells The photovoltaic effect was first reported by Edmun d Bequerel in 1839. His observations of producing an electric current by th e action of light on a silver coated platinum electrode immersed in electrolyte have giv en way to this discovery. In 1876 William Adams and Richard Day discovered that photo current could be produced in a sample of selenium when contacted by two heated pla tinum contacts [2]. The photovoltaic action of the selenium was found to be different from its photoconductive action in which current was produced spontaneously by the action of light. No external power supply was needed and a rectifying junction h ad been formed between the semiconductor and the metal contact. In 1894, Charl es Fritts prepared what was probably the first large area solar cell by placing a layer of selenium between gold and another metal. Photovoltaic effects were observed in copper -copper oxide thin film structures, in lead sulphide and thallium sulphide in the followin g years. These early cells were thin film Schottky barrier devices, as a semitransparent layer of metal deposited on top of the semiconductor provided both the asymmetric electron ic junction, which is necessary for photovoltaic action and access to the junction for the incident light. The photovoltaic effect of these related to the existence of a barri er to current flow at one of the semiconductor-metal interface (i.e., rectifying act ion) by Goldman and Brodsky in 1914. Later, during the 1930s, Walter Schottky, Neville M ott and others developed the theory of metal-semiconductor barrier layers.


3 However, researchers were not excited by the photov oltaic properties of materials like selenium, but the photoconductivity. The obser vations that the current produced from the materials was proportional to the intensity of the light and their relation to the wavelength meant that photoconductive materials wer e ideal for photographic light meters. The photovoltaic effect in barrier structur es was an additional benefit because the light meter could operate without a power supply. D uring 1950s, the development of good quality silicon wafers for applications in the new solid state electronics produced potentially useful quantities of power by photovolt aic devices in crystalline silicon. This followed the discovery of a way to manufacture p-n junctions in silicon. Better rectifying action and better photovoltaic ef fect was produced when developing ptype skin by exposing naturally n-type silicon wafe rs to the gas boron trichloride and later etching away part of the skin to give access to the n type layer beneath. Chapin, Fuller and Pearson in 1954 reported the first silicon sola r cell with a conversion efficiency of 6%, six times higher than the best pervious attempt An estimated production cost of some $200 per Watt hindered the consideration of th ese cells for power generation for several decades. However, these solar cells introdu ced the possibility of power generation in remote locations where fuel could not be easily delivered. Silicon solar cells were then widely developed for space applications when requir ement of reliability and light weight made the cost of the cells unimportant. In 1954, an efficiency of 6% was produced with cadm ium sulphide p-n junction and in the following years higher efficiencies were indicated by simulation studies of p-n


4 junction photovoltaic characteristics in gallium ar senide, indium phosphide and cadmium telluride [2]. Silicon still remained and remains t he foremost photovoltaic material because of its benefiting advances for the microele ctronic industry. The crisis in energy supply experienced by the oildependent western world in the 1970s led to an abrupt growth of interest in altern ative sources of energy, and funding for research and development in those areas have also g rown. Photovoltaics was of high interest during this period, and many strategies fo r producing photovoltaic devices and materials more cheaply and with more efficiency wer e explored. Means to lower cost included photoelectrochemical junctions and materia ls such as polycrystalline silicon, amorphous silicon, other ‘thin film’ materials and organic conductors whereas strategies for higher efficiency included tandem and other mul tiple band gap designs. But none of these efforts helped to achieve widespread commerci al development Again during the 1990s, interest in photovoltaics e xpanded with growing awareness of the need to secure sources of electric ity alternative to fossil fuels. During this period, the economics of photovoltaics improve d primarily through economies of sale. In the late 1990s there was an expansion in t he photovoltaic production at a rate of 15-25% per annum, driving a reduction in cost.


5 1.3 Economics of Photovoltaics Predicting economic futures is challenging. One thi ng we can guarantee is that as we produce more solar cells, the price will go down as shown in the figure 1.1. With PV module price in $/Wp on the left hand side shipment s in MWp/year on the right hand side we can see that just like the computer industry whe n you produce more (red line), the price will drop substantially (blue line). It shoul d be open to the US market for PV to directly compete with fossil fuel electricity if we break the $2/Wp mark. This was supposed to happen in 2006, but unfortunately, the price hasn’t dropped as much. The reason being that majority of solar cells are made from silicon. Silicon that is not pure enough or defect-free enough for the semiconductor industry is good for making solar cells. Most solar cells are made from the cast of s ilicon from the semiconductor industry. This supply is now completely used up which created a shortage of silicon to make solar. Once this is corrected, the prices of solar cells w ill likely drop back down to the curve on the graph. The entire production of solar cells is just a GW, just like one power plant. The prices are around $3.56/Wp as they climbed from $3. 12/Wp. However, as the PV production is increasing rapidly and prices will drop. In order to know their course in the U.S., the Industry deve loped a Roadmap. This graph is an industry prediction in gigaWatts per Year. By 2020 the U.S. is expected to produce over 30GW and the world is up over 80GW.


6 Figure 1.1 Economy of Scale. [3] Figure 1.2 PV Roadmap Developed by the Industry. [4 ]


7 The world PV production is outpacing predictions. T he world PV installations in 2004 rose to 0.93 GigaWatts (GW = 109W), representi ng growth of 62% over 2003 installations and the consolidated world production of PV increased to 1.15 GW. This growth rate, while impressive, must be kept in cont ext of the global energy market. In 2000 the peak electrical generation capacity in the U.S. was 825 GW while the cumulative total global installed solar PV was less than a single GW [5]. Figure 1.3 World PV Module Production. [6] The global solar power market, as measured by annua l solar power system installed capacity, grew at a CAGR of 47.4% from 59 8 MW in 2003 to 2,826 MW in 2007 [1]. According to a Solarbuzz forecast named Green World," in one of several possible scenarios, annual solar power system insta lled capacity may increase to 9,917 MW in 2012, and solar power industry revenue may in crease from $17.2 billion in 2007 to $39.5 billion in 2012, which we believe will be driven largely by surging market


8 demand, rising grid prices and government initiativ es. The scope of the government incentives for solar power depends, to a large exte nt, on political and policy developments relating to environmental concerns in a given country, which could lead to a significant reduction in or a discontinuation of the support for renewable energies in such country. Federal, state and local governmental bodies in many of our key markets, most notably Germany, Italy, Spain, the United Stat es, France and South Korea have provided subsidies and economic incentives in the f orm of rebates, tax credits and other incentives to end users, distributors, system integ rators and manufacturers of solar power products to promote the use of solar energy in on-g rid applications and to reduce dependency on other forms of energy. These governme nt economic incentives could be reduced or eliminated altogether. In particular, po litical changes in a particular country could result in significant reductions or eliminati ons of subsidies or economic incentives. Electric utility companies that have significant po litical lobbying powers may also seek changes in the relevant legislation in their market s that may adversely affect the development and commercial acceptance of solar ener gy. While the challenges are enormous, so are the opportunities. 1.4 Benefits of Solar Energy Solar power has several advantages over both forms of energy, conventional and renewable energy. The energy coming from the sun is practically free and after the initial investment has been recovered solar energy reduces the depende nce on conventional source of


9 energy. Solar energy supports local jobs and create s wealth, which elevates local economies. Solar energy is clean, quiet as it has no moving pa rts, renewable and sustainable unlike other conventional energy sources such as ga s, oil, and coal. It does not contribute to global warming, acid rain, or smog, on the contr ary, it helps in lowering harmful green house gas emissions. Solar energy reduces our dependence on foreign or c entralized sources of energy. It can reduce electric bills and can also supply ho mes with electricity when there is a power outage. The solar energy systems can installe d in a remote location as they can be operated entirely independent from a power or gas g rid Solar energy systems are virtually maintenance free and will last at least 25 years [1]. System sizes can be increased in the future as your electricity needs grow. 1.5 Thin Film Photovoltaics Majority of commercial solar cells in use today are made of silicon, the same semiconductor material that is used in the microele ctronics industry. Typical commercial solar cells have an efficiency ranging between 6% a nd 18%, meaning that for every 1,000 watts of sunlight striking a solar module, 60 to 18 0 watts of electricity will be produced [7]. Although silicon is abundant in the earth's su rface, processing it to pure crystalline form is expensive, resulting in recent supply short ages and high costs. Uncertain raw


10 material costs for photovoltaic grade silicon conti nue to show a demand that far out paces the supply in near future. Solar cells and modules made from certain thin film semiconductors have been shown to be much less expensive to produce in a lar ger volume and requiring much less raw material to produce when compared to silicon ba sed PV cells. Recent advances in thin-film PV are beginning to gain interest in comm ercial and residential building markets, as well as interest in space and near-spac e applications. Extensive research and development on thin film cells has been conducted f or more than 30 years, and recent advances in manufacturing and product commercializa tion have increased worldwide share of thin film photovoltaics to over 10% in 200 7 [7]. The three most common thin-film technologies are am orphous silicon (a-Si), cadmium telluride (CdTe) and copper-indium-galliumdiselenide (CIGS). Of these three, CIGS currently has demonstrated the highest laborat ory efficiency at 19.5% (NREL, measured in earth conditions) with CdTe close behin d it [8]. CIGS thin-film technologies can be placed on a wide variety of substrate materi als making it possible to manufacture very lightweight, flexible solar cells on metals an d also plastics. To make it more understandable, the thickness of a flexible CIGS de vice is approximately the same as the thickness of a human hair, making it very flexible and lightweight.


11 Thin film solar cells and modules require a structu ral "substrate" to support them, such as glass which is low in cost and enables cont inuous and scaleable manufacturing. The expenditure required to establish large-volume thin film PV product manufacturing plants enables rapid capacity expansion and lowers the cost per watt of products as much of the equipment to process these substrates is use d in other industries. The substrate and raw materials used in thin film P V products are less expensive than the cost of most semiconductor materials. Prod uct cost can be reduced with increasing thin film manufacturing capacity and pro cess yield improvements. Thin film photovoltaic technologies also exhibit pe rformance advantages in generating energy in low light level and increased temperature environments and as a result position them particularly well for applicat ions in regions with less direct sunlight, such as in Northern Europe.


12 CHAPTER II PHOTOVOLTAIC DEVICE PHYSICS 2.1 Introduction As the name itself suggests the word ‘Photovoltaics ’ has two parts. Photo is derived from the Greek word for light and volt rela ting to electricity pioneer Alessandro Volta. So, Photovoltaic’s could literally be transl ated as Light-electricity, which means they convert light energy into electrical energy (P hotoelectric Effect) as discovered by a French physicist Edmond Becquerel in 1839. This dev ice is commonly called as Solar cell, which can be defined as a simple p-n junction diode that generates the charge carriers up on light incidence. Before Getting into details of the behavior of the solar cells, it is very essential to understand the funda mentals of the materials, which the solar cell consists of. All the elements can be categorized into three typ es, a conductor, an insulator, and a semiconductor and the key property that determine s whether a material is an insulator, a conductor, or a semiconductor is the location of th e Fermi energy relative to the valence and conduction bands, and the size of the energy ga p between these two bands. In the case of insulators there is a large energy gap betw een the valence and conduction bands and the Fermi energy lies between the two bands. Th is means that the valence band is completely full and the conduction band is complete ly empty. If we apply a modest


13 voltage across the solid, electrons will try to res pond to it by picking up energy from the electric eld and moving along the eld lines towar ds the positive end. It requires a lot of energy, 5-8 eV, to excite the electrons enough to g et to the conduction band. So, it requires much energy to traverse the band gap, sinc e the width of the band gap is very large. A metal is an excellent conductor because, a t room temperature, it has electrons in its conduction band constantly, with little or no e nergy being applied to it. This may be because of its narrow or nonexistent band gap and t he conduction band may be overlapping the valence band so they share the elec trons. The band diagram would be drawn with Ec and Ev very close together, if not overlapping. Now, the semiconductors are generally certain eleme nts that allow, but still resist the flow of electricity. These semiconductors lie s omewhere between good conductors and poor conductors. Semiconductors are very import ant because, semiconductors have a unique atomic structure that allows their conductiv ity to be controlled by stimulation with electric currents, electromagnetic fields, or even light. The band gap is wide enough to where current is not going through it at all times, but narrow enough to where it does not take a lot of energy to have electrons in the condu ction band creating a current. They have fully occupied valence band, at T=0, but the f orbidden energy gap is not very large, due to this they do not conduct in normal condition s but these electrons are loosely bound and so any excitation causes them to break the bond resulting in conduction. This makes it possible to construct devices from semiconductor s that can amplify, switch, convert sunlight to electricity or produce light from elect ricity.


14 Figure 2.1 Energy Band Diagram for Electrons in a S emiconductor. Semiconductors can be classified as intrinsic and e xtrinsic semiconductors. An intrinsic semiconductor is one, which is pure enoug h that impurities do not affect its electrical behavior. Here, all carriers are created due to thermally or optically excited electrons from the full valence band into the empty conduction band. Electrons and holes flow in opposite direction in an electric field, th ough they contribute to the same direction since they are oppositely charged. An extrinsic sem iconductor is the one that has been doped with impurities to modify the number and type of free charge carriers. When a semiconductor is doped with a donor impurity it has an extra electron, which makes it an n-type semiconductor. Similarly when an acceptor im purity is incorporated; it gives rise to an extra hole, which makes it a p-type semicondu ctor. The energy levels for an atom are discrete but they are so closely spaced that they form continuous energy bands. In any semiconductor there is a forbidden energy region in which allowed states cannot exist. The energy ba nd above this energy gap is called the conduction band and the one below is called the val ence band. And the forbidden energy


15 region is called the Energy Bandgap (Eg) which is o ne of the most important parameters in semiconductors. The Fermi level is defined as the energy level belo w which all states will have at most two electrons of opposite spin according to Pa uli’s exclusion principle [9]. It can be also defined as the energy level where the probabil ity of finding an electron is . The Fermi distribution function is given by kT E EF e E f) ( 1 1 ) (+ = (2.1) where k is the boltzman’s constant, T is the absolu te temperature, EF is the Fermi energy. For an intrinsic semiconductor the Fermi level lies approximately in the middle of the bandgap. This Fermi level shifts towards the conduc tion band for n-type and towards the valence band for p-type semiconductors. The Fermi l evels can be calculated using the equations given below [10]. For n-type ) ln(C D C FN N kT E E= (2.2) For p-type ) ln(V A F VN N kT E E= (2.3) where k is the boltzman’s constant, T is the absolu te temperature, EF is the Fermi energy, EC is the energy level at the bottom of the conductio n band, EV is the topmost energy level of the valence band, NC and NV is the effective density of state in the conductio n band and valence band respectively, ND and NA is the donor and acceptor concentration respectively [11].


16 2.2 Photovoltaic Effect The "photovoltaic effect" is the basic physical pro cess through which a solar cell converts light from the sun into electricity. Sunli ght is composed of photons, or "packets" of energy that contain different amounts of energy corresponding to the different wavelengths of light. When photons are incident on a solar cell, they may get reflected or absorbed, or they may pass right through. When abso rbed, the energy of the photon is transferred to an electron in an atom of the cell. With its newfound energy, the electron is able to escape from its normal position associated with that atom to become part of the current in an electrical circuit. By leaving this p osition, the electron causes a hole to form. Special electrical properties of the solar cell lik e built-in electric field provide the voltage needed to drive the current through an external loa d such as a light bulb [12]. 2.3 P-N Junction When a p-type semiconductor is suitably joined to n -type semiconductor, the contact surface is called a p-n junction. Most sem iconductor devices contain one or more p-n junctions. The p-n junction is of great importa nce because it is the control element for the semiconductor devices. P-n junction diodes form the basis of not only sola r cells, but of many other electronic devices such as LEDs, lasers, photodiode s and bipolar junction transistors (BJTs). A p-n junction aggregates the effects of re combination, generation, diffusion and drift into a single device.


17 A simple p-n junction consists of two semiconductor regions with opposite doping type as shown in Figure 2.2. The region on t he left is p -type with an acceptor density Na, and the region on the right is n -type with a donor density Nd. The dopants are assumed to be shallow, so that the electron (hole) density in the n -type ( p -type) region is approximately equal to the donor (acceptor) density Figure 2.2 Cross Section of a P-N Junction. [13] In an abrupt p-n junction device both the regions a re uniformly doped and the transition between the two regions is abrupt. In pn junctions where one side is distinctly higher-doped than the other will, it is found that only the low-doped region needs to be considered, since it primarily determines the devic e characteristics and this structure is referred to as a one-sided abrupt p-n junction. The junction is biased with a voltage Va as shown i n Figure 2.2. We call it a forward bias if a positive voltage is applied to th e p-doped region and if a negative


18 voltage is applied to the p-doped region we call it reversed-biased. The contact to the ptype region is also called the anode, while the con tact to the n-type region is called the cathode, in reference to the anions or positive car riers and cations or negative carriers in each of these regions. The principle of operation will be explained using a gedanken experiment, an experiment, which is in theory possible but not nec essarily executable in practice [14]. We imagine that one can bring both semiconductor re gions together, aligning both the conduction and valence band energies of each region This yields the so-called flatband diagram shown in Figure 2.3. Figure 2.3 Energy Band Diagram of P-N Junction Befo re and After Merging the N-Type and P-Type Regions. This does not automatically align the Fermi energie s, EF,n and EF,p. Also, this flatband diagram is not in equilibrium since both e lectrons and holes can lower their energy by crossing the junction. A motion of electr ons and holes is therefore expected


19 before thermal equilibrium is obtained. The diagram shown in Figure 2.3 (b) is called a flatband diagram. It is named as flat band as it re fers to the horizontal band edges. It also implies that there is no field and no net charge in the semiconductor. In order to reach thermal equilibrium, electrons/ho les close to the metallurgical junction diffuse across the junction into the p -type/ n -type region where hardly any electrons/holes are present. This process leaves th e ionized donors (acceptors) behind, creating a region around the junction, which is dep leted of mobile carriers. We call this region the depletion region, extending from x = xp to x = xn. The charge due to the ionized donors and acceptors causes an electric fie ld, which in turn causes a drift of carriers in the opposite direction. The diffusion o f carriers continues until the drift current balances the diffusion current, thereby reaching th ermal equilibrium as indicated by a constant Fermi energy. This situation is shown in F igure 2.4: While in thermal equilibrium no external voltage is applied between the n -type and p -type material, there is an internal potential, f i, which is caused by the work function difference between the n -type and p -type semiconductors. This potential equals the built-in potential, which will be further discussed in the next section.


20 Figure 2.4 Energy Band Diagram of P-N Junction in T hermal Equilibrium. [15] The built-in potential in a semiconductor equals th e potential across the depletion region in thermal equilibrium. Since thermal equili brium implies that the Fermi energy is constant throughout the p-n diode, the built-in pot ential equals the difference between the Fermi energies, EFn and EFp, divided by the electronic charge. It also equals the sum of the bulk potentials of each region, f n and f p, since the bulk potential quantifies the distance between the Fermi energy and the intrinsic energy. This yields the following expression for the built-in potential. 2lni a d t in N N V =f (2.4) We now consider a p-n diode with an applied bias vo ltage, Va. A forward bias corresponds to applying a positive voltage to the a node (the p-type region) relative to the cathode (the n-type region). A reverse bias corresp onds to a negative voltage applied to the cathode. Both bias modes are illustrated with F igure 2.5. The applied voltage is


21 proportional to the difference between the Fermi en ergy in the n-type and p-type quasineutral regions. As a negative voltage is applied, the potential acr oss the semiconductor increases and so does the depletion layer width. As a positiv e voltage is applied, the potential across the semiconductor decreases and with it the depletion layer width. The total potential across the semiconductor equals the built -in potential minus the applied voltage, or: a iV=f f (2.5) Figure 2.5 Energy Band Diagram of P-N Junction unde r Reverse and Forward Bias.[16] 2.4 P-N Heterojunction Heterojunction p-n diodes can be found in a wide ra nge of heterojunction devices including laser diodes, high electron mobility tran sistors (HEMTs) and heterojunction bipolar transistors (HBTs). Such devices take advan tage of the choice of different


22 materials, and the corresponding material propertie s, for each layer of the heterostructure. The heterojunction p-n diode is in principle very s imilar to a homojunction. The main problem that needs to be tackled is the effect of t he bandgap discontinuities and the different material parameters, which make the actua l calculations more complex even though the p-n diode concepts need almost no changi ng. The flatband energy band diagram of a heterojunctio n p-n diode is shown in the figure below. As a convention we will assume D Ec to be positive if Ec,n > Ec,p and D Ev to be positive if Ev,n < Ev,p. Figure 2.6 Flatband Energy Diagram of P-N Heterojun ction. [17] The built-in potential is defined as the difference between the Fermi levels in both the n -type and the p -type semiconductor. From the energy diagram we fin d: p F n F iE E q, ,=f (2.6)


23 which can be expressed as a function of the electro n concentrations and the effective densities of states in the conduction band: n c p p c n c iN n N n kT E q, 0 0ln + D =f (2.7) The built-in voltage can also be related to the hol e concentrations and the effective density of states of the valence band: p v n n v p v iN p N p kT E q, 0 0ln + D =f (2.8) Combining both expressions yields the built-in volt age independent of the free carrier concentrations: p v n c p c n v p i n i a d v c iN N N N kT n n N N kT E E q, , , ,ln 2 ln 2 + + D D =f (2.9) where ni,n and ni,p are the intrinsic carrier concentrations of the n -type and p -type region, respectively. D Ec and D Ev are positive quantities if the bandgap of the n -type region is smaller than that of the p -type region and the sum of both equals the bandgap difference. The band alignment must also be as shown in Figure 2.6. The above expression reduces to that of the built-in junction of a homojunction if the material parameters in the n -type region equal those in the p -type region. If the effective densities of states are the same, the expression for the heterojunction reduces to: p i n i a d v c in n N N kT E E q, ,ln 2 + D D =f (2.10)


24 2.5 Solar Cell Parameters Solar cells can be modeled as a current source in p arallel with a diode. The solar cells behave like a diode when there is no light pr esent to generate any current. As the intensity of incident light increases, current is g enerated by the PV cell, as illustrated in Figure 2.7. Figure 2.7 I-V Curve of a Solar Cell and its Electr ical Circuit Diagram. [18] In an ideal solar cell, the total current I is equal to the current I generated by the photoelectric effect minus the diode current ID, according to the equation: = = 10 kT qV l D le I I I I I (2.11) where I0 is the saturation current of the diode, q is the e lementary charge 1.6x10-19 Coulombs, k is a constant of value 1.38x10-23J/K, T is the cell temperature in Kelvin, and V is the voltage produced by the cell. I-V curve of an illuminated PV cell has the shape s hown in Figure 2.8 as the voltage across the measuring load is swept from zer o to VOC, and many performance


25 parameters for the cell can be determined from this data, as described in the sections below. Figure 2.8 Illuminated I-V Sweep Curve. ISC represents to the maximum current that passes thro ugh the cell that corresponds to the short circuit condition when the impedance is low. It occurs at the beginning of the sweep when the voltage is zero. I n an ideal cell, this maximum current value is the total current produced in the solar ce ll by photon excitation. ISC = IMAX at V=0 The open circuit voltage is the maximum voltage dif ference across the cell, and it occurs when there is no current passing through the cell. VOC =VMAX at I=0 The power produced by the cell in Watts can be easi ly calculated along the I-V sweep by the equation P=IV At the ISC and VOC points, the power will be zero and the


26 maximum value for power will occur between the two. The voltage and current at this maximum power point are denoted as VMP and IMP respectively. Figure 2.9 Maximum Power for an I-V Sweep. The Fill Factor (FF) is essentially a measure of qu ality of the solar cell. It is calculated by comparing the maximum power to the th eoretical power ( PT) that would be output at both the open circuit voltage and short c ircuit current together. Fill Factor can also be interpreted graphically as the ratio of the rectangular areas depicted in Figure 2.10. Figure 2.10 Fill Factor from the I-V Sweep.


27 A larger fill factor is desirable, and corresponds to an I-V sweep that is more square-like. Typical fill factors range from 0.5 t o 0.82. Efficiency is the ratio of the electrical power out put Pout, compared to the solar power input, Pin, into the PV cell. Pout can be taken to be PMAX since the solar cell can be operated up to its maximum power output to get the maximum efficiency. in MAX MAX in outP P P P = =h h (2.12) Pin is taken as the product of the irradiance of the i ncident light, measured in W/m2 or in suns (1000 W/m2), with the surface area of the solar cell [m2]. The maximum efficiency (MAX) found from a light test is not only an indication of the performance of the device under test, but, like all of the I-V par ameters, can also be affected by ambient conditions such as temperature and the intensity an d spectrum of the incident light. For this reason, it is recommended to test and compare PV cells using similar lighting and temperature conditions. During operation, the efficiency of solar cells is reduced by the dissipation of power across internal resistances. These parasitic resistances can be modeled as a parallel shunt resistance (RSH) and series resistance (RS), as depicted in Figure 2.11.


28 Figure 2.11 Simplified Equivalent Circuit Model for a Photovoltaic Cell. For an ideal cell, RSH would be infinite and would not provide an alterna te path for current to flow, while RS would be zero, resulting in no further voltage dro p before the load. Decreasing RSH and increasing Rs will decrease the fill factor (FF) and PMAX as shown in Figure 2.12. If RSH is decreased too much, VOC will drop, while increasing RS excessively can cause ISC to drop instead. Figure 2.12 Effect of Series and Shunt Resistances.


29 The series and shunt resistances, RS and RSH, can be approximated from the I-V curve as shown in Figure 2.13. Figure 2.13 Shunt and Series Resistances from the I -V Curve. If incident light is prevented from exciting the so lar cell, the I-V curve shown in Figure 2.14 can be obtained. This I-V curve is sim ply a reflection of the “No Light” curve from Figure 1 about the V-axis. The slope of the linear region of the curve in the third quadrant (reverse-bias) is a continuation of the linear region in the first quadrant, which is the same linear region used to calculate RSH in Figure 2.13. It follows that RSH can be derived from the I-V plot obtained with or w ithout providing light excitation, even when power is sourced to the cell.


30 Figure 2.14 I-V Curve of Solar Cell without Light E xcitation. 2.6 Tandem Solar Cells These structures, also called a cascade or multijun ction cells, can achieve a higher conversion efficiency by capturing a larger portion of the solar spectrum. In the typical tandem solar cell, individual cells with different bandgaps are stacked on top of one another in such a way that the sunlight falls first on the material having the highest bandgap. The top cell absorbs the high energy photo ns while remaining transparent to the low energy photons to allow them to fall on the cel ls below it where they are absorbed according to their appropriate bandgaps. These sele ctive absorption processes continue through to the last cell, which has the smallest ba ndgap. The schematic of a typical tandem solar cell is shown in figure 2.15.


31 Figure 2.15 Schematic of Tandem Solar Cell. [19] A tandem solar cell can be fabricated in two differ ent ways. Two single junction solar cells are made independently in the mechanica l stack approach, one with a high bandgap and one with a lower bandgap. Then the two cells are mechanically stacked, one on top of the other. In the monolithic approach, on e complete solar cell is made first, and then the second cell is grown or deposited directly on the first cell. Much of today's research in tandem solar cells focu ses on gallium arsenide as one (or all) of the component cells. These cells have e fficiencies of more than 35% under concentrated sunlight—which is very high for PV dev ices. The tandem solar cells in focus in our work are the CdSe – CIGS Solar Cells.


32 2.6.1 CdSe – CIGS Tandem Cells For bandgaps of 1.7eV and 1.0eV for top cell and bo ttom cell respectively, efficiencies greater than 25% are achievable [20]. Simulations indicate that efficiencies of 25 – 30% can be achieved with CdSe/CIGS thin-film t andem devices [20]. The main objective to achieve this is to develop a transpare nt CdSe device of 16% conversion efficiency. The tandem structure of a CdSe – CIGS Solar cell is shown in the figure 2.16. Figure 2.16 Structure of CdSe-CIGS Tandem Solar Cel l. 2.6.2 CIGS Solar Cell CIGS solar cells have been widely investigated as f uture generation thin film solar cells. Lab efficiencies of 19.9% [21] are reported while commercially manufactured CIGS solar cells have efficiencies ~ 10% [22]. CIGS (Copper Indium Gallium di Selenide) acts as a p-type absorber layer and has a very high absorption coefficient due to its direct bandgap. Cu vacancies are the reason for its p-type behavior. The n-type layer is


33 CdS. Molybdenum forms the p-type contact for CIGS a nd ZnO:Al forms the n-type contact for CdS. The devices fall under the classif ication of substrate configuration as light is incident through the top contact ZnO:Al. S oda lime glass is the most widely used substrate for CIGS Solar Cells. The low cost substr ate contains an alkali and acts as a sodium source for CIS thin films which upon diffusi on improves the grain growth and device performance. Addition of gallium not only in creases bandgap but also improves the adhesion of the film to the Mo substrate. The s chematic of the CIGS solar cell is as shown in the figure 2.17. Figure 2.17 Structure of CIGS Solar Cell. 2.6.3 CdSe/ZnSe Solar Cell The highest attained thin-film efficiencies for CdS e are around 6%, and were not transparent [20]. Extensive research has been done to make this structure transparent while restricting to the use of transparent contact Transparent CdSe/ZnSe structures have been developed to demonstrate record Jsc’s of 17.4 mA/cm2 [21]. In this structure SnO2 serves as the n contact and ZnSe:Cu as the p contac t. These structures have also exhibited sub band gap transmission of 80% [23]. Inspite of a fairly favorable valance bad alignment, the Fermi level seems to be near the mid dle of the CdSe bandgap as the Voc’s


34 achieved were only around 300mV with ZnSe:Cu. The s tructure of a typical device is shown in the figure 2.18. Figure 2.18 Structure of CdSe/ZnSe Solar Cell. The current density of 17.4mA/cm2 is the highest reported for a transparent thinfilm CdSe device and it indicates the high electron ic quality of the CdSe absorber layer. The device type that was targeted was metal/semicon ductor/metal (MSM ) in which the semiconductor is completely depleted, and thus Voc is determined by the contact energy of the two transparent p and n type contacts. Study has been done on the n-type contacts and SnO2 was found to have superior performance over ZnO an d CdS even though they contributed in a small increase in the Voc but the currents were low in comparision to the SnO2[24]. Focus had been made on the p-type contacts wh ich was a bigger challenge. A reliable p-type contact should be transparent and should also have proper alignment of the valence band and Fermi level with the absorber layer. ZnSe and ZnTe were pursued as they were meeting of the criteria.


35 -2 -1 0 1 2 3 4 ZnTeZnSeCdSeZnOSnO2CdS ---------------------------------Energy(eV) Figure 2.19 Band Alignments for CdSe and Transparen t Contacts. The valence band of ZnSe aligns well with that of C dSe with reference to the figure 2.19 and should be an ideal p contact. The d ashed line in the figure is the demarcation line for p-type characteristics [24]. B ut from the earlier discussion, the low Voc’s indicate the contact energies of ZnSe:Cu is n ot close to the valence band of CdSe assuming SnO2 is close to the conduction band of CdSe. Thus a do wnward movement of the Fermi level is to be achieved to get the voltag e as high as 1 Volt. An approach has been made to solve this problem by doping the ZnSe layer with Nitrogen. Initial results showed successful incorpo ration of N but no trace of significant doping was observed [22]. An alternative approach o f using ZnTe as the p-type layer was considered.


36 2.6.4 CdSe/ZnTe Solar Cell As its higher valence band encourages p-type charac ter, ZnTe is a good choice and previously reported achieved Voc of 475mV [24] indicates lower contact energy than that of ZnSe. Voc around 575 mV were achieved by a different deposit ion procedure with necessary increment of the thickness to 2000A0. An issue with the ZnTe layer is that the current densities were low in comparison to the ZnS e contacts. The currents were about 3mA/cm2. This was attributed to the thickness of the ZnTe and lower bandgap of 2.2eV compared to 2.6eV of ZnSe. Efforts were made to und erstand these devices. This thesis aims at doping the widow layer to improve device pe rformance. Cu seemed to be an effective p-type dopant and is being investigated.


37 CHAPTER III DEVICE FABRICATION AND MEASUREMENTS 3.1 Introduction Fabrication details of CdSe Solar Cells will be dis cussed in this chapter. 3.2 Processing of CdSe Solar Cells CdSe/ZnSe and CdSe/ZnTe form the top solar cell of the tandem stack. Temperatures during CdSe deposition process are ver y high. Corning 7059 glass is used as a substrate as it can withstand high processing temperatures above 7000C. Fluorine doped tin oxide is used as an n-type ohmic contact to CdSe, while Cu is used as a front ptype contact to ZnSe and ZnTe. Processing details o f the top cell are described below. 3.2.1 Substrate Typical dimensions of the substrate are 1.25 X 1.35 X 0.05 inches. 3.2.2 Cleaning Procedure The substrate goes through a regular cleaning proce dure before depositing Fluorine doped SnO2. This is a very important step as any contaminants present on the surface of the substrate could affect the succeedin g deposition steps and the device performance as a whole. The substrate is first rins ed in DI water and scrubbed using a


38 brush to remove any particles present on the surfac e. To remove any further surface contamination due to particles absorbed chemically, the substrate is dipped in a 10% HF solution for 5 seconds and immediately rinsed with DI water. It is again dipped in the same solution for 2 seconds and after an immediate final rinse with DI water, the substrate is then blown dry with nitrogen. 3.2.3 Back Contact The factors for being a good back contact are that it should be transparent, conductive and have appropriate contact energy. SnO2: F, TEC glass and ITO are the three TCO’s used as back contacts. Fluorine doped S nO2 has a band gap of 3.5 eV and is a very good TCO because of its high transmission of 90 % and low sheet resistance of 710 ohms/sq. Besides doped In2O3 and ZnO doped SnO2 is the best known representative of the class of transparent conductors and finds use in fo rm of poly-crystalline thin films. Metaloxides often behave like semiconductors with a wide band gap due to their strong chemical bonds. To reduce its resistivity SnO2 can be doped with fluorine (group VII). In this case F1substitutes O2and therefore acts as an electron donor resulting in a conduction mechanism of the n-type. The specific re sistivity of polycrystalline doped SnO2 can be as low as 10-3 cm and is limited mainly by low mobility’s in the o rder of 20 cm2/Vs [25], smaller than in single crystals due to im purities, dislocations and grain boundary effects. The apparent band gap appears in total blue-shifted due to the degenerate doping level. Carrier concentrations in doped SnO2 are lower than in In2O3:Sn


39 (ITO) by almost a factor of two, because the solubi lity of fluorine in SnO2 is inferior to that of Sn in In2O3. This results in a lower infrared reflectivity and higher resistance of SnO2:F. Despite these drawbacks the lower costs mak e it an interesting alternative for applications, where large areas have to be coated. Furthermore it is chemically quite stable. Fluorine Doped Tin Oxide The Fluorine doped SnO2 is deposited by the MOCVD process and is the n-type contact to CdSe. During MOCVD, a series of surface reactions occur. These reactions include adsorption and desorption of the precursor molecules, surface diffusion, nucleation and growth, and desorption of reaction p roducts. The source for tin is TMT (Tetra Methyl Tin). The source for Fluorine is Halo carbon 13B1 (Difluoroethylene) and acts as the dopant and Helium as the carrier gas. T o prevent the diffusion of Fluorine atoms, a bi-layer comprising undoped and doped tin oxide is deposited. During the deposition of undoped layer only Oxygen and TMT are reacted and 13B1 is added to them during the deposition of the doped layer. The Schematic of the CVD reactor is shown if Figure 3.1. The substrate temperature duri ng the whole process is maintained at 4400C using the RF coils encircling the reactor and are water cooled. Four samples can be accommodated at a time on the graphite sample holde r and it is placed at an elevated angle of 5 degrees to improve uniformity of the dep osited layer. For the first 8 minutesTMT, Halocarbon 13B1 and oxygen are flown through t he reactor to deposit the n-type Fluorine doped layer of SnO2. The substrates are annealed in the presence of ox ygen for


40 the next 5 minutes. For the last 5 minutes an undop ed layer of SnO2 is deposited. The thickness of the film is approximately half micron. Figure 3.1 Schematic of MOCVD Reactor. [26] The technique allows for relatively fast deposition that is controlled by adjusting the numerous deposition parameters such as precurso r partial pressure, gas flow, substrate temperature, chamber temperature, reactor back pressure and so forth. Tech Glass SnO2:F is commercially available in a multilayer st ructure as Tech glass. Current applications include photovoltaics, electrochromics and displays. Optical design of these and other applications requires knowledge of the op tical constants, in some cases, over the whole solar spectrum. This material is deposite d in several steps and has a fairly complex structure.


41 The commercially available transparent conductive s ubstrates Tech20 and Tech15 glass by Libbey Owens Ford are commonly referred to as tin-oxide glass, but in reality they are multilayer structures composed by differen t materials. On a soda-lime-silicate (glass) substrate a thin intrinsic SnO2 layer is deposited. It is then followed by a thin S iO2 film and finally a thick SnO2:F layer. The numbers 20 and 15 refer to the nomina l sheet resistance of 20 / and 15 / respectively [25], where the sheet resistance is d efined as the ratio of specific resistivity and film thick ness. Figure 3.2 Structural Model for Tech 20 Glass. [25] Undoped SnO2 is a defect compound tending to form numerous oxyg en vacancies resulting in carrier concentrations of 1017-1019 cm-3. Although the conductivity is much smaller than that of SnO2:F, the free electron influence should nevertheless be observable. It must be pointed out that the SnO2:F layer turns opaque above 1.5 m due to its free carriers’ influence. Tech 20 is the glass we used in our work. The glass was cut into pieces nearly to the dimensions of Corning 7059 substrates. The subs trates were rinsed with soap water


42 and then put in a beaker of methanol which is then kept in ultrasonic for about 1 hour to remove any chemically absorbed dust particles from the surface of the substrate and then dried out with blowing nitrogen. 3.2.4 Absorber Layer Cadmium Selenide, which belongs to the II-VI group of the periodic table, is used as the absorber layer because of its fixed optical bandgap of 1.7 eV and a high chemical stability. Cd and Se have 2 and 6 electrons respect ively in their outer most orbit. Every Cadmium atom transfers its 2 electrons to 6 valence electrons of Se to form CdSe and a vacancy of a Selenium atom frees two electrons of C admium making CdSe n-type. CdSe crystallizes in two forms, either wurtzite (Hexagon al) or cubic (Zinc blende) structures. CdSe deposited in this work has Hexagonal structure CdSe films grown with larger grain size have better quality and also enhance the trans port properties of minority charge carriers. Preparation of CdSe Source The CdSe source is prepared by using a high purity (99.999%) CdSe powder. Utmost care is taken so that the material is contam inant free as they may affect the device performance. By pressing CdSe powder in a circular mold a circular disk of 2 mm thick and 1 inch in diameter is prepared. Deposition Procedure for CdSe CdSe can be deposited by various methods like Therm al evaporation, Sputtering, Chemical vapor deposition, Electrodeposition, CBD a nd CSS. CSS is a simpler process


43 and can also produce films of good electronic prope rties. The deposition rate is high so that 1-2m thick films can be deposited in a short time. The source is kept on a graphite holder and is separated by 4 mm from the substrate by quartz spacers. Each of the two quartz lamps is fixed to a reflector and are placed one over the other so that the heat is localized. A Schematic of the CSS tube is shown in Figure 3.3. The chamber is pumped down to less than 1 Torr through a mechanical pump and purged with Helium thrice. It is then pumped down to a base pressure of 0.92 Torr an d backfilled with Helium to a pressure of 3.92 Torr. The source and the substrate are then heated to 6700C and 5600C respectively using temperature controllers. The dep osition is carried out for 17 minutes after which both the lamps are turned off and a 2 m icron thick CdSe film having wurzite structure is formed. Increasing the substrate tempe rature was found to reduce the sticking coefficient of the Cd and Se atoms, resulting in a thinner film. The sticking coefficient of Se is low at high temperatures, so the films are Cd rich, which causes them to be n-type. Films deposited by CSS were found to be free of pin holes and of a high electronic quality. The quality of the films mainly depends on the parameters like pressure, substrate and source temperatures and the spacing b etween them. Figure 3.3 Schematic of CSS Chamber. [27]


44 3.2.5 Window Layer To transmit maximum amount of light to the absorber layer, we need a window layer with a high bandgap. Zinc Selenide with a ban d gap of 2.7 eV can be used as a window layer. It is a II-VI semiconductor widely us ed in many opto-electronic applications. The crystal structure of ZnSe is show n in Fig 4.11. It crystallizes into a Zincblende structure. Deposition Procedure for ZnSe The source used is High purity (99.999%) ZnSe powde r. ZnSe is thermally evaporated at room temperature and deposited on fil ms deposited with CdSe. The evaporation chamber is pumped down below 3x10-6 Torr and the source is heated in radak furnace to get desired deposition rates. A schematic diagram of the evaporation chamber is s hown in Figure 3.4 [28]. The chamber has 4 radak furnaces with a capability to h eat up 3 sources at the same time. The temperature of the sources and the substrate was co ntrolled by temperature controllers. Deposition Procedure for ZnTe ZnTe is also deposited by thermal evaporation but i n a different vacuum chamber from that of ZnSe. The chamber has three radak furn aces and all the three can be heated at the same time. The sources are loaded with ZnTe, Se and Copper. The chamber is pumped down to micro torr range and ZnTe is deposit ed onto the substrate deposited with


45 CdSe. The thickness is registered in the thickness monitor and the temperature controlled by temperature controllers. Deposition Procedure for Cu Doped Window La yer Copper doping of ZnTe is achieved by co-evaporating both Cu and ZnTe. Several experiments were done changing the thicknesses of t he undoped and doped layers of ZnTe. Experiments were also done changing the conce ntration of copper during the deposition of the doped layer of ZnTe by varying th e deposition rate. 3.2.6 Front Contact Higher conductivity, transparency nad ability to fo rm an ohmic contact with the window layer are the prome characteristics of the f ront contact. Copper is deposited as front contact by thermal evaporating Copper pellets (99.999% pure) in the chamber shown in Fig 3.5. The pellets are loaded onto tungs ten boats and heated to desired temperatures. To keep the reflection losses minimum the thickness was maintained at 30A. A mask of 0.1 cm2 area dots was used for depositing copper on the Zn Se film. The chamber is initially pumped to the micro Torr range The chamber used to evaporate is shown in figure 3.5. The source is heated using a v ariac following a specific voltage-time profile.


46 After Cu deposition, the samples were left to sit i n air for about 12 hours before measuring the parameters. The 12 hour exposure to a ir showed significantly better response and could be attributed to Cu diffusion in to ZnSe and doping it, resulting in higher Voc’s. 3.3 Device Characterization Fabricated solar cells were characterized using I-V and Spectral response measurements. Data from these measurements was used to improve device performance by changing process parameters. Current-voltage (I-V) measurements were carried out using a Keithley 2410 sourcemeter. The sourcemeter was connected to a com puter through an interface and measurement was performed using a Labview program. Voltage is swept from -0.2V to 0.7V in light and dark conditions. The software pro gram calculates and generates precise values for Voc, Jsc, and FF automatically.


47 Figure 3.4 Schematic of ZnSe Evaporation Chamber. [ 22]


48 External Quantum Efficiency (Q.E.) measurement was done using an Oriel cornerstone 260 monochrometer. Q.E is defined as th e number of electron-hole pairs collected for each incident photon. The measurement s were calibrated using a Silicon reference cell for 400-900nm. The output current at each wavelength is measured using Figure 3.5 Schematic of Cu Evaporation Chamber. [27 ] an ammeter and was normalized to the current from t he silicon reference cell for CdSe cells and Silicon. The normalized current is multip lied with the Q.E of the reference cell to obtain Q.E of the sample. Current Density Jsc is calculated by integrating the area under the Q.E curve.


49 CHAPTER IV RESULTS AND DISCUSSIONS 4.1 Results The main objective of this work was to improve the device performance by doping the window layer of the CdSe solar cells. Bu t before experimenting with the doping of the window layer, the CdSe absorber layer had to be optimized. A new CdSe source that was prepared as mentioned in the previo us chapter. After which a series of experiments were conducted to develop and optimize the conditions of CdSe deposition in order to achieve the standard performance of dev ices. 4.1.1 Optimization of CdSe as Absorber Layer CdSe layer deposition was tried in a different way by depositing a thick layer of CdSe on a Corning 7059 glass substrate by CSS proce ss and then using the same glass substrate as the source for depositing the CdSe lay er of desired thickness. Initial depositions of CdSe were done with the same tempera tures for substrate and source that were used to deposit with CdSe pellet as source. Th e resulting films were not as thick as 2 microns and had a large thickness gradient with t hickness tapering towards the edges. The temperature of the source was lowered in 100C increments and a change in the uniformity of the deposited layer was observed. Un iformity in the CdSe layer was not observed until the temperature of the source was dr opped down to 6400C, but the films


50 still had a small thickness gradient which can be o verlooked as the Cu dots are deposited on the central portion of the substrate. Devices were made by depositing a ZnSe window layer on top of the CdSe layer. The device performance was not as good as the cells deposited by standard deposition procedures using a pellet as the source [27]. The D ark and Light IV curves are shown in figure 4.1 (a) and (b) respectively. -0.005 0 0.005 0.01 0.015 0.02 0.025 -0.2- Voltage(Volts)Current Density(mA/cm^2) (a) -0.005 0 0.005 0.01 0.015 0.02 -0.2- Voltage(Volts)Current Density(mA/cm^2) (b) Figure 4.1 Dark and Light IV Curves for CdSe Glass Source.


51 As a result, we had to go back to the former proced ure where CdSe was deposited by the CdSe pellet source directly by CSS. 4.1.2 CdSe/ZnSe Solar Cells The performance of the CdSe had to be verified, and to achieve this, a ZnSe window layer was deposited on the top of CdSe layer Standard CdSe/ZnSe solar cells that were fabricated previously were redone [27]. T he best of the cells produced a voltage around 320mV and currents about 12.41mA/cm2 with a fill factor of 40% as shown in figure 4.2 and 4.3. This showed that the CdSe layer has been optimized and ready for the next step of depositing a ZnTe layer on top of it. Spectral Response for CdSe G11-13-7-C Total Current= 12.41 mA/cm^2 0% 10% 20% 30% 40% 50% 60% 70% 80% 400500600700800900 Wavelength, (nm)Q.E. Figure 4.2 Spectral Response of CdSe/ZnSe Solar Cel l.


52 -5E-05 -1E-19 5E-05 1E-04 0.00015 0.0002 0.00025 0.0003 -0.3-0.2- Voltage(Volts)Current Density(mA/cm^2) (a) -0.0025 -0.002 -0.0015 -0.001 -0.0005 0 0.0005 0.001 0.0015 0.002 0.0025 -0.3-0.2- Voltage(Volts)Current Density(mA/cm^2) (b) Figure 4.3 Dark and Light IV Curves for CdSe/ZnSe S olar Cell. 4.1.3 CdSe/ZnTe Solar Cells CdSe/ZnTe solar cells prepared by vacuum evaporatio n have exhibited a voltage of 400mV but the currents were as low as 3mA [22]. The ZnTe powder source in use was tellurium rich (Zn 45%, Te 55%). So, the substrate was heated in order to prevent excess tellurium from sticking to the growth surface and a s a result making the film tellurium deficient. 2000C was selected as the starting temperature and incr eased in steps of 500C.


53 The cells deposited at 3000C exhibited the highest voltages but the currents w ere less than 1mA. The voltages at each temperature are shown in the table. Table 4.1 Voltages for CdSe/ZnTe Solar Cells at Dif ferent Substrate Temperatures. Substrate Temperature(0C) Voltage(milli Volts) 200 40 250 130 300 160 350 80 400 50 500 0 Due to equipment failure the deposition of the ZnTe was switched to the CIGS chamber. Unfortunately at the same time the MOCVD c hamber for Tin Oxide deposition also had problems. We started using the TEC 25 glas s substrates and the device performance was inferior compared to the cells fabr icated in the old chamber. The TEC glass was suspected of playing an important role in this failure, and a series of experiments were done to investigate the effect of the TCO. 4.1.4 Effect of TCO on Device Performance Devices made on TEC glass in the CIGS chamber did n ot perform as devices fabricated in the old chamber. As both the ZnTe cha mber and the MOCVD chamber had


54 problems at the same time, it was necessary to dete rmine the influence of these changes independently. So, devices had to be made using a t ransparent back contact which was known to give good results. ITO that was being used to make CdTe solar cells was used as the TCO to compare the performance with TEC glas s. Devices made with ITO had no significant effect on the performance but improved the currents by a very small value. So, concluding that the TCO had no significant effect o n the device performance, it was apparent that the ZnTe layer was limiting performan ce. 4.1.5 Copper Doping of ZnTe Voltages around 630mV were achieved with ZnTe/CdSe where the ZnTe was deposited by CSS from a ZnTe/glass source that was deposited from powder by CSS [23]. Using vacuum deposition of ZnTe produced lowe r Voc’s [20]. However doping was not possible in a CSS reactor due to process constr aints, and it was desired to revisit ZnTe by vacuum evaporation and use Cu doping. The copper doped ZnTe films were deposited by co-ev aporation. Cu dots were deposited, and results of dot to dot resistance mea surements are plotted as shown in figure 4.4. From the slopes the conductivity of the film was calculated to be 1.7e3 S/cm. Assuming a mobility of 1 cm2/Vs results in doping concentration of order 1e22 h oles/cm3 which indicates a substantial doping. However, extr apolation of the slopes indicates a 200-300 contact resistance with the Cu dots. This was puzz ling as tunneling contact should have been realized at these charge densities This was overlooked then, since Voc was the primary target and should not be affected b y contact resistance.


55 Figure 4.4 Plot of Dot to Dot Resistance Measuremen ts. Efforts were then directed to device fabrication. I n the following the ZnTe:Cu is deposited in the CIGS deposition chamber. Typical V oc’s are of order 250 mV and Jsc’s are 1 mA/cm2. Typical dark and light IV curves are shown below. It is obvious that there is significant shunting which is hurting Voc. Figure 4.5(a) Dark IV Curves for Cu Doped CdSe/ZnTe Solar Cell.


56 Figure 4.5(b) Light IV Curves for Cu Doped CdSe/ZnT e Solar Cell. The above IV curves are for a 200 nm thick ZnTe:Cu layer. It is speculated that the Cu is the cause of shunting. To reduce its infl uence a sample was made in which the first 100 nm of ZnTe was undoped, and a 100 nm dope d layer deposited on top of it. The effect on the IV is shown below in figure 4.6. The undoped sample shows minimal shunting, while th e doped is still clearly shunted even though the 100 nm doped layer is isola ted from the junction by a 100 nm undoped layer.


57 Figure 4.6 Dark IV Curves for 100nm Undoped and Cu Doped CdSe/ZnTe Solar Cell. Subtracting the shunt from the doped IV curve produ ces a net dark IV that with superposition would result in a Voc of order 500 mV The QE response for these devices is shown below. Figure 4.7 QE Response for 100nm Cu Doped CdSe/ZnTe Solar Cell.


58 As can be seen, there is notable difference in the spectra for doped vs. undoped. In particular the QE is lower in the region below 550 nm where ZnTe absorbs most for the doped film. To check this further another sample wa s made the same as the doped sample except that the undoped region was increased from 1 00 to 200 nm. This resulted in the drop in QE shown above. To compare directly, the ra tio of the 100 nm doped to 200 nm doped is plotted below. Figure 4.8 QE Response of Undopedx2 Thickness/Doped CdSe/ZnTe Solar Cell. As can be seen, the ratio is about 0.5 in the regio n below 550 suggesting that doubling of the undoped thickness cut the QE in hal f. This indicates that even the undoped ZnTe layer is dead. Further, the transmissi on for 200 nm of ZnTe is about 65% in the region 550-750 nm which is consistent with t he ratio in that region shown above. Also, the shunting showed little improvement indica ting that it is very difficult to keep the Cu from reaching the junction region with ZnTe.


59 4.1.6 CdSe/ZnTexSe1-x Solar Cells From the doping results it was evident that the dop ing really helped the device performance but was being limited by the undoped Zn Te layer. So, efforts were made to improve the undoped ZnTe layer. The substrate tempe rature was raised to 5000C to prevent incorporation of excess Tellurium. In the p rocess of heating the substrate to 5000C, the CdSe may start losing Se from it. So, Se flu x was introduced to compensate this loss. The Se fills any tellurium vacancies pro duced at such a high temperature. Care has been taken by adjusting the deposition rates to prevent Se from driving off Te from ZnTe. Early experiments resulted in bad devices, and the IV curves were electrically shorted. The same ZnTe deposition with Se flux was done on glass to see the properties of the layer. Surprisingly, the glass substrate had only slight traces of a deposited material on the substrate. The ZnTe was deposited at 5 times the rate of Se for this run. The Se flux at the growth surface of the substrate might h ave been stopping the ZnTe from being deposited on the substrate. So, for the next run, t he rate of the ZnTe has been further increased by 5 times. A thick layer of ZnTe with Se was evident on the substrate. The transmission response showed the presence of a fair amount of Se. This was repeated on top of a CdSe layer which still resulted in shorted IV curves. The ZnTe with Se might have crystallized and would be leaving spaces in be tween the grain boundaries and there by allowing the copper dots to reach the interface and as a result shorting the junction. Efforts were made to make this layer thicker, but h ad the same results were the same.


60 CHAPTER V CONCLUSIONS As discussed in the first chapter, the goal of achi eving efficiencies greater than 25-30 % in a solar cell is possible only by fabrica ting a Tandem cell. A 4-terminal tandem solar cell has two cells of suitable band ga ps placed one over the other with a proper encapsulant between them. According to the i nitial investigation, low band gap CIGS serves well as an absorber layer in the bottom cell. Significant efforts have been put in finding the suitable absorber for the top ce ll. In order to attain high efficiencies the band gap of the material should be between 1.5 eV a nd 2.0 eV. Further investigation resulted in opting for CdSe. The band gap of CdSe i s 1.7 eV. As a part of this study, the doping of the window l ayer for the CdSe solar cell has been investigated. The experiments performed partly confirmed positive effect of copper doping. The various experiments performed showed th at the copper diffuse readily into ZnTe window layer and is hard to prevent copper fro m reaching the CdSe/ZnTe interface. Experiments confirmed insignificant influence of th e TCO on device performance. ITO was used to confirm this result, and it resulted in the increase of current by a very small value. Doping has been varied with thickness and w as found to help the device performance but showed a huge amount of shunting in the IV Curves. Efforts were made to make the undoped layer thick, and results showed reduction in shunting but the device


61 performance was still inferior. This confirmed the undoped ZnTe layer to be defective, and a series of experiments were conducted to make the undoped ZnTe layer better. Se flux was introduced to make the layer better but in itial experiments done at high substrate temperatures resulted in electrically shorted cells This was assumed to happen due to crystallization of the ZnTexSe1-x layer allowing the copper to pass through grain boundaries and reach the interface. Further experim ents consisted of depositing a undoped ZnTe layer and depositing a ZnTexSe1-x later on top of it but resulted in shorted IV curves with voltages of around 30mV. This showed the positive effects of copper doping on the ZnTe window layer. The future works that can be suggested is to optimi ze the undoped layer before doping it with copper. Depositing a 1000A0 ZnTe layer by CSS and depositing a doped layer of 1000A0 on top of it can also give some important informat ion about the behavior of the ZnTe layer.


62 REFERENCES [1] [2] Jenny Nelson, “The Physics of Solar Cells”, Imp erial College Press, 2007. [3] Science Special energy issue 30 July 1999 Vol 285, Issue 5428, Pages 629-792. [4] National Renewable Energy Laboratory, 2003. "So lar electric power: The U.S. photovoltaic industry roadmap," at http://www.nrel. gov/ncpv/pdfs/30150.pdf [5] Solarbuzz, 2005a. “Marketbuzz 2005: Annual Worl d Solar Photovoltaic (PV) Market Report”, at -intro.htm. [6] PV News, published by the Prometheus Institute, April 2007, ISSN 0739-4829 [7] .cfm [8] [9] W.N.Shafarman et al,” Characterization of CuInS e2 Solar Cells with High Ga Content,” Proceedings of the 25th Photovoltacis Specialist Conference, 898, (IEEE, 19 95) [10] M.A.Contreras et al, Progress in Photovoltaics Res.Appl., 7, 311, (1999) [11] J.H.Scofield et al,” Sputtered Mo Bilayer Cont act for CuInSe2 Based Polycrystalline Thin Film Solar Cells,” Thin Solid Films, 260, 26, (1995) [12] photovoltaic.html [13] r4/ch4_2.htm [14] Solid State Electronic Devices, Fifth edition, B. G. Streetman, Prentice Hall, 2000. [15] Electrons and holes in semiconductors, W. Shoc kley, D. Van Nostrand Company, 1959. [16] S.M.Sze, "Physics of semiconductor devices”, W iley, New York (1981).


63 [17] Device Electronics for Integrated Circuits, Se cond edition, R.S. Muller and T. I. Kamins, Wiley & Sons, 1986. [18] oc0 [19] tructures.html#heterojunctions. [20] P. Mahawela, S. Jeedigunta, C. S. Ferekides an d D. L. Morel, “Development of IIVI High Band Gap Devices for High Efficiency Tandem Solar Cells”, Proceedings of the 29th IEEE PV Specialist Conference, New Orleans, May, 2 002, p. 724. [21] D. Bonnet and E. Rickus, Proceedings of the 14th IEEE PVSC, 1980, p. 629. [22] P. Mahawela, S. Jeedigunta, S. Vakkalanka, C. S. Ferekides and D. L. Morel, “Transparent High Performance Cdse Thin-Film Solar Cells”, Presented at the European Materials Research Society Meeting, Strasbourg, Jun e, 2004. [23] Su-Huai Wei, S. B. Zhang, and Alex Zunger, App l. Phys. Lett., 72(4), 3199 (1998). [24] Y. Hatanaka, M. Niraula, A. Nakamura, and T. A oki, Applied Surface Science, 175176 ,462 (2001). [25] K.Von Rottkay, M.Rubin, “Optical Indices of Py rolytic Tin-Oxide Glass”, LBNL Publication, 1996. [26] L. Nemani, “Effect of SnO2 Roughness and CdS Thickness on the Performance of CdS/CdTe Solar Cells”, Master’s Thesis, University of South Florida, Tampa, 2005. [27] S. Jeedigunta, “Development of Cadmium Selenid e as an Absorber Layer for Tandem Solar Cells”, Master’s Thesis, University of South Florida, Tampa, March 2004. [28] P. Mahawela, “Development of High Bandgap Effi ciency Photovoltaic Device”, Doctoral Dissertation, University of South Florida, Tampa, FL, April, 2004.

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Copper doped window layer for CdSe solar cells
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by Sheetal Kumar Chanda.
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Thesis (M.S.E.E.)--University of South Florida, 2008.
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ABSTRACT: CdSe solar cells with ZnTe as the window layer deposited by CSS process have shown V[subscript]oc's around 630mV. However the currents were very low and also the voltages were not meeting the desired objectives. To improve the performance the contact energy at the ZnTe/Cu interface should be minimized by doping the window layer. Thermal evaporation was used to deposit ZnTe to have more control over the composition of the film. Initial experiments were done by depositing Cu doped ZnTe films on plain glass by co-evaporating both ZnTe and Cu. The conductivity was in the order of 10e3 which shows copper present in the film in the order of 1e22 S/cm¨. This accomplishes a tunneling contact with the top electrode. Using the ZnTe:Cu contacts in complete devices resulted in disappointing voltages and currents. Efforts were made to deal with the poor performance of the cells. Devices were made on different types of TCO coated glass substrates but, were resulting in the same numbers which shows the type of TCO has an insignificant effect on the performance. The Cu doping has been helping in raising the V[subscript]ocs but at the same time marred the currents whose effect has been unexplainable. Further experiments have been made changing the ZnTe thickness and concentration of Cu doping. Experiments were done increasing the substrate temperature as high as 500C during ZnTe deposition and a Se flux has been introduced so as to compensate the loss of Se from CdSe at such high substrate temperature. But these experiments resulted in dismal performance indicating the domination of defects in the undoped ZnTe layer.
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Advisor: Don Morel, Ph.D.
Cadmium selenide
Zinc teluride
Copper doping
Tech glass
Tunneling contact
Dissertations, Academic
x Electrical Engineering
t USF Electronic Theses and Dissertations.
4 856