USF Libraries
USF Digital Collections

Probabilistic error analysis models for nano-domain vlsi circuits

MISSING IMAGE

Material Information

Title:
Probabilistic error analysis models for nano-domain vlsi circuits
Physical Description:
Book
Language:
English
Creator:
Lingasubramanian, Karthikeyan
Publisher:
University of South Florida
Place of Publication:
Tampa, Fla
Publication Date:

Subjects

Subjects / Keywords:
Reliability
Worst-case input
Sequential circuits
Redundancy models
Dissertations, Academic -- Electrical Engineering -- Doctoral -- USF   ( lcsh )
Genre:
non-fiction   ( marcgt )

Notes

Abstract:
ABSTRACT: Technology scaling to the nanometer levels has paved the way to realize multi-dimensional applications in a single product by increasing the density of the electronic devices on integrated chips. This has naturally attracted a wide variety of industries like medicine, communication, automobile, defense and even house-hold appliance, to use high speed multi-functional computing machines. Apart from the advantages of these nano-domain computing devices, their usage in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for comprehensive error analysis to enhance their reliability. Moreover, these nano-electronic devices have increased propensity to transient errors due to extremely small device dimensions and low switching energy. The nature of these transient errors is more probabilistic than deterministic, and so requires probabilistic models for estimation and analysis. In this dissertation, we present comprehensive analytic studies of error behavior in nano-level digital logic circuits using probabilistic reliability models. It comprises the design of exact probabilistic error models, to compute the maximum error over all possible input space in a circuit-specific manner; to study the behavior of transient errors in sequential circuits; and to achieve error mitigation through redundancy techniques. The model to compute maximum error, also provides the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. The model for sequential logic that can measure the expected output error probability, given a probabilistic input space, can account for both spatial dependencies and temporal correlations across the logic, using a time evolving causal network. For comprehensive error reduction in logic circuits, temporal, spatial and hybrid redundancy models, are implemented. The temporal redundancy model uses the triple temporal redundancy technique that applies redundancy in the input space, spatial redundancy model uses the cascaded triple modular redundancy technique that applies redundancy in the intermediate signal space and the hybrid redundancy techniques encapsulates both temporal and spatial redundancy schemes. All the above studies are performed on standard benchmark circuits from ISCAS and MCNC suites and the subsequent experimental results are obtained. These results clearly encompasses the various aspects of error behavior in nano VLSI circuits and also shows the efficiency and versatility of the probabilistic error models.
Thesis:
Dissertation (Ph.D.)--University of South Florida, 2010.
Bibliography:
Includes bibliographical references.
System Details:
Mode of access: World Wide Web.
System Details:
System requirements: World Wide Web browser and PDF reader.
Statement of Responsibility:
by Karthikeyan Lingasubramanian.
General Note:
Title from PDF of title page.
General Note:
Document formatted into pages; contains X pages.
General Note:
Includes vita.

Record Information

Source Institution:
University of South Florida Library
Holding Location:
University of South Florida
Rights Management:
All applicable rights reserved by the source institution and holding location.
Resource Identifier:
usfldc doi - E14-SFE0003469
usfldc handle - e14.3469
System ID:
SFS0027784:00001


This item is only available as the following downloads:


Full Text

PAGE 1

Probabilistic Error Analysis Models for Nano Domain VLSI Circuits by Karthikeyan Lingasubramanian A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in Electrical Engineering Dep artment of Electrical Engineering College of Engineering University of South Florida Major Professor: Sanjukta Bhanja Ph.D. Nagarajan Ranganathan, Ph.D. Syed M. Alam, Ph.D. Wilfrido A. Mor eno, Ph. D. Paris H. Wiley, Ph.D. Date of Approval: March 3, 2010 Keywords: Reliability, Worst case input, Sequential circuits, Redundancy models Copyright 2010 Karthikeyan Lingasubramanian

PAGE 2

DEDICATION TomyFamilyandFriends

PAGE 3

ACKNOWLEDGEMENTS IwouldliketothankmymajorprofessorDr.SanjuktaBhanjaforbelievinginmeandfor givingmethisopportunity.Withouthersupportthisdissertationwouldn'thavebeenpossible. Shehastrainedmeineveryaspectofresearchandhashelpedmemoldmyselfasabetter researcher.Moreovershehasalsobeenagoodfriendtome. MysincerethankstoDr.NagarajanRanganathan,Dr.SyedM.Alam,Dr.WilfredoA. MorenoandDr.ParisH.Wileyforservinginmycommittee.Iwouldliketothankthemall fortheirvaluablesupportandadviceandmostimportantlyforallottingtheirtimeinspiteof theirbusyschedule. IwouldliketothankallthefacultiesandstaffoftheDepartmentofElectricalEngineering andCollegeofEngineering. Iwouldliketothankallmypresentandformercolleagues,Javier,Anitha,Srinath,Dinuka, Jose,Pruthvi,Thara,Shiva,Nirmal,Vivek,Satish,PraveenandSaket,fortheirunconditional support. IamreallyverygratefulfortheinvaluablesupportandmotivationthatIreceivedfrommy family. IwouldalsoliketothankallmyfriendsthatIeverhadinmywholelife.

PAGE 4

TABLEOFCONTENTS LISTOFTABLESiv LISTOFFIGURESv ABSTRACTviii CHAPTER1INTRODUCTION1 1.1Motivation2 1.2Signicance3 1.3Contribution5 1.4ScopeofApplication8 1.5Organization10 CHAPTER2RELATEDWORK12 2.1SEUModeling12 2.2DynamicErrorModeling13 2.2.1CalculationofErrorBounds13 2.2.2CalculationofAverageError16 2.2.3ErrorReductionThroughRedundancy19 2.3RelationtoState-of-the-Art22 CHAPTER3DESIGNFUNDAMENTALS24 3.1ProbabilisticRepresentationofDigitalCircuits24 3.2ModelingErrorinDigitalCircuits29 CHAPTER4MAXIMUMERRORMODELING33 4.1MaximumaPosteriori(MAP)Estimate35 4.1.1CalculationofMAPUpperBoundsUsingShenoy-ShaferAlgorithm38 4.1.2CalculationoftheExactMAPSolution52 4.1.3CalculatingtheMaximumOutputErrorProbability55 4.1.4ComputationalComplexityofMAPEstimate55 4.2ExperimentalResults56 4.2.1ExperimentalProcedureforCalculatingMaximumOutputError Probability56 i

PAGE 5

4.2.2Worst-caseInputVectors58 4.2.3Circuit-SpecicErrorBoundsforFault-TolerantComputation59 4.2.4ValidationUsingHSpiceSimulator61 4.2.5ResultswithMultiple 65 4.3Discussion66 CHAPTER5MODELINGERRORINSEQUENTIALCIRCUITS67 5.1SequentialLogicModel68 5.1.1TDMModel69 5.2ErrorModel70 5.2.1Structure70 5.2.2InferenceScheme74 5.2.3OutputErrorProbability78 5.3ExperimentalResults78 5.3.1ExperimentalProcedure79 5.3.2OutputErrorProbabilities80 5.3.3NumberofTimeSlices80 5.3.4OutputErrorPropagationAcrossTimeSlices81 5.3.5OutputErrorProbabilitiesfor 0 = 183 5.3.6ValidationUsingHSpiceSimulation84 5.4Discussion85 CHAPTER6REDUNDANCYSCHEMESFORERRORMITIGATION86 6.1TemporalRedundancySchemeUsingTripleTemporalRedundancy(TTR) Technique87 6.1.1DeterminationoftheSetofWorst-CaseInputCombinationsfor SelectiveRedundancyinTTR87 6.1.2ExperimentalSetupforTTR89 6.2SpatialRedundancySchemeUsingCascadedTripleModularRedundancy (CTMR)Technique93 6.2.1SensitivityAnalysisforSelectiveRedundancyinCTMR94 6.3HybridRedundancy94 6.4ExperimentalResults95 6.4.1ErrorMitigationThroughTemporalRedundancy96 6.4.2ErrorMitigationThroughSpatialRedundancy97 6.4.3ErrorMitigationThroughHybridRedundancy98 6.4.4ComparisonBetweentheRedundancySchemes99 6.4.5ErrorMitigationThroughHybridRedundancywithDifferent CombinationsofSpatialandTemporalRedundancies101 6.4.6DelayandAreaPenalties102 6.5Discussion103 CHAPTER7CONCLUSIONANDFUTUREDIRECTIONS104 ii

PAGE 6

REFERENCES106 ABOUTTHEAUTHOREndPage iii

PAGE 7

LISTOFTABLES Table4.1.ValuationsofthevariablesderivedfromcorrespondingCPTs40 Table4.2.Combination41 Table4.3.Worst-caseinputvectorsfromMAP58 Table4.4.RuntimesforMAPcomputation61 Table4.5.Comparisonbetweenmaximumerrorprobabilitiesachievedfromthe proposedmodelandtheHSpicesimulatorat = 0 0562 Table5.1.Conditionalprobabilistictablesforerror-freeanderror-proneNAND logic73 Table5.2.Conditionalprobabilistictableforerror-proneNANDlogichavingvariablegateerrorprobabilities, 0and 173 Table5.3.Outputerrorprobabilitiesat = 0 001 0 003 0 005 0 0180 Table5.4.Outputerrorprobabilitiesat = 0 001 0 003 0 005 0 01comparedwith HSpicesimulationresults84 iv

PAGE 8

LISTOFFIGURES Figure1.1.Signicanceofthisdissertation4 Figure1.2.Scopeofapplication8 Figure2.1.(a)ProbabilistictransfermatrixforerroneousNANDgatewitherror probability [45](b)Markovrandomeld[47]17 Figure2.2.NANDmultiplexingschemeintroducedbyVonNeumann[1]20 Figure2.3.Someoftherelatedworksonreliabilitymodelsfordynamicerrorsin VLSIcircuits22 Figure3.1.Representationofadigitalcircuitasaprobabilisticgraph25 Figure3.2.Minimalrepresentationoftheprobabilisticgraph27 Figure3.3.Errormodel30 Figure3.4.Conditionalprobabilistictablesfortheidealanderroneousnodesinthe errormodel31 Figure4.1.(a)Digitallogiccircuit(b)Errormodel(c)Probabilisticerrormodel36 Figure4.2.Searchtreewheredepthrstbranchandboundsearchperformed38 Figure4.3.Illustrationofthefusionalgorithm41 Figure4.4.Partialillustrationofbinaryjointreeconstructionmethodfortherst chosenvariable44 Figure4.5.Completeillustrationofbinaryjointreeconstructionmethod45 Figure4.6.(a)MessagepassingwithclusterC11asroot(b)Messagepassingwith clusterC1asroot(c)Messagestoragemechanism47 Figure4.7.BinaryjointreefortheprobabilisticerrormodelinFig.4.1.(c)51 Figure4.8.SearchprocessforMAPcomputation53 v

PAGE 9

Figure4.9.Flowchartdescribingtheexperimentalsetupandprocess57 Figure4.10.Circuit-specicerrorboundalongwithcomparisonbetweenmaximum andaverageoutputerrorprobabilitiesfor(a) c 17,(b) max flat ,(c) voter ,(d) pc ,(e) count ,(f) alu 4,(g) malu 460 Figure4.11.Outputerrorprobabilitiesfortheentireinputvectorspacewithgateerror probability = 0 05for c 1763 Figure4.12.(a)Outputerrorprobabilities ( + ) ,calculatedfromprobabilistic errormodel,withgateerrorprobability = 0 05for max flat (b)CorrespondingHSpicecalculations64 Figure4.13.Comparisonbetweentheaverageandmaximumoutputerrorprobability andruntimefor =0.005, =0.05andvariable rangingfrom0.0050.05for max flat 65 Figure5.1.(a)Digitallogiccircuit(b)Correspondingprobabilisticmodel(c)DAG representationwhichisnotminimal(d)TDMmodel68 Figure5.2.ErrormodelobtainedfromTDMmodelwith3rdordertemporaldependence71 Figure5.3.(a)Digitallogiccircuit(b)Correspondingprobabilisticmodel(c)Moral graphobtainedbyaddingundirectedlinksbetweenparentsofcommon childnodes(d)Correspondingjointreeobtained76 Figure5.4.Flowchartforexperimentalprocedure79 Figure5.5.Numberoftimeslicesneededby bbara and bbtas for = 0 Š 0 00681 Figure5.6.(a)Transitionofoutputerrorprobabilityacrosstimeslicesfor bbara s 27and mc with = 0 01(b)Transitionofoutputerrorprobabilityacross timeslicesfor lion lion 9and bbtas with = 0 0182 Figure5.7.(a)Transitionoferror-freeanderror-proneoutputprobabilitiesacross timeslicesfor bbtas lion 9and lion with = 0 01(b)Transitionoferrorfreeanderror-proneoutputprobabilitiesacrosstimeslicesfor bbara with = 0 0182 Figure5.8.Outputerrorprobabilitiesfor( 0= 0 01, 1= 0 02)and( 0= 0 02, 1= 0 01)83 Figure6.1.Determinationofthesetofworst-caseinputcombinationsbybacktrackingthroughthesearchtreeusedforMAPcomputationgiveninFig.4.8.88 Figure6.2.ExperimentalsetupforTTRincorporatingselectiveredundancy90 vi

PAGE 10

Figure6.3.SpatialredundancyschemeusingCTMRtechniqueincorporatingmajoritylogic94 Figure6.4.HybridredundancyschemeusingCTMRandTTRtechniques95 Figure6.5.Percentagemitigationofoutputerrorachievedthrough5%and15% temporalredundancywith =0.00196 Figure6.6.Percentagemitigationofoutputerrorachievedthrough5%and15%spatialredundancywith =0.00198 Figure6.7.Percentagemitigationofoutputerrorachievedthrough5%and15%hybridredundancywith =0.00199 Figure6.8.Comparisonbetweentheredundancyschemesfor(a)5%and(b)15% redundancywith =0.001100 Figure6.9.Percentagemitigationofoutputerrorachievedthroughhybridredundancywithdifferentcombinationsofspatialandtemporalredundancies while =0.001101 Figure6.10.(a)Delaypenaltyintemporalredundancy(b)Areapenaltyinspatial redundancy102 vii

PAGE 11

PROBABILISTICERRORANALYSISMODELSFORNANO-DOMAINVLSI CIRCUITS KarthikeyanLingasubramanian ABSTRACT Technologyscalingtothenanometerlevelshaspavedthewaytorealizemulti-dimensional applicationsinasingleproductbyincreasingthedensityoftheelectronicdevicesonintegratedchips.Thishasnaturallyattractedawidevarietyofindustrieslikemedicine,communication,automobile,defenseandevenhouse-holdappliance,tousehighspeedmulti-functional computingmachines.Apartfromtheadvantagesofthesenano-domaincomputingdevices, theirusageinsafety-centricapplicationslikeimplantablebiomedicalchipsandautomobile safetyhasimmenselyincreasedtheneedforcomprehensiveerroranalysistoenhancetheir reliability.Moreover,thesenano-electronicdeviceshaveincreasedpropensitytotransienterrorsduetoextremelysmalldevicedimensionsandlowswitchingenergy.Thenatureofthese transienterrorsismoreprobabilisticthandeterministic,andsorequiresprobabilisticmodels forestimationandanalysis.Inthisdissertation,wepresentcomprehensiveanalyticstudies oferrorbehaviorinnano-leveldigitallogiccircuitsusingprobabilisticreliabilitymodels.It comprisesthedesignofexactprobabilisticerrormodels,tocomputethe maximum errorover allpossibleinputspaceinacircuit-specicmanner;tostudythebehavioroftransienterrors insequentialcircuits;andtoachieveerrormitigationthroughredundancytechniques.The modeltocomputemaximumerror,alsoprovidestheworst-caseinputvector,whichhasthe highestprobabilitytogenerateanerroneousoutput,foranygivenlogiccircuit.Themodel forsequentiallogicthatcanmeasuretheexpectedoutputerrorprobability,givenaprobabilisviii

PAGE 12

ticinputspace,canaccountforbothspatialdependenciesandtemporalcorrelationsacross thelogic,usingatimeevolvingcausalnetwork.Forcomprehensiveerrorreductioninlogic circuits,temporal,spatialandhybridredundancymodels,areimplemented.Thetemporalredundancymodelusesthetripletemporalredundancytechniquethatappliesredundancyinthe inputspace,spatialredundancymodelusesthecascadedtriplemodularredundancytechnique thatappliesredundancyintheintermediatesignalspaceandthehybridredundancytechniques encapsulatesbothtemporalandspatialredundancyschemes.AlltheabovestudiesareperformedonstandardbenchmarkcircuitsfromISCASandMCNCsuitesandthesubsequent experimentalresultsareobtained.Theseresultsclearlyencompassesthevariousaspectsof errorbehaviorinnanoVLSIcircuitsandalsoshowstheefciencyandversatilityoftheprobabilisticerrormodels. ix

PAGE 13

CHAPTER1 INTRODUCTION IntegratedCircuitsareusedinawiderangeofimportantapplicationslikeautomobile, aircraft,medicine,defense,communicationandevenhouse-holdappliances.Criticalapplicationslikemedicinedemandhighaccuracyandefciencyduetostringentsafetyrequirements, whileapplicationslikeautomotive,defensedemandmorerobustnessduetoextremeworkingconditions[41,42,39].Alsothedemandformulti-dimensionalapplicationsinasingle producthasincreasedthedensityoftheelectronicdevicesonachipeventuallyresultingin reductionofdevicefeaturesize,pushingthetechnologytonanometerlevels[60,59].ComplementaryMetalOxideSemiconductor(CMOS)transistors,whicharethecurrentgeneration electronicdevices,havebeenshrunktosub-50nmdimensions[59].Thisreductioninfeature sizeresultsinvariationsindeviceandprocessparameters,whichinturnleadstotransientdynamicfaultsindigitalcircuits.Inthisdissertation,wepresentanerrormodelthatcanhandle thesetransientdynamicfaultsusingprobabilisticmethods.Usingthiserrormodel,wepresent auniquemethodtocalculatemaximumerrorsindigitalcircuits.Also,basedonthiserror model,wepresentatimeevolvingprobabilisticnetworkthatcancalculateerrorinsequentialcircuits.Finally,wepresenttemporal,spatialandhybridredundancytechniques,which incorporatesselectiveredundancyusingthebaseerrormodel,forerrormitigationindigital circuits. 1

PAGE 14

1.1Motivation Whyuseprobabilisticmodels? Nano-domaincomputingdevicesarelikelytohavehigher errorrates(bothintermsofdefectandtransientfaults)astheyoperatenearthethermallimit andinformationprocessingoccursatextremelysmallvolume[61,47].Nano-CMOS,beyond 22nm,isnotanexceptioninthisregardasthefrequencyscalesupandvoltageandgeometry scalesdown.Theresultingerrors,duetouncontrollablevariationsindeviceandprocessparametersliketemperatureandthresholdvoltage,arehighlyintractablefordeterministictesting toolsusedtodetectpermanentfaults.Afreshlookatreliabilityinatechnologyindependent fashionisbothtimelyandnecessary.Giventheinherentstochasticnatureofthedevicesinthe nano-regime,insteadofdeterministiclogicmodelsprobabilisticmodelswouldbemoreappropriate.Thisrequiresasignicantshiftinthedesignandtestingparadigm,withreliability adoptingacentralroleindesignofelectronicdevices. Whymodelmaximumerror? Industrieslikeautomotiveandhealthcarehavetraditionallyaddressedhighreliabilityrequirementsbyemployingredundancy,errorcorrections,and choiceofproperassemblyandpackagingtechnology.Inaddition,rigorousproducttesting atextendedstressconditionsltersoutevenanentirelotinthepresenceofasmallnumberoffailures[39].Anotherrapidlygrowingclassofelectronicchipswherereliabilityis verycriticalisimplantablebiomedicalchips[41,42].Moreinterestingly,someofthesafety approaches,suchasredundancyandcomplexpackaging,arenotreadilyapplicabletoimplantablebiomedicalapplicationsbecauseoflowvoltageandlowpoweroperationandsmall formfactorrequirements.Authorsin[41]identiedthatconventionalapproachesindevice andparasiticmodeling,circuittechniques,andmanufacturingandtestneedtoimprovedue toextremelowpowerandhighreliabilityrequirements,sincetheseconstraintsposeserious complexitiesincircuitdesignthroughunpredictabledesignenvironment.Inaddition,webelieveourmethodofcalculatingmaximumprobabilityoferrorandtheproposedmaximum 2

PAGE 15

errorprobabilityawaredesigniswellsuitedforimplantablebiomedicalICdesign.Whiletwo designimplementationchoicescanhavedifferentaverageprobabilitiesoffailures,thelower averagechoicemayinfacthavehighermaximumprobabilityoffailureleadingtoloweryield inmanufacturingandmorerejectsduringchipburn-inandextendedscreening.Also,when theinputspaceforacircuitiscompletelyrandomandequallyprobable,calculationofaverage errorwillsufce.But,asinsomecases,whentheinputspacegetsbiased,theaverageerror informationwillnotbecomprehensiveenoughtounderstandtheerrorbehaviorinthecircuit. Therefore,usingmaximumprobabilityoffailureasacriticaldesignmetricalongwithaverage casewouldberequiredindesignofsafetycriticalelectronicchips. Whymodelerrorinsequentialcircuits? Mostofthereal-timeapplicationsofelectronic devices,likerandomaccessmemories,needsthemtobesequentialinnature.Sequentialcircuitsconsistofacombinationallogicblock,setofinputs,setofstatebitswherethevaluesof thenextstatebitisfedbacktothepresentstateinthenextclockcyclethroughlatches.At agiventimeinstance ti,thestatesignals stiareuniquelyidentiedasafunctionofprimary inputsignals itiandstatesignals sti Š 1oftheprevioustimeinstancegivingrisetotemporal correlations.Duetothis,erroroccurringinthecombinationalpartofthecircuitatonetime instancemightpropagatetowardsseveralconsecutivetimeinstancesmakingthedevicemore vulnerable[54,51].Thestaticreliabilitymodelsusedforcombinationalcircuitsarenotadequatetomodelthetemporaldependenciesbetweenthecircuitnodes,atthecombinational partofthesequentialcircuit,atdifferenttimeinstances[52,53,54,51,55].Inordertohandle thisamoredynamicmodelwhichcanevolvethroughconsecutivetimeinstancesisneeded. 1.2Signicance Theerrorsthatcanoccurinnano-domainVLSIcircuitscanbewidelydividedintotwo categories, hardfaults and softerrors .Hardfaultsrefertoanypermanentfaultsthatcan 3

PAGE 16

Reliability issues in Nano-domain VLSI circuits Soft errors This work Hard faults Physical defects Electrical Faults Shorts and Opens Logical Faults Stuck-at Faults Silicon substrate defectsStatic permanent errors High energy neutronsSingle Event Upsets Local errors Dynamic errors Device and process parameter variations Global errors Figure1.1.Signicanceofthisdissertation occurinacircuitcomponentduetophysicaldefectslikeoxideabnormalitiesinthetransistor, electricaldefectslikeshortsandopens,logicaldefectslikestuck-atanddelayfaults.Soft errorsrefertothefailuresincircuitcomponentsduetoexternalconditionslikehighenergy neutroninteractionordeviceparametervariations.Outofthesecategories,softerrorsare thetoughesttomodelduetotheirtransientnature,sincetheexternalconditionsresponsible fortheseerrorsarehighlyunpredictableatthenanometerlevels.So,thereliabilitymodels usedtoaddresshardfaultscannotbeusedtomodelsofterrors,sincetheyarecompletely deterministic.Therefore,comprehensiveprobabilisticmodels,likeourmodel,arewellsuited tohandlethetransientsofterrors. Themostprevalentsofterrorsinnano-domainVLSIcircuitsarewidelycategorizedinto SingleEventUpsets(SEUs)duetoexternalparticleinteraction,anddynamicerrorsdueto deviceandprocessvariabilities.WhilefailuresduetoSEUsaremorelocalized,inthesense, theyoccurinaparticularcomponentinthecircuitandgetspropagated,dynamicerrorsare moreglobal,inthesensethat,theycanoccuronmultiplecomponentsofthecircuitatthe sametime.So,themodelsthataddressfailuresduetoSEUsarenotenoughtomodeldynamic 4

PAGE 17

errors.Ourmodel,presentedinthiswork,targetsthedynamicerrorsbygivingprovisionsto addresserrorbehaviorinmultiplecircuitcomponentsatthesametime. Alsoourmodelcanbeconsideredasacompleteandcomprehensivemodelthatcanaccuratelycalculate bothmaximumandave rageerrors indigitalcircuits.Thisversatilityoffersa widerdiagnosticapplicationspace,whichaidsthecollectionofavarietyofinformationsets thatarehighlyessentialforICtesting. 1.3Contribution Thecontributionsofthisdissertationareasfollows, € Amethodtocalculate maximum outputerrorindigitalcircuitsusingaprobabilistic modelispresented. Givenacircuitwithaxedgateerrorprobability ,thiserrormodelcanprovide themaximumoutputerrorprobabilityandtheworst-caseinputvector,whichcan beveryusefultestingparameters.Itsalsoshownthattheseworst-caseinputvectorsnotonlydependonthecircuitstructurebutcoulddynamicallychangewith Itisshownthatthemaximumoutputerrorprobabilitiesaremuchlargerthanaverageoutputerrorprobabilities,forcomparativelylowervaluesofindividualgate errorprobability ,therebysignifyingtheimportanceofmaximumerrorasadesignparameter. Thecircuit-specicerrorboundsforfault-tolerantcomputationarepresentedand itisshownthatmaximumoutputerrorsprovideatighterbound.Also,itisshown thattheerrorboundforanindividualgateplacedinacircuitcanbedependenton thecircuitstructure. 5

PAGE 18

Throughthiswork,anefcientdesignframeworkthatemploysinferenceinbinary jointreesusing Shenoy-Shafer algorithm,toperformMAPhypothesisaccurately, isbeingappliedforthersttimeinthecontextofdigitalcomputingmachines. ThevalidityoftheerrormodelistestedthroughcomparisonwithcircuitsimulationsusingHSpiceandtheresultsshowedthatthehighest%differenceofthe errormodeloverHSpiceisjust1.23%,signifyingitsaccuracy. Thepossibilityofefcienterrorincorporationinthismodelispresentedbyprovidingvariable valuestodifferentgatesofacircuit,insteadofprovidingthesame valuetoallgates.Thisformationoftheerrormodelcanhelpinusefuldiagnostic studieslikeerrorsensitivityanalysis. € Anexactprobabilisticerrormodelthatcanstudytransienterrorbehaviorin sequential logicispresented. Thismodelcanaccuratelycalculatetheaverageoutputerrorprobabilityinany givensequentialcircuit. A minimal timeevolvingprobabilisticnetwork,namely,theTemporalDependency Model(TDM),thatcanhandlebothspatialdependenciesbetweennodesinasingle timesliceandtemporaldependenciesbetweennodesindifferenttimeslices,is presented. Itisshownthattheincreaseinoutputerrorprobabilitiesismorethan2folds,even foraslightincreasein value,therebyindicatingthevulnerabilityofsequential circuitstotransienterrors. Thecrucialstudyoferrorpropagationacrossdifferenttimeinstances,inasequentialcircuit,canbeperformedusingthismodel.Thisstudyisimportantto understanderrorbehaviorinsequentialcircuits. 6

PAGE 19

Itisshownthatthenumberoftimeslicesneededbythemodel,toconvergetoa nalaverageoutputerrorvalue,iscompletelydependentonthecircuitstructure. Theexibilityoftheerrormodelisshownbyincorporatingunequalgateerror probabilityvalues, 0and 1,tostudytheeffectof0 1and1 0errorson theoutputofacircuit.Givenagateoutputsignal, 0representstheprobability oferroroccurrencewhentheidealvalueofthesignalis'0',and 1representsthe probabilityoferroroccurrencewhentheidealvalueofthesignalis'1'. ThevalidityoftheerrormodelistestedthroughcomparisonwithcircuitsimulationsusingHSpiceandtheresultsshowedthatthehighestpercentagedifference oftheerrormodeloverHSpiceisonly6.25%,signifyingitsaccuracy. € Usingtheprobabilisticerrormodel,temporal,spatialandhybridredundancytechniques areperformed,toachieveerrormitigationindigitallogiccircuits. Efcienterrorreductionisachievedthrough selective redundancy,whichisestablishedbyapplyingredundancyonlytothemostinuentialinputcombinationsand themostsensitivenodes. Throughexperimentalresults,therelativebenetsofthetemporal,spatialand hybridredundancyschemesarepresentedandhybridredundancyisshowntobe thebestschemeforerrormitigationindigitallogiccircuits. Itisshownthatincreasingtheamountofredundancyresultsinbettererrormitigationinallthethreeschemes. Itisshownthattheerrormitigationpercentagefor15%temporalredundancy,is morethan10%forallcircuits,whilefor15%spatialredundancy,itismorethan 20%forallcircuitsandfor15%hybridredundancy,itismorethan30%forall circuits,therebyshowingthehighyieldofhybridredundancyscheme. 7

PAGE 20

Automobiles Communication Medicine Defense Accuracy Precision Safety Has to be Reliable Figure1.2.Scopeofapplication Delayandareapenaltiesintemporalandspatialredundanciesrespectivelyare presentedanditsisshownthattheareapenaltyismuchhigherthanthedelay penalty. 1.4ScopeofApplication DigitalVLSIcircuitsarewidelyusedincriticalandessentialapplicationslikeautomobiles,defense,medicineandcommunication.Theneedforreliablecomputationinthese circuitsareoftheutmostimportanceduetothenatureofitsapplications.VLSIcircuitsare usedintheautomobilebrakesystem,implantablebio-medicaldeviceslikepacemaker,aircraftcontrolsystemandmulti-functionalsmartphoneslikeiPhone.Thescaledcomputational devicesincurrentgenerationnano-domainVLSIcircuitshasimmenselyimproveditsapplicationspace.Theadventofsmartphonesandimplantablebio-medicalchipsaremadepossible primarilybythisscalingtrend.AtthesametimeVLSIcircuitsatnano-domainsufferfrom variousreliabilityissuesthatshouldbeaddressedduringthedesignprocess. 8

PAGE 21

Innano-domaindigitalVLSIcircuits,affectedbymultipleerrors,therecanbeonemaximumerrorthatcanevenbreakdowntheentiredevice.Whileprimarilyallofthecurrent reliabilitystudiesestimatetheoveralladverseeffectbyconsideringtheaverageofallerrors, estimatingtheworst-casemaximumerrorhasprovedtobetediousandcumbersome.Ourreliabilitymodel,presentedinthisdissertation,canefcientlyestimatethisworst-casemaximum errorandtheinputvectorassociatedwiththiserror,throughintelligentdiagnosticstudies. InICtesting,theusageofaprobabilisticerrormodelandtheinformationabouttheworstcaseinputvectorcanhelptoimprovetestingtechniqueslikescanchains,burn-intestand hierarchicaltesting.ScanchainsarewidelyusedinDesignforTest(DFT)methodologies forICtesting.Thebasicideaistoformachainofip-opsthataremadescan-ableand thedesiredtestpatterncanbeseriallyinsertedintotheip-opchain.Thetestpatternis appliedtothelogiccircuitsdrivenbytheip-opchainafterwhichthelogiccircuitoutputs canalsobecapturedintothesameordifferentip-opchainforserialshift-out.Insuch asetup,includingtheworst-caseinputvectorinthetestpatternscanspeedupthetesting process,sincethemosthazardousbehaviorofthecircuit-under-testcanbedetectedwiththe worst-caseinputvector.Burn-intestsareperformedtondoutdeviceswithinherentdefects ormanufacturingdefects[44].Thesedeviceswillgofaultywhensubjectedtohighstress.The ICissubjectedtolongtesttimeandstressconditions,suchasextremeVddandtemperatures, duringaburn-intest.Toaidtheburn-intest,aprobabilisticerrormodelthatcantargetand exerciseindividualdevicefaultmodeswouldhelptoexpeditethefailuremechanismsand toscreenforinherentfaultsinashortertesttime.Morespecically,theworstcaseinput vectorsgeneratedaccordingtoourmethodiswellsuitedforapplicationduringtheburnintest.Finally,inhierarchicaltesting,theentirecircuit-under-testisdividedintoseveral internalmoduleswherethesemodulescanbetestedindividually.Suchahierarchicaldivision reducesthesizeofcircuit-under-testfacilitatingrigorousprobabilisticerroranalysisandthe applicationofworstinputvectorstothetargetedinternalmodules. 9

PAGE 22

Thereliabilitymodelforerrorestimationinsequentialcircuits,presentedinthisdissertation,canbeusedtoperformefcientdiagnosticstudiesinessentialreal-timeapplicationslike computermemories.Inthesesequentialcircuits,foraxedinputvector,theintermediatesignalscangetstuckatawrongvalueduetothepresenceoferror.Thiscouldpropagateacross severaltimeinstancesandthisbehaviorcanhappentoanyinputvector.Suchdeterministic approachesprovidesinaccurateestimationoftheerrorbehaviorinsequentialcircuits.Our model,whichisaprobabilisticreliabilitymodel,takescareofthisdiscrepancybytreating bothinputandsignalspaceinaprobabilisticmanner,therebyensuringefcientdiagnostic studiesforreliability. Whilethethreeerrormitigationschemes,temporal,spatialandhybrid,presentedinthis dissertation,canbeusedforerroroptimizationinanynano-domainVLSIcircuit,thetradeoffstudiesbetweenthemcanprovideessentialapplication-specicinformationforcircuit designers.Iftheapplicationdemandslesserarea,thenmoreimportanceshouldbegiven totemporalredundancythanspatialredundancy.Iftheapplicationhashighprobabilityof erroroccurrenceinthesignalspacethantheinputspace,thenmoreimportanceshouldbe giventospatialredundancythantemporalredundancy.Thetrade-offstudiespresentedin thisdissertation,canprovideinformationrelatedtotheabovescenarios,whicharecrucialfor circuitdesign. 1.5Organization Thisdissertationisorganizedasfollows, € Chapter2providestherelatedresearchworksdoneintheeldofprobabilisticreliability analysisforVLSIcircuits. € Chapter3providesthefundamentaldesignconceptsoftheprobabilisticerrormodel. 10

PAGE 23

€ Chapter4explains,indetail,aboutthemodelingofmaximumerrorsinlogiccircuits usingaprobabilisticerrormodel. € Chapter5explains,indetail,aboutmodelingoferrorsinsequentialcircuitsusinga dynamictime-evolvingprobabilisticerrormodel. € Chapter6explains,indetail,aboutthetemporal,spatialandhybridredundancyschemes usedforerrormitigationindigitallogiccircuits. € Chapter7providestheconclusionandfuturedirectionsofthiswork. 11

PAGE 24

CHAPTER2 RELATEDWORK Innanometerlevelcircuits,duetodevicescaling,themostprevalentanddetrimentalerrors aresofterrorsthatarecausedmainlybyexternalparticleinteractionsandvariationsindevice andprocessparameters.WhiletheformerresultsinlocalizedfailureslikeSingleEventUpsets (SEUs),thelatterleadstomoreglobaldynamicerrors. 2.1SEUModeling ThemodelingofdevicefailuresduetoSEUsaredoneindifferentlevelsofdesignabstraction,likedevicelevel,circuitlevelandgatelevel[62,69,70,71,73,85,74].Initialworkon externalradiationinteractiononsemiconductorswasdoneasearlyas1967[62],inwhichthe authorsproposedonedimensionaldriftdiffusionmodelstostudytheradiationeffectsonsemiconductordevicesusedwidelyinspaceapplications.Thisworkwasfollowedbyanumber ofsignicantdevicelevelmodelsformemoryelements,usingnumericalsimulation[63,64]. Inordertohandlemorecomplexsituations,whichareintractablebynumericalsimulation models,analyticandempiricalmodelswereproposed[67].Thestudyofexternalparticle interactionwithsemiconductordevices,whichismoreofamultidimensionalphenomenon, wasenhancedthroughtheadventoftwodimensionalandthreedimensionalmodels[65,66], whichaccuratelymeasuredthechargeparticledriftanddiffusionmechanisms.Atthecircuit level,SEUmodelingisdonebyaddressingcircuitparameterslikesupplyvoltage,threshold voltageandclockperiod;andcircuitcharacteristicslikeelectricalmasking,logicalmask12

PAGE 25

ingandlatchingwindoweffects.SimulationbasedmodelslikeSEMM[69]andSERA[56] encapsulatesthesecircuitaspectstoprovidesofterrorrateanalysisindigitallogiccircuits. Whileoptimizationtechniquesusingdual-VddandgatesizingareusedtomodelSEU[70],its effectsoninterconnectsarealsomodeledattheplacementlevel[71],usingsimulatedannealing.Atthegatelevel,SEUmodelingisbasedprimarilyonthedetectionoftheprobabilityof erroroccurrenceatthegateoutputs.Logicalabstractiontoolslikebinarydecisiondiagrams areusedtoperformsofterrorrateanalysisinbothcombinational[72]andsequential[51]circuits,whileacompletelyprobabilisticmodelbasedonBayesiannetworkswasusedin[85]to detectSEUsindigitallogiccircuits.WhilepracticalexperimentslikeinjectingSEUsinchips usinglaserpulsestoverifyfaulttolerance[74,75]wereperformed,populartestingtechniques likebuilt-inself-testmechanism[76]werealsousedtostudysofterrors. 2.2DynamicErrorModeling Dynamicerrorsaretransientsofterrorscausedbytheuncontrollableandunpredictable uctuationsindeviceandprocessparametersduetoscaling.TheseglobalerrorscancoexistwiththelocalSEUsandstatichardfaults,andtheycanhappenrandomlyatanynodein thecircuit,makingthemuntraceable.Thebasicconceptofdynamicerrormodelingisthe assumptionthateverycircuitcomponentwillhaveanitepropensitytobeerroneous.Based onthisidea,researchersapproacheddynamicerrormodelingprobleminthreebroadcategories,calculationoferrorbounds,calculationofaverageerror,anderrorreductionthrough redundancy. 2.2.1CalculationofErrorBounds ThestudyofreliablecomputationusingunreliablecomponentswasinitiatedbyVonNeumann[1]whoshowedthaterroneouscomponentswithsomesmallerrorprobabilitycanpro13

PAGE 26

videreliableoutputsandthisispossibleonlywhentheerrorprobabilityofeachcomponent islessthan1 / 6.Inthisheuristicstudy,Neumannrepresentedthelogicgatesasautomatons whicharegovernedbylogicfunctions.Itwasstatedthattheprobabilityoferrorintheautomatonanditsoutputcannotexceed1 / 2,sincethesystemwillbecomeirrelevantatthat bound.Keepingthisasthebasicupperboundfortheprobabilityoferrorintheoutput,the errorprobabilityoftheautomatonwasstudiedthroughamajorityorgan,inwhichthreecopies ofthesameautomatonwerecreatedandthemajorityofthethreeoutputswasconsideredtrue. Thisarrangementwasproventoreducetheerrorprobabilityofthebasesystem,andthrough thisitwasshownthattheerrorprobabilityoftheautomatoncannotbe 1 / 6,sinceatthis upperboundthesystembecomesunsustainable. ThisworkwaslaterenhancedbyPippenger[3]whorealizedVonNeumann'smodelusing formulasforbooleanfunctions.Herethedigitallogiccomponentsarerealizedusingfunctions whosenumberofargumentsrelatetothenumberofinputsinthecomponent.Throughthis arrangement,itwasshownthatforafunctioncontrolledby k -arguments,theerrorprobability ofeachcomponentshouldbelessthan ( k Š 1 ) / 2 k toachievereliablecomputation.Through this,aninterestingresultwasshownfor3-inputcomponents,whoseerrorprobabilitybound forreliablecomputationwas1 / 3,whichisgreaterthantheVonNeumannboundof1 / 6, therebycreatingcuriosity.Thisworkwaslaterextendedbyusingnetworksinsteadofformulas torealizethereliabilitymodel[4].In[5],HajekandWellerusedtheconceptofformulasto showthatfor3-inputgatestheerrorprobabilityshouldbelessthan1 / 6,therebyreiterating VonNeumann'sbound.Laterthisworkwasextendedfor k -inputgates[6]where k waschosen tobeodd.Theauthorsclaimedthatsince k + 1inputgatescansimulate k inputgates,their modelcanbeeasilyusedtocomputeboundsforgateswithevennumberofinputs.Fora specicevencase,EvansandPippenger[7]showedthatthemaximumtolerablenoiselevel for2-inputNANDgateshouldbelessthan ( 3 Š 7 ) / 4 = 0 08856 14

PAGE 27

LaterthisresultwasreiteratedbyGaoetal.[8]for2-inputNANDgate,alongwithother resultsfor k -inputNANDgateandmajoritygate,usingbifurcationanalysisthatinvolves repeatediterationsonafunctionrelatingtothespeciccomputationalcomponent.TheprobabilityoftheoutputlineofaNANDgate,givenby Z ,wasassociatedwiththeprobabilitiesof theinputlines X and Y usingtheequation, Z =( 1 Š )( 1 Š XY )+ XY =( 1 Š )( 2 Š 1 ) XY (2.1) where istheprobabilityoferrorintheNANDgate.Inordertostudytheerrorbehavior,a networkofNANDgates,wheretheoutputofeachgateisconnectedtotheinputofatleast oneothergate,wascreatedandtheinputs X and Y areconsideredtobeequallyprobableto beatlogic'1'.Thecorrespondingequationforthisnetworkwaswrittenas, Xi + 1=( 1 Š )+( 2 Š 1 ) X2 i(2.2) Theinitialvalue X0wasarbitrarilychosenandaniterativeprocesswasperformedtoobtain consequent Xivalues.Afterthesolutionhasconverged,valuesfromthelastfewiterations areplottedagainstthecorresponding valuestoobtainthebi-modalgraphforbifurcation analysis.Thisbi-modalgraphclearlyshowedthatreliablecomputingusingerroneous2-input NANDgatesisnotpossiblewhenitserrorprobability = 0 08856 Whilethereexiststudiesofcircuit-specicboundsforcircuitcharacteristicslikeswitching activity[9],thestudyofcircuit-specicerrorboundswouldbehighlyinformativeanduseful fordesigninghigh-endcomputingmachines. 15

PAGE 28

2.2.2CalculationofAverageError Manyresearchersarecurrentlyfocusingoncomputingtheaverageerrorfromacircuit andalsoontheexpectederrortoconductreliability-redundancytrade-offstudies.In[45],a ProbabilisticTransferMatrix(PTM)basedmodelforreliabilitystudieswasproposed.Inthis methodeachcircuitsignalisrepresentedusingrandomvariablesandthefunctionalityofeach erroneousgateisrepresentedinamatrixformusingthePTMs(Fig.2.1.(a)).Eachgatein theunderlyingdigitalcircuitwasrepresentedbyanindividualPTM.Tocalculatetheerror probabilityofthecircuit,aPTMfortheentirecircuitisformedbymultiplyingtheindividual gatePTMs.Ifgates g1and g2areconnectedinseries,undertheconditionthatwhen g1gets aninput gI 1itresultsin g2givinganoutput gO 2,thecombinedPTMcanbewrittenas p ( gO 2| gI 1)=alljp ( gO 2| j ) p ( j | gI 1) (2.3) Ifgates g1and g2areconnectedinparallel,undertheconditionthatwhen g1getsaninput gI 1itresultsinoutput gO 1andwhen g2getsaninput gI 2itresultsinoutput gO 2,thecombinedPTM canbewrittenas p ( gO 2| gI 1)= p ( gO 2| gI 2) p ( gO 1| gI 1) (2.4) Thisisanexactmethodbutitiscomputationallyexpensive. AnapproximatemethodbasedonProbabilisticGateModel(PGM)isdiscussedbyHan etal.in[15].HerethePGMsareformedusingthesumofproductequationsgoverningthe functionalitybetweenaninputandanoutput.Foranygate,withanoutput Ziandwitherror probability ,itsPGMcanbewrittenas, Zi= Ei( 1 Š )+( 1 Š Ei) (2.5) 16

PAGE 29

01 X1 X2 X3 X4 (a) (b) Figure2.1.(a)ProbabilistictransfermatrixforerroneousNANDgatewitherrorprobability [45](b)Markovrandomeld[47] where Eiisthesumofproductequation.Fora2-inputANDgatewithinputs I1and I12, Ei= I1I2.Sothecorresponding Zicanbewrittenas, Zi=( I1I2)( 1 Š )+( 1 Š ( I1I2)) (2.6) AllthegatesinthecircuitwererepresentedwithindividualPGMsandtheoverallreliabilityof thecircuitwascalculatedbymultiplyingtheindividualgatereliabilities,whichwereassumed tobeindependent.ThisapproximatemodelwasprovedtobefasterthantheexactPTMmodel. AMarkovRandomField(MRF)basedprobabilisticmodelforreliabilitystudieswasproposedin[47],whichconcentratedmoreonharderrorsthansofterrors.Here,thecircuit signalswererepresentedasrandomvariablesinaMarkovrandomnetwork,whereeverynode isdependentonlywiththedirectlyconnectednodesthatarecalleditsneighbors(Fig.2.1.(b)). Givenasetofrandomvariables = { X1, Xn} formingaMarkovnetwork,theprobability 17

PAGE 30

ofanyrandomvariable, Xi,intheMarkovnetworkwasdescribedusingGibbsdistributionas follows, P ( Xi|{ Š Xi} )= 1 Z eŠ1 kTc Uc( X )(2.7) where Z isanormalizingconstantthatboundstheprobabilityvalueto[0,1], kT isthethermal energy, c iscliqueinthesetofcliques associatedwith Xiand Ucisthecliqueenergy.A typicalcliqueinthecircuitrepresentationofMarkovnetworkwillcompriseofthenodes representingtheinputsandoutputofagate.Inthissense,everygatewillhaveitsownclique andcliqueenergy.Thelogicgateswererepresentedusingtheirsumofproductstermandthe cliqueenergyforeachgatewasderived.Foraninverterwithinput x0andoutput x1,theclique energywasderivedasfollows, U = Š (( 1 Š x0) x1+ x0( 1 Š x1)) (2.8) = Š ( x1Š x0x1+ x0Š x0x1) = 2 x0x1Š x0Š x1Thenegativesigninthecliqueenergysigniedthedesignconditionthatcliqueenergiesof validstatesshouldbelowerthanthoseofinvalidstates.ThecorrespondingGibbsdistribution wasgivenas, P ( x0, x1)= 1 Z eŠ1 kT( 2 x0x1Š x0Š x1)(2.9) Theprobabilityofoutput x1= 1wascalculatedbymarginalizing P ( x0, x1) overallpossible valuesof x0. P ( x1)= 1 Zx0= { 0 1 }eŠ1 kT( 2 x0x1Š x0Š x1)(2.10) = ex 1 kT+ e( 1 Š x 1 ) kT 2 ( 1 + e1 kT) 18

PAGE 31

Likewise,theprobabilitydistributionofeverysignalinthecircuitwasrepresentedusingGibbs distribution.Correspondingprobabilitydistributionsfortheprimaryoutputsofthecircuitwas determinedbypropagatingthemarginalizeddistributionsacrossvariouscliquesusingbelief propagationalgorithm.Sincethesedistributionswereassociatedwiththermalenergy kT comprehensivereliabilitystudiesonnanoarchitecturesworkingundercriticalthermallimits, wereperformedbyalteringthe kT valuesandexaminingthesignalprobabilitydistributions. Although,thisworkprovidedsomemuchneededinsightonthermalbehaviorofnano-domain circuits,itwasperformedonerrorfreedevicesinsteadoferroneousones. Anotherworkonreliabilitystudiesusingprobabilisticmodelcheckingwasproposed in[58].Thismethodemployeddiscrete-timeMarkovChainsforprobabilisticmodelchecking.Inanothersignicantwork[99],theaverageoutputerrorindigitalcircuitswascalculated usingaprobabilisticreliabilitymodelthatemployedBayesianNetworks. 2.2.3ErrorReductionThroughRedundancy Theterm'redundancy'meanstheusageofmultipleredundantcopiesofthesameerroneouscomponentinordertotestorimproveitsreliability.VonNeumann,inhislegendary work,wasoneofthersttoproposeonesuchmethodologycalled multiplexing andheused ittostudythereliabilityofNANDlogic[1].Thismodelwascreatedbytakingmultiple copiesofthesameerroneousNANDgateandsupplyingtheminputsignalsrandomlyfrom variousbundlesofinputlines.Thissetupensureseffectiveduplicationofallpossiblesignals attheoutputs.Toobtainbettererrortolerance,twomoreNANDmultiplexingsetupsarecascadedwiththepreviousone.WhiletherstNANDmultiplexingsetupcalledthe"Executive Unit"performedthelogiccomputation,thefollowingtwounitscalledthe"RestorativeUnit" restoredthecorrectcomputationvalues.(Fig.2.2.) VonNeumannalsointroducedthewidelyusedredundancytechniquecalledTripleModularRedundancy(TMR)[1].InTMR,threecopiesofthesameerroneouslogiccomponent 19

PAGE 32

Randomizing Unit Randomizing Unit Randomizing Unit Executive UnitRestorative Unit Figure2.2.NANDmultiplexingschemeintroducedbyVonNeumann[1] wascreatedandthecorrectvaluewasdeterminedbyperformingthemajorityvotingoutofthe threeoutputs.Giventhreedifferentsignals X Y and Z ,themajorityvotingcouldbeperformed usingthefunction, XY + YZ + XZ .Usingthis,VonNeumannshowedsignicantreductionin theprobabilityoferroroccurrenceinlogicdevices.AsanextensionofTMR,amoregeneral modelcalledN-ModularRedundancy(NMR)[2]wasproposed,whereNischosentobeodd tofacilitatemajorityvoting.IfTMRwasusedtochoosethemajorityof2outof3inputs, NMRwasusedtochoosethemajorityof n + 1outof2 n + 1inputs.Also,givenanerroneous systemwitherrorprobability ,thereliabilityRthroughperformingTMRwasgivenby, R ( TMR )= 3+ 3 2( 1 Š ) (2.11) andthecorrespondingreliabilitythroughperformingNMRwasgivenby, R ( NMR )=ni = 0N ( N Š i ) i ( 1 Š )iN Š i(2.12) 20

PAGE 33

where N = 2 n + 1.Thesebasemodelsforhardwareredundancywerelaterappliedinessential applicationslikefault-tolerantmicroprocessordesign[10],andalsopavedthewaytoavariety oftechniquesforsoftware,dataandtimeredundancies.Apartfrombeingusedinthecircuit level,theywerealsousedindifferentlevelsofdesignabstractionslikein[73],whereSelective TMR(STMR)wasusedinFPGA'stominimizeerrorbehaviorduetoSEUs. FromtheinitialworksofVonNeumann,thestudyoffault-tolerantcomputationexpanded itsbarriersintoeldslikenano-computingarchitectures.AnexpansionoftheTMRtechnique calledCascadedTripleModularRedundancy(CTMR)[11]wasusedforreliabilitystudiesof nanochipsusingsingle-electrondevicesandquantumcellularautomatagates.WhileTMR isreferredtoassinglelevelredundancytechnique,CTMRisreferredtoasmultilevelredundancytechnique,whereoutputsfromthreedifferentTMRunitsweresuppliedtoanother majoritygatetoperformmultiplelevelsofvotinginordertoobtainbettererrorreduction.A generalizedCTMRtechnique,calledCascadedGeneralModularRedundancy(CGMR)was alsoproposedinthiswork[11]. In[12],thereliabilityofrecongurablearchitectureswasobtainedusingNANDmultiplexingtechnique.TheprocessorsinthearchitecturewereimplementedwithNANDmultiplexingsystemwitharedundancyfactorof3.Inthedesign,redundantsparecircuitrieswere alsodevelopedtoenhanceerrorcorrectionandminimizeerrordetection.In[13],majority multiplexingwasusedtoachievefault-tolerantdesignsfornanoarchitectures.Theyfurther enhancedthemajoritymultiplexingmodelforsmallinputerrorprobabilities,byremovingthe restorativestage,sinceeffectiverestorationispossiblewithoutthatstage.Arecentcomparativestudyofsomeofthesemethods[14],indicatesthata1000-foldredundancywouldbe requiredforadeviceerror(orfailure)rateof0.011. 1Notethatthisdoes not mean1outof100deviceswillfail,itindicatesthedeviceswillgenerateerroneous output1outof100times.21

PAGE 34

Reliability models for dynamic errors in VLSI circuits Reliability models for dynamic errors in combinational circuits Reliability models for dynamic errors in sequential circuits Error boundsAverage error Redundancy Maximum error Von Neumann [1] Pippenger[3] Feder[4] Hajeket al. [5] Evans et al. [6, 7] Gaoet al. [8] Marculescuet al. [9] Krishnaswamyet al. [45] Han et al. [15] Baharet al. [47] Norman et al. [58] Rejimonet al. [99] This work Depledge[10] Spagocciet al. [11] Han et al. [12] Roy et al. [13] This work This workVon Neumann [1] Mathuret al. [2] Figure2.3.SomeoftherelatedworksonreliabilitymodelsfordynamicerrorsinVLSIcircuits 2.3RelationtoState-of-the-Art Thisworkconcentratesonthefollowing, € Modeling dynamicerrors ,whichareglobal,asopposedtolocalizedSEUs.Thisis doneusingaprobabilisticerrormodel,whereefcienterrorincorporationinmultiple nodesispossible.Alsointhismodel,theerrorinjectionandprobabilityoferrorfor eachgatecanbemodiedeasily.Moreover,bothxedandvariablegateerrorscanbe accommodatedinasinglecircuitwithoutaffectingcomputationalcomplexity. € Estimationof maximumerrorasopposed toave rageerr or ,sinceforhigherdesign levelsitisimportanttoaccountformaximumerrorbehavior,especiallyifthisbehavior isfarworsethantheaveragecasebehavior.Thisestimationisperformedasadiagnostic studyinourerrormodel,usingtheMaximum aposteriori (MAP)hypothesis,wherethe 22

PAGE 35

outputnodesareforcedtobeerroneousandtheinformationispropagatedtowardsthe inputnodestoestimatethepossibleinputconguration,thatcanprovideamaximum errorintheoutput. € Estimationofoutputerrorin sequentialcircuitsasopposedtocombinationalcircuits sincethetransienterrorsthatoccursinaparticulartimeframe,ofasequentialcircuit, willpropagatetoconsecutivetimeframestherebymakingthedevicemorevulnerable.Thisestimationisperformedusinga minimal timeevolvingprobabilisticnetwork, namely,theTemporalDependencyModel(TDM),thatcanhandlebothspatialdependenciesbetweennodesinasingletimesliceandtemporaldependenciesbetweennodes indifferenttimeslices. € Designing temporal,spatialandhybridredundancyschemes ,usingourprobabilistic errormodel,toachieveerrormitigation.WeperformtemporalredundancyusingTriple TemporalRedundancy(TTR)techniqueandspatialredundancyusingCTMRtechnique. Alsoefcienterrorreductionisachievedthrough selective redundancy,byapplying redundancyonlytothemostinuentialinputcombinationsandthemostsensitivenodes. 23

PAGE 36

CHAPTER3 DESIGNFUNDAMENTALS 3.1ProbabilisticRepresentationofDigitalCircuits Adigitalcircuitisbasicallyanetworkofdigitalsignalsconnectedtogetherthroughgates whosefunctionalitiesarebasedonbooleanlogic.Thisnetworkcanberepresentedaccurately usingagraphicalmodel,wherethenodesrepresentthedigitalsignalsandtheedgesrepresent thebooleanlogicfunctionalityofthegates.Alsotheseedgesshouldbeunidirectional,since informationowindigitalcircuitsisunidirectionalfrominputtooutput.Inordertoassistefcientdiagnosticstudiesondigitalcircuits,theirgraphicalrepresentationcanbemodeledas probabilisticgraphicalmodelswhereeachnodeisarandomvariablewithtwopossiblestates, 'logic0'and'logic1'orsimply'0'and'1'.Torepresentthedigitalfunctionalities,eachrandomvariableshouldbeassociatedwithaprobabilitydistributionfunction(pdf).Considerthe exampleinFig3.1.,whereadigitalcircuitanditsprobabilisticgraphicalmodelaregiven.As discussed,eachnodefrom N 1to N 8isarandomvariablewhosevaluewillbeeither'0'or'1'. Inanetworkrepresentinganydigitalcircuit,thenodescorrespondingtotheprimaryinputs (i.e., N 1, N 2, N 3inourexample)willalwaysbecompletelyindependentandeveryother child nodewillbedependentonatleastone parent node.Thiskindofinterdependencybetween nodesgivesrisetoconditionalprobabilitydistribution,andsothepdf'sarerepresentedas ConditionalProbabilisticTables(CPTs).Fig3.1.providestheCPTsforallthenodes.Since N 1, N 2, N 3areprimaryinputs,theirpdf'scanbecontrolledbytheuser.Thechildnode N 4 isdependentonitsparentnodes N 1and N 2throughANDlogic,andthecorrespondingCPT 24

PAGE 37

N1N2N3 N4 N5 N6 N8 N7 N1N2N3 N4N5N6 N7 N8 N3 0 (or) 1 N1 N2N4 0 0 0 1 1 0 1 1 0 0 0 1 N1 N2P(N4=0 | N1,N2) P(N4=1 | N1,N2) 0 0 0 1 1 0 11 1 0 1 0 1 0 0 1 N2N5 0 1 1 0 N2P(N5=0 | N2) P(N5=1 | N2) 0 1 0 1 1 0 N2 N3N6 0 0 0 1 1 0 1 1 0 1 1 1 N2 N3P(N6=0 | N2,N3) P(N6=1 | N2,N3) 0 0 0 1 1 0 11 1 0 0 1 0 1 0 1 N4 N5N7 0 0 0 1 1 0 1 1 1 0 0 0 N4 N5P(N7=0 | N4,N5) P(N7=1 | N4,N5) 0 0 0 1 1 0 11 0 1 1 0 1 0 1 0 N5 N6N8 0 0 0 1 1 0 1 1 1 1 1 0 N5 N6P(N8=0 | N5,N6) P(N8=1 | N5,N6) 0 0 0 1 1 0 11 0 1 0 1 0 1 1 0 N2 0 (or) 1 N1 0 (or) 1 P(N3=0) P(N3=1) 0.5 0.5 P(N2=0) P(N2=1) 0.5 0.5 P(N1=0) P(N1=1) 0.5 0.5N1: N2: N3: N4: N5: N6: N7: N8: Digital Circuit Corresponding Probabilistic Graph model Digital signals governed by Boolean logi cCorresponding Conditional Probabilistic Tables (CPTs) for the graph Figure3.1.Representationofadigitalcircuitasaprobabilisticgraph 25

PAGE 38

shouldreectthisfunctionality.Thiscanbeachievedbyprovidingthepdfasfollows, P ( N 4 = 0 | N 1 N 2 )= 0if N 1=1and N 2=1 1otherwise P ( N 4 = 1 | N 1 N 2 )= 1if N 1=1and N 2=1 0otherwise (3.1) SimilarlytheCPTsfor N 5shouldobeyNOTlogic, N 6shouldobeyORlogic, N 7shouldobey NORlogic,and N 8shouldobeyNANDlogic. Oncethegraphmodelforadigitalcircuitisready,thenextobviousquestioniswhetherthe modelcapturesalltheinterdependenciesbetweenthenodes.Forexample,intheprobabilistic graphgiveninFig3.1.,thenode N 7isdirectlydependentonnodes N 4, N 5andindirectlydependentonnodes N 1, N 2.Also,node N 8isdirectlydependentonnodes N 5, N 6andindirectly dependentonnodes N 2, N 3.Ifweaddedgesrepresentingtheseindirectdependencies,then theresultingprobabilisticgraphwillbeasseeninFig3.2.(a).Butaretheseedgesnecessary? Inthegivendigitalcircuit,itcanbeseenthattherelationofthesignal N 7towardsthesignals N 1, N 2istakencarebythesignals N 4, N 5,i.e.anychangeinsignals N 1, N 2willbecapturedbytheirdirectoutputsignals N 4, N 5andthesamechangeswillbetranslatedtosignal N 7 through N 4and N 5.So,inthecorrespondingprobabilisticgraphmodel,wecancomfortably saythatnode N 7isindependentofnodes N 1, N 2givennodes N 4, N 5.Inasimilarfashion, wecanalsosaythatnode N 8isindependentofnodes N 2, N 3givennodes N 5, N 6.Inother words,wecansaythatalltheindirectdependenciesaretakencarebythedirectdependencies. Asaresultalltheextraedgesrepresentingindirectdependenciescanberemovedfromthe probabilisticgraphmodelgiveninFig3.2.(a)resultinginFig3.2.(b),whichissimilartothe initialmodelgiveninFig3.1.Thisrepresentationistheabsolute minimal ,inthesensethat 26

PAGE 39

N1N2N3 N4N5N6 N7 N8 N1N2N3 N4N5N6 N7 N8 Indirect dependencies Direct dependencies Not a minimal representationMinimal representation (a)(b) Figure3.2.Minimalrepresentationoftheprobabilisticgraph removingevenoneedgewillcollapsetheinterdependenciesbetweenthenodesandeventually resultsinanincompleterepresentationofthegivendigitalcircuit. Theprobabilisticgraphmodelcanberepresentedmathematicallyastheconditionalfactoringofajointprobabilitydistribution.Anyprobabilityfunction P ( y1, y2, yN) canbe writtenas, P ( y1, yN)= P ( yN| yN Š 1, yN Š 2, y1) P ( yN Š 1| yN Š 2, yN Š 3, y1) P ( y1) (3.2) where y1, y2, yNarerandomvariables.Thisexpressionholdsforanyorderingofthese randomvariables.FortheexampleprobabilisticgraphmodelinFig3.1.,thisprobability 27

PAGE 40

functioncanbewrittenas, P ( n 1 n 8 )= P ( n 8 | n 7 n 6 n 5 n 4 n 3 n 2 n 1 ) P ( n 7 | n 6 n 5 n 4 n 3 n 2 n 1 ) P ( n 6 | n 5 n 4 n 3 n 2 n 1 ) P ( n 5 | n 4 n 3 n 2 n 1 ) P ( n 4| n 3 n 2 n 1 ) P ( n 3 ) P ( n 2 ) P ( n 1 ) (3.3) where n 1 n 8aretherandomvariablesrepresentedbythenodes N 1 N 8respectively. Butthisequationdoesnotperfectlyrepresentthestructureofthecorrespondingprobabilistic graphmodel.Asdiscussedearlier,intheminimalrepresentationoftheprobabilisticgraph model,everychildnodeisconnectedonlytoitsparentnodes.SoEqn.3.2canberestructured asfollows, P ( y1, yN)=vP ( yv| Pa ( Yv)) (3.4) where Pa ( Yv) aretheparentsofthenode Yv,representingitsdirectcauses.Fortheexample probabilisticgraphmodelinFig3.1.,thisrestructuredjointprobabilityfunctioncanbewritten as, P ( n 1 n 8 )= P ( n 8 | n 6 n 5 ) P ( n 7 | n 5 n 4 ) P ( n 6 | n 3 n 2 ) P ( n 5 | n 2 ) P ( n 4 | n 2 n 1 ) P ( n 3 ) P ( n 2 ) P ( n 1 ) (3.5) 28

PAGE 41

3.2ModelingErrorinDigitalCircuits Anyunexpectedchangeinthelogicstateofthedigitalsignalsgivesrisetoerrorindigital circuits.Inordertounderstandandstudytheseerrors,weneedamodelthatcandetectthese unexpectedchanges.Onesuchwayofdoingthatistocomparetheerroneouscircuitwithits idealerror-freecounterpart.ConsiderthecircuitinFig3.3.(a),whereeachsignalotherthan theprimaryinputsignalscanbeerroneousthroughthefaultygates.Notethatweassumethat primaryinputsignalsareerror-free.Inordertocreatetheerrordetectionmodel,twocopiesof thecircuitiscreated,whereonecopyrepresentsthecircuitinitsnormalerroneousformand theothercopyrepresentsthecircuitinitsidealform.Whentheprimaryoutputsofthesetwo copiesarecompared,anyerroroccurrencewillbecomeevidentthroughthepossiblepresence ofdissimilarlogicstates.TheappropriatelogicgatetodothisoperationistheXORgate, whichproducesa'1'initsoutputwhenitsinputshavedissimilarlogicstatesandprovidesa'0' initsoutputwhenitsinputshavesimilarlogicstates.Fig3.3.(b)illustratestheerrordetection modelfordigitalcircuitsbasedontheabovementionedconcept. N 4e, N 5e, N 8earethe erroneoussignalsand N 4 N 5 N 8aretheidealsignals.Signal C 1givesthecomparison betweentheerroneousandidealprimaryoutputs N 7and N 7e;signal C 2givesthecomparison betweentheerroneousandidealprimaryoutputs N 8and N 8e.Itshouldbenotedthatthe idealerror-freeportionandthecomparatorportionarectitiousandusedonlyforstudying thegivencircuit. Thecorrespondingprobabilisticgraphmodelforerrordetectioncanbecreatedasshown inFig3.3.(d).Letssaythateachgateinthedigitalcircuithas %chanceofbeingfaulty. canbetermedasthe gateerrorprobability .Thiscanbeaccommodatedinthecorresponding 29

PAGE 42

N1N2N3 N4eN5eN6e N7eN8e N1N2N3 N4 N5 N6 N4eN5eN6e C1C2 N7N8N7eN8e Ideal Circuit Erroneous CircuitComparators Erroneous digital circuitCircuit model used to detect error in the erroneous digital circuit (b) (a) N1N2N3 N4eN5eN6eN7eN8e N1N2N3 N4N5N6 N7 N8 N4eN5eN6eN7eN8e C1 C2 Probabilistic graph model representing the erroneous digital circuit Probabilistic graph model representing the error detection modelIdeal Nodes Erroneous Nodes C 1 C2 Comparator Nodes (d) (c) Figure3.3.Errormodel 30

PAGE 43

N1N2N3 N4N5N6 N7 N8 N1 N2P(N4=0 | N1,N2) P(N4=1 | N1,N2) 0 0 0 1 1 0 1 1 1 0 1 0 1 0 0 1 N2P(N5=0 | N2) P(N5=1 | N2) 0 1 0 1 1 0 N2 N3P(N6=0 | N2,N3) P(N6=1 | N2,N3) 0 0 0 1 1 0 1 1 1 0 0 1 0 1 0 1 N4 N5P(N7=0 | N4,N5) P(N7=1 | N4,N5) 0 0 0 1 1 0 1 1 0 1 1 0 1 0 1 0 N5 N6P(N8=0 | N5,N6) P(N8=1 | N5,N6) 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0N4: N5: N6: N7: N8: Corresponding Conditional Probabilistic Tables (CPTs) N4eN5eN6eN7eN8e N1 N2P(N4e=0 | N1,N2) P(N4e=1 | N1,N2) 0 0 0 1 1 0 11 1111N2P(N5e=0 | N2) P(N5e=1 | N2) 0 1 11N2 N3P(N6e=0 | N2,N3) P(N6e=1 | N2,N3) 0 0 0 1 1 0 11 1111N4eN5eP(N7e=0 | N4e,N5e) P(N7e=1 | N4e,N5e) 0 0 0 1 1 0 11 1111N5eN6eP(N8e=0 | N5e,N6e) P(N8e=1 | N5e,N6e) 0 0 0 1 1 0 11 1111N4e: N5e: N6e: N7e: N8e: Corresponding Conditional Probabilistic Tables (CPTs) N 4 N 5 N 6 N 7 N 8 N 4 e N 5 e N 6 e N 7 e N 8 e Ideal Nodes Erroneous Nodes Figure3.4.Conditionalprobabilistictablesfortheidealanderroneousnodesintheerror model 31

PAGE 44

probabilisticgraphmodelbychangingtheCPTsasfollows, P ( N 4e= 0 | N 1 N 2 )= if N 1=1and N 2=1 1 Š otherwise P ( N 4e= 1 | N 1 N 2 )= 1 Š if N 1=1and N 2=1 otherwise (3.6) where N 4eistheerroneousoutputsignalofafaultyANDgateasshowninFig3.3.(a).Accordingly,thecorrespondingCPTsforrestoftheerroneousnodesareprovidedinFig3.4. 32

PAGE 45

CHAPTER4 MAXIMUMERRORMODELING Inthischapter,wepresentaprobabilisticmodeltostudythe maximum outputerrorover allpossibleinputspaceforagivenlogiccircuit.Wepresentamethodtondouttheworstcaseinputvector,i.e.,theinputvectorthathasthehighestprobabilitytogiveanerroratthe output.Intherststepofourmodel,weconvertthecircuitintoacorresponding edge-minimal probabilisticnetworkthatrepresentsthebasiclogicfunctionofthecircuitbyhandlingthe interdependenciesbetweenthesignalsusingrandomvariablesofinterestinacompositejoint probabilitydistributionfunction P ( y1, y2, yN) .Eachnodeinthisnetworkcorrespondstoa randomvariablerepresentingasignalinthedigitalcircuit,andeachedgecorrespondstothe logicgoverningtheconnectedsignals.Theindividualprobabilitydistributionforeachnode isgivenusingconditionalprobabilitytables. Fromthisprobabilisticnetworkweobtainourprobabilisticerrormodelthatconsistsof threeblocks,(i)idealerrorfreelogic,(ii)errorpronelogicwhereeverygatehasagateerror probability i.e.,eachgatecangowrongindividuallybyaprobabilisticfactor and(iii)a detectionunitthatusescomparatorstocomparetheerrorfreeanderroneousoutputs.Theerror pronelogicrepresentstherealtimecircuitundertest,whereastheideallogicandthedetection unitarectitiouselementsusedtostudythecircuit.Boththeideallogicanderrorpronelogic wouldbefedbytheprimaryinputs I .Wedenotealltheinternalnodes,bothintheerrorfree anderroneousportions,by X andthecomparatoroutputsas O .Thecomparatorsarebasedon XORlogicandhenceastate"1"wouldsignifyerrorattheoutput.Anevidenceset o iscreated byevidencingoneormoreofthevariablesinthecomparatorset O tostate"1"( P ( Oi= 1 )= 33

PAGE 46

1).ThenperformingMAPhypothesisontheprobabilisticerrormodelprovidestheworstcaseinputvector iMAPwhichgivesmax iP ( i o ) .Themaximumoutputerrorprobabilitycan beobtainedfrom P ( Oi= 1 ) afterinstantiatingtheinputnodesofprobabilisticerrormodelwith iMAPandinferencing.Theprocessisrepeatedforincreasing valuesandnallythe value thatmakesatleastoneoftheoutputsignalscompletelyrandom( P ( Oi= 0 )= 0 5 P ( Oi= 1 )= 0 5)istakenastheerrorboundforthegivencircuit. ItisobviousthatwecanarriveatMAPestimatebyenumeratingallpossibleinputinstantiationsandcomputethemaximum P ( i o ) byanyprobabilisticcomputingtool.Theattractive featureofthisMAPalgorithmliesoneliminatingasignicantpartoftheinputsearch-subtree basedonaneasilyavailableupper-boundof P ( i o ) byusingprobabilistictraversalofabinary Jointreewith Shenoy-Shafer algorithm[23,24].Theactualcomputationisdividedintotwo theoreticalcomponents.First,weconvertthecircuitstructureintoabinaryJointreeandemployShenoy-Shaferalgorithm,whichisatwo-passprobabilisticmessage-passingalgorithm, toobtainmultitudeofupperboundsof P ( i o ) withpartialinputinstantiations.Next,weconstructaBinarytreeoftheinputvectorspacewhereeachpathfromtherootnodetotheleaf noderepresentsaninputvector.Ateverynode,wetraversethesearchtreeiftheupperbound, obtainedbyShenoy-Shaferinferenceonthebinaryjointree,isgreaterthanthemaximum probabilityalreadyachieved;otherwiseweprunetheentiresub-tree.Experimentalresults onafewstandardbenchmarkshowthattheworst-caseerrorssignicantlydeviatefromthe averageonesandalsoprovidestighterboundsfortheonesthatusehomogeneousgate-type (c17withNAND-only).Salientfeaturesanddeliverablesareitemizedbelow: € Wehaveproposedamethodtocalculate maximum outputerrorusingaprobabilistic model.Throughexperimentalresults,weshowtheimportanceofmodelingmaximum outputerror.(Fig.4.10.) 34

PAGE 47

€ Givenacircuitwithaxedgateerrorprobability ,ourmodelcanprovidethemaximum outputerrorprobabilityandthe worst-case inputvector,whichcanbeveryusefultesting parameters. € Wepresentthecircuit-specicerrorboundsforfault-tolerantcomputationandweshow thatmaximumoutputerrorsprovideatighterbound. € Wehaveusedanefcientdesignframeworkthatemploysinferenceinbinaryjointrees usingShenoy-ShaferalgorithmtoperformMAPhypothesisaccurately. € Wegiveaprobabilisticerrormodel,whereefcienterrorincorporationispossible,for usefulreliabilitystudies.Usingourmodeltheerrorinjectionandprobabilityoferror foreachgatecanbemodiedeasily.Moreover,wecanaccommodatebothxedand variablegateerrorsinasinglecircuitwithoutaffectingcomputationalcomplexity. Wewouldlikethereaderstonotethatwewillberepresentingasetofvariablesbybold capitalletters,setofinstantiationsbyboldsmallletters,anysinglevariablebycapitalletters. Alsoprobabilityoftheevent Yi= yiwillbedenotedsimplyby P ( yi) orby P ( Yi= yi) 4.1MaximumaPosteriori(MAP)Estimate Letusdenetherandomvariablesinourprobabilisticerrormodelas Y = I X O composedofthethreedisjointsubsets I X and O where € I1, Ik I arethesetof k primaryinputs. € X1, Xm X arethe m internallogicsignalsforboththeerroneous(everygatehasa failureprobability )anderror-freeideallogicelements. € O1, On O arethe n comparatoroutputs,eachonesignifyingtheerrorinoneofthe primaryoutputsofthelogicblock. 35

PAGE 48

I1I2I3 X1 X2 X3 X4X5 X6 O1 I1 I2 I3 X1 X2 X3 X4 X5 X6 O1 Block 1Block 2 Block 3 Block 1Block 2 Block 3 (b)(c) X1 X2 X3 I1I2I3 (a) Block 1Error-free logicBlock 2Error-prone logicBlock 3Comparator logic Figure4.1.(a)Digitallogiccircuit(b)Errormodel(c)Probabilisticerrormodel € N = k + m + n isthetotalnumberofnetworkrandomvariables. Anyprimaryoutputnodecanbeforcedtobeerroneousbyxingthecorrespondingcomparatoroutputtologic"1" ,thatisprovidingan evidence o = { P ( Oi= 1 )= 1 } toacomparator output Oi.Givensomeevidence o ,theobjectiveoftheMaximum aposteriori estimateisto ndacompleteinstantiation iMAPofthevariablesin I thatgivesthefollowingjointprobability, MAP ( iMAP, o )= max iP ( i o ) (4.1) Theprobability MAP ( iMAP, o ) istermedasthe MAPprobability andthevariablesin I are termedas MAPvariables andtheinstantiation iMAPwhichgivesthemaximum P ( i o ) is termedasthe MAPinstantiation Forexample,considerFig4.1.IntheprobabilisticmodelshowninFig4.1.(c),wehave { I 1 I 2 I 3 } I ; { X 1 X 2 X 3 X 4 X 5 X 6 } X ; { O 1 } O X 3istheidealerror-freeprimary outputnodeand X 6isthecorrespondingerror-proneprimaryoutputnode.Givinganevidence o = { P ( O 1 = 1 )= 1 } to O 1indicatesthat X 6hasproducedanerroneousoutput.TheMAP hypothesisusesthisinformationandndstheinputinstantiation, iMAP,thatwouldgivethe 36

PAGE 49

maximum P ( i o ) .Thisindicatesthat iMAPisthemostprobableinputinstantiationthatwould giveanerrorintheerror-proneprimaryoutputsignal X 6.Inthiscase, iMAP= { I 1 = 0 I 2 = 0 I 3 = 0 } .Thismeansthattheinputinstantiation { I 1 = 0 I 2 = 0 I 3 = 0 } willmostprobably provideawrongoutput, X 6 = 1(sincethecorrectoutputis X 6 = 0). WearriveattheexactMaximum aposteriori (MAP)estimateusingthealgorithmsbyPark andDarwiche[29][30].ItisobviousthatwecouldarriveatMAPestimatebyenumerating allpossibleinputinstantiationsandcomputethemaximumoutputerror.Tomakeitmore efcient,ourMAPestimatesrelyoneliminatingsomepartoftheinputsearch-subtreebased onaneasilyavailableupper-boundofMAPprobabilitybyusingaprobabilistictraversalofa binaryJointreeusing Shenoy-Shafer algorithm[23,24].Theactualcomputationisdivided intotwotheoreticalcomponents. € First,weconvertthecircuitstructureintoabinaryJointreeandemployShenoy-Shafer algorithm,whichisatwo-passprobabilisticmessage-passingalgorithm,toobtainmultitudeofupperboundsofMAPprobabilitywithpartialinputinstantiations(discussed inSection.4.1.1).ThereaderfamiliarwithShenoy-Shaferalgorithmcanskiptheabove section.Toourknowledge,Shenoy-ShaferalgorithmisnotcommonlyusedinVLSI context,soweelaboratemoststepsofjointreecreation,two-passjointreetraversaland computationofupperboundswithpartialinputinstantiations. € Next,weconstructaBinarytreeoftheinputvectorspacewhereeachpathfromtheroot nodetotheleafnoderepresentsaninputvector.Ateverynode,wetraversethesearch treeiftheupperbound,obtainedbyShenoy-Shaferinferenceonthebinaryjointree,is greaterthanthemaximumprobabilityalreadyachieved;otherwiseweprunetheentire sub-tree.Thedepth-rsttraversalinthebinaryinputinstantiationtreeisdiscussedin Section.4.1.2wherewedetailthesearchprocess,pruningandheuristicsusedforbetter 37

PAGE 50

} 0 1 { } 1 { I IN} 0 2 0 1 { } 2 1 { I I I IN } 1 2 0 1 { } 2 1 { I I I IN} 0 3 0 2 0 1 { } 3 2 1 { I I I I I IN } 1 3 0 2 0 1 { } 3 2 1 { I I I I I IN } 0 3 1 2 0 1 { } 3 2 1 { I I I I I IN } 1 3 1 2 0 1 { } 3 2 1 { I I I I I IN } 1 1 { } 1 { I IN} 0 2 1 1 { } 2 1 { I I I IN } 1 2 1 1 { } 2 1 { I I I IN} 0 3 0 2 1 1 { } 3 2 1 { I I I I I IN } 1 3 0 2 1 1 { } 3 2 1 { I I I I I IN } 0 3 1 2 1 1 { } 3 2 1 { I I I I I IN } 1 3 1 2 1 1 { } 3 2 1 { I I I I I IN {} {}N Figure4.2.Searchtreewheredepthrstbranchandboundsearchperformed pruning.Notethatthepruningiskeytothesignicantlyimprovedefciencyofthe MAPestimates. 4.1.1CalculationofMAPUpperBoundsUsingShenoy-ShaferAlgorithm ToclearlyunderstandthevariousMAPprobabilitiesthatarecalculatedduringMAPhypothesis,letusseethebinarysearchtreeformedusingtheMAPvariables.Acompletesearch throughtheMAPvariablescanbeillustratedasshowninFig.4.2.whichgivesthecorrespondingsearchtreefortheprobabilisticerrormodelgiveninFig.4.1.(c).Inthissearch tree,therootnode N willhaveanemptyinstantiation;everyintermediatenode NiinterIinterwillbe associatedwithasubset IinterofMAPvariables I andthecorrespondingpartialinstantiation iinter;andeveryleafnode Ni Iwillbeassociatedwiththeentireset I andthecorresponding completeinstantiation i .Alsoeachnodewillhave v childrenwhere v isthenumberofvalues orstatesthatcanbeassignedtoeachvariable Ii.Sincewearedealingwithdigitalsignals, everynodeinthesearchtreewillhavetwochildren.SincetheMAPvariablesrepresentthe primaryinputsignalsofthegivendigitalcircuit,onepathfromtheroottotheleafnodeofthis searchtreegivesoneinputvectorchoice.InFig.4.2.,atnode N01 { I 1 I 2 }, Iinter= { I 1 I 2 } and iinter= { I 1 = 0 I 2 = 1 } .ThebasicideaofthesearchprocessistondtheMAPprobability MAP ( i o ) byndingtheupperboundsoftheintermediateMAPprobabilities MAP ( iinter, o ) 38

PAGE 51

MAPhypothesiscanbecategorizedintotwoportions.Therstportioninvolvesnding intermediate upperbounds ofMAPprobability, MAP ( iinter, o ) ,andthesecondportioninvolves improving theseboundstoarriveattheexactMAPsolution, MAP ( iMAP, o ) .Thesetwo portionsareintertwinedandperformedalternativelytoeffectivelyimproveontheintermediateMAPupperbounds.Theseupperboundsandnalsolutionarecalculatedbyperforming inferenceontheprobabilisticerrormodelusingShenoy-Shaferalgorithm[23,24]. Shenoy-Shaferalgorithmisbasedonlocalcomputationmechanism.Theprobabilitydistributionsofthelocallyconnectedvariablesarepropagatedtogetthejointprobabilitydistributionoftheentirenetworkfromwhichanyindividualorjointprobabilitydistributionscan becalculated.TheShenoy-shaferalgorithminvolvesthefollowingcrucialinformationand calculations. € Valuations :Thevaluationsarefunctionsbasedonthepriorprobabilitiesofthevariables inthenetwork.Avaluationforavariable Yicanbegivenas Yi= P ( Yi, Pa ( Yi)) where Pa ( Yi) aretheparentsof Yi.Forvariableswithoutparents,thevaluationscanbegiven as Yi= P ( Yi) .ThesevaluationscanbederivedfromtheCPTsasshowninTable4.1. € Combination :Combinationisapointwisemultiplicationmechanismconductedtocombinetheinformationprovidedbytheoperandfunctions.Acombinationoftwogiven functions faand fbcanbewrittenas fa b= fa fb,where a and b aresetofvariables. Table4.2.providesanexample. € Marginalization :Givenafunction fa b,where a and b aresetofvariables,marginalizingover b providesafunctionof a andthatcanbegivenas fa= fmar ( b ) a b.Thisprocess providesthemarginalsofasinglevariableorasetofvariables.Generallytheprocess canbedonebysummingormaximizingorminimizingoverthe marginalizingvariables in b .Normallythesummationoperatorisusedtocalculatetheprobabilitydistributions. InMAPhypothesisbothsummationandmaximizationoperatorsareinvolved. 39

PAGE 52

Table4.1.ValuationsofthevariablesderivedfromcorrespondingCPTs CPTValuation Error-freeAND P ( X 1 = 1 | I 1 I 2 ) P ( I 2 = 0 )= 1 P ( I 2 = 1 )= 1 P ( I 1 = 0 )= 1 0 0 P ( I 1 = 1 )= 1 0 1 Error-freeAND X 1 I 1 I 2 X 1 000 1 001 1 010 1 011 0 100 0 101 0 110 0 111 1 Error-proneAND P ( X 4 = 1 | I 1 I 2 ) P ( I 2 = 0 )= 1 P ( I 2 = 1 )= 1 P ( I 1 = 0 )= 1 P ( I 1 = 1 )= 1 1Error-proneAND X 4 I 1 I 2 X 4 000 1001 1010 1011 100 101 110 111 1Input P ( I 1 = 0 ) 0.5 P ( I 1 = 1 ) 0.5 Input I 1 I 1 0 0.5 1 0.5 40

PAGE 53

Table4.2.Combination xy fxy 00 1 01 1 10 1 11 0 yz fyz 00 1 01 0 10 0 11 0 xyz fxyz= fxy fyz 000 1x1 001 1x0 010 1x0 011 1x0 100 1x1 101 1x0 110 0x0 111 0x0 I1I2 X1X2 O1 Block 1 Block 2 Block 3 I1 I2 X1 X2 O1 I1 I2 X1 X2 O1 I2 X1 X2 O1 I1 I2 X1 X2 I1 I2 X1 X2 ( O1)mar(O1) I1 I2 X2 I1 I2 X2 (( O1)mar(O1) X1)mar(X1) I1 I2 I1 I2 ((( O1)mar(O1) X1)mar(X1) X2)mar(X2) I1 I1 (((( O1)mar(O1) X1)mar(X1) X2)mar(X2) I2)mar(I2)Valuation NetworkEliminating O1Eliminating X1 Eliminating X2Eliminating I2 (a)(b) Figure4.3.Illustrationofthefusionalgorithm 41

PAGE 54

ThecomputationalschemeoftheShenoy-Shaferalgorithmisbasedon fusion algorithm proposedbyShenoyin[25].Givenaprobabilisticnetwork,likeourprobabilisticerrormodel inFig.4.3.(a),the fusion methodcanbeexplainedasfollows, € ThevaluationsprovidedareassociatedwiththecorrespondingvariablesformingavaluationnetworkasshowninFig.4.3.(b).Inourexample,thevaluationsare I 1for { I 1 } I 2for { I 2 } X 1for { X 1 I 1 I 2 } X 2for { X 2 I 1 I 2 } O 1for { O 1 X 1 X 2 } € Avariable Yi Y forwhichtheprobabilitydistributionhastobefoundoutisselected. Inourexampleletussayweselect I 1. € Chooseanarbitraryvariableeliminationorder.Fortheexamplenetworkletuschoose theorderasO1,X1,X2,I2.Whenavariable Yiiseliminated,thefunctionsassociated withthatvariable f1 Yi, fj Yiarecombinedandtheresultingfunctionismarginalized over Yi.Itcanberepresentedas, ( f1 Yi fj Yi)mar ( Yi).Thisfunctionisthenassociated withtheneighborsof Yi.Thisprocessisrepeateduntilallthevariablesintheelimination orderareremoved.Fig.4.3.illustratesthefusionprocess. Eliminating O 1yieldsthefunction ( O 1)mar ( O 1 )associatedtoneighbors X 1 X 2. Eliminating X 1yieldsthefunction (( O 1)mar ( O 1 ) X 1)mar ( X 1 )associatedtoneighbors X 2 I 1 I 2. Eliminating X 2yieldsthefunction ((( O 1)mar ( O 1 ) X 1)mar ( X 1 ) X 2)mar ( X 2 )associatedtoneighbors I 1 I 2. Eliminating I 2yieldsthefunction (((( O 1)mar ( O 1 ) X 1)mar ( X 1 ) X 2)mar ( X 2 ) I 2)mar ( I 2 )associatedtoneighbor I 1. Accordingtoatheorempresentedin[24],combiningthefunctionsassociatedwith I 1yieldstheprobabilitydistributionof I 1. I 1 (((( O 1)mar ( O 1 ) X 1)mar ( X 1 ) 42

PAGE 55

X 2)mar ( X 2 ) I 2)mar ( I 2 )=( I 1 O 1 X 1 X 2 I 2)mar ( O 1 X 1 X 2 I 2 )=ProbabilitydistributionofI1[24].Notethatthefunction I 1 O 1 X 1 X 2 I 2representsthejointprobabilityoftheentireprobabilisticerrormodel. € Theaboveprocessisrepeatedforalltheothervariablesindividually. Toperformefcientcomputation,anadditionalundirectednetworkcalled jointree is formedfromtheoriginalprobabilisticnetwork.Thenodesofthejointreecontains clusters of nodesfromtheoriginalprobabilisticnetwork.Theinformationoflocallyconnectedvariables, providedthroughvaluations,ispropagatedinthejointreeby messagepassing mechanism. ToincreasethecomputationalefciencyoftheShenoy-Shaferalgorithm,aspecialkindof jointreenamed binaryjointree isused.Inabinaryjointree,everynodeisconnectedtono morethanthreeneighbors.Inthisframeworkonlytwofunctionsarecombinedataninstance, therebyreducingthecomputationalcomplexity.Wewillrstexplainthemethodtoconstruct abinaryjointree,asproposedbyShenoyin[24],andthenwewillexplaintheinference schemeusingmessagepassingmechanism. Thebinaryjointreeisconstructedusingthefusionalgorithm.Theconstructionofbinary jointreecanbeexplainedasfollows, € Tobeginwithwehave, = Asetthatcontainsallthevariablesfromtheoriginalprobabilisticnetwork. Inourexample, = { I 1 I 2 X 1 X 2 O 1 } = Asetthatcontainsthesubsetsofvariables,thatshouldbepresentinthe binaryjointree.i.e.,thesubsetsthatdenotethevaluationsandthesubsetswhose probabilitydistributionsareneededtobecalculated.Inourexample,letussay thatweneedtocalculatetheindividualprobabilitydistributionsofallthevariables.Thenwehave, = {{ I1 } { I2 } { X1,I1,I2 } { X2,I1,I2 } { O1,X1,X2 } { X1 } { X2 } { O1 }} 43

PAGE 56

O1,X1,X2 O1 Choose O1 O1,X1,X2 X1,X2 O 1,X1,X 2 O 1 C hoose O 1 O 1,X1,X 2 X 1,X 2 O1,X1,X2,I2,I1} = {{I1},{I2},{X1,I1,I2},{X2,I1,I 2},{O1,X1,X2},{X1},{X2},{O1}} = {{O1,X1,X2},{O1}} i= {O1,X1,X2} j= {O1} k= {O1,X1,X2} O1= O1-{ i, j} U { k} = {{O1,X1,X2},{O1}} -{{O1,X1 ,X2},{O1}} U {{O1,X1,X2}} = {{O1,X1,X2}} i= {O1,X1,X2} j= {O1,X1,X2} –O1 = {X1,X2} O1,X1,X2 O1 O1,X1,X2 = U { j} = {{I1},{I2},{X1,I1,I2},{X2,I1,I2},{ O1,X1,X2},{X1},{X2},{O1}} U {X1,X2} {{I1},{I2},{X1,I1,I2},{X2,I1,I2},{O1 ,X1,X2},{X1},{X2},{O1}} U {X1,X2} = {{I1},{I2},{X1,I1,I2},{X2, I1,I2},{X1},{X2},{X1,X2}} = {O1,X1,X2,I2,I1} = {X1,X2,I2,I1} Figure4.4.Partialillustrationofbinaryjointreeconstructionmethodfortherstchosen variable N= Asetthatcontainsthenodesofthebinaryjointreeanditisinitiallynull. E= Asetthatcontainstheedgesofthebinaryjointreeanditisinitiallynull. Wealsoneedanorderinwhichwecanchoosethevariablestoformthebinaryjoin tree.Inourexample,sincethegoalistondouttheprobabilitydistributionofI1, thisordershouldreectthevariableeliminationorder(O1,X1,X2,I2,I1)usedin fusionalgorithm. €1:while | | > 1 do2:Chooseavariable Y 3:Y= { i | Y i}4:while | Y| > 1 do5:Choose i Yand j Ysuchthat || i j|||| m n|| forall m, n Y6:k= i j44

PAGE 57

O1,X1,X2 O1 O1,X1,X2,I2,I1} ={{I1},{I2},{X1,I1,I2},{X2,I1,I 2},{O1,X1,X2},{X1},{X2},{O1}} Choose O1 O1,X1,X2 X1,X2 X1,X2,I2,I1} ={{I1},{I2},{X1,I1,I2},{X2, I1,I2}, {X1},{X2},{X1,X2}} Choose X1 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 X2,I2,I1} ={{I1},{I2},{X2,I1,I2},{X2},{X2,I1,I2}} Choose X2 X2,I1,I2 X2,I1,I2 X2 X2,I1,I2 X2,I1,I2 I1,I2 O1,X1,X2 O1 O1,X1,X2 X1,X2 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 X2,I1,I2 O1,X1,X2 O1 O1,X1,X2 X1,X2 I2,I1} ={{I1},{I2},{I1,I2}} Choose I2 X2,I1,I2 X2 X2,I1,I2 X2,I1,I2 I1,I2 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 X2,I1,I2 O1,X1,X2 O1 O1,X1,X2 X1,X2 O 1,X1,X 2 O 1 O1,X1,X2,I2,I1 } ={{ I1 } { I2 } { X1,I1,I2 } { X2,I1,I2 } { O1,X1,X2 } { X1 } { X2 } { O1 }} C hoose O 1 O 1,X1,X 2 X 1,X 2 X 1,X2,I2,I1 } ={{ I1 } { I2 } { X1,I1,I2 } { X2,I1,I2 } { X1 } { X2 } { X1,X2 }} C hoose X1 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 X2 ,I1,I 2 O 1,X1,X 2 O 1 O 1,X1,X 2 X 1,X 2 X 2,I2,I1 } ={{ I1 } { I2 } { X2,I1,I2 } { X2 } { X2,I1,I2 }} C hoose X2 X2 ,I1,I 2 X2 X2 ,I1,I 2 X2 ,I1,I 2 I 1,I 2 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 X2 ,I1,I 2 O 1,X1,X 2 O 1 O 1,X1,X 2 X 1,X 2 I2 I1,I2 I1 I 2,I1 } ={{ I1 } { I2 } { I1,I2 }} C hoose I2 X2 ,I1,I 2 X2 X2 ,I1,I 2 X2 ,I1,I 2 I 1,I 2 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 X2 ,I1,I 2 O 1,X1,X 2 O 1 O 1,X1,X 2 X 1,X 2 I2 I 1,I 2 I1 I1} ={{I1},{I1}} Choose I1 X2,I1,I2 X2 X2,I1,I2 X2,I1,I2 I1,I2 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 X2,I1,I2 O1,X1,X2 O1 O1,X1,X2 X1,X2 I2 I1,I2 I1 I 1 } ={{ I1 } { I1 }} C hoose I1 X2 ,I1,I 2 X2 X2 ,I1,I 2 X2 ,I1,I 2 I 1,I 2 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 X2 ,I1,I 2 O 1,X1,X 2 O 1 O 1,X1,X 2 X 1,X 2 I2 I 1,I 2 I1 I1 I1 X2,I1,I2 X2 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 O1 O1,X1,X2 I2 I1,I2 X2 ,I1,I 2 X2 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 O 1 O 1,X1,X 2 I2 I 1,I 2 I1 Cluster C1 Cluster C2 Cluster C4 Cluster C3 Cluster C5 Cluster C7 Cluster C9 Cluster C11 Cluster C6 Cluster C8 Cluster C10Binary Join tree Figure4.5.Completeillustrationofbinaryjointreeconstructionmethod 45

PAGE 58

7:N=N{ i}{ j}{ k}8:E=E{{ i, k} { j, k}}9:Y= YŠ{ i, j}10:Y= Y{ k}11:endwhile12:if | | > 1 then13:Take iwhere i= Y14:j= iŠ{ Y }15:N=N{ i}{ j}16:E=E{{ i, j}}17: = { j}18:endif19: = Š{ i | Y i}20: = Š{ Y }21:endwhile € Thenalstructurewillhavesomeduplicateclusters.Twoneighboringduplicateclusters canbemergedintoone,ifthemergednodedoesnotenduphavingmorethanthree neighbors.Aftermergingtheduplicatenodeswegetthebinaryjointree. Fig.4.4.andFig.4.5.illustratethebinaryjointreeconstructionmethodfortheprobabilisticerrormodelinFig.4.3.(a).Fig.4.4.explainsaportionoftheconstructionmethodfor therstchosenvariable,hereitis O 1.Fig.4.5.illustratestheentiremethod.Notethat,even thoughthebinaryjointreeisconstructedwithaspecicvariableeliminationorderfornding outtheprobabilitydistributionofI1,itcanbeusedtondouttheprobabilitydistributionsof othervariablestoo. 46

PAGE 59

X2,I1,I2 X2 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 O1 O1,X1,X2 I2 I1,I2 I1 C1 C2 C4 C3 C5 C7 C9 C11 C6 C8 C10 MC1 C2 MC2 C3= (MC1 C2 O1)mar(O1) MC4 C3 MC3 C5= MC2 C3 MC4 C3O1 MC6 C5= X1X1 MC5 C7= (MC6 C5 MC3 C5)mar(X1) MC8 C7 MC7 C9= (MC8 C7 MC5 C7)mar(X2) X2I2MC10 C9= I2 MC9 C11= (MC10 C9 MC7 C9)mar(I2)I1 direction of message passingRoot X2,I1,I2 X2 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 O1 O1,X1,X2 I2 I1,I2 I1 C1 C2 C4 C3 C5 C7 C9 C11 C6 C8 C10 MC3 C2= MC4 C3 MC5 C3 MC4 C3 MC5 C3= (MC6 C5 MC7 C5)mar(I1,I2)O1 MC6 C5= X1X1 MC7 C5= MC8 C7 MC9 C7 MC8 C7 MC9 C7= MC10 C9 MC11 C9 X2I2MC10 C9= I2 MC11 C9= I1I1 Root MC2 C1= (MC3 C2)mar(X1,X2) X2,I1,I2 X2 X1 X1,X2 X1,X2,I1,I2 X1,I1,I2 O1 O1,X1,X2 I2 I1,I2 I1 C1 C2 C4 C3C5C7C9C11 C6C8 C10 X2,I1,I2 I1,I2 C7C9 MC7 C9= (MC8 C7 MC5 C7)mar(X2) MC9 C7= MC10 C9 MC11 C9 X2 ,I1,I 2 X2 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 O 1 O 1,X1,X 2 I2 I 1,I 2 I1 C 1 C2 C 4 C3 C5 C 7 C9 C 11 C6 C8 C 1 0 M C 1 C2 M C2 C3 = ( M C 1 C2 O 1 ) m ar ( O1 ) M C 4 C3 M C3 C5 = M C2 C3 M C 4 C3 O 1 M C6 C5 = X1 X1 M C5 C7 = ( M C6 C5 M C3 C5 ) m ar ( X1 ) M C8 C7 M C 7 C 9 = ( M C8 C 7 M C5 C 7 ) m ar ( X2 ) X2 I2 M C 1 0 C 9 = I 2 M C9 C11 = ( M C 1 0 C9 M C 7 C9 ) m ar ( I2 ) I 1 Roo t X2 ,I1,I 2 X2 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 O 1 O 1,X1,X 2 I2 I 1,I 2 I1 C 1 C2 C 4 C3 C5 C 7 C9 C 11 C6 C8 C 1 0 M C3 C2 = M C 4 C3 M C5 C3 M C 4 C3 M C5 C3 = ( M C6 C5 M C 7 C5 ) m ar ( I1,I2 ) O 1 M C6 C5 = X1 X1 M C 7 C5 = M C8 C 7 M C9 C 7 M C8 C7 M C9 C7 = M C 1 0 C9 M C 11 C9 X2 I 2 M C 1 0 C 9 = I 2 M C 11 C 9 = I 1 I 1 Roo t M C2 C1 = ( M C3 C2 ) m ar ( X1,X2 ) X2 X1 X 1,X 2 X 1,X 2 ,I1,I 2 X 1,I1,I 2 O 1 O 1,X1,X 2 I2 I1 C 1 C2 C 4 C3 C5 C 11 C6 C8 C 1 0 X2 ,I1,I 2 I 1,I 2 C 7 C9 X2 ,I1,I 2 I 1,I 2 C 7 C9 M C 7 C 9 = ( M C8 C 7 M C5 C 7 ) m ar ( X2 ) M C9 C7 = M C 1 0 C9 M C 11 C9 (a)(b) (c) Figure4.6.(a)MessagepassingwithclusterC11asroot(b)MessagepassingwithclusterC1 asroot(c)Messagestoragemechanism 47

PAGE 60

Inferenceinabinaryjointreeisperformedusingmessagepassingmechanism.Initially allthevaluationsareassociatedtotheappropriateclusters.Inourexample,atFig.4.6.,the valuationsareassociatedtothesefollowingclusters, € I 1associatedtocluster C11 € I 2associatedtocluster C10 € X 1associatedtocluster C6 € X 2associatedtocluster C7 € O 1associatedtocluster C2 Amessagepassedfromcluster b ,containingavariableset B ,tocluster c ,containingavariable set C canbegivenas, Mb c=( ba = cMa b)mar ( B \ C )(4.2) where bisthevaluationassociatedwithcluster b .Ifcluster b isnotassociatedwithany valuation,thenthisfunctionisomittedfromtheequation.Themessagefromcluster b can besenttocluster c onlyaftercluster b receivesmessagesfromallitsneighborsotherthan c Theresultingfunctionismarginalizedoverthevariablesincluster b thatarenotincluster c .Tocalculatetheprobabilitydistributionofavariable Yi,theclusterhavingthatvariable aloneistakenasrootandthemessagesarepassedtowardsthisroot.Probabilityof Yi, P ( Yi) iscalculatedattheroot.Inourexample,atFig.4.6.(a),tondtheprobabilitydistribution ofI1,thecluster C11 ischosenastheroot.Themessagesfromalltheleafclustersare senttowards C11 andnallytheprobabilitydistributionofI1canbecalculatedas, P ( I 1 )= MC9 C11 I 1.Alsonotethatthe orderofthemarginalizingvariables isO1,X1,X2,I2which exactlyreectstheeliminationorderusedtoconstructthebinaryjointree.Aswementioned before,thisbinaryjointreecanbeusedtocalculateprobabilitydistributionsofothervariables 48

PAGE 61

also.Inourexample,atFig.4.6.(b),tondouttheprobabilitydistributionofO1,cluster C1 ischosenasrootandthemessagesfromtheleafclustersarepassedtowards C1 andnally theprobabilitydistributionofO1canbecalculatedas, P ( O 1 )= MC2 C1.Notethatthe order ofthemarginalizingvariables changestoI1,I2,X1,X2.Wecanalsocalculatejointprobability distributionsofthesetofvariablesthatformsaclusterinthebinaryjointree.Inourexample, thejointprobability P ( I 1 I 2 ) canbecalculatedbyassigningcluster C9 asroot.Inthisfashion, theprobabilitydistributionsofanyindividualvariableorasetofvariablescanbecalculated bychoosingappropriaterootclusterandsendingthemessagestowardsthisroot.During theseoperationssomeofthecalculationsarenotmodiedandsoperformingthemagainwill proveinefcient.Usingthebinaryjointreestructurethesecalculationscanbestoredthereby eliminatingtheredundantrecalculation.Inthebinaryjointree,betweenanytwoclusters b and c ,boththemessages Mb cand Mc barestored.Fig.4.6.(c)illustratesthisphenomenon usingourexample. Ifanevidenceset e isprovided,thentheadditionalvaluations { eYi| Yi e } providedby theevidenceshastobeassociatedwiththeappropriateclusters.Avaluation eYiforavariable Yicanbeassociatedwithaclusterhaving Yialone.Inourexample,ifthevariableO1is evidenced,thenthecorrespondingvaluation eO 1canbeassociatedwithcluster C1 .While ndingtheprobabilitydistributionofavariable Yi,theinferencemechanism(asexplained before)withanevidenceset e willgivetheprobability P ( Yi, e ) insteadof P ( Yi) .From P ( Yi, e ) P ( e ) iscalculatedas, P ( e )= YiP ( Yi, e ) .Calculationoftheprobabilityofevidence P ( e ) is crucialforMAPcalculation. TheMAPprobabilities MAP ( iinter, o ) arecalculatedbyperforminginferenceonthebinary jointreewithevidences iinterand o .Letussaythatwehaveanevidenceset e = { iinter, o } then MAP ( iinter, o )= P ( e ) .Foragivenpartialinstantiation iinter, MAP ( iinter, o ) iscalculated bymaximizingovertheMAPvariableswhicharenotevidenced.Thiscalculationcanbedone bymodifyingthemessagepassingschemetoaccommodatemaximizationoverunevidenced 49

PAGE 62

MAPvariables.SoforMAPcalculation,themarginalizationoperationinvolvesbothmaximizationandsummationfunctions.Themaximizationisperformedovertheunevidenced MAPvariablesin I andthesummationisperformedoveralltheothervariablesin X and O ForMAP,amessagepassedfromcluster b tocluster c iscalculatedas, Mb c= max{ Ib}{ B \ C }{ Xb Ob}{ B \ C }ba = cMa b(4.3) where Ib I \ Iinter, Xb X Ob O and { Ib, Xb, Ob} B Herethemostimportantaspectisthatthemaximizationandsummationoperatorsin Eqn.4.3arenon-commutative. [XmaxIP ]( y ) [ maxIXP ]( y ) (4.4) Soduringmessagepassinginthebinaryjointree,the validorderofthemarginalizingvariables orthe validvariableeliminationorder shouldhavethesummationvariablesin X and O beforethemaximizationvariablesin I .Amessagepassthroughaninvalidvariableeliminationordercanresultinabadupperboundthatisstuckatalocalmaximaanditeventually resultsintheeliminationofsomeprobableinstantiationsoftheMAPvariables I duringthe searchprocess.Butaninvalideliminationordercanprovideusaninitialupperboundofthe MAPprobabilitytostartwith.Theclosertheinvalidvariableeliminationordertothevalid one,thetighterwillbetheupperbound.Inthebinaryjointree,anyclustercanbechosenas roottogetthisinitialupperbound.Forexample,inFig.4.6.(b)choosingcluster C1 asroot resultsinaninvalidvariableeliminationorder(I1,I2,X1,X2)andmessagepasstowardsthis rootcangivetheinitialupperbound.Alsoitisessentialtouseavalidvariableelimination orderduringtheconstructionofthebinaryjointreesothatthereisatleastonepaththatcan provideagoodupperbound. 50

PAGE 63

X1,X2,X6 X3 X3,X6 X1,X2,X3,X6 X3,X1,X2 O1 O1,X3,X6 C1 X6 X1,X2,X4,X5,X6 X6,X4,X5 X1,X2,X4,X5 X1 X1,X2,X4,X5,I1,I2 X1,I1,I2 X2,X4,X5,I1,I2 X2 X2,X4,X5,I1,I2,I3 X2,I2,I3 X4,X5,I1,I2,I3 X4 X4,X5,I1,I2,I3 X4,I1,I2 X5,I1,I2,I3 X5 X5,I1,I2,I3 X5,I2,I3 I1,I2,I3 I3 I1,I2 I2 I1 C2 C4C3 C5 C6 C8C7 C9 C10 C12C11 C13 C14 C15 C16 C17 C18 C20C19 C21 C22 C23C24 C25 C26 C28 C27 C29 C31 C30 ProbabilityRoot Cluster MAP({}, o ) C2 MAP({I1=0}, o ), MAP({I1=1}, o ) C31 MAP({I1=0,I2=0}, o ), MAP({I1=0,I2=1}, o ) C30 MAP({I1=0,I2=0,I3=0}, o ), MAP({I1=0,I2=0,I3=1}, o ) C28 Figure4.7.BinaryjointreefortheprobabilisticerrormodelinFig.4.1.(c) 51

PAGE 64

Fig.4.7.givesthecorrespondingbinaryjointree,fortheprobabilisticerrormodelgiven inFig.4.1.(c),constructedwithavalidvariableeliminationorder(O1,X3,X6,X1,X2,X4, X5,I3,I2,I1).Inthismodel,therearethreeMAPvariablesI1,I2,I3.TheMAPhypothesis onthismodelresultsin iMAP= { I 1 = 0 I 2 = 0 I 3 = 0 } Theinitialupperbound MAP ( {} o ) iscalculatedbychoosingcluster C2 asrootandpassingmessagestowards C2 .Asspeciedearlierthisupperboundcanbecalculatedwithany clusterasroot.With C2 asroot,anupperboundwillmostcertainlybeobtainedsincethe variableeliminationorder(I3,I2,I1,X4,X5,X1,X2,X3,X6)isaninvalidone.Butsince themaximizationvariablesareattheverybeginningoftheorder,having C2 asrootwillyield alooserupperbound.Instead,if C16 ischosenasroot,theeliminationorder(O1,X3,X6, X1,I3,X4,X5,I2,I1)willbeclosertoavalidorder.Soamuchtighterupperboundcanbe achieved.Tocalculateanintermediateupperbound MAP ( iinter, o ) ,theMAPvariable Iinewly addedtoform iinterisrecognizedandtheclusterhavingthevariable Iialoneisselectedas root.Bydoingthisavalideliminationorderandproperupperboundcanbeachieved.For example,tocalculatetheintermediateupperbound MAP ( { I 1 = 0 } o ) wheretheinstantiation { I 1 = 0 } isnewlyaddedtotheinitiallyemptyset iinter,avalideliminationordershouldhave themaximizationvariablesI2,I3attheend.Toachievethis,cluster C31 ischosenasroot therebyyieldingavalideliminationorder(O1,X3,X6,X1,X2,X4,X5,I3,I2). 4.1.2CalculationoftheExactMAPSolution ThecalculationoftheexactMAPsolution MAP ( iMAP, o ) canbeexplainedasfollows, € Tostartwithwehavethefollowing, Iinter subsetofMAPvariables I .Initiallyempty. iinter partialinstantiationsetofMAPvariables Iinter.Initiallyempty. id1, id2 partialinstantiationsetsusedtostore iinter.Initiallyempty. 52

PAGE 65

} 0 1 { } 1 { I IN} 0 2 0 1 { } 2 1 { I I I IN } 1 2 0 1 { } 2 1 { I I I IN} 0 3 0 2 0 1 { } 3 2 1 { I I I I I IN } 1 3 0 2 0 1 { } 3 2 1 { I I I I I IN {} {}NIgnored {} {}N } 0 1 { } 1 { I IN } 1 1 { } 1 { I IN{} {}N } 0 1 { } 1 { I IN} 0 2 0 1 { } 2 1 { I I I IN } 1 2 0 1 { } 2 1 { I I I IN } 1 1 { } 1 { I IN{} {}NIgnoredIinter = {} iinter= {} Iinter = {I1} id 1= {I1=0} Iinter = {I1} id 1= {I1=1} MAP({I1=0}, o ) > MAP({I1=1}, o ) MAP( iMAP, o ) = MAP({I1=0}, o ) iinter= {{I1=0}} Choose I1 Iinter = {I1,I2} id 1= {I1=0,I2=0} Choose I2 Iinter = {I1,I2} id 1= {I1=0,I2=1} MAP({I1=0,I2=0}, o ) > MAP({I1=0,I2=1}, o ) MAP( iMAP, o ) = MAP({I1=0,I2=0}, o ) iinter= {{I1=0,I2=0}} Choose I3 } 1 1 { } 1 { I INIgnoredMAP({I1=0,I2=0,I3=0}, o ) > MAP({I1=0,I2=1,I3=1}, o ) MAP( iMAP, o ) = MAP({I1=0,I2=0,I3=0}, o ) iinter= {{I1=0,I2=0,I3=0}} = iMAPIinter = {I1,I2,I3} id 1= {I1=0,I2=0,I3=0} Iinter = {I1,I2,I3} id 1= {I1=0,I2=0,I3=1} } 0 1 { } 1 { I I N } 1 1 { } 1 { I I N {} {} N I i nt er = {I1 } i d 1 = {I1=0 } I i nt er = {I1 } i d 1 = {I1=1 } MAP({I1=0}, o ) > MAP({I1=1}, o ) MAP ( i MAP o ) = MAP({I1=0}, o ) i i nt er = {{I1=0} } C hoose I1 } 0 1 { } 1 { I I N } 0 2 0 1 { } 2 1 { I I I I N } 1 2 0 1 { } 2 1 { I I I I N } 0 3 0 2 0 1 { } 3 2 1 { I I I I I I N } 1 3 0 2 0 1 { } 3 2 1 { I I I I I I N {} {} N Ig nore d C hoose I 3 } 1 1 { } 1 { I I N Ig nore d MAP({I1=0,I2=0,I3=0}, o ) > MAP({I1=0,I2=1,I3=1}, o ) MAP ( i MAP o ) = MAP({I1=0,I2=0,I3=0}, o ) i i nt er = {{I1=0,I2=0,I3=0}} = i MAP I i nt er = {I1,I2,I3 } i d 1 = {I1=0,I2=0,I3=0 } I i nt er = {I1,I2,I3 } i d 1 = {I1=0,I2=0,I3=1 } } 0 1 { } 1 { I I N } 0 2 0 1 { } 2 1 { I I I I N } 1 2 0 1 { } 2 1 { I I I I N } 1 1 { } 1 { I I N {} {} N Ig nore d I i nt er = {I1,I2 } i d 1 = {I1=0,I2=0 } C hoose I 2 I i nt er = {I1,I2 } i d 1 = {I1=0,I2=1 } MAP({I1=0,I2=0}, o ) > MAP({I1=0,I2=1}, o ) MAP ( i MAP o ) = MAP({I1=0,I2=0}, o ) i i nt er = {{I1=0,I2=0} } {} {} N I i nt er = { } i i nt er = { } Figure4.8.SearchprocessforMAPcomputation iMAP MAPinstantiation.Atrst, iMAP= iinit,where iinitiscalculatedby sequentially initializingtheMAPvariablestoaparticularinstantiationandperforminglocal taboosearch aroundtheneighborsofthatinstantiation[30]. MAP ( iMAP, o ) MAPprobability.Initially MAP ( iMAP, o )= MAP ( iinit, o ) calculatedbyinferencingtheprobabilisticerrormodel. v ( Ii) numberofvaluesorstatesthatcanbeassignedtoavariable Ii.Sincewe aredealingwithdigitalsignals, v ( Ii)= 2forall i €1:Calculate MAP ( iinter, o ) ./* ThisistheinitialupperboundofMAPprobability. */2:if MAP ( iinter, o ) MAP ( iMAP, o ) then 53

PAGE 66

3:MAP ( iMAP, o )= MAP ( iinter, o )4:else5:MAP ( iMAP, o )= MAP ( iMAP, o )6:iMAP= iMAP7:endif8:while | I | > 0 do9:Chooseavariable Ii I .10:Iinter= Iinter{ Ii} .11:while v ( Ii) > 0 do12:Chooseavalue iv ( Ii)of Ii13:id1= iinter{ Ii= iv ( Ii)} .14:Calculate MAP ( id1, o ) frombinaryjointree.15:if MAP ( id1, o ) MAP ( iMAP, o ) then16:MAP ( iMAP, o )= MAP ( id1, o )17:id2= id118:else19:MAP ( iMAP, o )= MAP ( iMAP, o )20:endif21:v ( Ii)= v ( Ii) Š 122:endwhile23:iinter= id224:if | iinter| = 0 then25:gotoline2926:endif27:I = I Š{ Ii}28:endwhile 54

PAGE 67

29:if | iinter| = 0 then30:iMAP= iMAP31:else32:iMAP= iinter33:endif Thepruningofthesearchprocessishandledinlines11-23.AfterchoosingaMAPvariable Ii,thepartialinstantiationset iinterisupdatedbyaddingthebestinstantiation Ii= iv ( Ii)therebyignoringtheotherinstantiationsof Ii.ThiscanbeseeninFig.4.8.whichillustratesthe searchprocessforMAPcomputationusingtheprobabilisticerrormodelgiveninFig.4.1.(c) asexample. 4.1.3CalculatingtheMaximumOutputErrorProbability Accordingtoourerrormodel,theMAPvariablesrepresenttheprimaryinputsignalsof theunderlyingdigitallogiccircuit.SoafterMAPhypothesis,wewillhavetheinputvector whichhasthehighestprobabilitytogiveanerrorontheoutput.Therandomvariables I that representtheprimaryinputsignalsaretheninstantiatedwith iMAPandinferenced.Sothe evidencesetforthisinferencecalculationwillbe e = { iMAP} .Theoutputerrorprobabilityis obtainedbyobservingtheprobabilitydistributionsofthecomparatorlogicvariables O .After inference,theprobabilitydistribution P ( Oi, e ) willbeobtained.Fromthis P ( Oi| e ) canbe obtainedas, P ( Oi| e )=P ( Oi, e ) P ( e )=P ( Oi, e ) O iP ( Oi, e ).Finallythemaximumoutputerrorprobabilityis givenby,maxiP ( Oi= 1 | e ) 4.1.4ComputationalComplexityofMAPEstimate ThetimecomplexityofMAPdependsonthatofthedepthrstbranchandboundsearch onthe inputinstantiationsearchtree andalsoonthatof inferenceinbinaryjointree .The 55

PAGE 68

formerdependsonthenumberofMAPvariablesandthenumberofstatesassignedtoeach variable.Inourcaseeachvariableisassignedtwostatesandsothetimecomplexitycan begivenas O ( 2k) where k isthenumberofMAPvariables.Thisistheworstcasetime complexityassumingthatthesearchtreeisnotpruned.Ifthesearchtreeispruned,thenthe timecomplexitywillbe < O ( 2k) Thetimecomplexityofinferenceinthebinaryjointreedependsonthenumberofcliques q andthesize Z ofthebiggestclique.Itcanberepresentedas q 2Zandtheworstcasetimecomplexitycanbegivenas O ( 2Z) .Inanygivenprobabilisticmodelwith N variables,representing ajointprobability P ( x1, xN) ,thecorrespondingjointreewillhave Z < N always[27].Also dependingontheunderlyingcircuitstructure,thejointreeofthecorrespondingprobabilistic errormodelcanhave Z << N or Z closeto N ,whichinturndeterminesthetimecomplexity. Sinceforeverypassinthesearchtreeinferencehastobeperformedinthejointreetoget theupperboundofMAPprobability,theworstcasetimecomplexityforMAPcanbegiven as O ( 2k + Z) .ThespacecomplexityofMAPdependsonthenumberofMAPvariablesforthe searchtreeandonthenumberofvariables N intheprobabilisticerrormodelandthesizeof thelargestclique.Itcanbegivenby2k+ N 2Z. 4.2ExperimentalResults TheexperimentsareperformedonISCAS85andMCNCbenchmarkcircuits.ThecomputingdeviceusedisaSunserverwith8CPUswhereeachCPUconsistsof1.5GHzUltraSPARC IVprocessorwithatleast32GBofRAM. 4.2.1ExperimentalProcedureforCalculatingMaximumOutputErrorProbability Ourmaingoalistoprovidethemaximumoutputerrorprobabilitiesfordifferentgateerror probabilities .Togetthemaximumoutputerrorprobabilitieseveryoutputsignalofacircuit 56

PAGE 69

Take the probabilistic model for a given digital logic circuit Provide evidence P(or= 0) = 0 and P(or= 1) = 1 to out put orwhere r = 1,…,n Perform MAP hypothesis Obtain the output probability P(or) = max P(oi= 1) where i= 1,…,n.i Obtain the input instantiation i andinstantiate the input variables in the probabilistic model with i and perform inference. Is r = n Obtain the probabilityP(o) = max P(or= 1) where r = 1,…,n.r No Yes Figure4.9.Flowchartdescribingtheexperimentalsetupandprocess hastobeexaminedthroughMAPestimation,whichisperformedthroughalgorithmsprovided in[31].TheexperimentalprocedureisillustratedasaowchartinFig.4.9.Thestepsareas follows, € First,anevidencehastobeprovidedtooneofthecomparatoroutputsignalvariables inset O suchthat P ( Oi= 0 )= 0and P ( Oi= 1 )= 1.Recallthatthesevariableshavea probabilitydistributionbasedonXORlogicandsogivingevidencelikethisissimilar toforcingtheoutputtobewrong. € Thecomparatoroutputsareevidencedindividuallyandthecorrespondinginputinstantiations i areobtainedbyperformingMAP. € Thentheprimaryinputvariablesintheprobabilisticerrormodelareinstantiatedwith eachinstantiation i andinferencedtogettheoutputprobabilities. 57

PAGE 70

Table4.3.Worst-caseinputvectorsfromMAP Circuits No.of Inputvector Gateerror Inputs probability c17 5 01111 0.005-0.2 max at 8 00010011 0.005-0.025 11101000 0.03-0.05 11110001 0.055-0.2 voter 12 000100110110 0.01-0.19 111011100010 0.2 € P ( Oi= 1 ) isnotedfromallthecomparatoroutputsforeach i andthemaximumvalue givesthemaximumoutputerrorprobability. € Theentireoperationisrepeatedfordifferent values. 4.2.2Worst-caseInputVectors Table4.3.givestheworst-caseinputvectorsgotfromMAPi.e.,theinputvectorsthat givesmaximumoutputerrorprobability.Thenotableresultsareasfollows, € In max flat and voter theworst-caseinputvectorsfromMAPchangeswith ,whilein c 17itdoesnotchange. € Intherange { 0.005-0.2 } for max flat hasthreedifferentworst-caseinputvectors while voter hastwo. € Itimpliesthattheseworst-caseinputvectorsnotonlydependonthecircuitstructurebut coulddynamicallychangewith .Thiscouldbeofconcernfordesignersastheworstcaseinputsmightchangeaftergateerrorprobabilitiesreduceduetoerrormitigation schemes.Hence,explicitMAPcomputationwouldbenecessarytojudgethemaximum errorprobabilitiesandworst-casevectorsaftereveryredundancyschemesareapplied. 58

PAGE 71

4.2.3Circuit-SpecicErrorBoundsforFault-TolerantComputation Theerrorboundforacircuitcanbeobtainedbycalculatingthegateerrorprobability thatdrivestheoutputerrorprobabilityofatleastoneoutputtoahardboundbeyondwhich theoutputdoesnotdependontheinputsignalsorthecircuitstructure.Whentheoutputerror probabilityreaches0 5 ( 50% ) ,itessentiallymeansthattheoutputsignalbehavesasanonfunctionalrandomnumbergeneratorforatleastoneinputvectorandso0 5canbetreatedas ahardbound. Fig.4.10.givestheerrorboundsforvariousbenchmarkcircuits.Italsoshowsthecomparisonbetweenmaximumandaverageoutputerrorprobabilitieswithreferencetothechangein gateerrorprobability .Thesegraphsareobtainedbyperformingtheexperimentfordifferent valuesrangingfrom0 005to0 1.Theaverageerrorprobabilitiesareobtainedfromour previousworkbyRejimonetal.[86].Thenotableresultsareasfollows, € The c 17circuitconsistsof6NANDgates.TheerrorboundforeachNANDgatein c 17 is = 0 1055,whichisgreaterthantheconventionalerrorboundforNANDgate,which is0 08856[7,8].TheerrorboundofthesameNANDgatein voter circuit(contains 10NANDgates,16NOTgates,8NORgates,15ORgatesand10ANDgates)is = 0 0292,whichislesserthantheconventionalerrorbound.Thisindicatesthatthe errorboundforanindividual NANDgateplacedinacircuit canbedependentonthe circuitstructure.Thesamecanbetrueforallotherlogics. € Themaximumoutputerrorprobabilitiesaremuchlargerthanaverageoutputerrorprobabilities,therebyreachingthehardboundforcomparativelylowervaluesof ,makingthemaverycrucialdesignparametertoachievetightererrorbounds.Onlyfor alu 4and malu 4,theaverageoutputerrorprobabilityreachesthehardboundwithin = 0 1 ( = 0 095 foralu 4 = 0 08 formalu 4 ) ,whilethemaximumoutputerrorprob59

PAGE 72

0 0.1 0.2 0.3 0.4 0.5 0.6 00.020.040.060.080.10.12Gate error probability Output error probability Max Avg c17= 0.1055 0 0.1 0.2 0.3 0.4 0.5 0.6 00.020.040.060.080.10.12Gate error probability Output error probability Max Avg max_flat = 0.069 (a)(b) 0 0.1 0.2 0.3 0.4 0.5 0.6 00.020.040.060.080.10.12Gate error probability Output error probability Max Avg voter = 0.0292 0 0.1 0.2 0.3 0.4 0.5 0.6 00.020.040.060.080.10.12Gate error probability Output error probability Max Avg pc = 0.0407 (c)(d) 0 0.1 0.2 0.3 0.4 0.5 0.6 00.020.040.060.080.10.12Gate error probability Output error probability Max Avg count = 0.071 0 0.1 0.2 0.3 0.4 0.5 0.6 00.020.040.060.080.10.12Gate error probability Output error probability Max Avg alu4 = 0.0255 (e)(f) 0 0.1 0.2 0.3 0.4 0.5 0.6 00.020.040.060.080.10.12Gate error probability Output error probability Max Avg malu4 = 0.0235 (g) Figure4.10.Circuit-specicerrorboundalongwithcomparisonbetweenmaximumandaverageoutputerrorprobabilitiesfor(a) c 17,(b) max flat ,(c) voter ,(d) pc ,(e) count ,(f) alu 4, (g) malu 4 60

PAGE 73

Table4.4.RuntimesforMAPcomputation Circuit No.of No.of Time Inputs Gates c17 5 6 0.047s max at 8 29 0.110s voter 12 59 0.641s pc 27 103 225.297s count 35 144 36.610s alu4 14 63 58.626s malu4 14 92 588.702s abilitiesforthesecircuitsreachthehardboundforfarlessergateerrorprobabilities ( = 0 0255 foralu 4 = 0 0235 formalu 4). € Whiletheerrorboundsforallthecircuits,except c 17,arelessthan0 08 ( 8% ) ,theerror boundsforcircuitslike voter alu 4and malu 4areevenlessthan0 03 ( 3% ) makingthem highlyvulnerabletoerrors. Table4.4.tabulatestheruntimeforMAPcomputation.Theruntimedoesnotchange signicantlyfordifferent valuesandsoweprovideonlyoneruntimewhichcorresponds toall values.ThisisexpectedasMAPcomplexity(discussedinSec.4.1.4)isdetermined bynumberofinputs,andnumberofvariablesinthelargestcliquewhichinturndependson thecircuitcomplexity.Ithastobenotedthat,eventhough pc haslessnumberofinputsthan count ,ittakesmuchmoretimetoperformMAPestimateduetoitscomplexcircuitstructure. 4.2.4ValidationUsingHSpiceSimulator UsingexternalvoltagesourceserrorcanbeinducedinanysignalanditcanbemodeledusingHSpice[43].InourHSpicemodelwehaveinducederror,usingexternalvoltagesources, ineverygate'soutput.Considersignal Ofistheoriginalerrorfreeoutputsignalandthesignal Opistheerrorproneoutputsignaland E isthe piecewiselinear (PWL)voltagesource 61

PAGE 74

Table4.5.Comparisonbetweenmaximumerrorprobabilitiesachievedfromtheproposed modelandtheHSpicesimulatorat = 0 05 Circuit Model HSpice %diffoverHSpice c17 0.312 0.315 0.95 max at 0.457 0.460 0.65 voter 0.573 0.570 0.53 pc 0.533 0.536 0.56 count 0.492 0.486 1.23 alu4 0.517 0.523 1.15 malu4 0.587 0.594 1.18 thatinduceserror.Thebasicideaisthatthesignal Opisdependentonthesignal Ofandthe voltage E .Anychangeofvoltagein E willbereectedin Op.If E = 0 v ,then Op= Of,and if E = Vdd ( supplyvoltage ) ,then Op = Of,therebyinducingerror.Thedatapointsforthe PWLvoltagesource E areprovidedbycomputationsonaniteautomatawhichmodelsthe underlyingerrorpronecircuitwhereindividualgateshaveagateerrorprobability Notethat,foraninputvectorofthegivencircuit,asinglesimulationruninHSpiceis notenoughtovalidatetheresultsfromourprobabilisticmodel.Alsothecircuithastobe simulatedforeachandeverypossibleinputvectorstondouttheworst-caseone.Foragiven circuit, theHSpicesimulationsareconductedforallpossibleinputvectors,whereforeach vectorthecircuitissimulatedfor 1 millionrunsandthecomparatornodesaresampled. From thisdatathemaximumoutputerrorprobabilityandthecorrespondingworst-caseinputvector areobtained. Table4.5.givesthecomparisonbetweenmaximumerrorprobabilitiesachievedfromthe proposedmodelandtheHSpicesimulatorat = 0 05.Thenotableresultsareasfollows, € ThesimulationresultsfromHSpicealmostexactlycoincideswiththoseofourerror modelforallcircuits. € Thehighest%differenceofourerrormodeloverHSpiceisjust1 23%. 62

PAGE 75

0 0.05 0.1 0.15 0.2 0.25 0.3 0.350 00 0 0 0 00 0 1 0 00 1 0 0 00 1 1 0 01 0 0 0 01 0 1 0 01 1 0 0 01 1 1 0 10 0 0 0 10 0 1 0 10 1 0 0 10 1 1 0 11 0 0 0 11 0 1 0 11 1 0 0 11 1 1 1 00 0 0 1 00 0 1 1 00 1 0 1 00 1 1 1 01 0 0 1 01 0 1 1 01 1 0 1 01 1 1 1 10 0 0 110 0 1 1 10 1 0 1 10 1 1 1 11 0 0 1 11 0 1 1 11 1 0 1 11 1 1Input vectorOutput error probability Model HSpice Figure4.11.Outputerrorprobabilitiesfortheentireinputvectorspacewithgateerrorprobability = 0 05for c 17 Fig.4.11.givestheoutputerrorprobabilitiesfortheentireinputvectorspaceof c 17with gateerrorprobability = 0 05.Thenotableresultsareasfollows, € Itcanbeclearlyseenthattheresultsfrom both theprobabilisticerrormodelandHSpice simulationsshowthat01111givesthemaximumoutputerrorprobability. Fig.4.12.(a)and(b)givetheoutputerrorprobabilities,obtainedfromtheprobabilistic errormodelandHSpicerespectively,for max flat withgateerrorprobability = 0 05.In ordertoshowthat max flat haslargenumberofinputvectorscapableofgeneratingmaximum outputerror,weplotoutputerrorprobabilities (( )+( )) ,where isthemeanofoutput errorprobabilitiesand isthestandarddeviation.Thenotableresultsareasfollows, € ItisclearlyevidentfromFig.4.12.(a)that max flat hasaconsiderablylargeamount ofinputvectorscapableofgeneratingoutputerrortherebymakingiterrorsensitive. EquivalentHSpiceresultsfromFig.4.12.(b)conrmsthisaspect. 63

PAGE 76

(a) (b) Figure4.12.(a)Outputerrorprobabilities ( + ) ,calculatedfromprobabilisticerrormodel, withgateerrorprobability = 0 05for max flat (b)CorrespondingHSpicecalculations 64

PAGE 77

0.45 0.5 i ty 0.35 0.4 o babil i Max Avg Ti 02 0.25 0.3 r ror pr o Ti me 0.1 0.15 0 2 u tput e r 0 0.05O u 0.0050.05variable(0.005 0.05)Gate error p robabilit y Figure4.13.Comparisonbetweentheaverageandmaximumoutputerrorprobabilityandrun timefor =0.005, =0.05andvariable rangingfrom0.005-0.05for max flat € ItisclearlyevidentthattheresultsfromprobabilisticerrormodelandHSpiceshowthe sameworst-caseinputvector,11101000,thatisobtainedthroughMAPhypothesis. 4.2.5ResultswithMultiple Apartfromincorporatingasinglegateerrorprobability inallgatesofthegivencircuit, ourmodelalsosupportstoincorporatedifferent valuesfordifferentgatesinthegivencircuit. Ideallythese valueshastocomefromthedevicevariabilitiesandmanufacturingdefects. Eachgateinacircuitwillhavean valueselectedinrandomfromaxedrange,say0.0050.05. WehavepresentedtheresultinFig.4.13.for max flat .Herewecomparetheaverageand maximumoutputerrorprobabilityandruntimewith =0.005, =0.05andvariable ranging from0.005-0.05.Thenotableresultsareasfollows, € Itcanbeseenthattheoutputerrorprobabilitiesforvariable areclosertothosefor =0.05thanfor =0.005implicatingthattheoutputsareaffectedmorebytheerroneous gateswith =0.05. 65

PAGE 78

€ Theruntimeforallthethreecasesarealmostequal,therebyindicatingtheefciency ofourmodel. 4.3Discussion Wehaveproposedaprobabilisticmodelthatcomputestheexactmaximumoutputerror probabilitiesforalogiccircuitandmappedthisproblemasmaximum aposteriori hypothesis oftheunderlyingjointprobabilitydistributionfunctionofthenetwork.Wehavedemonstrated ourmodelwithstandardISCASandMCNCbenchmarksandprovidedthemaximumoutput errorprobabilityandthecorrespondingworst-caseinputvector.Wehavealsostudiedthe circuit-specicerrorboundsforfault-tolerantcomputing.Theresultsclearlyshowthatthe errorboundsarehighlydependentoncircuitstructureandcomputationofmaximumoutput errorisessentialtoattainatighterbound. 66

PAGE 79

CHAPTER5 MODELINGERRORINSEQUENTIALCIRCUITS Sequentialcircuitsconsistofacombinationallogicblock,setofinputs,setofstatebits wherethevaluesofthenextstatebitisfedbacktothepresentstateinthenextclockcycle throughlatches.Atagiventimeinstance ti,thestatesignals stiareuniquelyidentiedasa functionofprimaryinputsignals itiandstatesignals sti Š 1oftheprevioustimeinstancegiving risetotemporalcorrelations.Duetothis,erroroccurringatonetimeinstancemightpropagate towardsseveralconsecutivetimeinstancesmakingitmorevulnerable. Inthischapter,wepresentatimeevolvingprobabilisticmodel(TemporalDependency ModelTDM)thatcanhandlethetemporaleffectsofrandomvariables.WeformtheTDM model(Fig.5.1.(d))byunrollingthebasicprobabilisticmodelintosufcientlylargenumber oftimeslicesandconnectingthepresentstatenodeofeachtimeslice PStitothenextstate nodeoftheprevioustimeslice NSti Š 1therebymaintainingthetemporalcorrelations. Toformtheerrormodelwehaveusedtheconceptofmitercircuitswheretwocopies ofthesamecircuit,onerepresentingtheidealcircuitandtheotherrepresentingtheerroneous circuit,arecompared.Foragivencircuit,anidealTDMmodelandanerroneousTDMmodel, whereeachgateiserror-pronebyafactor ,arecreated.Theidealanderroneousprimary outputnodes, Otiand Oe tirespectively,ateachtimeslice tiareconnectedtoanXORlogic basedcomparatornode Ctitherebyformingatimeevolvingmitermodel.Theoutputerror probabilityiscalculatedbyinferencingtheerrormodelandobtainingtheprobabilityofstate "1"atthecomparatornodes, P ( Cti= 1 ) ,ateachtimeslice tiiterativelybyaddingtimeslices untiltheresultsconverge.Thenumberoftimeslicesneededforagivensequentialcircuitis 67

PAGE 80

PS NS X1 O X2 I (a) (b) (c)(d) PSt 1 It 1 X1t 1 X2t 1 NSt 1 Ot 1 PSt 2 It 2 X1t 2 X2t 2 NSt 2 Ot 2 PSt 3 It 3 X1t 3 X2t 3 NSt 3 Ot 3 PSt 1 It 1 X1t 1 X2t 1 NSt 1 Ot 1 PSt 2 It 2 X1t 2 X2t 2 NSt 2 Ot 2 PSt 3 It 3 X1t 3 X2t 3 NSt 3 Ot 3 Latch I PS X1 X2 O NS Figure5.1.(a)Digitallogiccircuit(b)Correspondingprobabilisticmodel(c)DAGrepresentationwhichisnotminimal(d)TDMmodel relatedtothetemporaldependenceofoutputerrorwhichinturnisgovernedbythetemporal correlationsinthecircuit.Ourresultsshowthatdifferentsequentialcircuitsexhibitdifferent degreeoftemporaldependenceandtherequiredamountoftimeslicesislessthan10forall thecircuits,whichissimilartotheobservationspresentedin[49]. 5.1SequentialLogicModel Wemodelthesequentialcircuitsintoatimeevolvedprobabilisticnetwork,namedastemporaldependencymodel(TDM),whichhandlestemporaldependencies.Inthissectionwe providethedetailsonthemodelingofasequentiallogicintoaTDMmodel. 68

PAGE 81

5.1.1TDMModel LetusconsiderthesequentialcircuitshowninFig.5.1.(a)wherethepresentstatenodeis representedas PS ,thenextstatenodeisrepresentedas NS ,theprimaryinputisrepresented as I ,theprimaryoutputisrepresentedas O andtheinternalnodesarerepresentedas X 1and X 2. TheequivalentprobabilisticmodelshowninFig.5.1.(c)canberepresentedby Gti= ( Vti, Eti) .Thenodesoftheprobabilisticmodel, V ,aretheunionofallthenodesforeach timeslice. V =ni = 1Vti(5.1) where n isthenumberoftimeslices.Inourexample Vti= { PSti, NSti, Iti, Oti, X 1ti, X 2ti} .The edges, E ,oftheprobabilisticmodelarenotjusttheunionoftheedgesinasingletimeslice, Eti,butalsoincludestheedgesbetweentimeslices,thatis,temporaledges, Eti, ti + 1.Ithastobe notedthatthecopiesofthesamevariable Xiinalltimeslicesfollowamarkovpropertysuch thatthefollowingtwosets { Xi t1, Xi ti Š 1} and { Xi ti + 1, Xi ti + k} areindependentgiven Xi ti. Forexample,inFig.5.1.(c), X 1t1and X 1t3areindependentofeachothergiven X 1t2.Sothe temporaledgescanbedenedas Eti, ti + 1= { ( Xi ti, Xi ti + 1) | Xi ti Vti, Xi ti + 1 Vti + 1} (5.2) where Xi tiisanynodeintimeslice tiand Xi ti + 1isthereplicaofthesamenodeintheadjacent timeslice ti + 1asshowninFig.5.1.(c).Thus,thecompletesetofedges E is E = Et1ni = 2( Eti+ Eti Š 1, ti) (5.3) Intheprobabilisticmodel(Fig.5.1.(c)),apartfromthedependenciesfromonetimeslice, wealsohavethedependenciesovertwocopiesofthesamevariable Xjacrossadjacenttime 69

PAGE 82

slices.Butitisevidentthat Xj tiand Xj ti Š 1areindependentofeachothergiventhepresent statenode PSj ti.Forexamplethenodes X 1t1and X 1t2,fromFig.5.1.(c),areindependent ofeachothergiventhepresentstatenode PSj t2;soevenifweremovethetemporaledges connectingthesenodesatconsecutivetimeslicestheunderlyingstructurewillstillbeintact. Thesamecanbetoldfor X 1t2and X 1t3. Sointheprobabilisticmodelallthetemporaledgesexceptthoseconnectingthepresent stateandnextstatenodesofadjacentslices(boldlinesinFig.5.1.(c))canberemovedto achievea minimal representationasshowninFig.5.1.(d),whichistermedasthe TDMmodel Inourexample,thenecessarytemporaledgescanbegivenas, Eti, ti + 1= { ( NSti, PSti + 1) | NSti Vti, PSti + 1 Vti + 1} (5.4) 5.2ErrorModel FromtheTDMmodelofagivensequentialcircuit,anerrormodelisdesignedwherethe erroneousbehaviorofthecircuitiscomparedwiththeidealerror-freebehaviorofthecircuit. 5.2.1Structure Theerrormodelcontainsthreesections,(i) error-freelogic wherethegatesareideal,(ii) error-pronelogic whereeachgategoeswrongindependentlybyanerrorprobability and(iii) XORbased comparatorlogic thatcomparebetweentheerror-freeanderror-proneprimary outputs.AtrsttwocopiesoftheTDMmodel,ofthegivensequentialcircuit,arecreated whereonecopyrepresentstheerror-freebehaviorofthecircuitwhiletheotherrepresents erroneousbehaviorofthecircuit.Fig.5.2.illustratestheerrormodelforthesequentialcircuit giveninFig.5.1.(a).The Error-freeblock includesnodesrepresentingtheidealcombinational partofallthetimeslices.The Error-proneblock includesnodesrepresentingtheerroneous combinationalpartofallthetimeslices.Ateachtimeslice tkanXORlogicbasednode 70

PAGE 83

Error-free block Error-prone block Comparator block e tX11e tX12e tNS1e tO1e tX21e tX22e tNS2e tO2e tX31e tX32e tNS3e tO311tX12tX1tNS1tO21tX22tX2tNS2tO31tX32tX3tNS3tO1tPS2tPS3tPSe tPS2e tPS31tI1tC2tC3tC 2tI 3tI Figure5.2.ErrormodelobtainedfromTDMmodelwith3rdordertemporaldependence 71

PAGE 84

Ctkisaddedtocomparebetweentheerror-freeanderror-proneprimaryoutputs Otkand Oe tkrespectively.Theseadditionalnodesareincludedinthe Comparatorblock .Notethatatevery timeslice tkbotherror-freeanderror-pronelogichastobefedfromthesameprimaryinput node Itkandatthersttimeslice t1botherror-freeanderror-pronelogichastoconnectto thesamepresentstate(PS)node PSt1.Alsothepresentstatenodes, PStkand PSe tk,forall timeslices tkareerror-free,sinceweassumeideallatches.Thecomparatornodes Ctkandthe primaryinputnodes Itkforalltimeslices tkarealsoassumedtobeerror-free. Anygivenprobabilityfunction P ( x1, x2, xN) canbewrittenas1P ( x1, xN)=vP ( xv| Pa ( Xv)) (5.5) where Pa ( Xv) aretheparentsofthevariable Xv,representingitsdirectcauses.Thisfactoring ofthejointprobabilityfunctioncanbedenotedasagraphwithlinksdirectedfromtherandom variablerepresentingtheinputsofagatetotherandomvariablerepresentingtheoutput.Our errormodelisonesuchgraphstructurewheretheprobabilities P ( xv| Pa ( Xv) areprovidedby ConditionalProbabilityTables (CPTs)asshowninTable5.1.ItgivestheCPTsforthenodes Otkwhoseparentsare X 1tkand X 2tk,and Oe tkwhoseparentsare X 1e tkand X 2e tkfromFig.5.2. ThenodesaregovernedbyNANDlogic. TheCPTsrepresenttheunderlyinglogicfunctionofeachgate.Inthissetupitiseasier toincorporatetheindividualgateerrorprobability byjustchangingtheprobabilitiesinthe CPT.ForexampleTable.5.1.givestheCPTsforerror-free Otkanderror-prone Oe tk.InerrorproneCPTwejusthavetoreplacetheprobabilityvalues0by and1by1 Š .Thisindicates thatthereis( 100)%chanceforthesignaltogotostate"1"whenithastogotostate"0" and( 100)%chanceforthesignaltogotostate"0"whenithastogotostate"1". 1Probabilityoftheevent Xi= xiwillbedenotedsimplyby P ( xi) orby P ( Xi= xi) .72

PAGE 85

Table5.1.Conditionalprobabilistictablesforerror-freeanderror-proneNANDlogic Error-freeNAND P ( X 1tk) P ( X 2tk) P ( Otk= 0 ) P ( Otk= 1 ) 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 Error-proneNAND P ( X 1e tk) P ( X 2e tk) P ( Oe tk= 0 ) P ( Oe tk= 1 ) 0 0 10 1 11 0 11 1 1Table5.2.Conditionalprobabilistictableforerror-proneNANDlogichavingvariablegate errorprobabilities, 0and 1 Error-proneNAND P ( X 1e tk) P ( X 2e tk) P ( Oe tk= 0 ) P ( Oe tk= 1 ) 0 0 1 11 0 1 1 11 1 0 1 11 1 1 10 0 Also,inourmodelwecanprovideunequalgateerrorprobabilitiesforanyvariable Xe tkat anytimeslice tk,suchthatif P ( Xtk= 0 )= 1,then P ( Xe tk= 0 )= 1 Š 0and P ( Xe tk= 1 )= 0; if P ( Xtk= 1 )= 1,then P ( Xe tk= 0 )= 1and P ( Xe tk= 1 )= 1 Š 1.ThecorrespondingCPTof thisimplementationforanerror-proneNANDlogicisgiveninTable.5.2. 0isbasicallythe errorprobabilityoflogic"0"and 1istheerrorprobabilityoflogic"1"attheoutputofagate. Increasing 0indicatesthatthecircuithasmore0 1errors,whereasincreasing 1indicates thatthecircuithasmore1 0errors.Withthisimplementation,wecanuseourerrormodel tostudytheeffectoftheseerrorsintheoutputofthecircuit. 73

PAGE 86

5.2.2InferenceScheme Theinferenceschemebasicallycalculatesthejointprobabilitydistribution P ( x1, xN) efcientlybypropagatingtheprobabilitydistributions P ( xv| Pa ( Xv) oflocallyconnectedvariablesandtherebycalculatestheupdatedindividualprobabilitydistributionsofallrandom variables.TheinferenceorpropagationofbeliefontheprobabilisticerrormodelisdoneusingtheHuginarchitecture[26,27]whichisan exact method.Theinferenceonourmodel canbeperformedbyformingclustersofnodes( cliques )whicharedirectlydependentoneach otherandperformingcomputationsonthoseclusters,therebyenablinglocalcomputing.The networkthatisformedusingthesecliquesiscalled jointree ,whereinformationcanbepropagatedbetweencliquesusingmessagepassingmechanism.Sinceextensiveliteratureisalready available,wewillnotbeexplainingtheinferenceschemeindetail.Interestedreadersplease referto[26,27]. Inordertoobtainajointree,a moralgraph iscreatedfromtheerrormodel,byadding undirectedlinksbetweentheparentsofeachcommonchildnode,anditistriangulated,to ensurethattherearenocycleswithmorethanthreenodes,toobtaina chordalgraph .Then thecliquesareformedfromthechordalgraphandtheyarelinkedaccordinglytoformthe jointree.Eachadjacentcliqueswillhaveoneormorecommonvariableswhicharetermed as separators .Thefollowingstepswillexplaintheformationofjointreeusinganexample circuitgiveninFig.5.3.(a)anditsequivalentprobabilisticmodelgiveninFig.5.3.(b). € A moralgraph ,asshowninFig.5.3.(c),isformedfromtheoriginalprobabilisticnetworkbyaddingundirectedlinksbetweentheparentsofeachcommonchildnode. Additionallinks(Fig.5.3.(c)):G1-G2,G3-G4 Theseadditionallinkshelpstoformcompletesubgraphsofeachparent-childset. Thenodesineachsubgraphcanformacliqueandtherebyenablelocalcomputation.Butthisgraphicalformdoesnotproducetheminimaljointreebecause 74

PAGE 87

someoftheindependenciesrepresentedbytheprobabilisticnetworkarelostdue toitsundirectednature.Thedependencystructureishoweverpreserved.This non-minimalrepresentationwilleventuallyleadtohighcomputationalneeds,even whenitdoesnotsacriceaccuracy. € Togetamoreminimalrepresentationofthejointreewhichcancapturetheconditionalindependencies,a chordalgraph isformed.Itisobtainedbytriangulatingthe moralgraph.Triangulationistheprocessofbreakingallcyclesinthegraphtomakea compositionofcyclesoverjustthreenodesbyaddingadditionallinks.Tocontrolthe computationaldemands,thegoalistoformachordalgraphwiththeminimumnumber ofadditionallinks. Additionallinks(Fig.5.3.(c)):Noadditionallinkssincetherearenocycleswith morethanthreenodes. € Thecliquesareformedfromthechordalgraphandtheyarelinkedaccordinglytoform thejointree(Fig.5.3.(d)).Eachadjacentcliqueswillhaveoneormorecommonvariableswhicharetermedas separators .InFig.5.3.(d),betweencliques C 1and C 2,the variables { G 3 G 4 } formtheseparatorset S 1.Also,anytwocliquessharingasetof commonvariableswillhavethesecommonvariablespresentinallthecliquesthatlie intheconnectingpathbetweenthesetwocliques.InFig.5.3.(d),thecliques C 1and C 4sharethecommonvariable { G 3 } andtheonlyclique, C 2,intheirpathalsocontains { G 3 } Toperformlocalcomputation,eachclique Ciisassociatedwithprobabilitypotentials Ciandeachseparator Sjisassociatedwithprobabilitypotentials Sj.Alsofromhereon,theset ofvariablesofanyclique Ciorseparator Sjwillberepresentedinboldlettersas Cior Sj.The inferenceisperformedasfollows, 75

PAGE 88

G2 G5 G4 G6 G3(a)G1 G2 G6 G3 G5 G4 G1 (b) G2 G6 G3 G5 G4 G1 (c) G1,G3,G4(d) G3,G4,G5 G1,G2,G3 G3,G6 S1 G3,G4 S2 G1,G3 S3 G3C1 C2 C3 C4 G 2 G5 G 4 G 6 G 3 ( a ) G1 G1,G 3 ,G4 ( d ) G3,G4,G5 G1,G 2 ,G 3 G 3 ,G6 S1 G 3 ,G4 S2 G1,G3 S 3 G 3 C 1 C 2 C 3 C 4 G 2 G 6 G 3 G5 G 4 G1 ( b ) G 2 G 6 G 3 G5 G 4 G1 ( c ) Figure5.3.(a)Digitallogiccircuit(b)Correspondingprobabilisticmodel(c)Moralgraphobtainedbyaddingundirectedlinksbetweenparentsofcommonchildnodes(d)Corresponding jointreeobtained € Initialization :Initiallyalltheentriesinthecliquepotentialsandseparatorsetpotentialsareassignedthevalue1.Inthejointreethevariablesofthegivenprobabilistic networkaredividedinseparatecliques.Eachcliquewillhaveitsownjointprobability governedbyitsvariables.Buteventuallyweneedtorealizethejointprobabilityofthe entirenetworkasgiveninEqn.3.2.Toachievethis,foreachvariable Yv,aparticular clique Ciwhichcontains Yvalongwithitsparents Pa ( Yv) isselectedandtheconditional probabilitypotentialof YvfromitsCPTismultipliedtothecliquepotential CiCi= CiP ( yv| Pa ( Yv)) (5.6) Example :(Fig.5.3.(d)) C 3= C 3P ( G 3 | G 1 G 2 ) (5.7) € Messagepassing :Afterinitializationthecliquepotentialsarenotconsistentwiththeir separatorpotentials.SothejointprobabilitygiveninEqn.3.2isnotperfectlyrealized. Toachievethisconsistency messagepassing isperformed.Atrstthemarginalprob76

PAGE 89

abilityoftheseparatorvariableshastobecomputedfromtheprobabilitypotentialof clique Cpandthenitisusedtoscaletheprobabilitypotentialofclique Cq. Marginalization : updated Sr=Cp\ SrCp(5.8) Scaling : Cq= Cqupdated Sr Sr(5.9) Example :(Fig.5.3.(d))Messagepassingfrom C 2to C 1 updated S 1=G 5C 2(5.10) C 1= C 1updated S 1 S 1(5.11) Thetransmissionofthisscalingfactoristheprimarynecessityforupdatingand messagepassing.Eventuallythejointprobabilityoftheentirenetworkcanbe representedas, P ( y1, yN)= iCi j Sj(5.12) Messagepassinginajointreehastobedoneinbothdirections,fromroottoleaf termedas outwardpass andfromleaftoroottermedas inwardpass .Aninward passfollowedbyanoutwardpasswillcompletelyupdateallthecliquesinthejoin tree. € Individualprobabilitydistributioncalculation :Thentheindividualprobabilitydistributionforeachvariablecanbecalculatedbychoosingaclique Cicontainingthevariable Yvandmarginalizingitspotential Cioveralltheothervariables Ci\ Yv.Thisprobability 77

PAGE 90

distribution P ( yv) isgivenas, P ( yv)=Ci\ YvCi(5.13) Example :(Fig.5.3.(d)) P ( G 6 )=G 3C 4(5.14) 5.2.3OutputErrorProbability Theoutputerrorprobabilityofagivensequentialcircuitcanbeobtainedbycalculatingthe probability, P ( Ctn= 1 ) ofthecomparatornode Ctnatthenaltimeslice tnbyinferencingthe correspondingerrormodel.Eachsequentialcircuitbasedonitsunderlyingstructurewillneed differentamountoftimeslices.Duringinferenceifatanytimeinstancearandomvariable representingasignalintheerror-pronelogicpicksupawrongvalue,thisvaluewillpropagate foraconsiderableamountoftimebeforethesignalgetsbacktoitsoriginalvalue.Thispattern willkeeponrepeatingthroughseveralsamples.Duetothisphenomenontherandomvariable takessometimetoconvergeatoneparticularprobabilitydistribution.Soforeachsequential circuitwehavetoiterativelycalculatetheoutputerrorprobabilitybyincreasingthetimeslices andstopwhentheoutputerrorprobabilitiesofconsecutivetimeslicesconverge.Thisisthe reasonforhavingcomparatornodesateverytimeslice.Thenumberoftimeslicesneededby asequentialcircuitispurelydependentontheunderlyingfunctionalityandcircuitstructure. 5.3ExperimentalResults Theoutputerrorprobabilitiesforvarioussequentialcircuitsarecalculatedusingourexperimentalsetup.WehaveperformedourexperimentsonstandardMCNCandISCASbenchmarkcircuits.WehaveusedHUGINtool[50]toperforminferenceontheerrormodeland wevalidatetheseresultswithequivalentHSpicesimulation. 78

PAGE 91

Take the error model for a given digital logic circuit with a given and fixed no. of time slices First time slice : P(PS=0)=0.5, P(PS=1)=0.5 All time slices : P(I=0)=0.5, P(I=1)=0.5 Inference the error model Output error probability = P(C=1) at final time slice Does output error probability converge No Yes Output error probability = P(C=1) at final time slice Add 1 time slice Figure5.4.Flowchartforexperimentalprocedure 5.3.1ExperimentalProcedure Fig.5.4.givestheexperimentalprocedureundertakentoobtaintheoutputerrorprobabilities.Atrstforagiven valuetheprobabilisticerrormodelisobtained.Theprimaryinput nodes Itkforallthetimeslices tkandthepresentstatenodes PSt1forthersttimeslice t1aresettobeequallyprobabletohavestate"0"orstate"1".Themodelistheninferenced andtheoutputerrorprobabilityisobtainedbynotingtheprobabilityofstate"1"atthecomparatornode, P ( Ctk= 1 ) ateverytimeslice tk.Thisinferenceisan exact oneanditalso handlesreconvergenceandspatio-temporaldependencies. P ( Ctn= 1 ) ofthenaltimeslice tnand P ( Ctn Š 1= 1 ) oftheprevioustimeslice tn Š 1arecheckedforconvergence.Iftheydonot convergethetimeslicesatbotherror-freeanderror-proneblocksareincreasedby1andthe procedureisrepeated.Thusthecircuitsareinferencedwithdifferentnumberoftimeslices 79

PAGE 92

Table5.3.Outputerrorprobabilitiesat = 0 001 0 003 0 005 0 01 Circuits = 0 001 = 0 003 = 0 005 = 0 01 train11 0.0055 0.0161 0.0265 0.0511 lion 0.0060 0.0177 0.0288 0.0545 lion9 0.0069 0.0200 0.0326 0.0614 bbara 0.0074 0.0213 0.0341 0.0621 bbtas 0.0072 0.0211 0.0344 0.0653 s27 0.0075 0.0220 0.0357 0.0676 mc 0.0084 0.0246 0.0399 0.0747 iterativelyandstoppedwhentheoutputerrorprobabilityvaluesconvergeatconsecutivetime slices. 5.3.2OutputErrorProbabilities Table5.3.givestheoutputerrorprobabilitiesforgateerrorprobabilities, =0.001,0.003, 0.005,0.01.Foraslightincreasein valuefrom0 001to0 003,thereisatleast2 87fold increaseinthecorrespondingoutputerrorprobabilities.Also,foraconsiderablylowinux oferroratthegatesfor = 0 005 ( 0 5% ) ,theoutputerrorprobabilityofmostofthecircuits exceed3%with mc producingthehighestoutputerrorprobabilityof3 99%whichisalmost8 foldhigherthantheindividualgateerrorprobability.Thesamecanbeseenfor = 0 01 ( 1% ) wheretheoutputerrorprobabilityofmostofthecircuitsexceed6%. 5.3.3NumberofTimeSlices Fig.5.5.showsthenumberoftimeslicesneededby bbara and bbtas for = 0 Š 0 006.It canbeseenthatthecircuitsneededlessnumberoftimeslicesforsmall valuesandthenthe needednumberoftimeslicesgraduallyincreasesalongwith value.For bbtas ,theneeded numberoftimeslicesgetssetto5at = 0 0013while bbtas takesupmoretimeslicesand 80

PAGE 93

0 1 2 3 4 5 6 7 8 9 10 00.0010.0020.0030.0040.0050.0060.007 Number of time slices Gate error probability bbara bbtas Figure5.5.Numberoftimeslicesneededby bbara and bbtas for = 0 Š 0 006 nallygetssetat9for = 0 005.Thenumberoftimeslicesneedediscompletelydependent onthecircuitstructure.Thefollowingstudieswillshedmorelightonthisaspect. 5.3.4OutputErrorPropagationAcrossTimeSlices Fig.5.6.(a)&(b)givesthetransitionofoutputerrorprobabilityacrosstimeslicesfor = 0 01.Hereweshowtwosetsofresultsthatshowsthedifferenceinthetransitionofoutput erroracrosstimeslices.Fig.5.6.(a)showstheoutputerrortransitionfor bbara s 27and mc ,wheretheoutputerrorincreasesgraduallyacrosstimeslicesandnallygetsconverged. WhereasinFig.5.6.(b),whichshowstheoutputerrortransitionfor lion lion 9and bbtas ,the outputerrorreachesamaximumvalueandthengraduallygetsbacktoasteadyvalue.This behaviorcanbeattributedtotherelationbetweenthepresentstatenodesandtheprimaryinput nodeswhichhaverandomunbiasedstatedistribution.Ifthepresentstatenodesareclosely connectedtotheinputnodesresultinginhavinganunbiasedstatedistribution,theoutputerror willnotbesignicant.Withabiasedstatedistributioninthepresentstatenodes,theoutput 81

PAGE 94

0.02 0.03 0.04 0.05 0.06 0.07 0.08 012345678910 Output error probability Number of time slices bbara s27 mc 0.02 0.03 0.04 0.05 0.06 0.07 0.08 012345678 Output error probability Number of time slices lion lion9 bbtas (a)(b) Figure5.6.(a)Transitionofoutputerrorprobabilityacrosstimeslicesfor bbara s 27and mc with = 0 01(b)Transitionofoutputerrorprobabilityacrosstimeslicesfor lion lion 9and bbtas with = 0 01 0 0.05 0.1 0.15 0.2 0.25 0.3 0.35 012345678Output probability Number of time slices bbtas OeO OeO lion9 lion OeO 0.124 0.126 0.128 0.13 0.132 0.134 0.136 0.138 0.14 0.142 0.144 01234567Output probabilityNumber of time slices O Oe bbara (a)(b) Figure5.7.(a)Transitionoferror-freeanderror-proneoutputprobabilitiesacrosstimeslices for bbtas lion 9and lion with = 0 01(b)Transitionoferror-freeanderror-proneoutput probabilitiesacrosstimeslicesfor bbara with = 0 01 82

PAGE 95

0 0.02 0.04 0.06 0.08 0.1 0.12 0.14 Output error probability Circuit 0= 0.01, 1= 0.02 0= 0.02, 1= 0.01 0 = 0.01, 1 = 0 02 0 = 0.02, 1 = 0 01 Figure5.8.Outputerrorprobabilitiesfor( 0= 0 01, 1= 0 02)and( 0= 0 02, 1= 0 01) errorbecomesmoresignicantandreachesamaximumvalueintheearlytimeslicesasshown inFig.5.6.(b). Fig.5.7.(a)&(b)givesthetransitionoferror-free( O )anderror-prone( Oe)outputprobabilitiesacrosstimeslicesfor = 0 01.TheresultsinFig.5.7.(a)showthat,forsomecircuits, thetemporaldependenceoftheerroneousoutputconformswiththatoftheidealerror-free output.Whereasincircuitslike bbara thisisnotthecaseasshowninFig.5.7.(b).Duetothis, theoutputerrorprobabilityin bbara takesmoretimetoconverge. 5.3.5OutputErrorProbabilitiesfor 0 = 1Inourmodelwecanprovideunequalgateerrorprobabilityvalues, 0and 1,tostudythe effectof0 1and1 0errorsontheoutputofacircuit.Fig.5.8.givestheoutputerror probabilitiesfor( 0= 0 01, 1= 0 02)and( 0= 0 02, 1= 0 01).Itcanbeclearlyseenthat when 0> 1theoutputerrorprobabilitiesarehigherforallcircuits.Thisindicatesthata 0 1errorcanmaketheoutputsmoreerroneousandsignalsthatstayatlogic"0"moreoften canbevulnerabletothiseffect.ThismightbefavorableinCMOStechnology,sincethe0 1 83

PAGE 96

Table5.4.Outputerrorprobabilitiesat = 0 001 0 003 0 005 0 01comparedwithHSpice simulationresults = 0 001 = 0 003 Circuits Errormodel HSpice % Errormodel HSpice % diff diff train11 0.0055 0.0057 3.51 0.0161 0.0159 1.26 lion 0.0060 0.0063 4.76 0.0177 0.0171 3.51 lion9 0.0069 0.0066 4.55 0.0200 0.0208 3.85 bbara 0.0074 0.0070 5.71 0.0213 0.0208 2.40 bbtas 0.0072 0.0069 4.35 0.0211 0.0203 3.94 s27 0.0075 0.0080 6.25 0.0220 0.0217 1.38 mc 0.0084 0.0088 4.55 0.0246 0.0250 1.60 = 0 005 = 0 01 Circuits Errormodel HSpice % Errormodel HSpice % diff diff train11 0.0265 0.0263 0.76 0.0511 0.0497 2.82 lion 0.0288 0.0277 3.97 0.0545 0.0522 4.41 lion9 0.0326 0.0339 3.83 0.0614 0.0607 1.15 bbara 0.0341 0.0345 1.16 0.0621 0.0595 4.37 bbtas 0.0344 0.0354 2.82 0.0653 0.0671 2.68 s27 0.0357 0.0345 3.48 0.0676 0.0638 5.96 mc 0.0399 0.0391 2.05 0.0747 0.0733 1.91 bitipismuchharderthan1 0bitipduetothelesserrorpronenessofpMOSascompared tonMOSsinceholesaretoughertobedislodgedbyexternalparticlebombardments.Itcan alsosignifythatcircuitswithseriespMOSconnectionscanbelesserrorproneascompared tocircuitswithparallelpMOSconnections. 5.3.6ValidationUsingHSpiceSimulation WevalidateourresultsbycomparingthemwithHSpicesimulationresults.Eventhough, ourerrormodelcanbeusedforanytechnology,thelackofbenchmarkcircuitsinanyof theotheremergingtechnologieshasforcedustocompareourmodelwithsimulationsusing 45nmCMOStechnology.Usingexternalvoltagesourceserrorcanbeinducedinanysignal 84

PAGE 97

anditcanbemodeledusingHSpice[43].InourHSpicemodelwehaveinducederror,using externalvoltagesources,ineverygate'soutput.Considersignal Ofistheoriginalerrorfree outputsignalandthesignal Opistheerrorproneoutputsignaland E isthe piecewiselinear (PWL)voltagesourcethatinduceserror.Thebasicideaisthatthesignal Opisdependent onthesignal Ofandthevoltage E .Anychangeofvoltagein E willbereectedin Op.If E = 0 v ,then Op= Of,andif E = Vdd ( supplyvoltage ) ,then Op = Of,therebyinducing error.ThedatapointsforthePWLvoltagesource E areprovidedbycomputationsona niteautomatawhichincorporatestheindividualgateerrorprobability .Thewidthofevery errorpulseisxedto1 ns .Theresultsareobtainedbyrunningthecircuitsfor5 million randominputvectorsandsamplingthecomparatoroutputs.Table5.4.givesthecomparison betweentheoutputerrorprobabilitiesobtainedfrominferenceintheerrormodelandHspice simulationfordifferentcircuitswithgateerrorprobability = 0 001 0 003 0 005 0 01.The %differenceiscalculatedas,((Errormodel-Hspice)/Hspice)x100.Thehighestrelative differencebetweentheinferenceresultsandHSpiceresultsisjust6 25%andonanaverage therelativedifferenceisonly4 43%. 5.4Discussion Wehaveproposedacompactprobabilisticmodelthatcanhandleerrorinsequentiallogic andwehavepresentedexperimentalresultsonISCASandMCNCbenchmarkcircuits.We haveobservedthatforlowgateerrorprobabilitieslike = 0 005 ( 0 5% ) ,theoutputerror probabilitiesareatleast5foldhigherandatmost8foldhigher.Also,ourobservations showedthatthedegreeoftemporaldependencediffersforvarioussequentialcircuits.Another interestingobservationindicatedthat0 1errorsaffectsthecircuitoutputmorethan1 0 errors.WehavealsovalidatedourmodelusingHSpicesimulationresultsandtheaverage% differenceisonly4 43%. 85

PAGE 98

CHAPTER6 REDUNDANCYSCHEMESFORERRORMITIGATION Reliablecomputingusingunreliablecircuitelementscanbeaccomplishedusingtheconceptofredundancy.Asthenamesuggests,thebasicideaof'redundancy'isbasedonanalyzinganygivenerroneouscircuitthroughmultipleredundantcomponentsorprocesses.The outputsfromtheseredundantcomponentsorprocessesaresubjectedtoavotingschemewhere themajorityvalueofthesignalunderconsiderationischosentobeitsultimateerror-free value.Inthischapter,thefollowinguniqueredundancyschemesarediscussed. € Temporalredundancyscheme-theredundancyisappliedintheinputspacebyprovidingmultipleinstancesofthesameinputcombinations,whicharehighlyprobableto createanerrorintheoutput. € Spatialredundancyscheme-theredundancyisappliedintheintermediatesignalspace byprovidingmultiplecopiesofthesamegates,whoseoutputsignalsareerroneous. € Hybridredundancyscheme-theredundancyisappliedinbothinputspaceandintermediatesignalspace,inordertoachievecomprehensiveerrorreductioninthegiven erroneouscircuit. 86

PAGE 99

6.1TemporalRedundancySchemeUsingTripleTemporalRedundancy(TTR)Technique TripleTemporalRedundancy(TTR)isanerrorreductiontechnique,wherespecicinput combinationsareapplied three timesandfromtheresultingsimulationoutputsthemajority valueisacceptedasthecorrectone.Performingthistechniqueontheentireinputspacewill resultalargeamountofunwantedcalculationsleadingtohighsimulationtime.Inorderto makeitmoreefcient,thetechniquehastobeappliedonlyonasubsetoftheinputspace, whereeachinputcombinationhasahighchanceofgivingawrongoutputcomparedtothose intherestoftheinputspace.Soasapreliminarystepforthisredundancytechnique,the abovementionedsubsetontheinputspaceshouldbedetermined.Thiscanbeachievedby usingthemodelthatcalculatesthemaximumoutputerrorandthecorrespondingworst-case inputcombination,explainedinChapter4. 6.1.1DeterminationoftheSetofWorst-CaseInputCombinationsforSelectiveRedundancyinTTR AsdiscussedinChapter4,themodelthatcalculatesmaximumoutputerrorprobability, determinesasingleworst-caseinputcombinationwhichhasthehighestprobabilitytoprovide anerrorintheoutput.Inordertogetasetofworst-caseinputcombinations,thesearchprocess explainedinSection4.1.2canbeextendedasfollows(Fig.6.1.), € Afterobtainingthemostprobableworst-caseinputcombination, iMAP,thecorrespondingMAPprobability, MAP ( iMAP, o ) ,isnoted. € ThenumberofinputcombinationsneededforTTRisdecidedandalowerboundof MAP ( i o ) ,calledLB MAP,withreferenceto MAP ( iMAP, o ) ,ischoseninordertocollectthesetofworst-caseinputcombinations.Thislowerboundcanbeadjustedbased ontheamountofinputcombinationsneededforTTR. 87

PAGE 100

Library of worst-case input combinations {I1=0,I2=0,I3=0} {I1=0,I2=1,I3=0} Backtrack route } 0 1 { } 1 { I IN} 0 2 0 1 { } 2 1 { I I I IN } 1 2 0 1 { } 2 1 { I I I IN} 0 3 0 2 0 1 { } 3 2 1 { I I I I I IN } 1 3 0 2 0 1 { } 3 2 1 { I I I I I IN {} {}NIgnored } 1 1 { } 1 { I INIgnoredMAP({I1=0,I2=0,I3=0}, o ) > LB_MAP MAP({I1=0,I2=0,I3=1}, o ) < LB_MAP Iinter = {I1,I2,I3} id 1= {I1=0,I2=0,I3=0} Iinter = {I1,I2,I3} id 1= {I1=0,I2=0,I3=1}Starting Node } 0 1 { } 1 { I IN} 0 2 0 1 { } 2 1 { I I I IN } 1 2 0 1 { } 2 1 { I I I IN} 0 3 0 2 0 1 { } 3 2 1 { I I I I I IN } 1 3 0 2 0 1 { } 3 2 1 { I I I I I IN{} {}N } 1 1 { } 1 { I INIgnored } 0 3 1 2 0 1 { } 3 2 1 { I I I I I IN } 1 3 1 2 0 1 { } 3 2 1 { I I I I I IN Iinter= {I1,I2,I3} id 1= {I1=0,I2=1,I3=0} Iinter= {I1,I2,I3} id 1= {I1=0,I2=1,I3=1} MAP({I1=0,I2=1,I3=0}, o )> LB_MAP No. of worst-case input combinations needed for TTR = 2 Lower Bound of MAP( i o ) = LB_MAP N o. of wo r s t c ase input combinations needed for TTR = 2 Lower Bound of MAP ( i o ) = LB_MA P Figure6.1.Determinationofthesetofworst-caseinputcombinationsbybacktrackingthrough thesearchtreeusedforMAPcomputationgiveninFig.4.8. € Thesearchprocessfortherestoftheworst-caseinputcombinationsapartfrom iMAP, startsfromthenode NiMAPIandbacktracksthroughthedepth-rstbranchandbound searchtree,collectingalltheinputcombinationswhichhave MAP ( i o ) abovethechosenlowerbound.Thissearchprocessisstoppedoncethetargetnumberofworst-case inputcombinationsforTTRisreached. € Finally,theresultingsetofworst-caseinputcombinationsareplacedinalibrarywhich canbeusedasareferencewhileperformingTTR. 88

PAGE 101

NotethatthesearchprocessforMAPcomputationisconductedinabinarytree,wherethe rootnode N andtheintermediatenodes NiinterIinterareconnectedtoonlytwochildnodes.Inthe processfordeterminingthesetofworst-caseinputcombinations,thebasicideaisthatevery inputcombination i inthevicinityof iMAPshouldbecheckedforthepossibilityofbeinga worst-caseonebycomparingthecorrespondingjointprobability MAP ( i o ) withthelower bound LB MAP .Also,notethatwheneveranintermediatenode,withtwounvisitedchild nodes,isencountered,thesearchpathgoesthroughthe'0'edgerstandthentothe'1'edge. IntheexamplegiveninFig.6.1.,thebacktrackingstartsfromnode N{ I 1 = 0 I 2 = 0 I 3 = 0 } { I 1 I 2 I 3 }and goestotheintermediatenode N{ I 1 = 0 I 2 = 0 } { I 1 I 2 }andevaluatesthenode N{ I 1 = 0 I 2 = 0 I 3 = 1 } { I 1 I 2 I 3 }tocheck whetherthecorrespondingcondition MAP ( { I 1 = 0 I 2 = 0 I 3 = 1 } o ) > LB MAP istrue. Sinceitisnottrue,theinputcombination { I 1 = 0 I 2 = 0 I 3 = 1 } isnotcategorizedasa worst-caseinputcombination.Thenthebacktrackingsearchgoesonelevelabovetonode N{ I 1 = 0 } { I 1 }andgetstoitsunvisitedchildnode N{ I 1 = 0 I 2 = 1 } { I 1 I 2 },whichhastwounvisitedchildnodes. Thechildnodealongthe'0'edge, N{ I 1 = 0 I 2 = 1 I 3 = 0 } { I 1 I 2 I 3 },isvisitedrstandthecorrespondingjoint probability, MAP ( { I 1 = 0 I 2 = 1 I 3 = 0 } o ) ,ischeckedforthecondition MAP ( { I 1 = 0 I 2 = 1 I 3 = 0 } o ) > LB MAP .Sinceitistrue,theinputcombination { I 1 = 0 I 2 = 0 I 3 = 1 } is consideredasaworst-oneandaddedtothelibrary.Sincethetargetof2worst-caseinput combinationsforTTRisreached,thesearchisstopped. 6.1.2ExperimentalSetupforTTR Inordertoachieveefcientcomputation,theunnecessarysimulationrunsareavoidedby incorporating selectiveredundancy inTTR.Thisisperformedthroughthefollowingsteps, € PerformingTTRonlyontheworst-caseinputcombinationsinsteadofrunningitonthe entireinputspace. € DecidingonthethirdrunofTTRbasedonthersttworuns. 89

PAGE 102

Random Input Generator Decision Block Run_flag TTR_flag Library of worst-case input combinations Majority Value Calculator Run Identifier Erroneous Circuit Ideal Circuit Comparators N1 N2 N3 N6eN5eN4eN7eN8eN4 N5 N6 N7 N8 N7mN8mC1 C2 Figure6.2.ExperimentalsetupforTTRincorporatingselectiveredundancy Fig.6.2.illustratestheexperimentalsetupforTTR.Thedescriptionofthevarioussegments areasfollows, € ErroneousCircuit:-Thisisthecircuitunderconsideration,whereeachgatehasagate errorprobability € IdealCircuit:-Thectitiousidealcounterpartoftheerroneouscircuit,underconsideration,usedtostudytheerroneousprimaryoutputsignals. € Comparators:-XORgatesusedtocomparebetweentheerroneousprimaryoutputsignalsandtheiridealcounterparts,inordertodetecttheoccurrenceofoutputerror. 90

PAGE 103

€ Libraryofworst-caseinputcombinations:-Collectionofinputcombinations,which havehighprobabilityofinducingerrorinthecircuitoutputascomparedtotherestof theinputspace. € RandomInputGenerator:-Thissegmentproducesrandomdigitalinputsignalswhich areappliedtotheprimaryinputsofboththeerroneouscircuitanditsidealcounterpart. € DecisionBlock:-ThissegmentdecidesonthenecessityofperformingTTRandthe necessityofthethirdrun.Itgetstheneededinformationfromthelibraryofworstcaseinputcombinations,therandominputgeneratorandthemajorityvaluecalculator. Italsosendsthedecisioninformationtotherandominputgeneratorandthemajority valuecalculator. € TTR flag :-AbooleanagthattriggersthenecessityofperformingTTR. TTR flag = 1,impliesTTRneeded. TTR flag = 0,impliesTTRnotneeded. € Run flag :-Abooleanagthattriggersthenecessityofperformingthethirdrun. Run flag = 1,impliesthirdrunisneeded. Run flag = 0,impliesthirdrunisnotneeded. € MajorityValueCalculator:-ThissegmentcomparestheoutputvaluesfromtheTTR runsanddeterminesthemajorityvalueoftheprimaryoutputsignals. € RunIdentier:-ComparestheoutputvaluesfromthersttwoTTRrunsandsendsthe informationtothedecisionblock. 91

PAGE 104

TheproceduretoperformTTRisasfollows, € Aninputcombinationgeneratedfromtherandominputgeneratorisprovidedtoboth theerroneouscircuitandtheidealcircuit.Thesameinputcombinationisalsosentto thedecisionblock. € Thegeneratedinputcombinationiscomparedwiththesetofworst-caseinputcombinations.Ifitconformswithanyoftheworst-caseinputcombination,then TTR flag = 1, else TTR flag = 0. € TTR agischeckedforitsstatus. If TTR flag = 1,thenthesameinputcombinationisappliedagainandthevalue iscomparedwiththatofthepreviousrun.Then Run ag istriggered. If TTR flag = 0,thenthenextinputcombinationisapplied. Run ag isnot triggered. € Run agischeckedforitsstatus. If Run flag = 1,thentheinputcombinationisappliedforthethirdtime.The majorityvaluefromthethreerunsisdetermined. If Run flag = 0,thentheinputcombinationisnotappliedforthethirdtime.The valuefromthesecondrunisdecidedasthemajorityvalue. € Thenthemajorityvalueoftheerroneousoutputsignalandtheidealoutputsignalare fedtoanXORcomparator. € Theoutputerrorprobabilitiesarecalculatedfromthecomparatoroutputs. Notethatthedecisionblockcanruninparallelwiththecircuitandsowhentheinputsare notfromthelibrary,thereisnopenaltyforthelibrarysearch.Alsonotethatifitisdecided 92

PAGE 105

thatTTRisneeded,thentheXORcomparatorswaitforthemajorityvaluestobedetermined beforecomparingtheerroneousandidealsignals,therebyavoidingtheoccurrenceofunnecessarysamplesintheiroutputsignals.AlsointheexamplegiveninFig.6.2.,ifTTRisnot performed,then N 7m= N 7e, N 8m= N 8e.IfTTRisperformed,then N 7m=majorityof N 7efromtheTTRruns, N 8m=majorityof N 8efromtheTTRruns. 6.2SpatialRedundancySchemeUsingCascadedTripleModularRedundancy(CTMR) Technique Intriplemodularredundancy,threecopiesoftheanyerroneousgatearecreatedandfrom theiroutputsthemajorityvalueisacceptedasthecorrectone.Letssaythatthethreecopies oftheerroneousdigitalsignalarerepresentedasA,BandC.Thenthemajorityvalueoutof A,B,Ccanbedeterminedbyimplementingthebooleanfunction AB + BC + AC .Themost importantaspecttonotehereisthattheerrorprobabilityofanyerroneousgatewillreduce whensubjectedtotriplemodularredundancythroughthemajoritygate.Anevenbettererror probabilitycanbeachievedusingCTMR,wheretwocascadinglevelsoftriplemodularredundancyisappliedbyreplicatingtheerroneousgateninetimesandproducingthreemajority outputswhichinturnaresuppliedtoanothermajoritygatetogetanalvalue.Fig.6.3.illustratestheCTMRtechniqueusedtoperformspatialredundancy.Thesignal N 8ewhoseinitial errorprobabilityis ,whensubjectedunderCTMR,attainsabettererrorprobability s< Toachieveefcientspatialredundancy,insteadofapplyingCTMRtoallgatesinthecircuit, onlysomeselectivegatescanbechosen.Todeterminethesegates,asensitivityanalysiscan beperformedonthecorrespondingprobabilisticerrormodelofthecircuit. 93

PAGE 106

ABC Majority of A, B, C Majority Gate (MG) N1N2N3 N4 N5 N6 N7N8 Ideal Circuit N1N2N3 N4eN5eN6e N7eN8e MG MG MG MG N5eN6eN8ewith error probability s< s Erroneous Circuit Comparators C2 C1 Figure6.3.SpatialredundancyschemeusingCTMRtechniqueincorporatingmajoritylogic 6.2.1SensitivityAnalysisforSelectiveRedundancyinCTMR Todeterminethesensitivityofanerroneousnode,thatnodeisperturbedsothatitwill haveadifferentgateerrorprobability s,whichcanbesimilartotheoneobtainedbyperformingCTMRonthatparticularnode,whileprovidinggateerrorprobability forallother nodes.Theoutputerrorprobabilitiesforthissetupiscalculatedas, Ps( Oi) .Thentheoutput errorprobabilities, P( Oi) ,areobtainedwithgateerrorprobability xedinalltheerroneous nodes.Thedifferencebetweentheoutputerrorprobabilities, Ps( Oi) and P( Oi) ,determines thenode'sdegreeofinuenceorsensitivity.Nodesarerankedonthebasisofthedecreasing orderofthedegreeofinuenceandthetoprankednodesareselectedasthe sensitivenodes 6.3HybridRedundancy Hybridredundancyschemeistheblendoftemporalredundancyandspatialredundancy. AsshowninFig.6.4.,hybridredundancycanbevisualizedasperformingtemporalredun94

PAGE 107

Random Input Generator Decision Block Run_flag TTR_flag Library of worst-case input combinations Majority Value Calculator Run Identifier Erroneous Circuit after Spatial Redundancy Ideal Circuit Comparators N1 N2 N3 N6eN5eN4eN7eN8eN4 N5 N6 N7 N8 N7mN8m s C1 C2 Figure6.4.HybridredundancyschemeusingCTMRandTTRtechniques dancyonanerroneouscircuitwhoseerrorbehaviorisoptimizedbyspatialredundancy.The spatialredundancyontheerrormodelisrstperformedandthenthemodiedstructureisused toperformtemporalredundancy.Thisprocedurecanbeinterpretedasperformingtemporal redundancyonacircuitwhosesensitivegateswillhaveagateerrorprobability scomparedto theless-sensitivenodeswithgateerrorprobability ,where s< .Thisredundancyscheme willhavetherelativemeritsofbothtemporalandspatialredundancyschemes. 6.4ExperimentalResults Theexperimentsareperformedusing8millionrandominputvectorsandtheprobability ofstate"1"atthecomparatoroutputs, P ( Ci= 1 ) ,areobserved.Forcircuitswithmorethan oneprimaryoutput,theoutputerrorisobservedasmaxiP ( Ci= 1 ) .Theresultsarepresented aspercentageimprovementsinmitigationofoutputerrorwithredundancyovertheoutput 95

PAGE 108

0 5 10 15 20 25 c17 Max_flat Voter Decoder Alu4 Malu4 Temporal Redundancy 5% Temporal Redundancy 15% Percentage mitigation of output error Circuits Figure6.5.Percentagemitigationofoutputerrorachievedthrough5%and15%temporal redundancywith =0.001 errorvalueswithoutredundancy.Alsoresultsfortwovaryingamountsofredundancy(5% and15%)arepresented,wherethevariationintemporalredundancyisachievedbyvarying thenumberofworst-caseinputcombinationswhileperformingTTRandvaryingthenumberofperturbednodeswhileperformingCTMR.Alltheresultspresentedinthissectionare forgateerrorprobability =0.001.CircuitsfromtheISCAS85benchmarksuiteareusedas testbenchesandtheexperimentsareperformedinaPentiumIV,2.00GHz,WindowsXP computer. 6.4.1ErrorMitigationThroughTemporalRedundancy Fig.6.5.givesthepercentagemitigationofoutputerrorachievedthrough5%and15% temporalredundancywith =0.001.Theimportantobservationsarelistedasfollows, 96

PAGE 109

€ Forallthecircuits,theerrormitigationpercentagefor15%temporalredundancy,is morethan10%.For5%temporalredundancy, c 17and voter showsignicanterror mitigationascomparedtoothercircuits. € Forsomecircuitslike c 17and max flat ,theerrormitigationpercentageisevenbeyond 20%when15%oftemporalredundancyisapplied. € Forallcircuits,theresultsclearlyshowtheimprovementinerrormitigationwhenthe amountofredundancyisincreased.Theimprovementismorethan13%incircuitslike c 17and max flat ,whileforothercircuitsitismorethan6%. 6.4.2ErrorMitigationThroughSpatialRedundancy Fig.6.6.givesthepercentagemitigationofoutputerrorachievedthrough5%and15% spatialredundancywith =0.001.Theimportantobservationsarelistedasfollows, € Signicanterrormitigationisachievedforallcircuitswith15%spatialredundancy.The errormitigationpercentageisabove20%forallthecircuitsfor15%spatialredundancy, with voter achievingalmost50%errormitigation, c 17achieving36%errormitigation and max flat malu 4achievingaround30%errormitigation. € For5%spatialredundancy,theerrormitigationpercentageismorethan10%forcircuits like c 17, max flat voter and alu 4,whileitiscloserto10%fortheothercircuits. € Theresultsclearlyshowsignicantimprovementinpercentageoferrormitigation, whenspatialredundancyisincreasedfrom5%to15%.Whiletheimprovementisas highas33%for voter ,forallthecircuitsexcept decoder ,theimprovementismorethan 15%. 97

PAGE 110

0 5 10 15 20 25 30 35 40 45 50 c17 Max_flat Voter Decoder Alu4 Malu4 Spatial Redundancy 5% Spatial Redundancy 15% CircuitsPercentage mitigation of output error Figure6.6.Percentagemitigationofoutputerrorachievedthrough5%and15%spatialredundancywith =0.001 6.4.3ErrorMitigationThroughHybridRedundancy Fig.6.7.givesthepercentagemitigationofoutputerrorachievedthrough5%and15% hybridredundancywith =0.001.5%hybridredundancyisachievedusingthecombination of5%temporaland5%spatialredundancies,while15%hybridredundancyisachievedusing thecombinationof15%temporaland15%spatialredundancies.Theimportantobservations arelistedasfollows, € Signicanterrormitigationisachievedforallcircuitswith15%hybridredundancy. Theerrormitigationpercentageisabove30%forallthecircuits,with voter achievingashighas60%errormitigation, c 17achieving51%errormitigationand max flat achievingaround47%errormitigation. € Evenfor5%hybridredundancy,theerrormitigationpercentageisashighas35%for voter ,whileitismorethan20%forthecircuitslike c 17and max flat 98

PAGE 111

0 10 20 30 40 50 60 70 c17 Max_flat Voter Decoder Alu4 Malu4 5% Hybrid (5%Spatial & 5%Temporal) 15% Hybrid (15%Spatial & 15%Temporal) CircuitsPercentage mitigation of output error Figure6.7.Percentagemitigationofoutputerrorachievedthrough5%and15%hybridredundancywith =0.001 € Theimprovementinerrormitigation,byincreasingtheamountofhybridredundancy from5%to15%,ishighlysignicantinallthecircuit.Whiletheimprovementisabove 24%incircuitslike c 17, max flat voter and malu 4,itisaround20%forthecircuits decoder and alu 4. 6.4.4ComparisonBetweentheRedundancySchemes Fig.6.8.givesthecomparisonbetweentheredundancyschemesfor5%and15%redundancywith =0.001.Theimportantobservationsarelistedasfollows, € Asexpected,hybridredundancyprovidesbettererrormitigationascomparedtotemporalandspatialredundancies.Theothernotableresultisthatspatialredundancyprovides bettererrormitigationascomparedtotemporalredundancy. 99

PAGE 112

0 5 10 15 20 25 30 c17 Max_flat Voter Decoder Alu4 Malu4 Temporal Redundancy 5% Spatial Redundancy 5% 5% Hybrid (5%Spatial & 5%Temporal) CircuitsPercentage mitigation of output error 0 10 20 30 40 50 60 70 c17 Max_flat Voter Decoder Alu4 Malu4 Temporal Redundancy 15% Spatial Redundancy 15% 15% Hybrid (15%Spatial & 15%Temporal) CircuitsPercentage mitigation of output error (a)(b) Figure6.8.Comparisonbetweentheredundancyschemesfor(a)5%and(b)15%redundancy with =0.001 € For5%redundancycase,theimprovementinerrormitigationusinghybridschemeas comparedtotemporalschemeisabove10%forcircuits c 17, max flat ,andabove18% for voter .Eventheleastimprovementisaround7%for decoder ,whiletheimprovement inothercircuitsisaround9%. € For5%redundancycase,theimprovementinerrormitigationusinghybridschemeas comparedtospatialschemeisabove10%foronly voter ,whiletheimprovementin c 17 isaround8%.Theimprovementinrestofthecircuitsislessthan7%. € For15%redundancycase,theimprovementinerrormitigationusinghybridschemeas comparedtotemporalschemeisabove20%forallcircuitsexcept decoder ,with voter showingthehighestimprovementofabout43%.Eventheleastimprovementisaround 18%for decoder € For15%redundancycase,theimprovementinerrormitigationusinghybridschemeas comparedtospatialschemeisabove10%forallthecircuitsexcept alu 4and malu 4. Thehighestimprovement,shownby max flat ,isaround16%,whiletheimprovement shownby alu 4and malu 4isabove8%. 100

PAGE 113

0 10 20 30 40 50 60 70 c17 max_flat voter decoder alu4 malu4 5%Spatial 5% Temporal 15%Spatial 5% Temporal 5%Spatial 15% Temporal 15%Spatial 15% Temporal CircuitsPercentage mitigation of output error Figure6.9.Percentagemitigationofoutputerrorachievedthroughhybridredundancywith differentcombinationsofspatialandtemporalredundancieswhile =0.001 6.4.5ErrorMitigationThroughHybridRedundancywithDifferentCombinationsof SpatialandTemporalRedundancies Fig.6.9.givesthepercentagemitigationofoutputerrorachievedthroughhybridredundancywithdifferentcombinationsofspatialandtemporalredundancieswhile =0.001.The combinationsinclude,5%spatialand5%temporal,15%spatialand5%temporal,5%spatial and15%temporal,15%spatialand15%temporal.Theimportantobservationsarelistedas follows, € Asexpected,thecombinationof15%spatialand15%temporalredundanciesyieldthe besterrormitigation,whilethecombinationof5%spatialand5%temporalredundanciesyieldtheworsterrormitigation. € Comparingthecombination15%spatialand5%temporalwiththecombination5% spatialand15%temporal,whichisexactlytheopposite,itisevidentthatproviding morespatialredundancyisbenecialforerrormitigation.Thedifferencebetweenthe 101

PAGE 114

1 1.05 1.1 1.15 1.2 1.25 1.3 1.35 5% 15% Delay Penalty (xdelay for 1 run)Temporal Redundancy 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5% 15% Area Penalty (xarea for 1 gate)Spatial Redundancy (a)(b) Figure6.10.(a)Delaypenaltyintemporalredundancy(b)Areapenaltyinspatialredundancy percentagemitigationofoutputerrorbetweenthesecombinationsisashighas18%for voter ,andmorethan10%for c 17and malu 4.Whilethedifferenceisaround8%for alu 4,itisaslowas4%for max flat and decoder 6.4.6DelayandAreaPenalties Fig.6.10.givesthedelaypenaltyduetomultiplerunswiththesameinputvectorintemporalredundancy,andtheareapenaltyduetomultiplecopiesofthesamegateinspatial redundancy.Theimportantobservationsareasfollows, € Areapenaltyismuchlargerthandelaypenalty.Whilethedelaypenaltyisjust1.1 timesthedelaywithoutredundancyfor5%temporalredundancyand1.3timesthe delaywithoutredundancyfor15%temporalredundancy,theareapenaltyis2.2times theareawithoutredundancyfor5%spatialredundancyand4.6timestheareawithout redundancyfor15%spatialredundancy. € Thisisobvioussincethedelaypenaltyisduetojust2additionalruns,whileareapenalty isdueto24additionalgates. 102

PAGE 115

6.5Discussion Wehaveperformedtemporal,spatialandhybridredundancy,usingourprobabilisticerror model,toachieveerrormitigationindigitallogiccircuits.Thepercentageoferrormitigation achievedusingallthethreetypesofredundanciesareshownthroughexperimentalresults. Onanaverage,for15%redundancy,16%errormitigationwasachievedwithtemporalredundancy,32%errormitigationwasachievedwithspatialredundancyand44%errormitigation wasachievedwithtemporalredundancy.Wehavealsoprovidedacomprehensivestudyof therelativemeritsoftheseredundancyschemes,indicatingtheeffectivenessofthehybrid redundancy,thatencapsulatesbothtemporalandspatialredundancytechniques. 103

PAGE 116

CHAPTER7 CONCLUSIONANDFUTUREDIRECTIONS Inthisdissertation,wehavepresentedreliabilitymodelsfornanoVLSIcircuitsusing probabilisticgraphsandhaveaccomplishedthefollowing, € Wehavecalculatedthe maximum erroroccurringindigitallogiccircuitsandthecorrespondingworst-caseinputcombination,throughmaximum aposteriori hypothesis, usinganefcientShenoy-Shaferalgorithm.Throughtheresultswehaveshownthe importanceofhandlingmaximumerrorbehaviorforachievingfaulttolerantcomputingmachines.Wehavealsostudiedthecircuit-specicerrorboundsforfault-tolerant computingandtheresultsclearlyshowthattheerrorboundsarehighlydependenton circuitstructureandcomputationofmaximumoutputerrorisessentialtoattainatighter bound. € Wehavecalculatedtheaverageoutputerrorin sequential digitallogiccircuitsandstudiedthetransienterrorbehavioracrossdifferenttimeinstances,usingadynamictimeevolvingprobabilisticerrormodel.Throughtheresults,wehaveshownthevulnerabilityofsequentialcircuitstotransienterrorsandthedependenceoferrorbehaviortothe circuitstructure. € Wehaveperformedtemporal,spatialandhybridredundancy,usingourprobabilisticerrormodel,toachieveerrormitigationindigitallogiccircuits.Wehaveshownsignicant errorreductionusingallthethreetechniquesandwealsohaveprovidedacomprehensivestudyoftherelativemeritsoftheseredundancyschemes,indicatingtheeffective104

PAGE 117

nessofthehybridredundancy,thatencapsulatesbothtemporalandspatialredundancy techniques. Somepossiblefuturedirectionsofthisworkareasfollows, € Thisworkcanbefurtherenhancedbyobtainingrealtimegateerrorprobability, ,values fromdevicephysicsandfabricationprocesses.Alsousingthismodeltosolvereliability issuesinreal-timetestbencheslikecircuitsusedinautomobilesandbiomedicalchips canfurtherenlargethescopeandeffectivenessofthemodel. € Tohandlelargecircuits,stochasticheuristicalgorithmstodetectbothaverageandmaximumerrorcanbeproposed.Thisworkcanserveasabaselineexactestimatetojudge theefcacyofthevariousstochasticheuristicalgorithmsthatwillbeessentialforcircuitsofhigherdimensions. € Theerrormodeltodetecterrorinsequentialcircuitscanbefurtherenhancedbyexploringerrormaskingeffects,likethelatchingwindowmaskingeffect,thatcanariseinan erroneouslatchconnectedinthefeedbackpath. € Theerrormodelscanbeenhancedbyaddressingdesignaspectsliketimingviolations leadingtodelayfaults. € Sinceourmodelcanbemoreversatile,apartfromaddressingglobalerroneousbehavior, weshouldalsoaddressspecicreliabilityissueslikesignalintegrity,bymodelingthe gateerrorprobabilityvaluesforeachgatebasedonthisspecicreliabilityissue. 105

PAGE 118

REFERENCES [1]J.VonNeumann,"ProbabilisticLogicsandtheSynthesisofReliableOrganismsfrom UnreliableComponents",in AutomataStudies (C.E.ShannonandJ.McCarthy,eds.), pages4398,PrincetonUniv.Press,Princeton,N.J.,1954. [2]F.P.MathurandA.Avi zienis,"ReliabilityAnalysisandArchitectureofaHybridRedundantDigitalSystem:GeneralizedTripleModularRedundancywithSelf-Repair", AFIPSJointComputerConferences ,pages375383,1970. [3]N.Pippenger,"ReliableComputationbyFormulasinthePresenceofNoise", IEEE TransonInformationTheory ,vol.34(2),pages194197,1988. [4]T.Feder,"ReliableComputationbyNetworksinthePresenceofNoise", IEEETranson InformationTheory ,vol.35(3),pages569571,1989. [5]B.HajekandT.Weller,"OntheMaximumTolerableNoiseforReliableComputation byFormulas", IEEETransonInformationTheory ,vol.37(2),pages388391,1991. [6]W.EvansandL.J.Schulman,"OntheMaximumTolerableNoiseofk-inputGatesfor ReliableComputationbyFormulas", IEEETransonInformationTheory ,vol.49(11), pages30943098,2003. [7]W.EvansandN.Pippenger,"OntheMaximumTolerableNoiseforReliableComputationbyFormulas", IEEETransactionsonInformationTheory ,vol.44(3),pages1299 1305,1998. [8]J.B.Gao,Y.QiandJ.A.B.Fortes,"BifurcationsandFundamentalErrorBoundsfor Fault-TolerantComputations", IEEETransactionsonNanotechnology ,vol.4(4),pages 395402,2005. [9]D.Marculescu,R.MarculescuandM.Pedram,"TheoreticalBoundsforSwitchingActivityAnalysisinFinite-StateMachines", IEEETransactionsonVLSISystems ,vol.8(3), pages335339,2000. [10]P.G.Depledge,"Fault-TolerantComputerSystems", IEEProc.A ,vol.128(4),pages 257272,1981. 106

PAGE 119

[11]S.SpagocciandT.Fountain,"FaultRatesinNanochipDevices",in Electrochemical Society ,pages354368,1999. [12]J.HanandP.Jonker,"ADefect-andFault-TolerantArchitectureforNanocomputers", Nanotechnology ,vol.14,pages224230,2003. [13]S.RoyandV.Beiu,"MajorityMultiplexing-EconomicalRedundantFault-tolerantDesignsforNanoArchitectures", IEEETransactionsonNanotechnology ,vol.4(4),pages 441451,2005. [14]K.Nikolic,A.Sadek,andM.Forshaw,"Fault-TolerantTechniquesforNanocomputers," Nanotechnology ,vol.13,pages357362,2002. [15]J.Han,E.Taylor,J.GaoandJ.A.B.Fortes,"ReliabilityModelingofNanoelectronic Circuits", IEEEConferenceonNanotechnology ,2005. [16]J.B.Gao,YanQiandJ.A.B.Fortes,"MarkovChainsandProbabilisticComputationAGeneralFrameworkforMultiplexedNanoelectronicSystems", IEEETransactionson Nanotechnology ,vol.4(2),pages395402,2005. [17]E.Taylor,J.HanandJ.A.B.Fortes,"TowardsAccurateandEfcientReliabilityModelingofNanoelectronicCircuits", IEEEConferenceonNanotechnology ,pages395398, 2006. [18]M.O.Simsir,S.Cadambi,F.Ivancic,M.RoettelerandN.K.Jha,"Fault-TolerantComputingUsingaHybridNano-CMOSArchitecture", InternationalConferenceonVLSI Design ,pages435440,2008. [19]C.ChenandY.Mao,"AStatisticalReliabilityModelforSingle-ElectronThreshold Logic", IEEETransactionsonElectronDevices ,vol.55,pages15471553,2008. [20]A.Abdollahi,"ProbabilisticDecisionDiagramsforExactProbabilisticAnalysis", IEEE/ACMInternationalConferenceonComputer-AidedDesign ,pages266272,2007. [21]M.R.ChoudhuryandK.Mohanram,"AccurateandScalableReliabilityAnalysisof LogicCircuits", Design,Automation,andTestinEurope(DATE)conference ,pages 14541459,2007. [22]S.Lazarova-Molnar,V.BeiuandW.Ibrahim,"AStrategyforReliabilityAssessment ofFutureNano-Circuits", WSEASInternationalConferenceonCircuits ,pages6065, 2007. [23]P.P.ShenoyandG.Shafer,"PropagatingBeliefFunctionswithLocalComputations", IEEEExpert ,vol.1(3),pages4352,1986. [24]P.P.Shenoy,"BinaryJoinTreesforComputingMarginalsintheShenoy-ShaferArchitecture", InternationalJournalofApproximateReasoning ,pages239263,1997. 107

PAGE 120

[25]P.P.Shenoy,"Valuation-BasedSystems:AFrameworkforManagingUncertaintyin ExpertSystems", FuzzyLogicfortheManagementofUncertainty ,pages83104,1992. [26]J.Pearl,"ProbabilisticReasoninginIntelligentSystems:NetworkofPlausibleInference",MorganKaufmannPublishers,Inc.,1988. [27]F.V.Jensen,S.LauritzenandK.Olesen,"BayesianUpdatinginRecursiveGraphical ModelsbyLocalComputation", ComputationalStatisticsQuarterly ,pages269-282, 1990. [28]R.G.Cowell,A.P.David,S.L.LauritzenandD.J.Spiegelhalter,"ProbabilisticNetworksandExpertSystems,"Springer-VerlagNewYork,Inc.,1999. [29]J.D.ParkandA.Darwiche,"SolvingMAPExactlyusingSystematicSearch", ConferenceonUncertaintyinArticialIntelligence ,2003. [30]J.D.ParkandA.Darwiche,"ApproximatingMAPusingLocalSearch", Conferenceon UncertaintyinArticialIntelligence ,pages403410,2001. [31]SensitivityAnalysis,Modeling,InferenceandMore(SAMIAM), http://reasoning.cs.ucla.edu/samiam/ ,AutomatedReasoningGroup,Universityof California,LosAngeles. [32]J.P.Roth,"DiagnosisofAutomataFailures:ACalculusandaMethod", IBMJournalof ResearchandDevelopment ,vol.10(4),pages278291,1966. [33]P.Goel,"AnImplicitEnumerationAlgorithmtoGenerateTestsforCombinationalLogic Circuits", IEEETransactionsonComputers ,vol.C-30(3),pages215222,1981. [34]H.FujiwaraandT.Shimono,"OnTheAccelerationofTestGenerationAlgorithms", IEEETransactionsonComputers ,vol.C-32(12),pages11371144,1983. [35]V.D.Agrawal,S.C.SethandC.C.Chuang,"ProbabilisticallyGuidedTestGeneration", IEEEInternationalSymposiumonCircuitsandSystems ,pages687690,1985. [36]J.Savir,G.S.DitlowandP.H.Bardell,"RandomPatternTestability", IEEETransactionsonComputers ,vol.C-33(1),pages7990,1984. [37]C.Seth,L.PanandV.D.Agrawal,"PREDICT-ProbabilisticEstimationofDigital CircuitTestability", IEEEInternationalSymposiumonFault-TolerantComputing ,pages 220225,1985. [38]S.T.Chakradhar,M.L.BushnellandV.D.Agrawal,"AutomaticTestGenerationusingNeuralNetworks", IEEEInternationalConferenceonComputer-AidedDesign ,vol. 7(10),pages416419,1988. 108

PAGE 121

[39]M.Mason,"FPGAReliabilityinSpace-FlightandAutomotiveApplications", FPGA andProgrammableLogicJournal ,2005. [40]E.ZanoniandP.Pavan,"ImprovingtheReliabilityandSafetyofAutomotiveElectronics", IEEEMicro ,vol.13(1),pages3048,1993. [41]P.Gerrish,E.Herrmann,L.TylerandK.Walsh,"ChallengesandConstraintsinDesigningImplantableMedicalICs", IEEETransactionsonDeviceandMaterialsReliability vol.5(3),pages435444,2005. [42]L.Stotts,"IntroductiontoImplantableBiomedicalICDesign", IEEECircuitsandDevicesMagazine ,pages1218,1999. [43]S.Cheemalavagu,P.Korkmaz,K.V.Palem,B.E.S.AkgulandL.N.Chakrapani,"A ProbabilisticCMOSSwitchanditsRealizationbyExploitingNoise", IFIPInternational ConferenceonVeryLargeScaleIntegration ,2005. [44]MilitaryStandard(MIL-STD-883),"TestMethodsandProceduresforMicroelectronics",1996. [45]S.Krishnaswamy,G.S.Viamontes,I.L.Markov,andJ.P.Hayes,"AccurateReliability EvaluationandEnhancementviaProbabilisticTransferMatrices", DesignAutomation andTestinEurope(DATE)Conference ,pages282287,2005. [46]J.Han,J.B.Gao,P.Jonker,Y.QiandJ.A.B.Fortes,"TowardHardware-Redundant Fault-TolerantLogicforNanoelectronics", IEEETransactionsonDesignandTestof Computers ,vol.22(4),pages328339,2005. [47]R.I.Bahar,J.Mundy,andJ.Chan,"AProbabilisticBasedDesignMethodologyfor NanoscaleComputation", InternationalConferenceonComputerAidedDesign(ICCAD) ,pages480486,2003. [48]D.BhaduriandS.K.Shukla,"NANOPRISM:AToolforEvaluatingGranularityvs. ReliabilityTrade-offsinNanoArchitectures", GreatLakesSymposiumonVLSI ,pages 109112,2004. [49]L.P.Yuan,C.C.TengandS.M.Kang,"StatisticalEstimationofAveragePowerDissipationinSequentialCircuits," DesignAutomationConference(DAC) ,pages377382, 1997. [50]HUGINInferenceTool, http://www.hugin.com/ ,HUGINEXPERTA/S,Aalborg,Denmark. [51]N.M.ZivanovandD.Marculescu,"SoftErrorRateAnalysisforSequentialCircuits", DesignAutomationandTestinEurope(DATE)Conference ,pages16,2007. 109

PAGE 122

[52]J.J.ShedletskyandE.J.McCluskey,"TheErrorLatencyofaFaultinaSequential DigitalCircuit", IEEETransactionsonComputers ,vol.C-25(6),pages655659,1976. [53]S.Y.Huang,K.T.Cheng,K.C.ChenandJ.Y.Lu,"Fault-SimulationBasedDesign ErrorDiagnosisforSequentialCircuits", DesignAutomationConference(DAC) ,pages 632637,1998. [54]H.AsadiandM.B.Tahoori,"SoftErrorModelingandProtectionforSequentialElements", IEEEInternationalSymposiumonDefectandFaultToleranceinVLSISystems pages463471,2005. [55]R.Baumann,"SoftErrorsinAdvancedComputerSystems", IEEEDesignandTestof Computers ,vol.22(3),pages258266,2005. [56]M.ZhangandN.R.Shanbag,"ASoftErrorRateAnalysis(SERA)Methodology", InternationalConferenceonComputerAidedDesign(ICCAD) ,pages111118,2004. [57]S.WinogradandJ.D.Cowan,"ReliableComputationinthePresenceofNoise", The MITPress ,1963. [58]G.Norman,D.Parker,M.KwiatkowskaandS.K.Shukla,"EvaluatingtheReliabilityof Defect-TolerantArchitecturesforNanotechnologywithProbabilisticModelChecking", InternationalConferenceonVLSIDesign ,pages907912,2004. [59]InternationalTechnologyRoadmapforSemiconductors(ITRS), http://www.itrs.net/Links/2005ITRS/ERD2005.pdf ,2005. [60]G.E.Moore,"CrammingMoreComponentsontoIntegratedCircuits", Electronics ,vol. 38(8),1965. [61]L.B.Kish,"EndofMoore'sLaw:Thermal(Noise)DeathofIntegrationinMicroand NanoElectronics", PhysicsLettersA ,vol.305(34),pages144149,2002. [62]C.W.Gwyn,D.L.ScharfetterandJ.L.Wirth,"TheAnalysisofRadiationEffects inSemiconductorJunctionDevices", IEEETransactionsonNuclearScience ,vol.NS14(6),pages153169,1967. [63]D.C.DAvanzo,M.VanziandR.W.Dutton,"One-DimensionalSemiconductorDevice Analysis, Tech.Rep.no.G-201-5 ,StanfordElectronicsLaboratories,StanfordUniversity,1979. [64]S.Selberherr,W.FichtnerandH.W.Potzl,"MINIMOS-AProgramPackagetoFacilitateMOSDeviceDesignandAnalysis", NASECODEI ,pages275279,1979. [65]P.E.CottrellandE.M.Buturla,"Two-DimensionalStaticandTransientSimulationof MobileCarrierTransportinaSemiconductor, NASECODEI ,pages3164,1979. 110

PAGE 123

[66]E.M.Buturla,P.E.Cottrell,B.M.Grossman,K.A.Salsburg,M.B.LawlorandC.T. McMullen,"Three-DimensionalFiniteElementSimulationofSemiconductorDevices", IEEEInt.SolidStateCircuitsConf.Dig.Tech.Papers ,pages7677,1980. [67]M.R.Pinto,C.S.RaffertyandR.W.Dutton,"PISCES-II:PoissonandContinuityEquationSolver", StanfordElectronicsLaboratories ,1984. [68]P.E.Dodd,"DeviceSimulationofChargeCollectionandSingle-EventUpset", IEEE TransactionsonNuclearScience ,vol.43(2),pages561575,1996. [69]G.R.Srinivasan,H.K.TangandP.C.Murley,"Parameter-Free,PredictiveModeling ofSingleEventUpsetsduetoProtons,NeutronsandPionsinTerrestrialCosmicRays", IEEETransactionsonNuclearScience ,vol.41(6),pages20632070,1994. [70]M.R.Choudhury,Q.ZhouandK.Mohanram,"DesignOptimizationforSingle-Event UpsetRobustnessusingSimultaneousDual-VDDandSizingTechniques", International ConferenceonComputerAidedDesign(ICCAD) ,pages204209,2006. [71]K.BhattacharyaandN.Ranganathan,"ANewPlacementAlgorithmforReductionof SoftErrorsinMacroCellbasedDesignofNanometerCircuits", IEEEComputerSociety AnnualSymposiumonVLSI(ISVLSI) ,pages9196,2009. [72]N.Miskov-ZivanovandD.Marculescu,"MARS-C:ModelingandReductionofSoft ErrorsinCombinationalCircuits", DesignAutomationConference(DAC) ,pages767 772,2006. [73]P.K.Samudrala,J.RamosandS.Katkoori,"SelectiveTripleModularRedundancy (STMR)BasedSingle-Event-Upset(SEU)TolerantSynthesisforFPGAs", IEEETransactionsonNuclearScience ,vol.51(5),pages29572969,2004. [74]W.A.Moreno,J.R.SamsonJr.andF.J.Falquez,"LaserInjectionofSoftFaultsfor theValidationofDependabilityDesign", JournalofUniversalComputerScience ,vol. 5(10),pages712729,1999. [75]ParisD.Wiley,"FaultTolerantDesignVericationThroughTheUseofLaserFault Injection", MastersThesis,DepartmentofElectricalEngineering,UniversityofSouth Florida ,2004. [76]A.Sanyal,S.M.AlamandS.Kundu,"ABuilt-InSelf-TestSchemeforSoftErrorRate Characterization", IEEEInternationalOn-LineTestingSymposium ,pages6570,2008. [77]S.BhanjaandN.Ranganathan,"SwitchingActivityEstimationofVLSICircuitsusing BayesianNetworks", IEEETransactionsonVLSISystems ,pages558567,2003. [78]S.BhanjaandN.Ranganathan,"CascadedBayesianInferencingforSwitchingActivity EstimationwithCorrelatedInputs", IEEETransactiononVLSISystems ,vol.12(12), pages13601370,2004. 111

PAGE 124

[79]S.BhanjaandN.Ranganathan,"ModelingSwitchingActivityUsingCascadedBayesian NetworksforCorrelatedInputStreams", InternationalConferenceonComputerDesign (ICCD) ,pages388390,2002. [80]S.BhanjaandN.Ranganathan,"AccurateSwitchingActivityEstimationofLargeCircuitsusingMultipleBayesianNetworks", 15thIntl.ConferenceofVLSIDesignand7th ASP-DesignandAutomationConference ,pages187192,2002. [81]S.BhanjaandN.Ranganathan,"DependencyPreservingProbabilisticModelingof SwitchingActivityusingBayesianNetworks", IEEE/ACMDesignAutomationConference(DAC) ,pages209214,2001. [82]S.BhanjaandS.Sarkar,"ProbabilisticModelingofQCACircuitsusingBayesianNetworks", IEEETransactionsonNanotechnology ,vol.5(6),pages657670,2006. [83]S.BhanjaandS.Sarkar,"SwitchingErrorModesofQCACircuits", IEEEConference onNanotechnology ,vol.1,pages383386,2006. [84]S.BhanjaandS.Sarkar,"GraphicalProbabilisticInferenceforGroundStateandNearGroundStateComputinginQCACircuits", IEEEConferenceonNanotechnology ,pages 290293,2005. [85]T.RejimonandS.Bhanja,"ATiming-AwareProbabilisticModelforSingle-Event-Upset Analysis", IEEETransactionsonVLSISystems ,vol.14(10),pages11301139,2006. [86]T.RejimonandS.Bhanja,"ProbabilisticErrorModelforUnreliableNano-logicGates", IEEEConferenceonNanotechnology ,pages717722,2006. [87]T.RejimonandS.Bhanja,"TimeandSpaceEfcientMethodforAccurateComputation ofErrorDetectionProbabilities", IEEComputersandDigitalTechniques ,vol.152(5), pages679685,2005. [88]T.RejimonandS.Bhanja,"AStimulus-FreeProbabilisticModelforSingle-Event-Upset Sensitivity", IEEEIntl.ConferenceonVLSIDesign ,2006. [89]T.Rejimon,L.HoffmannandS.Bhanja,"AProbabilisticModelforSingle-EventUpset", 12thNASASymposiumonVLSI ,2005. [90]T.RejimonandS.Bhanja,"AnAccurateProbabilisticModelforErrorDetection", 18th InternationalConferenceinVLSIDesign ,pages717722,2005. [91]T.RejimonandS.Bhanja,"ScalableProbabilisticComputingModelsusingBayesian Networks", IEEEMidwestSymposiumonCircuitsandSystems ,pages712715,2005. [92]S.RamaniandS.Bhanja,"AnytimeProbabilisticSwitchingModelusingBayesianNetworks," InternationalSymposiumonLowPowerElectronicDesign ,pages8689,2004. 112

PAGE 125

[93]N.RamalingamandS.Bhanja,"CausalProbabilisticInputDependencyLearningfor SwitchingModelinVLSICircuits", ACMGreatLakeSymposiumonVLSI ,pages112 115,2005. [94]S.SrivastavaandS.Bhanja,"HierarchicalProbabilisticMacromodelingforQCACircuits", IEEETransactionsonComputers ,vol.56(2),pages174190,2007. [95]S.SrivastavaandS.Bhanja,"BayesianMacromodelingforCircuitLevelQCADesign", IEEEConferenceonNanotechnology ,pages3134,2006. [96]S.SrivastavaandS.Bhanja,"HierarchicalBayesianMacromodelingforQCACircuits", 12thNASASymposiumonVLSI ,2005. [97]S.BhanjaandS.Srivastava,"BayesianModelingofQuantum-dotCellularAutomata Circuits", NSTI,NanotechnologyConference ,2005. [98]S.Bhanja,K.LingasubramanianandN.Ranganathan,"AStimulus-FreeGraphicalProbabilisticSwitchingModelforSequentialCircuitsusingDynamicBayesianNetworks", ACMTransactionsonDesignAutomationofElectronicSystems ,vol.11(3),pages773 796,2006. [99]T.Rejimon,K.LingasubramanianandS.Bhanja,"ProbabilisticErrorModelforNanoDomainLogicCircuits", IEEETransactionsonVLSI ,vol.17(1),pages5565,2008. [100]K.LingasubramanianandS.Bhanja,"ProbabilisticMaximumErrorModelingforUnreliableLogicCircuits", ACMGreatLakeSymposiumonVLSI ,pages223226,2007. [101]K.LingasubramanianandS.Bhanja,"ProbabilisticErrorModelingforSequential Logic", IEEEInternationalConferenceonNanotechnology ,pages616620,2007. [102]K.LingasubramanianandS.Bhanja,"AnErrorModeltoStudytheBehaviorofTransientErrorsinSequentialCircuits", IEEEInternationalConferenceonVLSIDesign pages485490,2009. [103]A.Shareef,K.LingasubramanianandS.Bhanja,"SelectiveRedundancy:Evaluation ofTemporalReliabilityEnhancementSchemeforNanoelectronicCircuits", IEEEConferenceonNanotechnology ,pages895898,2008. [104]S.Bhanja,K.LingasubramanianandN.Ranganathan,"EstimationofSwitchingActivityinSequentialCircuitsUsingDynamicBayesianNetworks", 18thInternational ConferenceinVLSIDesign ,pages586591,2005. 113

PAGE 126

ABOUTTHEAUTHOR KarthikeyanLingasubramanianreceivedtheB.E.degreeinelectronicsandcommunicationengineeringfromKumaraguruCollegeofTechnology,India,in2001.Hereceived hisM.S.degreeinelectricalengineeringfromUniversityofSouthFlorida,Tampa,USA,in 2004,whereheiscurrentlypursuingthePh.D.degreeinelectricalengineering.Hisresearch interestsincludedesignautomationandtesting,comprehensivenano-domainprobabilisticand statisticalmodelsforestimationandoptimizationoferrorandpower.


xml version 1.0 encoding UTF-8 standalone no
record xmlns http:www.loc.govMARC21slim xmlns:xsi http:www.w3.org2001XMLSchema-instance xsi:schemaLocation http:www.loc.govstandardsmarcxmlschemaMARC21slim.xsd
leader nam 22 Ka 4500
controlfield tag 007 cr-bnu---uuuuu
008 s2010 flu s 000 0 eng d
datafield ind1 8 ind2 024
subfield code a E14-SFE0003469
035
(OCoLC)
040
FHM
c FHM
049
FHMM
090
XX9999 (Online)
1 100
Lingasubramanian, Karthikeyan.
0 245
Probabilistic error analysis models for nano-domain vlsi circuits
h [electronic resource] /
by Karthikeyan Lingasubramanian.
260
[Tampa, Fla] :
b University of South Florida,
2010.
500
Title from PDF of title page.
Document formatted into pages; contains X pages.
Includes vita.
502
Dissertation (Ph.D.)--University of South Florida, 2010.
504
Includes bibliographical references.
516
Text (Electronic dissertation) in PDF format.
538
Mode of access: World Wide Web.
System requirements: World Wide Web browser and PDF reader.
3 520
ABSTRACT: Technology scaling to the nanometer levels has paved the way to realize multi-dimensional applications in a single product by increasing the density of the electronic devices on integrated chips. This has naturally attracted a wide variety of industries like medicine, communication, automobile, defense and even house-hold appliance, to use high speed multi-functional computing machines. Apart from the advantages of these nano-domain computing devices, their usage in safety-centric applications like implantable biomedical chips and automobile safety has immensely increased the need for comprehensive error analysis to enhance their reliability. Moreover, these nano-electronic devices have increased propensity to transient errors due to extremely small device dimensions and low switching energy. The nature of these transient errors is more probabilistic than deterministic, and so requires probabilistic models for estimation and analysis. In this dissertation, we present comprehensive analytic studies of error behavior in nano-level digital logic circuits using probabilistic reliability models. It comprises the design of exact probabilistic error models, to compute the maximum error over all possible input space in a circuit-specific manner; to study the behavior of transient errors in sequential circuits; and to achieve error mitigation through redundancy techniques. The model to compute maximum error, also provides the worst-case input vector, which has the highest probability to generate an erroneous output, for any given logic circuit. The model for sequential logic that can measure the expected output error probability, given a probabilistic input space, can account for both spatial dependencies and temporal correlations across the logic, using a time evolving causal network. For comprehensive error reduction in logic circuits, temporal, spatial and hybrid redundancy models, are implemented. The temporal redundancy model uses the triple temporal redundancy technique that applies redundancy in the input space, spatial redundancy model uses the cascaded triple modular redundancy technique that applies redundancy in the intermediate signal space and the hybrid redundancy techniques encapsulates both temporal and spatial redundancy schemes. All the above studies are performed on standard benchmark circuits from ISCAS and MCNC suites and the subsequent experimental results are obtained. These results clearly encompasses the various aspects of error behavior in nano VLSI circuits and also shows the efficiency and versatility of the probabilistic error models.
590
Advisor: Sanjukta Bhanja, Ph.D.
653
Reliability
Worst-case input
Sequential circuits
Redundancy models
690
Dissertations, Academic
z USF
x Electrical Engineering
Doctoral.
773
t USF Electronic Theses and Dissertations.
4 856
u http://digital.lib.usf.edu/?e14.3469