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Stress-strain management of heteroepitaxial polycrystalline silicon carbide films

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Title:
Stress-strain management of heteroepitaxial polycrystalline silicon carbide films
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English
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Locke, Christopher William
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University of South Florida
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Subjects / Keywords:
Chemical Vapor Deposition
Heteroepitaxy
Polysilicon
Residual Stress
Silicon Carbide
Dissertations, Academic -- Electrical Engineering Materials Science -- Doctoral -- USF   ( lcsh )
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bibliography   ( marcgt )
non-fiction   ( marcgt )

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ABSTRACT: Silicon carbide (SiC) is one of the hardest known materials and is also, by good fortune, a wide bandgap semiconductor. While the application of SiC for high-temperature and high-power electronics is fairly well known, its utility as a highly robust, chemically-inert material for microelectrical mechanical systems (MEMS) is only beginning to be well recognized. SiC can be grown on both native SiC substrates or on Si using heteroepitaxial growth methods which affords the possibility to use Si micromachining methods to fabricate advanced SiC MEMS devices. The control of film stress in heteroepitaxial silicon carbide films grown on polysilicon-on-oxide substrates has been investigated. It is known that the size and structure of grains within polycrystalline films play an important role in determining the magnitude and type of stress present in a film, i.e. tensile or compressive. Silicon carbide grown on LPCVD polysilicon seed-films exhibited a highly-textured grain structure and displayed either a positive or negative stress gradient depending on the initial thickness of the polysilicon seed-layer. In addition a high-quality (111) oriented 3C-SiC on (111)Si heteroepitaxial process has been developed and is reported. SiC MEMS structures, both polycrystalline (i.e., poly-3C-SiC) and monocrystalline (i.e., 3C-SiC) were realized using micromachining methods. These structures were used to extract the stress properties of the films, with a particular focus on separating the gradient and uniform stress components.
Thesis:
Disseration (Ph.D.)--University of South Florida, 2011.
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Includes bibliographical references.
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by Christopher William Locke.
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Document formatted into pages; contains 125 pages.
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Includes vita.

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Stress Strain Management of Heteroepitaxial Polycrystalline Silicon Carbide Films by Christopher Locke A dissertation submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy Department of Electrical Engine ering College of Engineering University of South Florida Major Professor: Stephen E. Saddow, Ph.D. Andrew M. Hoff, Ph.D. Sylvia Thomas, Ph.D. Rasim Guldiken, Ph.D. Andrea Severino, Ph.D. Date of Approval: March 28, 2011 Keywords: S ilicon C ar bide, H eteroepitaxy, R esidual S tress, C hemical V apor D eposition, P olysilicon Copyright 2011, Christopher Locke

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ACKNOWLEDGEMENTS I have reached a milestone in my life that would not have been realized without the nurturing support of those whom bel ieved in me. First, I would like to thank my parents, Pete and Sandy, and sisters, Kimberly and Sara, who have always been at my side providing the unconditional love and support which has fostered my spirit to drive through the difficult times. I would like to thank my advisor, Dr. Stephen Saddow, who believed in me and supported me through my graduate years, both as mentor and friend. I have been truly blessed to have been guided by such a magnificent person. A great deal of appreciation is owed to Dr Andrew Hoff who has helped with my research and has been so generous to offer me a teaching assistant position. Many thanks are owed to Dr. Sylvia Thomas, Dr. Andrea Severino, Dr. Guldiken, and Dr. Ashok Kumar for their much appreciated support. I wou ld like to thank my friend Dr. Chris Frewin for his unyielding loyalty and his gracious generosity t hat help ed me get to this milestone. I would like to express my grat itude for the invaluable services and advice that Robert Tufts and Richard Everly have provided me over the years. Many thanks to Dr. Francesco LaVia, Ruggero Anzalone, Cor r ado Bon giorno, Massimo Camarda at IMM CNR. I would like to extend my thanks to Dr. John Bumgarner and Dr. Priscila Spagnol for their valuable contribution during the e arly development of the polysilicon on oxide stack. I would like to thank Dr. Submaranian “Subbu” Krishnan and Dr. Sunil Arya for offering their services and facility. And a final heartfelt thank you to my engineering family the SiC Group!

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i TABLE OF CONTENTS LIST OF TABLES i ii LIST OF FIGURES i v ABSTRACT vii CHAPTER 1 SILICON CARBIDE: A MATERIAL FOR MICROELECTROMECHANICAL SYSTEMS (MEMS) 1 1.1 Introduction 1 1.2 Heteroepitaxial Silicon Carbide 4 1.2.1 Why Heteroepitaxial Silicon Ca rbide? 6 1. 2.2 F abrication of Silicon Carbide MEMS 8 1.2.3 Stress Induced Deformation of Heteroepitaxial Films 1 1 1.3 Polysilicon on Oxide Substrates for Heteroepitaxial Silicon Carbide 1 2 1.4 Influence of Polysilicon Seed Layer Thickn ess on Silicon Carbide Film Stress 1 4 1.5 Overview of the Organization of This Dissertation 1 6 CHAPTER 2 H ETEROEPITAXIAL SILICON CARBIDE STRUCTURE, GROWTH, AND THIN FILM MECHANICS 1 7 2.1 Crystal Structure of Silicon Carbide 1 7 2.2 Overview of CVD 1 9 2.2.1 Early Stages of CVD Film Growth 2 2 2.3 Overview of Heteroepitaxial Defects 2 4 2.3.1 Line Defects 2 4 2. 3.2 Planar Defects 2 6 2.3.3 Grain Boundaries 3 2 2.4 Structural Evolution of Polycrystalline Thin Films 33 2. 5 Mechanical Pr operties of Thin Films 34 2.5.1 Sources of Stress es in Thin Films 35 2.5.2 Stress Control of Polycrystalline Silicon Carbide Films via CVD Process Parameters 3 7 2. 5.3 Analysis of Thin Film Stress 45 2.5.3.1 Stoney Equation 46 2.5.3.2 Can tilever Deflection 50 2.5.3.3 Plana r Rotating Beam 5 3

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ii 2.6 CVD Reactor Hardware 5 5 CHAPTER 3 DEVE LOPMENT OF LOW TEMPERATURE POLY SiC GROWTH PROCESS FOR POLY Si ON OXIDE SUBSTRATES 5 8 3.1 Motivation for Reducing Process Temperature 59 3.2 Low Te mperature Process Development 6 0 3.2.1 Low Temperature Baseline Process 6 1 3.2.2 Optimized Low Temperature Process 6 4 3.3 Poly SiC Growth on Poly Si on Oxide Substrates 6 7 3.3.1 Motivation for 3C SiC Growth on Oxide Layers 6 8 3.3.2 Deposition of Poly Si Layer on SiO 2 / (111)Si 7 0 3.3.3 Poly silicon Carbide Growth Process 7 1 3.4 Analysis of the Poly SiC on Oxide Film 7 3 3.4.1 AFM Analysis 7 3 3.4.2 XRD Analysis 7 5 3.5 Summary 7 7 CHAPTER 4 I NFLUENCE OF POLYSILICON SEED LAYER THICKNES S ON POLY SiC RESIDUAL STRESS 79 4.1 Fabrication of SiC MEMS on an O xide R elease L ayer 8 1 4.1.1 Test Growth on Patterned Polysilicon on Oxide Substrates 8 2 4.1.2 Poly SiC MEMS Fabrication Procedure 8 4 4.2 Film Morphology 8 7 4.3 Stress Stra in Analysis 89 CHAPTER 5 SUMMARY AND FUTURE WORKS 9 6 5 .1 Summary 9 6 5 .2 Future Work 9 8 5 .2.1 3C SiC Growth on SOI Substrates 9 9 5 .2.2 Residual Stress Characterization 100 5.2.3 MEMS Fabrication 10 1 REFERENCES 10 3 APPENDICES 111 A pp endix A M echanics of the B iaxial D eflection of a Plate 1 12

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iii LIST OF TABLES Table 1.1 Properties of commonly used SiC polytypes compared with Si and Diamond. 3 Table 4.1 Maximum stress gradient values from cantilever deflection mea surements acquired via optical profilometry 9 5

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iv LIST OF FIGURES Figure 1.1 Illustration of the affect of lattice mismatch in heteroepitaxy 5 Figure 1.2 Schematic representation of antiphase domain boundary (APB) annihilati on with film thickness 7 Figure 1.3 Fabrication of a free standing cantilever 10 Figure 2.1 Four examples of SiC polytype stacking sequences 1 8 Figure 2.2 Sc h ematic diagram of mechanistic steps which occur during the CVD pr ocess 20 Figure 2.3 Generalized process trend showing the dependence of process temperature and pressure on growth rate via CVD 21 Figure 2.4 (a) flat susceptor design, and (b ) tilted susceptor design 2 2 Figure 2.5 Stacking faults revealed in a (100)3C SiC film via PV TEM. SF density estimated to be ~ 5x10 4 cm 1 2 7 Figure 2.6 Example of hetero defects in (100)3C SiC from X TEM 2 8 Figure 2.7 Schematic representa tion of micro twin defect in SiC on Si heteroep itaxy 2 9 Figure 2.8 Micro twinned crystal defect (dark cluster in center of micrograph) observed with plan view TEM (PV TEM) 2 9 Figure 2.9 Geometrical consideration of the formation of an APB when SiC is grown on (100)Si substrate with an atomic step 30 Figure 2.10 S tacking fault generation schematic showing the error in crystal layer formation resulting in a stacking fault defect 31 Figure 2.1 1 Evolution of grain structure with film gro wth 34

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v Figure 2.1 2 Relationship of the DCS fraction in the gas mixture to, (a) the residual film stress and, (b) the strain gradient 38 Figure 2.1 3 Results using DCS to control residual stress in poly SiC films 39 Figure 2.1 4 Residual stres s versus deposition pressure trends for poly SiC 42 Figure 2.1 5 Poly SiC residual film stress and growth rate vs. temperature at 0.17 Torr deposition pressure 43 Figure 2.1 6 The use of tailored N 2 doping during poly SiC deposition to control fil m strain 45 Figure 2. 17 The generation of biaxially deformed film substrate system from, (a) an initially stress free system 4 7 Figure 2. 18 Illustration of a cantilever structure with length, “L”, width,” b”, and thickness, “h” 5 0 Figure 2. 19 Stress states present in a thin film cantilever far from the anchor point 5 2 Figure 2.2 0 Schematic illustration of a conventional planar micro rotating structure (Drieenhuizen 1993) used to measure strain gradient in a thin film 5 4 Figure 2.2 1 Photograph of the MF2 CVD horizontal reactor at USF 5 7 Figure 3.1 Initial baseline low temperature (1200 C) CVD growth process schedule 6 2 Figure 3.2 Plot of the deposition rate vs. inverse temperature using the optimized low temperature/ low pressure growth process at various growth temperatures 6 7 Figure 3.3 AFM micrographs of the surfaces of the SiC deposition grown on (a) poly Si/ SiO 2 / (111)Si, (b) (111)Si, and (c) (100)Si 7 4 Figure 3.4 Cross section SEM micrograph of a 3C SiC film grown on the poly Si/ SiO 2 / (111)Si compliant stack 7 5 Figure 3.5 SiC films grown on (a) poly Si/ SiO 2 / (111)Si, (b) (111)Si, and (c) (100)Si substrates 7 6 Figure 4.1 Stress as a function of deposition temperature for polysilicon films 8 0

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vi Figure 4.2 (a) Mask layout details of the first test mask consisting of cantilevers/ combs, bridges, and planar rotators of various dimensions 8 2 Figure 4.3 Optical micrographs of 3C SiC grown on the patterned poly Si/ SiO 2 / (111)Si substrates 8 3 Figure 4.4 Summary of the patte rning of anchor points for the SiC based MEMS structures prior to epitaxial growth of the 3C SiC 8 5 Figure 4.5 A polysilicon on oxide substrate after poly SiC deposition 8 6 Figure 4.6 Optical image of the patterned and dry etched poly SiC 8 7 Figure 4.7 Top: Atomic force microscopy (AFM) scans of the polysilicon seed layer (a) 20nm thick and, (b) 100nm thick 89 Figure 4.8 SEM images viewed from a 45 tilt of poly SiC cantilevers fabricated from poly SiC grown on polysilicon on oxide usi ng a (a) 20 nm thick seed layer and, (b) 100 nm thick seed layer 91 Figure 4.9 SEM images taken at a 45 tilt angle of planar rotator structures displaying the stress gradients present in (a) poly SiC film grown on a 20 nm polysilicon seed layer (b) poly SiC grown on a 100 nm polysilicon seed layer 91 Figure 4.10 SEM image of the cantilevers from Figure 4.8(a) and the planar rotator structures from Figure 4.10(a) 92 Figure 4.11 Schematic of an optical profilometer 9 4 Figure 4. 12 Op ti cal profilometer data of poly SiC cantilevers micromachined from poly SiC grown from (a) a 20 nm poly Si seed layer and, (b) a 100 nm thick poly Si seed layer 9 5 Figure A.1 (a) Schematic of a bending moment applied to a plate and a cross section d iagram (b) showing the resulting stress gradient 1 12 Figure A.2 Geometric parameters defining a simply bent beam 11 5 Figure A.3 Cantilever deformed by a bending moment 11 6

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vii A BSTRACT Silicon carbide (SiC) is one of the hardest known materia ls and is also, by good fortune, a wide bandgap semiconductor. While the application of SiC for high temperature and high power electronics is fairly well known, its utility as a highly robust, chemically inert material for microelectrical mechanical syst ems (MEMS) is only beginning to be well recognized. SiC can be grown on both native SiC substrates or on Si using heteroepitaxial growth methods which affords the possibility to use Si micromachin in g methods to fabricate advanced SiC MEMS devices. The cont rol of film stress in heteroepitaxial silicon carbide films grown on polysilicon on oxide substrates has been investigated. It is known that the size and structure of grains within polycrystalline films play an important role in determining the magnitude and type of stress present in a film, i.e. tensile or compressive. Silicon carbide grown on LPCVD polysilicon seed films exhibited a highly textured grain structure and displayed either a positive or negative stress gradient depending on the initial thick ness of the polysilicon seed layer. In addition a high quality (111) oriented 3C SiC on (111)Si heteroepitaxial process has been developed and is reported. SiC MEMS structures, both polycrystalline (i.e., poly 3C SiC) and monocrystalline (i.e., 3C SiC) we re realized using micromachin in g methods. These structures were used to extract the stress properties of the films, with a particular focus on separating the gradient and uniform stress components.

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1 CHAPTER 1: SILICON CARBIDE: A MATERIAL FOR MICROELECT ROMECHANICAL SYSTEMS (MEMS) 1.1 Introduction Although silicon is a well suited material for a wide range of sensor and actuator applications, it is limited for electronic devices at temperatures below 250C. In addition its mechanical properties begin to degrade at temperatures above 600C (Mehregany, 1998) which limit its use for high temperature and harsh environment applications. Consequently when silicon based MEMS technology is used in harsh environments, the expensive and bulky cooling and packagin g systems that need to be implemented in order to keep the devices within operating limits are expensive or sometimes prohibitive. As the demand grows to implement cost saving and space saving microsensor and microactuator technologies in harsh environmen ts, one must look for other material options that can satisfy the requirement of long term device survivability and low production costs. To meet the demands for high temperature ( a need for an electronic material exhibiting a wide bandgap, good mechanical (and chemical) stability, and good thermal stability over a large temperature range. An ideal material platform for harsh environment MEMS would also exhibit an extensive range of robustness that would withstand a multitude of en vironments. It would be chemically inert to corrosive attack, it would exhibit outstanding wear resistance, it would

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2 demonstrate radiation hardness (i.e., rad hard), and it could be biologically implantable. Although this may appear to be an unrealistic “wish list”, there are material candidates that seem to meet these demanding criteria. Diamond is one such candidate that is currently being explored. It is the hardest known natural material, scoring a 10 on the Mohs hardness scale. It has the highest thermal conductivity of any known material; five times greater than silver, the second highest thermal conductor. It has a wide band gap and can be doped to exhibit semiconductor properties. It has excellent thermal and mechanical stability, except in hi gh temperature ( surface turns to graphite). This drawback excludes it for use as a material for combustion microsensors. Therefore diamond based MEMS have found limited use, mostly in low temperature RF applications and in biomedical applications as a coating for Si based sensors and devices. Silicon Carbide (SiC) is another candidate that appears to fulfill the requirements of a MEMS platform material for a multitude of harsh environmenta l conditions. It has long been recognized as a semiconductor with excellent physical, electrical and chemical characteristics (see Table 1.1). It has excellent mechanical and electrical stability at high temperatures. It is inert to nearly all wet chemi stry, and it can only be etched by molten alkaline hydroxides at temperatures at temperatures exceeding 1800C. Silicon carbide demonstrates excellent wear resistance, having a 9.15 wear resistance ratin g as compared to 10 for diamond. It is the third hardest known material, only diamond and boron nitride exceed it. Silicon carbide can be thermally oxidized to form a passivating SiO 2 layer, although the oxidation rate is

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3 slow when compared to silicon. Surface passivation using a hydrogen terminated surface has been shown to form flatband conditions for several hours (C. Coletti 2008) 100mm diameter silicon carbide wafers grown from bulk crystals are commercially available from several manufacturers; 1 50mm wafers with defect densities less than 10 cm 2 have been recently reported. Monocrystalline and polycrystalline silicon carbide has been epitaxially grown on silicon substrates up to 150mm in diameter. Table 1.1 Properties of commonly used SiC poly types compared with Si and Diamond. (Casady and Johnson 1996) (Harris 1995) Property 4H SiC 6H SiC 3C SiC Si Diamond Energy bandgap at 300K 3.20 3.00 2.29 1.12 5.45 Intrinsic Carrier Concentration at 300K (cm 3 ) 5x10 9 1.6x10 6 1.5x10 1 1x10 10 ~ 10 27 Critical breakdown electric field (MV/cm) 2.2 2.5 2.12 0.25 1 10 Saturated electron drift velocity (x 10 7 cm/s) 2.0 2.0 2.5 1.0 1.5 Electron mobility (cm 2 /V s) 1000 600 800 1450 480 Hole mobility (cm 2 /V s) 115 100 40 470 1600 Thermal Conductivit y at 300K (W cm 1 K 1 ) 3.7 3.6 3. 6 1.49 6 20 Coefficient of Thermal Expansion at 300K (10 6 K 1 ) 4.3 c 4.7 c 4.3 c 4.7 c 3.2 3.0 1.0 Lattice constant (a, c in ) a=3.0730 c=10.053 a=3.0806 c=15.1173 a=4.3596 a=5.430 a=3.5668 Elastic coefficient* (GPa) *calculated C 44 =600 C 11 =500 C 12 =92 C 44 =168 C 11 =352 C 12 =120 C 44 =233 C 11 =167 C 12 =65 C 44 =80 C 11 =1 079 C 12 = 124 C 44 = 578

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4 1.2 Heteroepitax ial Silicon Carbide Epitaxy is the growth of a thin layer on a crystal substrate in which the substrate is a template for the growth such that the proper atomic arrangement is achieved. Heteroepitaxy is the growth of an epitax ial layer on a seed crystal of a different crystal type. Cubic SiC, more commonly referred to as 3C SiC, may be heteroepitaxially grown on Si substrates. Since the growth of single crystal, large area, bulk 3C SiC crystals has not been demonstrated, hete roepitaxy is needed to grow 3C SiC crystals. However, the near 20% lattice mismatch between Si and SiC typically leads to an epitaxial film that is highly defective and therefore not suitable for electronic devices. This is generally because interfacial defects propagate into the 3C SiC device layer and result in high leakage currents in 3C SiC/Si devices. Indeed, the issues impeding the growth of high quality, monocrystalline 3C SiC/Si heteroepitaxial films have proven to be so difficult to overcome tha t many groups have abandoned 3C SiC/Si. In this thesis, we aim to use a novel substrate alongside a tailored stoichiometric bilayer structure to mitigate film stresses arising from defects with the goal of developing device quality 3C SiC/Si layers.

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5 Figure 1. 1 Illustration of the effect of lattice mismatch in heteroepitaxy. The denotes the location of a missing row of atoms which is known as a line defect. Note the stretched and compressed covalent bonds at the interface resulting from the lattice mismatch between the two crystals. [ref] As seen in the above figure, there is a strain in the epilayer from an attempt by the epilayer ( a 3C SiC = 4.3596) to accommodate the substrate’s lattice constant (a Si = 5.43095) (Harris 1995) The attempt to accommodate the mismatch not only produces crystal defects, but these defects in the epitaxial layer have a mosaic morphology in the case of the (100)3C SiC/(100)Si system. While a carbonization step is normally employed which converts the starting Si sur face to SiC and acts as a buffer layer to reduce the stress, this does not completely accommodate the lattice mismatch. With this buffer layer, there are still a fair amount of dislocations which must be reduced if 3C SiC is to be useful for electronic de vices such as MOSFETs. One of the most successful methods to grow 3C SiC is by chemical vapor deposition (CVD). The standard precursor chemistry typically used is the silane propane hydrogen gas system. Although extensive work has been performed since t he early 1980’s, there is still a lack of good quality 3C SiC on Si epitaxial material. While 3C SiC Si 3C SiC Si

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6 growth rates up to 40 m/h on undulant Si (100) substrates by cold wall CVD have been reported to produce SiC substrates with near bulk quality, defects originat ing from the undulant substrate persist (Nagasawa, Yagi and Kawahara 2002) More relevant for device manufacturing were studies performed using hot wall CVD, which resulted in growth rates up to 50 m/h (Reyes, spring MRS 2006). While these films were re latively flat (i.e., low residual stress) they were far from ‘defect free’ which is generally a minimum condition to allow for electronic devices to be successfully realized. 1.2.1 Why Heteroepitaxial Silicon Carbide? Unlike the more commonly studied hex agonal forms of SiC, 4H SiC and 6H SiC, 3C SiC has the ability to be heteroepitaxially grown on Si, allowing for the growth of SiC on large area substrates. Si wafers are inexpensive and are currently manufactured as large as 12 inches in diameter. 3C Si C could be epitaxially grown on large area Si wafers to produce seeds for bulk growth. Currently, only bulk SiC is available in the 4H and 6H polytype with boule sizes capable of producing a maximum 4 inch size wafer at a cost of nearly $2000 $2500 per wa fer (Cree Inc. 2009 ) Furthermore bulk SiC grown by physical vapor transport contains screw dislocation densities near 1 0 200 cm 2 that can penetrate into the epitaxial layer during growth and lead to device failure. Because of the cubic crystal struct ure of 3C SiC, these screw dislocations are energetically unfavorable and do not in occur in 3C heteroepitaxy. Heteroepitaxy opens opportunities for silicon carbide growth on a variety of novel substrates in order to exploit or suppress certain attributes In order to reduce the detrimental effects stemming from the coefficient of thermal expansion mismatch between SiC and Si,

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7 3C SiC has been grown on Si x Ge (1 x) substrates 3C SiC films have also been grown on silicon substrates patterned with inverted n anopyramids to successfully reduce defect propagation via defect annihilation w ithin the films ( D'Arrigo 2010 ) see Figure 1.2 Fabrication of devices, e.g. MEMS, can be facilitated by growing polycrystalline SiC on sacrificial oxide release layers by usi ng a polysilicon seed layer. The oxide layer can be etched with hydrofluoric acid (HF) to release the patterned SiC MEMS structures. This avoids problems that silicon wet etchants may present when releasing SiC directly from a Si substrate masking effec ts due to bubble formation on the substrate surface and the increased risk of structural damage due to agitation, especially with submicron thick films. The polysilicon seed layer can be tailored to impact the grain characteristics of the poly SiC film, resulting in a highly textured poly SiC film (C. L. Frewin 2009) Indeed this preliminary work was the motivation for this dissertation research where the next logical step was to realize MEMS devices on the poly SiC on oxide wafers. Figure 1.2 Schem atic representation of antiphase domain boundary (APB) annihilati on with film thickness. The solid line represents the Si SiC interface. Note that the APB s form at the atomic step s of the Si surface (Mendez, et al. 2005)

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8 1.2.2 Fabrication of Si licon C arbide MEMS Although the micromachining of single crystal bulk silicon carbide, i.e. 4H SiC and 6H SiC, has been demonstrated using SiC epi on SiC bulk substrate s to produce pressure sensors (Okojie 1996) heteroepitaxial SiC has the advantage of being g rown on relatively inexpensive, high quality, large area Si substrates and readily processed using many of the conventional Si bulk micromachining techniques T he high etch resistance of silicon carbide to the wet chemistries used to process Si and SiO 2 a llows SiC to act as an etch stop during a broad range of processing steps Figu re 1.3 shows a process flow demonstrating the realization of diaphragm and cantilever structures from epi SiC on Si. In the case of the backside etch, the SiC membrane serves as an etch stop to provide excellent thickness control of the membrane. Freestanding SiC microstructures, like the cantilever shown in Figure 1.3, are first patterned using dry etching (plasma) and then the structure is released by etching the bulk silico n with an anisotropic wet etchant e.g. KOH, TMAH, or EDP. As previously mentioned, wet etching isn’t practical to use to pattern silicon carbide, so plasma etching techniques have been developed. The fluorine based plasma chemistries developed for the e tching of Si, SiO 2 and Si 3 N 4 are also used for SiC. SF 6 NF 3 CHF 3 and CF 4 are commonly mixed with O 2 at pressures below 200 mTorr to promote reactive ion etching and suppress sputtering of the substrate (M. Z. Mehregany 1998) Although, the oxygenated plasmas quickly erode common photoresist masks, p hotoresists, such as AZ 4620 manufactured by AZ Electronic Materials are available that are resistant enough against erosion in fluorine based plasmas to serve as a dry etch soft mask. Photoresist masks can exhibit etching selectivity up to 1:1, which is fine for

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9 patterning larger feature sizes ( 4 or processing thin SiC films. However, aluminum or nickel hard masks are preferred for patterning SiC in etching plasmas since only thin metal coatings are needed owing to the high selectivity of the metal films (1:40 for Ni on 3C SiC). Nevertheless, a luminum hard masks are prone to an effect called micromasking, a phenomena that occurs when sputtered atoms from the metal mask deposit on the surrounding etc h field and masks the undying material of the etch field. Grass like structures result if the etching environment has a high degree of anisotropy. The addition of small amounts of hydrogen to the gas mixture reduces this effect (M. Z. Mehregany 1998)

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10 (a) (b) (c) (d) (e) Figure 1.3 Fabrication of a free standing cantilever. (a) CVD growth of 3C SiC film on a Si substrate. (b) Mask material (shown in orange) is spun (photoresist) or deposited (metal) on the wafer and then patterned. (c) The 3C SiC is dry etched using SF 6 / O 2 plasma. (d) Mask layer is removed. (e) Structure is released by etching the underlying silicon with a heated 20% KOH solution.

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11 Surface micromachining is a process in which sacrificial thin films are used as a platform for the deposition of a structural layer, but are then removed to release a freestanding MEMS structure. S ilicon bulk micromachining techniques can be used for processing monocrystalline, polycrystalline, and amorphous SiC, however, conventional surface micromachining is currently only possible with poly and amorphous SiC. Polycrystalline SiC structural layers can be deposited on a poly Si or SiO 2 sacrificial layer to exploit the fact that SiC is highly resistant to Si and SiO 2 etch ants. When poly Si is used as a sacrificial layer, a thin oxide layer is used to protect the underlying Si substrate during the release of the structure from the sacrificial layer. Poly SiC grown on SiO 2 and Si 3 N 4 films tend to form randomly oriented, eq uiaxed grains. In contrast, the crystal grains of the poly SiC film grown on poly Si matches the textured grains of poly Si, forming a polycrystalline epitaxy (Zorman 1996) This suggests that one could vary the microstructure of the SiC film to tailor t he device’s performance by selecting the appropriate poly Si substrate deposition conditions. The work discussed in this dissertation explores the influence of thickness dependant microstructure changes (i.e. grain size and grain texture) of thin polysili con films on the SiC film. 1.2.3 Stress Induced Deformation of Heteroepitaxial Films As discussed earlier, heteroepitaxial SiC offers several benefits over bulk grown SiC since heteroepitaxial SiC can be incorporated into current silicon processing tec hnology and a variety of substrates can be implemented to suit design/ fabrication needs. Unfortunately, the heteroepitaxial growth of 3C SiC on Si is exacerbated by a 20% lattice mismatch and 8% coefficient of thermal expansion (CTE) between Si and 3C Si C

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12 (refer to Table 1.1), which leads to in plane stress within the film. The stress that develops within the SiC film near the SiC Si interface is tensile, resulting in concave bowing of the wafer or, in the case of growth on (111)Si substrates, film delam ination and cracking. Often the atomic bonds along crystal planes will break and reform to relieve film stress, leaving behind dangling bonds which are referred to as misfit dislocations (Smith 1995) At the edge of the wafer or areas where the film subs trate system terminate, deformation of the film edge will occur due to the film being “pinned” at the film substrate interface, refer to Figure 1.3(a). This deformation will cause out of plane bending of free standing structures As the film grows, a stre ss gradient parallel to the direction of growth frequently develops within 3C SiC films, causing out of plane deformation of released structures, Figure 1.3(b). These material growth related issues need to be addressed before 3C SiC can be realistically c onsidered as a replacement for Si based MEMS device structures. 1.3 Polysilicon on Oxide Substrates for Heteroepitaxial Silicon Carbide SiC is a semiconductor material that is desirable for many power electronics and MEMS applications due to its wide ban d gap, mechanical resilience, robust thermal properties, and chemical inertness. However, many of these inherent properties create extreme difficulties when processing MEMS devices with this material SiC chemical resi stance reduces the effectiveness of wet chemical etching and requires the use of dry etching techniques involving reactive ion etching (i.e., DRIE/RIE ) Fortunately 3C SiC, can be grown heteroepitaxially on Si substrates and the addition of this Si layer allows for many more processing op tions in device manufacturing. For example, one can utilize the Si substrate as a sacrificial layer for the creation of freestanding 3C SiC MEMS structures (Beheim and Evans 2006) (Carter, et al. 2000) However, the recipes used to

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13 etch Si in DRIE/RIE ha ve a similar etch rate with SiC, thereby excluding selectivity and reducing accuracy for the desired structure (Beheim and Evans 2006) (McLane and Flemish 1996) (Rosli, Aziz and Hamid 2006) Freestanding SiC MEMS devices using sacrificial Si layers have a lso encountered difficulties during device fabrication resulting from unetched Si preventing the complete release of the structure (Beheim and Evans 2006) (Carter, et al. 2000) Silicon dioxide, SiO 2 has been traditionally used as an etch stop in Si proc essing involving DRIE/RIE and can be easily removed by wet chemistry processes to allow for the full release of freestanding structures (Federico, et al. 2003) With this in mind, silicon on insulator, SOI substrates provide an excellent media for the c reation of freestanding SiC devices by providing not only an oxide for the etc h stop for DRIE/RIE, but also a Si crystal seed layer for the heteroepitaxial growth of the 3C SiC (Shimizu, Ishikawa and Shibata 2000) (Myers, Saddow, et al. 2004) SOI provide s some additional benefits for the growth of 3C SiC as shown in previous studies (Shimizu, Ishikawa and Shibata 2000) (Myers, Saddow, et al. 2004) The high temperatures required for the growth of single crystal 3C SiC soften the SiO 2 layer, allow dispers ion of stress caused by the ~ 20% lattice mismatch between SiC and Si and suppress the formation of voids caused by Si evaporation at the 3C SiC/ Si interface (Carter, et al. 2000) Although thick SOI seed layers (>50 nm) have been shown to produce 3C SiC films that are of comparable quality when compared to 3C SiC films grown on single crystal Si substrates, the benefits of the epitaxial growth of 3C SiC on SOI are realized when 3C SiC is deposited on a thin (<50 nm) seed layer of Si, which produces excel lent quality 3C SiC (Shimizu, Ishikawa and Shibata 2000) (Myers, Saddow, et al. 2004) However, a major drawback of using SOI in the production of 3C

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14 SiC devices is the fact that it requires extensive processing techniques (Shimizu, Ishikawa and Shibata 2 000) (Myers, Saddow, et al. 2004) These processes add to the overall production cost of the device In addition many MEMS devices do not require single crystal SiC material for proper functionality. A cost efficient, easily produced wafer stack consist ing of poly Si/ SiO 2 / Si layers could replace the SOI substrate if poly SiC is desired as a material for MEMS application s The SiC Group at the University of South Florida has been investigating the optimization of the new process of growing thin film 3C SiC on a thin ( poly crystalline Si (poly Si) seed layer. The poly Si is CVD deposited on a CVD deposited SiO 2 / Si (111) stack and poly 3C SiC is formed on this poly Si seed layer The CVD deposited poly Si seed layer appears to exhibit a highly textured gr ain structure, in other words, the polycrystalline grains are oriented in a preferred direction. The texturing of the poly Si layer is very sensitive to its deposition temperature. It is reported that the films are deposited favoring the <110> orientatio n and, once annealed, tend to arrange in the <111> orientation (Parr and Gardiner 2001) Growing the 3C SiC via the poly Si seed layer on an oxide release layer will provide a versatile substrate for the fabrication of free standing, highly crystalline 3C SiC MEMS structures with low residual stress 1.4 Influence of Polysilicon Seed Layer Thickness on Silicon Carbide Film Stress The behavior of polycrystalline films is largely determined by the grain morphology and the general orientation of the crystall ites within the film (i.e., film texture). Smaller grain size, especially when they exhibit columnar structure, usually results in a higher concentration of small angle grain boundaries. These boundaries tend

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15 to be areas of lower density and the interato mic forces within the boundary try to close the gaps, which results in a tensile stress on the surrounding crystallites (Koch 1994). Polysilicon films deposited at temperatures 1 0C form a conical grain structure and exhibit compressive stress (Parr an d Gardiner 2001) The origin of the compressive stress is not well understood, but is believed to be a result of hydrogen incorporation into the growing film (Yu et. al) or the insertion of excess adatoms into the grain boundaries (citation) Early in th e deposition small, randomly oriented grains grow and compete with one another depending on their orientation with respect to the growing film. Crystallites oriented for fast vertical growth will out compete slower growing misoriented grains. This result s in few er, but larg er, conically shaped grains as the film grows (see Figure 1.5). Compressive polysilicon films tend to exhibit positive stress gradients and, as a result, curl upward when released from the substrate (Madou 2002). Silicon carbide films were grown on polysilicon seed layers deposited under conditions which favor cone shaped grain growth and compressive intrinsic stress. Cant ilevers fabricated from 3C SiC films grown on a ~20nm thick polysilicon layer demonstrated a positive gradient str ess, i.e. upward curl, whereas cantilevers fabricated from 3C SiC films grown from a ~100nm polysilicon seed layer developed a negative gradient stress, i.e. downward curl. Surface probe analysis of the polysilicon layers revealed substantial size and mor phology differences of the surface structure of the gains. Transmission electron microscopy (TEM) of the 3C SiC film grown on the 100nm thick polysilicon seed layer showed relatively well ordered grains near the SiC Si interface with increasing randomness of the grain orientations away from the interface.

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16 1.5 Overview of the Organization of This Dissertation SiC demonstrates roboust electrical, chemical, and mechanical performance suitable for use in harsh environments where Si based MEMS devices would f ail. Unfortunately, the chemical inertness is a desirable property for device application; it presents challenges for the processing of heteroepitaxial SiC films. Coupled with the inherent problems of heteroepitaxial growth, new techniques to reduce or e liminate these issues must be investigated if SiC is to be realized as the preferred fabrication material for harsh environment devices. Chapter 2 will discuss the principles of CVD growth and hardware, since chemical vapor deposition is the primary means of growing 3C SiC. An overview of crystal defects and polycrystalline film growth as they apply to heteroepitaxial growth of 3C SiC on Si will be then be presented. The chapter will conclude with a mechanical analysis of thin film stress. Chapter 3 wil l discuss the first experiments to realize high quality poly 3C SiC films on poly Si on oxide wafers. Chapter 4 presents the first experiments aimed at producing MEMS structures on the poly 3C SiC on oxide layers developed and presented in Chapter 3. Bas ed on the lessons learned in this phase of the research the MEMS structures were re designed so that stress strain information could be extracted directly from the released MEMS structures. Finally, Chapter 5 will discuss future research exploring post fa brication annealing of MEMS structures micromachined from the stoichiometry dependent bilayer film and further characterization of the microstructure of the polycrystalline SiC films.

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17 CHAPTER 2: HETEROEPITAXIAL SILICON CARBIDE STRUCTURE, GROWTH, AND TH IN FILM MECHANICS 2.1 Crystal Structure of Silicon Carbide Silicon carbide can exist in many different crystal structures depending on growth conditions, a phenomenon called polytypism. Polytypism is a special case of polymorphism, in which the crystal structures between two polymorphs differ only in the way identical, two dimensional layers of close packed layers are stacked. In the case of SiC, polytypes vary by the different stacking sequences of the tetragonally bonded Si C subunits, with more than 220 polytypes known to exist (Foll 2006). However, an overwhelming majority of electronic materials research is concerned with only three of these polytypes: 4H SiC, 6H SiC, and 3C SiC. The 4H, 6H, and 3C designation, called the Ramsdell notation, is the most wide spread method of identifying polytypes (Foll 2006) The number letter prefix designates the quantity of close packed Si C layers required for each unit cell and whether the polytype is a hexagonal (H), cubic (C), or rhombohedral (R) crystal sys tem. For example, 4H SiC indicates a hexagonal crystal system comprised of a repetitive, uniquely ordered stacking sequence of four (4) Si C subunit layers. The hexagonal close packed structure is a main reason for the high stability of the hexagonal SiC polytypes. The 4H SiC polytype has the highest stability due to the

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18 alternating cubic and hexagonal layers (Park, et al. 1994) 6H SiC has a low, anisotropic electron mobility, while 4H SiC has a much higher electron mobility and is less anisotropic, i.e less directionally dependent (Casady and Johnson 1996) Thus 4H SiC is, at present, the most commonly used polytype for electronic devices (Saddow and Agarwal 2004) Figure 2.1 Four examples of SiC polytype stacking sequences. Each point represents a lattice point on which the Si C basis is attached. Each layer is the close packed plane of the crys tal system and is differentiated by “A”, “B”, or “C”, which is determined by the relation of each layer’s lattice point positions to the interstitial spaces of the other layers (Saddow and Agarwal 2004) The ‘A’, ‘B’, and ‘C’ labels in Figure 2.1 denote the position of the lattice points, a collection of periodic points in space, on which the Si C subunits are located. As seen in Figure 2.1, 4H SiC has a stacking sequence of ABCB, or 4 layers, therefore the designation is 4H. This structure has an equa l number of cubic and hexagonal lattice sites. The 6H SiC structure has 6 stacking layers before the sequence repeats ABCACB, and, finally, 3C SiC is a continuation of the ABC stacking sequence which has purely cubic symmetry. Due to differences in stack ing sequence, the electrical, mechanical and optical properties vary for each polytype of SiC, as shown in Table 1.1.

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19 2.2 Overview of CVD Chemical vapor deposition (CVD) is a technique in which a solid film is formed onto a surface by a chemical reaction emanating from vapor phase precursors. The chemical reactions generally undergo activation by ohmic heating, RF induction heating, plasma, or light. It is a technique often employed for the uniform growth of high quality thin films. The common types of CVD are 1) Organometallic Vapor Phase Epitaxy (OMVPE) 2) Plasma Enhanced Chemical Vapor Deposition (PECVD) 3) Photo CVD 4) Low Pressure CVD and 5) Atmospheric Pressure CVD. Chemical vapor deposition involves a series of sequential steps beginning with th e vapor phase and progressing through a series of quasi steady state reactions which culminate in the development of a sold film. The progression from vapor phase to film growth can be summarized by the following sequence of events. First, the gaseous re actants diffuse through the stagnant fluid layer (i.e. so called ‘boundary layer’) to the growth surface. Second, the reactants adsorb on the surface and then usually undergo some surface migration to reach a reaction site (i.e., dangling chemical bond). Third, the reactants undergo a chemical reaction which may be catalyzed by the surface. Fourth, the reaction by products undergo desorption from the surface. Fifth, the reaction by products diffuse through the boundary layer, enter the gas stream and ar e exhausted out of the reactor. Finally, the condensed product is incorporated into the structure of the developing film. The process is summarized in Figure 2.2 below.

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20 Figure 2.2 Sc h ematic diagram of mechanistic steps which occur during the CVD proc ess (1) Gas inlet, (2) dissociation of reactants, (3) diffusion of reactants to the surface, (4) adsorption of reactants to the surface, (5) heterogeneous surface reaction, (6) desorption of by products, (7) diffusion of by products back into the bulk ga s (Park and Sudarshan 2001) Although many rate limiting steps are known to exist, the deposition rate of CVD processes is primarily governed by two mechanisms: mass transport and surface kinetics. These two rate limiting steps are influenced by sever al process parameters. The temperature and pressure of the reaction environment greatly impact the deposition pr o cess. The p r essure co nt rols the thickness of the boundary layer and, as a result, affects the rate of the reactant and product diffus i on (Siv aram 1995). At low pressures, the boundary layer is thinner, which m i n i m i zes the diffusion time across the region. This is known as the reaction rate limited CVD re g ime; where the rate of de p osition is li m ited by the reaction rate of reactants on the sur face and is more sensitive to temperature (Sivaram 1995). If the temperature is low, then an oversupply of reactants is created due to the molecules reacting slowly (Sivaram 1995). If the temperature is high, then the surface reactions take place quickly and the reaction rate is limited by the diffusion of

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21 molecules. This is generally the case for high pressures as the boundary layer is thicker and diffusion becomes the rate limiting step. The growth regi m e (transport li m ited or surface reaction li m ited ) is deter m ined by the s lowest process ( d iffusion or chemical reaction) (Smith 1995) Figure 2.3 ill u st r at e s how both the temperat u re and pressure d u ring CVD affects the g r ow th rate. Figure 2.3 G eneralized process trend showing the dependence of proc ess temperature and pressure on growth rate via CVD (Smith 1995 ) Another important process parameter that influences reaction rate is gas velocity. The CVD process involves the transport of precursor gases through the use of a carrier gas, which is d esigned to flow in a laminar manner although occasionally some turbulence is present (Park and Sudarshan 2001) When a fluid flows over a stationary surface, a thin layer of fluid immediately above the surface is stationary. This is known as the boundary layer, as stated above, and is inversely proportional to the gas velocity

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22 and directly proportional to the fluid viscosity and pressure. In a horiz o ntal CVD react o r design, the boundary layer increases along the direction of the carrier gas flow (as the temperature of the gas increases), which leads to an exponential decrease in the deposition rate. Tilting the susceptor increases t h e gas velocity by continuously decreasing the cross sectional area and thus red u ces the thickness of the boundary layer alo ng the flow direction (Rossi 1988) Figure 2.4 illustrates these principles. (a) (b) Figure 2.4 Illustration flat susceptor design, and (b) tilted susceptor design (Pierson 1999) 2.2.1 Early Stage s of CVD Film Growth The initial stages of film growth are characterized by three major phenomena which occur independent of the type of film growth technique. The material first condenses out of the vapor phase and nucleates on a substrate. This condensation process begins with the reactant speci es impinging on the surface and bond ing to the substrate ato ms at the gas substrate interface The probability that an impinging atom will be adsorbed onto the surface is related to a quantity called the sticking coefficient, which is the ratio of the amount of material condensed on the surface to the total amount of impinging atoms, Figure 2.1 (Sivaram, S 1995) Once an atom is adsorbed onto the surface it must overcome a surface binding energy, Q desorb in order to leave the surface.

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23 s which an atom stays on the surface, is expressed by: kT Q exp 1 desorb s (2.1) When Q desob is large in comparison to kT, the adsorbed atom will spend a long time on the surface, so the chance of the atom being incorporated on the surface is high (Sivaram, S 1995) When the energy of the surface atoms is on the order of kT, then the adsorbed atom will have a high probability of being desorbed. Once incorporated onto the surface, the condensed atoms or molecules tend to aggregate and form sm all clusters on the surface of the substrate, a process called nucleation. These small clusters are in a constant free energy struggle between the releasing of free energy when forming a cluster and having to pay an energy cost when forming a surface inte rface between two distinct phases. Small clusters are unstable if the energy released from the formation of its volume cannot sustain the creation of its surface. Once the clusters have reached a critical size, any addition of molecules to the cluster re leases energy instead of costing energy and nucleation growth can be sustained. Then the randomly formed nucleation sites reach a saturation density and undergo island coalescence via the diffusion and continuing capture of adatoms. This saturation point occurs when the internuclear distances are on the order of the mean surface diffusion length. As the islands grow, they assimilate subcritical nuclei and coalesce with other islands, forming a connected network. Eventually, the steady state growth above the first layer occurs. However,

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24 CVD processes add an additional step to the film growth process; a chemical reaction among the surface adsorbed reactants occurs at the gas substrate interface. Whereas simple condensation is always exothermic, a majorit y of CVD reactions are endothermic which means they must usually wait until they interact with the heated substrate. Another important feature of the CVD process that complicates this general growth sequence is that the intrinsic impurities, in the form o f reaction products, need to be considered in the vicinity of the film growth (Sivaram, S 1995) 2.3 Overview of Heteroepitaxial Defects Given the nature of heteroepitaxy, i.e. growing a crystalline material on a different crystalline material (substrate ), it is nearly impossible to generate a perfect, mono crystalline film. Other than the introduction of impurities from contamination, the common source of extrinsic crystal defects found in heteroepitaxy stems from a mismatch between the lattice constant and the coefficient of thermal expansion between the substrate and film. These disparities create line defects, such as dislocations, or planar defects as is the case for micro twins, stacking faults, and grain boundaries. 2.3.1 Line Defects Dislocatio ns are linear defects resulting from the deviation of atoms from the lattice site positions of the crystalline structure. The disruptions of the atomic arrangement associated with dislocations typically extend through the structure along a line. Dislocat ions that commonly occur in heteroepitaxy are of the edge and misfit type.

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25 Edge dislocations can be thought of as a disturbance originating from the insertion or removal of a partial plane of atoms from the crystal structure. The region at the end of the partial plane, where the atomic arrangement maximally deviates from the normal lattice sites, is called the dislocation line The surrounding region is the dislocation core which is an area of large strain and dangling bonds that runs alongside the disl ocation line. The energy of propagation for an edge dislocation is much lower than the total bond energy of the atoms lying in the propagation plane. This is explained by the fact that an edge dislocation proceeds through a crystal peristaltic fashion. At any given moment, only one bond is broken while the atoms surrounding the dislocation are distorted from their equilibrium positions. Another type of dislocation that is closely related to the edge dislocation, but is not seen in 3C SiC heteroepitaxy, is the screw dislocation This dislocation is often thought of as a crystal system which has been subjected to shear stress sufficient enough to overcome the elastic limits of the crystal. The result is the shifting of one side of the crystal relative to the other side by one or more lattice constants. In this case, the dislocation line runs in the direction of the shift. Referencing the atoms located within a plane perpendicular to the dislocation line, if an attempt is made to form a closed path aroun d the dislocation line by connecting the atoms together, a helix will be formed. The once parallel planes of the crystal are now joined by a helical path; this is why this type of dislocation is referred as a screw dislocation. Although this dislocation is not seen in as grown crystalline 3C SiC films, its introduction is important for the understanding of grain boundaries.

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26 Heteroepitaxial dislocations, called misfit dislocations form at the interface of two crystals with different lattice constants. I n an attempt to minimize the interatomic bonding strain induced by the lattice mismatch, the atomic planes of the thin film will be distorted at the interface and will no longer be equally spaced. The roughly equidistant points along the interface where t he lattice deviations are the greatest correspond to the misfit dislocations. If the heteroepitaxial film has a coefficient of thermal expansion different than the substrate, then when temperature changes occur, usually during post growth cooling, misfit dislocations occur in order to relieve in plane stress present near the film substrate interface. 2.3.2 Planar Defects Planar defects correspond to disturbances of the crystal structure resulting from the two dimensional deviation of atoms from their c orresponding lattice sites. Planar defects commonly found in heteroepitaxial films are stacking faults (SF) micro twins, antiphase boundaries (APB), and double position boundaries (DPB) Stacking faults occur when a mistake occurs in the stacking sequenc e of the planes of atoms along certain directions. If planes of densely packed spheres (atoms) are to be stacked on each other, one finds that there are two sets of interstitial spaces to place the next densely packed plane. As a result, it is possible t o lay three planes in succession without the co alignment of interplanar atoms. In a perfect crystalline structure, a stacking sequence will eventually repeat in a periodic fashion. The face centered cubic (FCC) structure is created when the stacking seq uence repeats as ABCABC…and the hexagonal close packed (HCP) structure is created from the sequence ABABAB… In the

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27 case of the zinc blende structure of 3C SiC, it is not unusual to see stacking errors occur in the stacking of the {111} planes since the ne arest neighbor bonding is not affected by stacking faults. In fact, the energy associated with stacking faults is very low when compared to other planar defects since the defect is only due to the nearest neighbor arrangement and not disturbances of the c rystal structure. This mistake may arise during the film growth or when plastic deformation has occurred to the film. Figures 2.5 and 2.6 show a plan view and cross sectional TEM micrograph of the stacking faults present in a 3C SiC film grown heteroepita xially on (100)Si. Figure 2.5 Stacking faults revealed in a (100)3C SiC film via PV TEM. SF density estimated to be ~ 5x10 4 cm 1 Data provided by C. Bon g iorno, IMM CNR, Catania, Italy

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28 Figure 2.6 Example of hetero defects in (100)3C SiC from X TEM. Note the defects along the (111) planes, also threading dislocations and stacking faults. Image courtesy C. Bongiorno, IMM CNR, Catania, Italy. Another type of planar defect resulting from the change of the planar stacking sequence is the micro t win or, simply, twin. The distinctive feature of a twin is that the planar arrangements on opposite sides of the stacking disruption are mirror images of each other. For example, the stacking sequence ABCABC A CBACBA…possesses a reflection about the A plan e located at the center of the palindrome. In the diamond or zinc blende structure, twinning occurs mostly about the (111) plane. Twinning causes a change in the crystal orientation. For crystal growth along the <111> direction in the zinc blende struct ure, the orientation of the crystal planes in the twinned region are along the < 111 > or <115> direction. A very smooth surface morphology can result in 3C SiC heteroepitaxial growth along the <111> direction since the twinning plane is the same as the gro wth plane. Figure 2.7 (a) shows a schematic representation of a micro twin while Figure 2.8 shows a plan view TEM micrograph of an actual micro twin present in a 3C SiC film grown on (100)Si.

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29 Figure 2.7 Schematic representation of micro twin defect in SiC on Si heteroep itaxy. (Mendez, et al. 2005) Figure 2.8 Micro twinned crystal defect (dark cluster in center of micrograph) observed with plan view TEM (PV TEM). Data courtesy of C. Bongiorno, IMM CNR, Catania, IT. A planar defect that frequentl y occurs during the growth of (100)3C SiC on (100)Si substrates is the antiphase boundary (APB). This type of defect is prevalent during APCVD growth and is significantly reduced at lower growth pressures (Cho and Carter 2001) The APB occurs when two is lands having different ordered phase

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30 coalesce. In the early stages of the film growth, partial surface steps may cause a relative position shift between the atomic stacking of different islands. In the case of SiC, due to surface roughness of the carboni zed Si substrate, some islands of SiC may sit higher relative to others. As the islands grow and coalesce, a Si or C layer of one island may bond with another Si or C atom of another island forming a Si Si or C C bond as illustrated in Figure 2.9. These boundaries tend to propagate along the {111} planes (Ishida, Takahashi and Okumura 2003) However, the etching experiments of Li and Giling have shown evidence that APBs can propagate along the {110} plane (Ishida, Takahashi and Okumura 2003) Figure 2.9 Geometrical consideration of the formation of an APB when SiC is grown on (100)Si substrate with an atomic step. Note the bonding of Si Si and C C atoms. (Cho and Carter 2001) The double position boundary (DPB) is a special case of twinning in whi ch separate domains are rotated about a 180 twin axis. This is seen when a FCC type crystal structure is grown in the (111) orientation on a (111) surface of a hexagonal crystal

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31 (Kong, et al. 1987) This is commonly seen in 3C SiC films grown on the basa l plane of the hexagonal SiC polytypes. As illustrated in Figure 2.10(a), the (111) surface has two equivalent types of sites that the C atoms can locate. As a result, two different nuclei orientations can develop which are rotated 60 relative to each o ther. When these nuclei coalesce into each other, a DPB is formed. In Figure 2.10(b), the relative shift of the stacking sequence between neighboring domains is shown. The upper case “A” represents the surface of the substrate, while the lower case “a b c…” represents the stacking layers of the epitaxy. One can see that every third layer offers the opportunity to form a perfect bond across the interface, Si C for example, the other planes cannot form this type of bond (Kong, et al. 1987) As a result, the boundary is somewhat disordered and the internal energy is high (Kong, et al. 1987) Figure 2.10 S tacking fault generation schematic showing the error in crystal layer formation resulting in a stacking fault defect. (a) top view representation and (b) side view showing the plane stacking sequence (Kong, et al. 1987)

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32 2.3.3 Grain Boundaries Since this dissertation involves the growth and characterization of polycrystalline films, it is worth looking at the role grain boundaries play in polycrysta lline systems. Polycrystalline materials consist of several small crystalline regions, called grains or crystallites, bonded together by crystallographically defective regions called grain boundaries. Grain boundaries are interfaces where two crystals ha ving different orientations meet without a disruption in the continuity of the material (Hirth 1968) Grain boundaries are generally categorized as low angle grain boundaries and high angle grain boundaries. Low angle grain boundaries can be viewed as be ing comprised of several distinct and isolated dislocations whose properties are directly dependent on the degree of misorientation, ( angle grain boundary is through a tilt and twist.boundary. In t he case of a tilt boundary, the crystal lattice can be visualized as being bent by an applied force about an axis parallel to the boundary plane. To reduce the energy associated by the bending, one can insert a wedge into the crystal. Edge dislocations, which are an extra plane of atoms, act like an imaginary wedge. As the bending angle is increased, more dislocations must be incorporated into the deformation in order to reduce the energy of the deformation. The twist boundary involves rotation about a n axis perpendicular to the boundary plane. In order to minimize the energy associated with the twist, two sets of perpendicular screw dislocations need to be introduced into a plane to create localized distortions. Generally, grain boundaries are never a pure tilt or twist boundary, but a combination of the two. When the angle of misorientation becomes large, the

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33 dislocations become numerous and begin to overlap each other creating a very disordered boundary region. 2.4 Structural Evolution of Polycrys talline Thin Films Grain formation in polycrystalline films grown using CVD processes is sensitive to several parameters such as temperature, deposition rate, dopant concentration, pressure, and impurity concentration. The structures of polycrystalline sy stems usually are governed by complicated, materials specific phenomena (Thompson 2000) The processes described in this section are simple, generalized trends of behavior for materials. Polycrystalline films typically begin with the nucleation and coale scence of individual crystal islands on a substrate, an overview of this process was discussed in section 2.2.1. Grain growth is largely driven by the minimization of the excess energy associated with the total grain boundary area; as the grain boundary a rea decreases, the grain size must increase. Grain structure formation can occur through two distinct evolutionary processes. In one case, the grain boundaries formed early after island impingement are immobile and grain growth proceeds from the epitaxia l growth of columnar structures. As the film grows, the grains oriented with the faster growing facets favoring vertical film growth will out compete slower growing, misoriented grains, Figure 2.1 1 Sometimes this is referred to as conical grain growth.

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34 Figure 2.1 1 Evolution of grain structure with film growth. Cross sectional slices of a simulated film at various thicknesses revealing grain evolution due to competitive grain growth among conical grains. The film thickness, h, is expressed in term s of the initial grain spacing, d 0 (Ophus 2010) When the grain boundaries are mobile, the in plane grain growth proceeds as the film thickens. The resulting grains appear to have an equiaxed columnar shape that traverses the thickness of the film. As the film grows, the in plane grain size increases with roughly the same scale. Often times, as unfavorable grain orientations are occluded due to competitive growth and the faster growing orientations drive film thickening, conical growth can lead to columnar grain growth with roughly parallel boundaries. 2.5 Mechanical Properties of Thin Films While many thin film devices may be sought after for their electronic, magnetic, or optical properties, these devices are often limited by their mechanical pr operties. In the course of the deposition of thin films of materials, large stresses can develop, sometimes exceeding the tensile strength of the bulk material. These intrinsic stresses are often held responsible for the failure of thin film devices; in extreme situations the film may crack or peel from the substrate from where they are grown. From a technological point of view, it is important to understand the mechanisms responsible for thin film

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35 stress and develop methods to reduce or compensate for t he impact these stresses have on thin film bases devices. 2.5.1 Sources of Stresses in Thin Films This section will open with a few distinctions that need to be introduced between widely employed and, occasionally misused, terminology. Stress, often den oted by the sectional area, A, whose units are the same as pressure. It is simply expressed as, A F (2.2) the displacement of a particle in a body based on a reference length, L. The length change may occur because of the application of an external or internal force, the expansion of a material from a temperature diffe rence, etc. It is frequently expressed as a ratio, L L (2.3) compressive stress and strain, respectively. Residual stresses are those stresses t hat exist within a body when thermal gradients or externally applied loads have been removed.

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36 Three sources of stress that can contribute to thin film’s residual stress are intrinsic, epitaxial, and thermal. Intrinsic stress refers to the collective st resses that develop during the growth of the film. It does not arise from the lattice mismatch or the thermal expansion related strains of the film substrate system, but occurs because of the film deposition process (e.g. nucleation, island coalescence, g rain growth, film thickening, etc.), and develops under non equilibrium conditions. Epitaxial stress arises when a lattice parameter mismatch exists between the film and the substrate. This occurs when the film is very thin and there is coherency betwe en the lattice sites of the film and the substrate. The misfit strain, mf by the distortion of the lattice spacing creates stress is given by s f s mf a a a (2.4) Where a s and a f are the substrate and film lattice constant, respectively. Once an epitaxial film reaches a critical thickness, t c the lattice becomes sufficiently strained and it becomes energetically favorable to form misfit dislocations in the film at the interface. The misfit dislocations introduce a stress field into the immediate area which relaxes the stressed interface. In the case of 3 C SiC, once the film grows past the critical thickness, 5 SiC lattice cells slightly exceed the distance spanned by 4 Si cells (i.e., 20% lattice mismatch). Sometimes epitaxial stress is lumped with other growth related stresses as a

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37 source of intrinsic s tress but there is this fine distinction which is important to understand in order to try and reduce/eliminate. Thermal stress is generated when strain is created from the material dependent differential expansion between the film and substrate during a t emperature change. This is often referred to as the Coefficient of Thermal Expansion (CTE). When the t f << t s the stress is related to the strain in the film at a certain temperature, T, by: T T 1 E dep s f f f therm (2.5) Where E f f f s are the thermal expansion coefficients of the film and substrate, respectively and T dep is the deposition temperature. In the case of SiC heteroepitaxy, the film is grown at temperatures usually exceeding 1300C and then cooled to room temperature. The strain difference between the Si substrate and the 3C SiC film due to this temperature c strain in the 3C SiC film. 2.5.2 Stress Control of Polycrystalline Silicon Carbide F i lms via CVD Process Parameters It has been known since the early 1980’s that Si rich silicon nitride, Si 3 N 4 thin films experienced stress relaxation when compared to fully stoichiometric Si 3 N 4 (Habermehl 1998) By varying the ratio of dichlorosilane, SiCl 2 H 2 to ammonia, NH 3

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38 the residual film stress can be tailored from a high state of tension to one of compression for Si rich films (Witczak 1994). Habermehl, repor ted that films with a silicon volume fraction of 10% 15% exhibited the lowest residual stress. A similar approach was adopted to control the residual stress and strain gradient of poly SiC films deposited by regulating the fraction of dichlorosilane (DCS) relative to the total gas flow when using a DCS and 1, 3 disilabutane (DSB) precursor chemistry (Roper 2006) The reported the increase of DCS introduced into the gas flow. The Si:C ratio increased with the DCS flow fraction. The measured residual film stress and strain gradient decreased monotonically with increasing DCS fraction see Figure 2.1 2 (a) and 2.1 2 (b) (Roper 2006) The stress reduction was attributed to th e larger atomic radius of Si compared to C. The excess Si in the film increased the average bond length thus reducing the tensile stress. (a) (b) Figure 2.1 2 Relationship of the DCS fraction in the gas mixture to, (a) the residual film stress and, (b) the strain gradient (Roper 2006 )

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39 Results from the study of the average residual stress of poly SiC films grown on (100)Si substrates (with and without SiO 2 thin film passivation) as a function of DCS flow were in agreement with the findings report ed by Roper et al. (X. A. Fu 2009) The average residual stress and the strain gradient decreased in unison with increasing DCS flow fraction, both having coinciding minima at a DCS flow rate of 35 standard cubic centimeters per minute (sccm), see Figure 2.1 3 The increased presence of DCS in the gas mixture also increased the growth rate from 30 relationship between residual stress and growth rate has also seen in investigations studying the residual stress in poly SiC f ilms as a function of deposition pressure. These poly SiC films exhibited a strong (a) (b) Figure 2.1 3 Results using DCS to control residual stress in poly SiC films. Influence of DCS flow rate on (a) the average residual film stress and, (b) the strain gradient measured from cantilevers fabricated from poly SiC films (X. A. Fu 2009). Polycrystalline SiC films grown on 100 nm thick polysilicon sacrificial layers deposited on thin Si 3 N 4 exhibi ted a high degree of (111)3C SiC texture and uniformity at the poly 3C SiC/ poly Si interface when a self limiting carbonization step was incorporated in the deposition process. In contrast, poly SiC films grown without the use

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40 of a cabonization step exhi bited voids at the poly SiC/ poly Si interface, formed randomly oriented grains, had higher surface roughness and completely penetrated the unconverted polysilicon layer (Wiser 2003) Similar results were reported using thin polysilicon layers deposited o n oxide to grow poly 3C SiC that is highly textured in the <111> direction (Frewin 2009). The incoroporation of a cabonization step in the SiC deposition process allows the formation of a thin, usually <50nm thick, SiC layer that prevents the evaporation of Si at the higher temperatures used for 3C SiC growth. Experimental evidence strongly suggests that the evaporation of Si is responsible for interfacial void and channel formation (S. E. Saddow 1999) Poly SiC will form on polysilicon via three dimen sional island growth using not only the Si from the source gas, but also from the underlying polysilicon as a result of thermally stimulated outdiffusion of Si and H 2 etching during the early stages of SiC growth (Wiser 2003). When two islands coalesce, v ertical Si migration from the polysilicon layer may contribute to sizable cavity and void formation, structures that may contribute to intrinsic tensile stress within the SiC film. Deposition pressure has been shown to have an impact on the residual stres s and stress gradients in poly SiC grown on (100)Si substrates (Fu 2004). The residual stress shifted from 710 MPa (tensile) to 98MPa (compressive) as the growth pressure was increased from 0.46 Torr to 5 Torr when grown using a SiH 2 Cl 2 and C 2 H 2 chemistr y at 900C, Figure 2.1 4 (a). It was reported that cantilevers fabricated from the moderately tensile films exhibited a nearly straight profile once released from the Si substrate, whereas the cantilevers fabricated from the compressive poly SiC films bent upward. All the films exhibited columnar grain structure with strong (111)3C SiC texture. However,

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41 the films having high tensile stress contained a large number of high angle grain boundaries with respect to the surface normal. In contrast, the microstr ucture of the compressive films exhibited columnar grain structure in which the boundaries were dominantly parallel to the surface normal. Liu et al. used a methylsilane, SiH 3 CH 3 and DCS precursor chemistry to grow poly SiC on (100)Si substrates at 800C to study the impact of deposition pressure on the residual film stress (Liu 2009). In contrast to the results reported by Fu, increasing the deposition pressure resulted in an increasing tensile film stress trend, Figure 2.1 4 (b). Atomic force microscopy (AFM) revealed that the surface projected grain size for the lower pressure growth was nearly twice the size of the higher pressure growth. The surface morphology certainly suggests that the increase of residal stress with respect to the deposition press ure may be due to grain boundary effects (Liu 2009). However, increasing the DCS flow fraction in the gas mixture also produced a decreasing tensile residual stress trend as reported by Roper et al. With increasing DCS fraction, the strain gradient chang ed from negative to positive, with the transition region coinciding with the minimum tensile residual stress.

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42 (a) (b) Figure 2.1 4 Residual stress versus deposition pressure tre nds for poly SiC (Fu 2004) (Liu 2009). The effect of deposition tem perature on the residual stress was also investigated by Liu et al. using methlysilane as a single precursor source for poly SiC growth on (100)Si substrates. Their results indicated a monotonic residual stress decrease from 1.4 GPa to 450 MPa as the grow th temperature was increased from 700C to 800C at 170 mTorr, see Figure 2.1 5 The suggested growth rate plateau from 800C to 850C seems to imply that there is a transition from the surface kinetics limited regime (where the growth rate increased with temperature) to the transport limited regime (where the growth rate plateaued) (Liu 2009) XRD analysis of the resulting films exhibited several reflection peaks that implied the film grown at the lower temperature had a more randomly oriented grain struc ture than the films grown at the higher deposition temperatures.

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43 Figure 2.1 5 Poly SiC residual film stress and growth rate vs. temperature at 0.17 Torr deposition pressure. Note the plateau after 800C which suggests that a surface kinetics limited regime transitioning to a mass transport limited regime (Liu 2009) It has also been reported that poly SiC films grown on oxidized (100)Si substrates exhibited residual stress that increased with deposition temperature using a tetramethylsilane, THS, s ingle precursor source (Hurtos 2000) However, X TEM analysis of the film substrate revealed that the film grown at the lower temperature (1080C) had a clearly defined, intact oxide layer on which the columnar, (111) textured poly SiC grew. The higher t emperature deposition (1130C) had no apparent oxide layer remaining and the poly SiC film exhibited randomly oriented, equiaxed crystallites. The deposition procedure incorporated high H 2 flow to avoid excess carbon in the films and was responsible for H 2 etching of the SiO 2 prior to growth. At 1080C, the H 2 etching was not significant enough to remove the SiO 2 layer. However, at 1130C the incomplete, or insufficient, removal of the oxide layer at the slightly higher deposition temperature appeared t o have triggered the small grain size (Hurtos 2000)

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44 An interesting approach to control strain gradients in poly SiC thin films adopts a bi layer structure using tailored N 2 doping during poly SiC growth was investigated by Zhang et al. The technique is s imilar to the Multipoly process (J. H. Yang 2000) a process that has been used to create near zero average film stress and near zero stress gradients in poly Si thin films. Alternate layers of compressive and tensile films are deposited by varying the d eposition temperatures. (J. H. Yang 2000). However, since the Multipoly process is composed of stacks of partially amorphous and fully crystalline layers, long term stability issues may arise due to recrystallization (Zhang 2006). The DSB single prescurs or is used as the Si and C source and ammonia, NH 3 is the doping source while all growths were carried out at 800C. Uniform doping of the full film thickness was performed for varying NH 3 to DSB flow ratio from 0 to 5%. All films exhibited negative str ain gradients (downward deflection) while the average film strain was tensile and increased from 0.10% to 0.21% when the NH 3 / DSB ratio was increased, Figure 2.1 6 N atoms occupy the C sites in the SiC lattice which causes the crystalline lattice to contr act from 4.360 to 4.345 SiC and Si (J. H. Zhang 2006).

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45 (a) (b) Figure 2.1 6 The use of tailored N 2 doping during poly SiC deposition to control film strain. (a) Relationship between average film strain and dopant doped top layer and 3% doped bottom later as a function of the ratio between top layer thickness to the total thickness (Zhang 2006) 2.5. 3 Analysis of Thin Film Stres s There are two principle methods that can be employed to assess the residual stress in thin films. The first is to measure the deformation of the substrate/film system using such means as a profilometer and then estimating the stress based on the radius of curvature. This is a ‘as grown’ technique that is frequently employed since it is not destructive and further film processing may be employed. The use of micro raman spectroscopy which measures shifts in the transverse optical (TO) and longitudinal opt ical (LO) peaks can also be employed to determine film stress. In addition x ray diffraction, in the so called XRR (x ray reflection) mode is often employed. However all of these microanalytical methods have limitations on their sensitivity and, ultimately one would like to assess the true mechanical properties of the stress in the film. This is particularly true for MEMS applications.

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46 The second method to assess the residual stress in the thin film is to fabricate MEMS test structures and then carefully m onitor the deformation/movement of these test structures as a function of film deposition properties. Clearly this second method is much more relevant to MEMS applications as one can have a true understanding of the actual film stress. However, this method is very time consuming and destructive. As a consequence the normal approach is to employ microanalytical methods first, track the stress level as a function of deposition conditions, and then use MEMS test structures to reveal the actual film stress. In this dissertation research this was the methodology employed, which is now discussed in further detail. 2.5. 3 .1 Stoney Equation The establishment of a mathematical relationship between the residual stress present in the film substrate system and the stre ss dependent displacement of the film substrate system, i.e. the Stoney Equation, is the goal of this section. Later, the relationship between the deflection of free standing structures sensitive to uniform and gradient intrinsic stresses present in the f ilm will be analyzed. Appendix A provides a brief introduction for those not familiar with the following derivation. It reviews the notation used in the following derivation and the mechanical analysis of a biaxially deformed plate, the model that is the basis of the Stoney Equation derivation. A stress free film with a thickness, t f is bonded to a stress free substrate with thickness, t s such that t s >> t f The lateral dimensions of the film and substrate, L, is such that L>> t s and t f Figure 2.20 i llustrates a series of steps depicting a way of creating a stressed thin film from a stress free film substrate system. First, it is imagined that the

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47 stress free film is removed from the stress free substrate and allowed to deform unrestrained by the sub strate, Figure 2. 17 (a). Film stresses are caused by an elastic accommodation of an incompatibility between the film and substrate (Nix 2005). Second, after the film has deformed, external forces are applied to the film in order to deform the film in ord er to match the substrate, Figure 2. 17 (b). The film is bonded to the substrate and the externally applied forces are removed. The substrate will prevent the film from returning to its undeformed state, but the forces from the film will cause the substrat e to deform, Figure 2. 17 (c). Both the film and substrate will bow biaxially and distort near their edges (not shown). (a) (b) (c) Figure 2. 1 7 The generation of biaxially deformed film substrate system from (a) an initially stress free syst em. (b) Application of an imaginary external force to the film in order to match the substrate width. The deformed film is attached to the substrate and exerts a stress on the substrate. (c) The biaxially stressed film substrate system bows in response (Nix 2005).

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48 The stress in the film is assumed to be isotropic and biaxial. Therefore, f zz xx (2.6) w here XX ZZ and f are the stress tensors in the x plane z plane and biaxial film stress, respectively. The force longitudina lly applied to the film is expressed as force per unit length, F Since the cross sectional area of the film can be thought of in terms of film thickness, t f multiplied by length, L, F can be expressed as: F = f f t (2.7) The bending moment, M, generated by F applied at the maximum moment arm distance from the neutral axis, t s / 2, is expressed by: M = 2 t t s f f (2.8) Substituting this bending moment into the mathematical expression derived from the mechani cal analysis of a biaxially deformed plate (see Appendix A) which relates the plate curvature and bending moment, is given by :

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49 3 s s t M 12 E 1 = 3 s f f s s t 2 t t 12 E 1 2 f f s s t t 6 E 1 (2.9) f is: R t 6 t 1 E f 2 s s s f (2.10) This is the well known Stoney Relationship. From this expression, one c an measure the curvature of the wafer and extract the stress present in the attached film. Notice that the results only depend on the elastic properties of the substrate and the dimensions of the film and the substrate. It does not depend on the properti es of the film. It is important to note that the stress determined by the measurement of the wafer curvature is different than the stress determined from structures fabricated from the film and released from the substrate. Wafer curvature measurements al low for the determination of global constrained stresses, i.e. stress in the wafer before it bends. Micromachined structures that are released from the curved wafers allow for the determination of residual stress, or stresses present after the wafer bendi ng. These residual stresses are attributed to the microstructure, defects, and inhomogeneities present in the film and are therefore much more relevant to films used in MEMS applications.

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50 2.5. 3 .2 Cantilever Deflection Beams are the most widely used stru ctural component in MEMS sensors and actuators. They require relatively few processing steps to fabricate and the mechanical principles which govern them are well defined, which makes the mapping of the measureable data into the final result more dependab le. One type of beam structure, the cantilever, is well suited to detect gradient stresses in the film. Gradient stresses are manifested as out of plane bends, which can be measured and quantified using beam mechanics. Cantilevers are simple to fabricat e and small enough to incorporate onto a device die for the purpose stress management. This section will discuss some basic mechanical properties of a microfabricated cantilever while deriving an expression relating the gradient stress to the curvature of the cantilever. Figure 2. 1 8 Illustration of a cantilever structure with length, “L”, width,” b”, and thickness, “h”. The coordinate axis is located so the x z plane coincides with the neutral plane of the cantilever beam (Nix 2005) A general re sidual stress in the plane of a thin film can be envisioned as a superposition of various stress fields represented by the following polynomial series:

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51 0 k k k total 2 h y (2.11) where, h, is the thickness of the cantilever and y is the ordinat e of a coordinate system whose x z plane is located at the neutral plane (midpoint) o f the cantilever, see Figure 2.18 0 is the stress contribution from a uniform, constant stress in the film that is symmetric about the neutral axis. The second term, 1 (y/(h/2)) which arises from the gradient stress, is anti symmetric about the neut ral axis and makes a linear contribution to the total stress field, see Figure 2. 19 Ignoring the higher terms of the polynomial series, the total stress can be expressed approximately as: 2 h y 1 0 total (2.12) When the cantilever structu re is released from the substrate, the film substrate adhesion is removed and the freed structure can deform to relieve its internal stress. The stress field prior to release is shown in Figure 2. 19 (a). After release, the unrestrained end of the cantilev 0 and the cantilever curls to relieve the gradient stress, shown in Figure 2. 19 (b) and (c). This is an idealized scenario in which the higher order terms of equation 2.11 are assumed to be negligible In fact, the higher order terms may make significant contributions, as may be the case in

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52 heteroepitaxial films or polycrystalline films where the defect concentrations or grain sizes may vary non linearly through the film. (a) (b) (c) Figur e 2. 1 9 Stress states present in a thin film cantilever far from the anchor point. (a) The superposition of a uniform constant stress and stress gradient present in the cantilever prior to release from the substrate. (b) After release from the substrate, the constant stress is relaxed via length change of the free standing cantilever. (c) The stress gradient is relaxed once the cantilever curls out of plane. (Fang 1996). The bending moment present in the cantilever, with width, b, is calculated using the gradient stress term in equation 2.12: M = 2 / h 2 / h ydy b = 2 / h 2 / h 1 ydy 2 h y b = 1 2 h b 6 1 (2.13) The variable, y, is a point between the neutral axis and the edge of the beam along the y axis, i.e. the moment arm. Using th e above bending moment and the area moment

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53 of inertia of a rectangle, I = (1/12)*b*h 3 1 can be expressed as a function of the radius of curvature, R: R 1 = I E M = 3 1 2 h b 12 1 E h b 6 1 R 2 h E 1 (2.14) Since the bending is biaxial, E = E f / (1 f ), where E f f are the elastic modulus and the Poisson’s ratio of the film, respectively. 2.5. 3 .3 Planar Rotating Beam Far field cantilever bending is primarily due to the presence of a strain gradient (curl). Nevertheless, near the boundary where the cantilever is attached to the substrate, an angular tilt deformation arises from the superposition of the uniform residual stress, 0 1. Howev er, the determination of the residual stress through the angular tilt at the boundary reflects the global residual stress, the stress of the SiC Si heteroepitaxial system. In order to evaluate the local residual stress present in the poly SiC film, free standing structures have to be realized. An effective technique, as reported by Goosen et al., makes use of a micro rotating structure to measure the local uniform residual stress in the film. The underlying principle of the ability to detect uniform res idual stress in the film is by a force couple

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54 generated by two free standing actuating beam structures on a central, rotating beam, Figure 2.2 0 When the structure is freed from the substrate, the slightly offset actuating beams contract (initially, in te nsion) or elongate (initially, in compression) causing the indicator beam (labeled “rotating beam” in the figure) to deflect. If the beam connections are considered to be ideal, the rotation angle of the indicator (rotating) beam is directly proportional to the strain in the film. A mathematical model can be easily derived using small angle approximations and triangular ratios. (a) (b) Figure 2. 20 Schematic illustration of a conventional planar micro rotating structure (Drieenhuizen 1993) used to me asure strain gradient in a thin film. The relationship between tip deflection, y, and the strain is given by: ) L ) 2 1 ( L ( ) L L ( y L g X B A g f (2.15) L g is the distance between the connection of the actuation beams, L A and L B, are the lengths of the actu ating beams which are designed to be equi dimensional in most cases. The distance, L g should be small in order to increase the sensitivity of the sensor,

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55 but not so close that they interact and cause unintentional buckling with films under compressive str ain. From the residual strain calculated from equation 2.15, it is possible to determine the residual stress for a biaxial film (equation 2.6) using the stress strain relationship: ) 1 ( E f f f (2.16) Now that the theoretical basis for both the observed stress in SiC films grown on Si substrates has been presented, along with the means to determine this stress, the next topic involves how the SiC/Si heteroepitaxial films were realized during this dissertation research. 2.6 CVD Reactor Hardware The CVD reactor used for this research was the horizontal hot wall reactor shown in Figure 2.24, which was designed and built by the SiC Group at the University of South Florida (Myers 2006). The reactor chamber wall is a fused quartz tube suppo rted by water cooled electropolished stainless steel endplates. The gases are regulated via mass flow controllers (MFC) and flow into the head plate (left side of Figure 2.2 1 ) by stainless steel gas lines. A round diffuser plate consisting of sev eral small, evenly spaced holes disperses the gas stream and helps to establish laminar flow. The gases are funneled from the diffuser plate by a quartz inlet tube to the hot zone of the reactor. The hot zone consists of a SiC coated graphite susceptor s urrounded by graphite foam

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56 insulating support. The susceptor provides a means of converting electromagnetic energy from the RF induction coils to thermal energy so the necessary CVD reaction can occur at the substrate surface. The ceiling of the suscepto r was designed with a gradual taper so that the height of the upstream portion is higher than the downstream portion of the susceptor. The taper causes an increase of the gas velocity as it moves through the susceptor and, as a result, decreases the thick ness of the boundary layer. This improves the film uniformity across the wafer. The graphite foam provides a physical means of supporting the susceptor and insulating the susceptor which reduces thermal gradients due to radiative and conductive losses in the susceptor. The water cooled copper coil surrounding the reactor in Figure 2.2 1 heats the reactor hot zone by radio frequency (RF) induction. A 50 kW/ 10 kHz solid state RF generator, manufactured by Mesta Electronics Inc., is capable of inductively heating the susceptor to temperatures greater than 2000C. The temperature of the hot zone is monitored by an optical pyrometer, which measures temperature by monitoring the susceptor’s black body emission. The pyrometer is aimed at a small hole in the s usceptor which has been bored to a depth near the growth zone, so that an accurate temperature measurement at the growth zone can be obtained. The temperature and gas flow is regulated by feeding the data back to the RF generator and MFCs, respectively, b y a computer interface written in LabView TM The CVD reactor is currently configured to flow propane (C 3 H 8 ) and silane (SiH 4 ) which serve as the SiC precursor gases, nitrogen (N 2 ) for n type doping, and argon (Ar) or hydrogen (H 2 ) as the carrier or anneal ing gas. The reactor also has the capability to use hydrogen chloride (HCl) or methyl chloride (CH 3 Cl) to add chlorine to the reactor chemistry (Reyes, 2008). The H 2 gas is purified via a palladium cell and the Ar is

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57 purified by a catalytic purifier. An Edwards DP 40 dry pump and throttle valve regulates the CVD chamber pressure. Figure 2.2 1 Photograph of the MF2 CVD horizontal reactor at USF. MF2 was used for the growth of all films reported in this thesis and is dedicated solely for 3C SiC on Si growth and processing (Myers 2006 ).

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58 CHAPTER 3 : DEVELOPMENT OF LOW TEMPERATURE POLY SiC GROWTH PROCESS FOR POLY Si ON OXIDE SUBSTRATES Micro electrical mechanical systems (MEMS) are used for numerous applications from automobile airbag sensors to combustion control, sensors and medical diagnostics such as DNA assays, just to name a few. These MEMS applications have been supported by Si MEMS, which can be readily made using micromachining techniques developed for the microelectronics industry. One of the powerful fabrication approaches for Si MEMS is the use of poly Si as the MEMS structure, such as cantilevers and membranes, that are deposited on oxide release layers. These mechanical layers are activated (i.e., released) simply by placing the sa mple in an HF solution which dissolves the oxide and thus leaves a free standing poly Si structure supported over the substrate surface. One of the drawbacks of Si MEMS is the fact that Si, while a very durable and easy to machine material, is not suitabl e for harsh environments due to the lack of material resilience at elevated temperatures and when exposed to harsh chemicals and radiation. SiC is a natural material for such harsh environment sensors, and since SiC can be micromachined using similar proc esses to Si, much work has been done to develop SiC based MEMS (Mehregany 1999) (Mehregany 1998) While the cubic form of SiC, 3C SiC, can be deposited directly on Si and the 3C SiC layer patterned using reactive ion etching (RIE), the only way to release the 3C SiC layer is wet KOH etching

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59 of the underlying Si. The resulting material is often rough due to Si residue from the etch which can diminish device performance in addition to adding cost to the device manufacture (KOH etching can take more than an hour in most cases). Being able to employ oxide release layer strategies to SiC based MEMS clearly would be a major step forward in SiC MEMS technology, but in order to achieve this goal two things must happen. First, a low temperature 3C SiC on Si growt h process must be developed, which will be discussed in the opening of this chapter. Second, a poly Si (or single crystal but very thin) layer must be deposited on top of the oxide release layer to allow for the formation of the 3C SiC film. In this chap ter research to realize exactly these objectives is discussed where we have demonstrated a high quality poly 3C SiC on oxide film process that is suitable for subsequent MEMS manufacture which will be the subject of future work as outlined in the following chapter. 3.1 Motivation for Reducing Process Temperature From an economic viewpoint, the faster growth rate of the high temperature (T > 1300 C) 3C SiC heteroepitaxial process would make its incorporation into SiC device fabrication desirable. However, the extreme temperatures severely limit the selection of materials during the fabrication to mainly refractory type materials. Otherwise, device structural integrity may be lost or undesirable diffusion into the surrounding area may lead to device failur e. For example, metals such as Au and Al, frequently used in device fabrication, have melting points far below 1380C and silicon dioxide, having a glass transition temperature near 1200C, exhibits plastic flow at the temperatures used for high temperatu re 3C SiC growth as described in Chapter 2. Another issue arises from the

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60 8% coefficient of thermal expansion (CTE) mismatch between 3C SiC and Si. When the 3C SiC hetero epitaxial film cools from the high growth temperature to ambient room temperature, thermal stress develops at the 3C SiC/ Si interface putting the 3C SiC film under tension and inciting stress relieving mechanisms, such as wafer bow, to emerge. SiC/ Si wafer, the greate r the bow. Excessive wafer bow can complicate subsequent processing of the wafer, induce the deformation of free standing structures, or cause catastrophic substrate fracture or film delamination. Another stress relieving mechanism is the formation of pl anar crystal defects such as glide twins and stacking faults. When these temperature related issues are considered, the development of a low temperature (T C) 3C SiC hetero epitaxial process appears to be a necessity if 3C SiC film growth is to be incorporated with other fabrication processes, especially for MEMS applications where oxide release layers are critical. 3.2 Low Temperature Process Development Since prior 3C SiC growth on (111)Si had been conducted using a high temperature growth regim e (~1380C), no low temperature process had been systematically developed. An established low temperature growth process would exploit the morphologically flat films possible on (111) oriented substrates, but with reduced wafer bow and fracturing associat ed with (111) oriented heteroepitaxial growth. A low temperature growth process would also be compatible for the growth of 3C SiC on oxide coated Si compliant substrates.

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61 3.2.1 Low Temperature Baseline Process The subsequent 3C SiC growth was performed as follows. A (111)Si wafer was placed in a horizontal, hot wall reactor heated by the RF induction of a SiC coated graphite susceptor. The wafer was loaded into a molded poly SiC plate to fix the position of the wafer within the reactor hot zone. This polyplate was then seated into a recess in the susceptor and the chamber was sealed and evacuated of residual gases. The chamber was then filled with palladium purified hydrogen to a pressure of 400 Torr. The 3C SiC process developed for this reactor inv olves two main process stages, namely the carbonization and growth stages (Reyes 2007) The pressure for the carbonization process was 400 Torr, and growth pressure was 100 Torr based on the high temperature process. The standard gases used for 3C SiC gr owth were: palladium purified hydrogen, H 2 which is used as the transport gas; propane (C 3 H 8 ), which is the carbon precursor; and a 10% silane (SiH 4 ) premixed in 90% hydrogen ballast(H 2 ), which is the silicon precursor. The carbonization stage occurred w hile the sample temperature was ramped to 1135C at a rate of ~35 C/min. Throughout the ramp a flow of 16 sccm of C 3 H 8 was maintained with a mass flow controller (MFC), and the H 2 carrier gas flow was maintained at 10 slm. Once the carbonization tempera ture was reached, the temperature was maintained for 3 min to allow conversion of the (111)Si surface into 3C SiC. After carbonization and creation of the 3C SiC template layer, the temperature was ramped a second time at a rate of ~35C/min to the growt h temperature of 1200C. During this ramp, we determined that it was advantageous to decrease the flow of C 3 H 8 while simultaneously introducing and increasing the flow of 10%SiH 4 / 90%H 2 in a step wise

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62 manner. At the growth temperature the input gas silico n to carbon ratio, Si/C, for the growth stage was 1.2. H 2 flow was maintained at 10 slm until 30C before the ramp was completed, where it was increased to 40 slm, and the pressure was simultaneously reduced from 400 Torr to 100 Torr. The temperature and gas flows were then held constant, allowing the continued epitaxial growth of 3C SiC on the carbonized (111)Si wafer. Figure 3.1 graphically summarizes the baseline low temperature process. Figure 3.1 Initial baseline low temperature (1200 C) CVD gro wth process schedule. The initial test dies yielded a hazy surface over the die that were placed on a standard test polyplate, a sintered SiC plate which holds the 8 x 10 mm silicon dies in a consistent location in the reactor hot zone. A series of expe riments were conducted in order to obtain a uniform, specular film deposition within the growth zone. As briefly discussed in Chapter 2, several parameters govern the film deposition when using chemical vapor deposition. In order to develop an optimized process only one growth parameter was changed at a time while all

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63 others were held constant. Sometimes this can be difficult to achieve if a multitude of experiments are conducted, since the process of film deposition itself alters the reactor condition. The first series of experiments involved decreasing the molar concentration of SiH 4 since it was reasoned that C 3 H 8 would not crack as effectively at the lower growth temperature, thus resulting in a Si saturated gas composition. The time of film growth was set at 20 minutes for all experiments since thin polycrystalline films are difficult to discern from thin monocrystalline films in the early stages of growth. In a series of four experiments, the Si/C ratio was varied in increments of 0.2 from 1.4 to 0.8, the C 3 H 8 molar concentration was held constant while the 10%SiH 4 / 90%H 2 flux was varied. The best result was obtained for a Si/C ratio of 1.2, although the film was visually hazy in appearance, it demonstrated the least haziness and had the largest g rain sizes of the four samples when viewed at 500X magnification using an optical microscope. The next series of experiments involved decreasing the precursor concentration in the H 2 carrier gas. The initial precursor molar fraction values for dilution o f 5.5 sccm of C 3 H 8 and 200 sccm of 10%SiH 4 / 90%H 2 in 40slm H 2 were x silane = 0.5x10 3 and x propane = 0.139x10 3 The total precursor concentration was reduced so that the flow rate for propane was 3 sccm. This resulted in molar fractions of x silane = 0.027x 10 3 and x propane = 0.075x10 3 The resulting film morphology was clear and colorful, which indicated very thin film growth. The same experiment was run for 40 minutes to realize a thicker film for a more reliable quality assessment. The resulting 40 min ute film growth was hazy and displayed a very granular morphology when viewed using 200X magnification optical microscopy. The SiC deposits on the polyplate revealed an important detail about the deposition pattern occurring in the hot zone of the reactor ; it appeared that the optimum deposition was

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64 occurring downstream from the position of the test dies. The H 2 carrier gas flow was then reduced in 5 slm increments from 40 slm to 20 slm while maintaining a constant precursor mole fraction. The best depos ition occurred at a 25 slm H 2 flow rate. A growth run was performed to assess the deposition rate. A 1 hour growth duration produced a 1.4 thick 3C SiC film. A series of experiments were planned to increase the deposition rate and improve film quality via modification of the Si/C ratio and precursor concentration. 3.2.2 Optimized Low Temperature Process Once the low temperature baseline process had produced heteroepitaxial films with a clear, specular morphology, the optimum Si/C ratio needed to be d etermined for the new growth process. Although it was determined that the best morphology occurred at a Si/C=1.2 during the establishment of the low temperature baseline process, the position of the growth zone was moved upstream via carrier gas flow adju stment (reduced flow in this case). As the reactants travel through the hot zone, the Si/C ratio of the gas is constantly shifting in favor of a carbon rich atmosphere. This is believed to be the result of the Si supplied by SiH 4 being unavailable for su rface reactions due to the formation of Si clusters in the gas stream (Vorob'ev, et al. 2000) Again, a series of film growths were conducted by varying only the Si/C ratio in 0.1 increments ranging from 1.2 to 0.9 while all other growth parameters were h eld constant. The samples were visually inspected under an optical microscope and it was determined that a Si/C=1.1 displayed the smoothest surface morphology with the fewest inclusions. Although visual inspection of the film provides only a qualitative assessment of film quality, surface

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65 morphology is frequently related to crystal defects and this approach is a valuable tool when simplicity and immediate feedback is required. An increase in the deposition rate was the focus on the next set of experime nts. The current growth schedule involved diluting 3 sccm of C 3 H 8 and 99 sccm of 10%SiH 4 / 90% H 2 in 25 slm of H 2 carrier gas while under 100 Torr of pressure at 1200 C. The precursor concentration was increased to x propane = 0.16x10 3 and x silane = C 3 H 8 = 4 sccm and 10%SiH 4 / 90%H 2 =120 sccm diluted in 25 slm of H 2 maintaining the Si/C ratio at 1.1. The flow rate of C 3 H 8 and 10% SiH 4 / 90% H 2 was increased to 4.0 sccm and 120 sccm, respectively. The resulting film was hazy and exhibited a granular morphology under optical microscope inspection. A growth run using a flow rate of C 3 H 8 =3.5 sccm and SiH 4 = 115 sccm also demonstrated degraded film quality. The process pressure was further reduced from 100 to 75 Torr, the lowest obtainable pressure for the low tem perature growth condition in the MF2 reactor. The pressure was decreased in an attempt to increase the amount of available reacting Si species by decreasing the tendency to form Si clusters. Computer modeling and experiments suggest that the deposition r ate is sensitive to the available Si bonding sites (Vorob'ev, et al. 2000) By decreasing the pressure, Si clusters should tend to dissociate, maintaining all other variables unchanged from the 100 Torr growth schedule. The resulting film grown at 3 sccm of C 3 H 8 99 sccm of 10%SiH 4 / 90% H 2 diluted in 25 slm H 2 carrier gas under 75 Torr yielded improved film morphology. Unfortunately attempts to increase the precursor molar concentration resulted in degraded film morphology. A growth run on an RCA cleaned quartered 50 mm (111) Si wafer was performed to assess the film deposition rate. A forty five minute 3C SiC deposition

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66 experiment was conducted and measurements via FTIR yielded a growth rate that ions resulted in a clear, specular film. The film morphology was assessed using optical microscopy and atomic force microscopy. However, the bowed substrate revealed the presence of residual film stress. No fractures could be seen visually with the unai ded eye, but under 200X, small cracks could be seen. A subsequent growth experiment was performed on an RCA cleaned, 50 mm (111)Si wafer using the optimized low temperature/ low pressure growth process. The duration of the growth plateau was 90 minutes a (measured at the wafer center). The wafer was noticeably bowed and fractures could be seen with the unaided eye across the wafer surface. The cracks formed a triangular pattern along the <110> directions on the wafer. T he low temperature (111)3C SiC process was then applied at increased growth temperatures up to 1380C. The plot of the natural logarithm of the growth rate versus the inverse of the deposition temperature is illustrated in Figure 3.2. The low negative sl ope suggests a transport limited regime for the 75 Torr low temperature growth process This was expected since a previous experiment showed that the growth rate decreased r at 1380C. Atomic force microscopy (AFM) scans were performed to ascertain the surface morphology of the 3C SiC films. X ray diffractometery (XRD) was performed on the 3C SiC film to verify the film orientation and crystalline quality.

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67 Figure 3.2 Plot of the deposition rate vs. inverse temperature using the optimized low temperature/ low pressure growth process at various growth temperatures. 3.3 Poly SiC Growth on Poly Si on Oxide Substrates The growth of polycrystalline SiC, grown on a poly Si seed layer previously deposited on an oxide release layer (see chapter 2) was studied next. Highly oriented 3C SiC films were formed directly on an oxide release layer, composed of a 20 nm thick poly Si seed layer and a 550 nm thick thermally deposite d oxide on a (111)Si substrate was investigated as an alternative to using SOI substrates for freestanding SiC films for MEMS applications The resulting SiC film was characterized by x ray diffraction (XRD) with the x ray rocking curve of the (111) diff raction peak displaying a FWHM of 0.115 (414 wa s better than that for 3C SiC films grown directly on (111)Si during the same deposition process. However, the XRD peak amplitude for the 3C SiC film on the poly Si seed layer was much less than tha t for the (111)Si control substrate due to slight in plane misorientations in the film. Surprisingly, the film was solely composed of (111)3C SiC grains and possessed no 3C SiC grains oriented along the <311> and <110> directions which were the original d irections of the poly Si seed

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68 layer. With this new process, MEMS structures such as cantilevers and membranes can be easily released leaving behind high quality 3C SiC structures. 3.3.1 Motivation for 3C SiC Growth on Oxide Layers SiC is a semiconductor material that is desirable for many power electronics and MEMS applications due to its wide band gap, mechanical resilience, robust thermal properties, and chemical inertness. However, many of these inherent properties create extreme difficulties when pr ocessing MEMS devices with this material SiC chemical resi stance reduces the effectiveness of wet chemical etching and requires the use of dry etching techniques involving reactive ion etching (i.e., DRIE/RIE ) Fortunately cubic silicon carbide, 3C SiC is the one polytype of SiC that can be grown heteroepitaxially on Si substrates and the addition of this Si layer allows for many more processing options in device manufacturing. For example, one can utilize the Si substrate as a sacrificial layer for the creation of freestanding 3C SiC MEMS structures (Beheim and Evans 2006) (Carter, et al. 2000) However, the recipes used to etch Si in DRIE/RIE have a similar etch rate with SiC, thereby excluding selectivity and reducing accuracy for the desired stru cture (Beheim and Evans 2006) (McLane and Flemish 1996) (Rosli, Aziz and Hamid 2006) Freestanding SiC MEMS devices using sacrificial Si layers have also encountered difficulties during device fabrication resulting from unetched Si preventing the complete release of the structure (Beheim and Evans 2006) (Carter, et al. 2000) Silicon dioxide, SiO 2 has been traditionally used as an etch stop in Si processing involving DRIE/RIE and can be easily removed by wet chemistry processes to allow for the full rel ease of freestanding structures (Federico, et al. 2003) With this in mind, silicon on insulator,

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69 SOI substrates provide an excellent media for the creation of freestanding SiC devices by providing not only an oxide for the etc h stop for DRIE/RIE, but al so a Si crystal seed layer for the heteroepitaxial growth of the 3C SiC (Shimizu, Ishikawa and Shibata 2000) (Myers, Saddow, et al. 2004) SOI provides some additional benefits for the growth of 3C SiC as shown in previous studies (Shimizu, Ishikawa and S hibata 2000) (Myers, Saddow, et al. 2004) The high temperatures required for the growth of single crystal 3C SiC soften the SiO 2 layer, allow dispersion of stress caused by the ~ 20% lattice mismatch between SiC and Si and suppress the formation of voids caused by Si evaporation at the 3C SiC/ Si interface (Carter, et al. 2000) Although thick SOI seed layers (>50 nm) have been shown to produce 3C SiC films that are of comparable quality when compared to 3C SiC films grown on single crystal Si substrates the benefits of the epitaxial growth of 3C SiC on SOI are only realized when 3C SiC is deposited on a thin (<50 nm) seed layer of Si, which produces excellent quality 3C SiC (Shimizu, Ishikawa and Shibata 2000) (Myers, Saddow, et al. 2004) However, a m ajor drawback of using SOI in the production of 3C SiC devices is the fact that it requires extensive processing techniques (Shimizu, Ishikawa and Shibata 2000) (Myers, Saddow, et al. 2004) These processes add to the overall production cost of the device In addition many MEMS devices do not require single crystal SiC material for proper functionality. A cost efficient, easily produced wafer stack consisting of poly Si/ SiO 2 / Si layers could replace the SOI substrate if poly SiC is desired as a material for MEMS application s

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70 3.3.2 Deposition of Poly Si Layer on SiO 2 / (111)Si For our experiments we replaced the expensive SOI wafer with a stack of poly Si/ SiO 2 / (111)Si, where the poly Si serve s as the seed layer for the subsequent growth of poly SiC. The results of the growth were surprising because, instead of producing a layer of typical poly SiC, the resulting growth was 3C SiC that was highly oriented in the <111> direction, and contained no grains in the <110> direction, which was the favored ori entation of the poly Si grains Substrate preparation for the growth experiments was as follows. A (111)Si wafer was RCA cleaned, followed by the CVD deposition of 5500 of silicon dioxide. After oxidation, a 50 nm thick film of p oly Si was deposited by LPCVD at a temperature of 610C and a pressure of 300 mTorr (Harbeke, et al. 1984) This process was chosen from the various poly Si recipes for many reasons. The first is that a compressive stress is produced between the resulting poly Si film and the oxide layer, which should help bring the Si crystal lattice into greater compliance with the 3C SiC crystal lattice (Yang, et al. 2000) A secondary reason for the growth of poly Si at this temperature is that it generates large columnar Si grains texture d mainly in the < 11 0> direction with a minor presence of grains textured in the <111> and <311> directions (Harbeke, et al. 1984) The resulting thin poly Si film was characterized by both AFM and XRD to ascertain the starting growth surface properties. The AFM, performed on a PSIA XE 100 microscope, shows a surface with grains of average area on the order of 5.5 nm 2 having an average surface roughness of 0.49 nm rms, but also indicated the presence of pinholes in the surface. The XRD measurements were performed on a Philips Panalytical X’pert Diffractometer operating at the Cu K measurements indicated alignment of the poly Si grains in the <110>, <111>, and <311>

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71 directions, as was expected from the literature (Harbeke, et al. 1984) (Yan g, et al. 2000) The pinholes created difficulties during the deposition of 3C SiC by creating a pathway for softened oxide material to flow onto the growth surface thus damaging the 3C SiC film morphology. Therefore, as outlined in the last section, the temperature for growth was reduced from the temperatures developed previously (M. Reyes, et al.) to eliminate this problem, resulting in the maximum growth temperature for 3C SiC on the film stack of 1200C. 3.3.3 Polysilicon Carbide Growth Process The final optimized growth process is as follows. The poly Si/ SiO 2 / (111)Si wafer stack was placed in a horizontal, hot wall reactor heated by the RF induction of a SiC coated graphite susceptor as outlined in Chapter 2 The wafer was loaded into a molded p oly SiC plate to fix the position of the wafer within the reactor hot zone. This poly SiC plate was then seated into a recess in the susceptor and the chamber was sealed and evacuated of residual gases. The chamber was then filled with palladium purified hydrogen to a pressure of 400 Torr. The 3C SiC process developed for th is reactor involves two main process stages, namely the carbonization and growth stages ( Reyes 2006) The pressure for the carbonization process was 400 Torr, and growth pressure was 100 Torr. The standard gases used for 3C SiC growth are: palladium purified hydrogen, H 2 which is used as the transport gas; propane ( C 3 H 8 ) which is the carbon precursor; and a 10% silane ( SiH 4 ) premixed in hydrogen, which is the silicon precursor. Th e carbonization stage occurred while the sample temperature was ramped to 1 135C at a rate of ~ 35 C/min. Throughout the ramp a 2.3810 3 C mole fraction was

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72 maintained. Once the carbonization temperature was reached, the temperature was maintained for 3 min to allow for conversion of the poly Si surface into 3C SiC. After carbonization and the creation of the 3C SiC template layer the temperature was ramped a second time at a rate of ~ 35C/min to the growth temperature of 1200C. During this ramp, we determined that it is advantageous to slowly decrease the flow of C 3 H 8 while simultaneously introducing and increasing the flow of SiH 4 H 2 flow was maintained at 10 slm until 30C before the ramp was completed, where it was increased to 25 slm, and the p ressure was reduced from 400 Torr to 100 Torr. At the growth temperature t he silicon to carbon ratio, Si/C, for the growth stage was 0.94, with a 3.9410 4 C mole fraction and a 3.7110 4 Si mole fraction. The temperature and gas flow were then held cons tant, allowing for the continued epitaxial growth of 3C SiC on the carbonized poly Si buffer layer. The reactor had no wafer rotation, so t he process parameters produced a upstream side downs tream side of the wafer due to precursor depletion. This rate measured using an Accent QS 1200 FTIR system to determine film thickness, was also verified on samples of 3C SiC grown on single crystal Si oriented in the <100> and <111> directions using ide ntical process conditions as reported above.

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73 3.4 Analysis of the Poly SiC on Oxide Film 3.4.1 AFM Analysis Atomic Force Microscopy ( AFM ) surface analysis was used to c haracterize the film morphology as shown in Fig ure 3.3 The growth of SiC on the poly Si/ SiO 2 / (111)Si substrate was compared with 3C SiC grown directly on (100) and (111)Si substrates. The morphology of the surface of the 3C SiC on the poly Si stack wa s similar to that of the 3C SiC grown on Si (111), showing growth of ordered trian gu lar island grains of similar size The AFM micrograph of 3C SiC grown on Si (100) has smaller, rounded, and more disassociated island growth with a large distribution in grain size A cross section SEM micrograph displays the growth of 3C SiC on the pol y Si stack near the downstream sector of the wafer shown in Fig ure 3.4 This cross section SEM, performed on a Hitachi 4800 microscope shows that the thickness of the 3C SiC film grown for 30 min on the poly Si stack wa s ~1.3 m verifying the growth rate as measured by FTIR An important aspect of this growth process is that the oxide remained perfectly intact and was unaffected during the growth of the 3C SiC.

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74 Figure 3.3 AFM micrographs of the surfaces of the SiC deposi tion grown on (a) poly Si/ SiO 2 were collected in contact mode using a SiN tip. The respective z resolution and r q values are (a) 78nm to 81.4nm, r q =17.9nm, (b) 117.3nm to 118.4nm, r q = 26.5nm, and (c) 47.7nm to 47.5nm, r q =6.57nm.

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75 Figure 3.4 Cross section SEM micrograph of a 3C SiC film grown on the poly Si/ SiO 2 / (111)Si compliant stack. The 3C SiC grown has a thickness of 2 Si layer was estimated to be ~20nm. Note that the SiC/ SiO 2 interface is undamaged. SEM analysis conducted by D. Evans, SRI, Largo, FL. 3.4.2 XRD Analysis Figure 3.5 x ray diffraction (XRD) s pectra and high resolution rocking curves performed on the 3C SiC films for determination of the crystal orientation and quality of the 3C SiC layer For the 3C SiC film grown on the poly Si/ SiO 2 / (111)Si stack a very strong peak was observed at 35.6 while a weaker peak at ~7 1 .8 is due to reflections from the (111) 3C SiC and (311) 3C SiC planes, respectively. It is also evident that there are no SiC reflections originating from the <110> direction, which were the main grain orientations present in the poly Si seed layer. A comparison of the relative peak intensities suggests a preference for grain alignment in the <111> direction while very few grains appear to be aligned along the <311> direction T he 3C SiC film s grown on (111)Si and (100)Si show dominant peaks at 35.6 and 41.4, respectively.

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76 c) F SiC films grown on (a) poly Si/ SiO 2 scans show that (a) and (b) possess a primary peak at 35.6, and (c) possesses a primary peak at 41.4. Insets: rocking curves for each of the 3C SiC films taken at their respective primary Bragg peaks. The FWHM values are 0.115 The rocking curves were taken at the primary Bragg peak for each the 3C SiC epitaxial films. The insets displayed in Fig ure 3.5 show the results of the rocking curves obtained for each substrate type. The rocking curve for the 3C SiC films on poly Si/ SiO 2 / (111)Si substrate disp layed a FWHM of 0.115 (414 the 3C S iC on (111)Si was 0.134 (482 and the 3C SiC on (100)Si displayed FWHM value of the 41.4 peak of 0.128 (460 Si/ SiO 2 / (111)Si versus the growth performed on single crystal Si appea rs to suggest

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77 that all films have relatively comparable crystallinity. This correlation proves to be very interesting because the growth of the 3C SiC film on the poly Si/ SiO 2 / (111)Si stack began on a poly Si seed layer with multiple orientations, and when compared to 3C SiC films by Carter, et al. (Carter 2000) grown on SOI of similar Si seed and oxide layer thickness es (50 nm and 0.5 m respectively) the reported FWHM value was 0.20 (720 SiC grown on the poly Si seed reported in this work. S peculat ion suggests that the result of the weak amplitude from the Bragg reflecti measurement from the rocking curves indicate a highly ordered polycrystalline 3C SiC layer in which the crystallites are misaligned relative to each other but all appear to be of the <111 > direction. While the <111> direction of the 3C SiC planes of the various grains are still approximately parallel to one another, producing a relatively narrow rocking curve, the (111) planes rotated about the <111> direction would produce a weak amplitu 3.5 Summary In summary, a well ordered polycrystalline 3C SiC film with grains predominantly along the <111> direction has been successfully grown on a poly Si/SiO 2 / (111)Si wafer and the process results verified multiple tim es. This process was developed to create a n easy to release 3C SiC layer for use in MEMS applications and, therefore, will be useful for MEMS applications that will benefit from 3C SiC structures. The cost effectiveness and relative ease for the depositio n of both oxide and poly Si make this

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78 process superior to the methods us ed to fabricate SOI substrates, and the oxide layer provides more device processing options than 3C SiC grown directly on single crystal Si. F ortuitously, the resulting 3C SiC films w ere highly ordered in the <111> direction and their quality assessed using AFM, SEM, and XRD analysis The quality of the ordered 3C SiC grown on the poly Si stack is comparable to that of 3C SiC grown on a single crystal Si and much better than that of 3 C SiC grown on conventional SOI as reported in literature.

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79 CHAPTER 4: I NFLUENCE OF POLYSILICON SEED LAYER THICKNESS ON POLY SiC RESIDUAL STRESS In Chapter 2, it was briefly discussed that the intrinsic stress present in thin films was determined by many non equilibrium growth processes that take place early during the film’s deposition. The grain structure, size and growth evolution are the manifestations of the cumulative effect of these processes and, as a result, they play a vital role in stress management. The use of a polysilicon seed layer to grow poly SiC can have the advantage as serving as a template to influence the grain growth evolution in the poly SiC film in a way that is analogous to using a carbonization plateau to reduce defects in crystalline 3C SiC. Polysilicon can exhibit intrinsic compressive or tensile stress depending on the deposition conditions, most notably the deposition temperature, Figure 4.1 (Harbeke, et al. 1984). Compressive polysilicon films are attractive candidate s as a seed layer for poly SiC films since the compressed grains should have a slightly reduced lattice parameter which would help reduce the lattice mismatch between Si and 3C SiC The nature of this compressive stress is not entirely understood, but it has been postulated to be a result of hydrogen incorporation (Yu 1997) the diffusion of excessive adatoms into the grain boundaries, or grain crowding due to lateral grain growth (X. A. J. Fu 2004) (Maier Schneider 1996). Polysilicon films grown at depo sition temperatures Schneider 1996)

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80 that evolves in a conical fashion, i.e. the grain size projected on the surface increases as the film thickness increases. Thicker polysilicon film s should have larger and highly textured grain faces on which poly SiC growth can begin. This should lead to large columns of highly textured poly SiC crystallites exhibiting lower uniform intrinsic stress and reduced stess gradients. Figure 4.1 S tress as a function of deposition temperature for polysilicon films. Note that the films deposited at < 580C are compressive and amorphous, while the films deposited at (Yu 1997) Chapter 3 discussed the establishment of a low temperature growth process based on the vitrification temperature of PECVD oxide (Polian 2002) and the preferential grain growth in the <111> direction of the poly SiC film grown on polysilicon on oxide substates. The low temperature process described in Chapter 3 was developed using unpatterned polysilicon on oxide substrates. The realization of poly SiC MEMS

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81 structures using polysilicon on oxide subst rates would mean that the oxide layer would have to be patterned and then coated with a thin polysilicon film CVD grown poly SiC is deposited on the substrate and then micromachined using standard Si based processing techniques. The opening of Chapter 4 will describe the details of the fabrication process following afterwards with a description of the methods used to characterize the structures. Chapter 4 will conclude with a discussion of the results. 4.1 Fabrication of SiC MEMS on an O xide R elease L a yer An acetate test mask was designed using fundamental beam structures of varying dimensions such as cantilevers, double clamped beams (bridges), and planar rotating structures shown in Figure 4.2 This mask set served as a test bed to find the optimum dimensions to use for stress strain sensitive microstructures fabricated from poly SiC grown on polysilicon on oxide substrates Due to the limitations of the printing emulsion used to print on the acetate, the feature resolution was limited to 20 wever, the low cost and rapid production time made the acetate masks a good choice for design trials. The acetate mask was attached to 5” x 5” soda lime glass squares using double sided cellophane tape to serve as a rigid frame to stabilize the mask durin g photolithography

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82 (a) (b) Figure 4.2 (a) Mask l ayout details of the first test mask consisting of cantilevers/ combs, bridges, and planar rotators of various dimensions. (b) wafer of 3C SiC on Si processed with this mask. 4.1.1 Test Growth on Patterned Polysilicon on Oxide Substrates A test process was performed on an unpatterned, previously fabricated monocrystalline, 2 inch (111)Si wafer containing a PECVD layer coated with a 90 nm thick LPCVD polysilicon layer It was unclear how well a patterned oxide would endure during the low temperature growth process, since all previous growth was done on fully intact substrates. The polysilicon on oxide wafer was patterned with AZ 4620, a robust photoresist use d in pl asma etching, and dry etched to remove unwanted material (described in more detail below). Poly SiC was then grown on t he mesa like poly Si/ oxide patterns (Figure 4.3) using the low temperature process described in Chapter 3

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83 Visual inspection of the waf er revealed that delamination of the 3C SiC film had occurred. Closer inspection of the film via optical microscopy showed evidence of film buckling and glass flow of the underlying oxide layer through pinholes in the polysilicon seed layer (see Figure 4. 3( a ) ). The delamination could have been caused by the discontinuous transition from a monocrystalline film (grown in windows in the oxide/polysilicon films) to a polysilicon film (grown on the mesas), or the oxide layer softening too much and loosing trac tion with the poly SiC during growth To correct this problem, the polysilicon seed layer was stripped from the remaining poly Si on oxide substrates so that a thin conformal layer of polysilicon could be uniformly deposited after the oxide was patterned for the anchor points. It was decided to grow the 3C SiC at 1150 C, which should be below the expected ~1200 C glass transition temperature of the oxide to prevent viscous flow, but hot enough to allow the compliant benefits of the softened oxide layer. The results are shown in Figure 4.3(b) (a) (b) Figure 4.3 Optical micrographs of 3C SiC grown on the patterned poly Si/ SiO 2 / (111)Si substrates. (a) 3C SiC grown at 1225 C from polysilicon only present on the oxide mesas (light colored regions) (b) 3C SiC grown at 1150 C from uniform, conformal polysilicon deposited over the entire substrate. Note the absence of film buckling at the edge of the oxide mesas and glass flow through pinholes in the polysilicon layer.

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84 4.1.2 Poly SiC MEMS Fabricat ion Procedure RCA cleaned (Kern and Poutinen 1970) 2 inch diameter, (111) oriented Si wafers were PECVD coated (111)Si wafers were then spin coated at 2200 rpm for 2 minutes using AZ 4620, a positiv photoresist coated wafer was then soft baked for 1 min at 115 C on a hotplate followed by a 20 min cooldown The photoresist was aligned and patterned with the anchor trenches usi ng a Quintel Mask Aligner. The exposure time was 22 seconds using a filtered UV source with a light intensity of 19 mW/ cm 2 optimized at g line emission The exposed wafer was then developed using AZ 400K, a developer suited for use with AZ 4620, dilute d 1:4 with deionized water. The patterned wafer was then rinsed with deionized water, dried with dry N 2 and examined. Etching of the wafer was carried out using an Alcatel AM 100 Deep Reactive Ion Etcher (DRIE). The plasma etching chemistry utilized a ga s mixture of octafluorocyclobutane, C 4 F 8 and methane, CH 4 excited by a 2500 W RF source. The etch rate of the oxide was ~300 nm/min. The residual photoresist mask was cleaned with acetone followed by a methanol rinse. The patterned oxide wafers were th en RCA cleaned prior to their loading in a LPCVD furnace for polysilicon deposition. The deposition temperature was held at 6 1 0 C under 25 0 mTorr pressure while 100 sccm of SiH 4 flowed. Previous measurements of thicker film depositions made using this r ecipe indicated that 1 min of actual deposition time was necessary to deposit ~20nm of polysilicon. The estimated film thickness was confirmed via ellipsometry. A second set of wafers were deposited with polysilicon

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85 using the same recipe with a 8 min dep osition time. Figure 4.4 illustrates a brief summary of the process. (a) (b) (c) Figure 4.4 Summary of the patterning of anchor points for the SiC based MEMS structures prior to epitaxial growth of the 3C SiC. (a) An oxide layer is PECVD deposit ed on a (111)Si substrate. (b) Windows for anchor points are etched into the oxide layer. (c) A 50 100 nm thick polysilicon layer, serving as a seed layer for 3C SiC growth, is LPCVD deposited on the patterned oxide. The patterned poly Si on oxide stac k was then diced in to quarters and loaded into a horizontal hotwall SiC CVD reactor (Figure 4.5). It was also decided to incorporate a control sample consisting of a patterned monocrystalline (111)Si quarter wafer deposited with the polysilicon seed layer to compare against the polysilicon on oxide substrate. The low temperature growth process is outline d in Chapter 3, section 3.2.2 was then employed to grow a 0 .5 um thick poly SiC film The reactor was then passively cooled under constant Ar purge to a mbient room temperature and extracted for detailed characterization

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86 Figure 4.5 A polysilicon on oxide substrate after poly SiC deposition. The anchor points for the structures are the “streets” between the lighter colored polysilicon/ oxide “mesas” The control sample ( patterned (111)Si ) is also shown for reference (top). Both samples were again spin coated at 2200 rpm with AZ 4620 then aligned and patterned with the MEMS structure mask. The exposed 3C SiC was DRIE etched using a n SF 6 /O 2 chemistr y under DC bias Figure 4.6 The attempt to release the MEMS structures using an HF vapor etch immediately revealed problems with surface tension stiction and suggested that a thicker oxide layer should be implemented in future polysilicon on oxide substr ates to facilitate structure release. The (111)Si substrate exposed after removal of the oxide was etched using a 1:20 NH 4 F: HNO 3 solution to allow enough clearance between the MEMS devices and the substrate. The MEMS structures were then rinsed in a hot IPA bath and dried on a hot plate at 90 C to facilitate release

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87 Figure 4.6 Optical image of the patterned and dry etched poly SiC. The lighter colored area is the exposed sacrificial oxide. The length of the longest cantilever is 1.5mm and the wi Note the rounded cantilever ends due to the resolution limitation of the acetate mask printing process. 4.2 Film Morphology The surface morphology of a 20 nm and 100 nm thick polysilicon film was imaged using a PSIA XE 100 atomic force mic roscope (AFM) operating in tapping mode to understand how the grain size of the seed layer varies between the two depositions. Referencing Figure 4.7(a), the 20 nm thick poly Si seed layer, and Figure 4.7(b), the 100 nm thick poly Si seed layer, it is cle ar that the grain size expands rapidly with film thickness. Maier Schneider et al. reported an increase in the compressive strain of polysilicon films with increasing thickness. They further explain that TEM analysis of the microstructure of the film rev ealed that the early stages of polysilicon deposition is littered with randomly oriented tiny grains which initially grow conically and then develop a columnar morphology. The 100 nm thick film exhibits noticeably larger,

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88 triangular grain morphology. In fact, the grains appear to have some degree of preferred orientation Figures 4.7(c) and 4.7(d) are AFM scans of the poly SiC films grown from the corresponding polysilicon seed layers shown above them. Both poly SiC films were about 0.4 urface image of the poly SiC grown on the 20 nm thick seed layer, Figure 4.7(c) exhibits a fine, granular grain structure, whereas the poly SiC grown on the 100 nm thick seed layer has large, discernable polygonal shaped grains having rounded caps and dee p trenches at the boundaries. From these observations alone, one could suspect that both poly SiC films have a stress gradient present through the thickness of the film.

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89 (a) (b) (c) (d) Figure 4.7 Top: Atomic force microscopy (AFM) sca ns of the polysilicon seed layer (a) 20nm thick and, (b) 100nm thick Bottom: AFM scans of the corresponding poly SiC film depositions, (c) poly SiC film grown on the 20 nm thick polysilicon film and, (d) poly SiC film grown on the 100 nm thick polysilic on film. Poly SiC film thickness is ~ 0 AFM data taken in tapping mode using SiN probes 4.3 Stress Strain Analysis The released SiC MEMS structures were examined using a Hitachi S 800 scanning electron microscope (SEM). Compa rison of the MEMS structures fabricated from the poly 3C SiC grown on the 20 nm poly Si seed layer and on the 100 nm poly Si showed opposite strain gradients present in the films. As seen in Figure 4.8(a), the

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90 polycrystalline 3C SiC grown from the 20 nm t hick seed layer produced a large positive stress gradient which resulted in upward bowed cantilevers. Because the poly SiC film grown on the 100 nm polysilicon seed layer exhibit ed a strong negative stress gradient and the wells wer e shallow, meaningful m easurements c ould not be made with the longer cantilevers since the longer cantilevers push ed into the substrate and lift ed the cantilever Figure 4.8(b). The bow present in the cantilevers fabricated from the polycrystalline 3C SiC film grown on both sub strates indicate d the presence of a substantial gradient str ess in both films The curvature, measured far from the anchor point of the cantilevers, was assumed to be circular in the far field and was approxim ated as circular segments The chord length a nd segment height was measured to determine the radiu Figure 4.10 (a). From these parameters, t he maximum value of the stress gradient was determined using equation 2.14. The results are shown in Table 4.1. The planar rotator structures were not sensitive enough to detect any uniform in plane stress due to the short actuator beams not having enough length change when released from the sacrificial release layer. However, the upward curling rotators micromachined from the poly SiC grown on the 20 nm seed layer provided out of plane deform ation data with minimum in flu ence from the anchors, an issue that has to be considered for cantilever measurements near the anchor point Figure 4.9(a) The measurements were determined in the same manner as the cantilever curvature. The results are show n in Table 4.1. Unfortunately, the large negative stress gradient of the planar rotator structures from the 100 nm seed layer substrate pressed the beams into the substrate, Figure 4.9(b).

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91 (a) (b) Figure 4.8 SEM images viewed from a 45 tilt of pol y SiC cantilevers fabricated from poly SiC grown on polysilicon on oxide using a (a) 20 nm thick seed layer and, (b) 100 nm thick seed layer. Note that the stress gradient is opposite in both cases indicating that the polysilicon film thickness is not yet optimized. (a) (b) Figure 4.9 SEM images taken at a 45 tilt angle of planar rotator structures displaying the stress gradients present in (a) poly SiC film grown on a 20 nm polysilicon seed layer (b) poly SiC grown on a 100 nm polysilicon seed la yer.

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92 Figure 4.10 SEM image of the cantilevers from Figure 4.8(a) and the planar rotator structures from Figure 4.10(a). Dimensions corrected for the tilt projection. Although the SEM data can provide some quantitative data for measuring t he cantilever deflection, the measurements are prone to large uncertainty errors when low angle tilt images are used. All measurements were taken using a Veeco Wyko NT9100

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93 optical profilometer. An optical profilometer is a non invasive method to measure the topology of a surface by using interferometry. Light is split by a beam splitter within the instrument and part of the beam passes through a microscope objective and reflects off the surface being examined. The other half of the beam serves as a refe rence beam and reflects off a very smooth reference mirror mounted within the optical assembly of the microscope objective. The two beams recombine and are projected on a digital camera. Depending on the length difference of the beam paths, the light wil l constructively or destructively interfere and form alternating light and dark fringe patterns. The focal plane of the objective lens is scanned vertically, intersecting the various surface features of the sample under investigation. The position of the servo controlled stage is monitored with the changing light intensity of the changing fringe patterns at each pixel of the digital camera. From this information, the height information of the sample can be extracted.

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94 Figure 4.11 Schematic of an opt ical profilometer. Light is split by a beam splitter and directed through the objective to the sample surface. The reflected light is combined with a reference beam and focused on a digital camera, which records the interference image. The sample is ver tically scanned and the height data is analyzed with the changing interferogram. All measurements were made using Vertical Step Interferometry (VSI). This technique uses a white light source for reliable measurement of smooth and rough surfaces. Figur e 4.10 shows topological images of the cantilevers made via optical profilometry. Optical profilometry provides quick, high resolution surface surveys using a vertically scanning sample stage and white light interferometry. The stress gradient data obtai ned from the profilometry measurements are shown in Table 4.1.

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95 Table 4.1 Maximum stress gradient values from cantilever deflection measurements acquired via optical profilometry. Positive gradient values indicate upward deflection and negative gradi ent values indicate downward deflection. S tructure (seed layer thick.) Thickness Pre Release Length Radius of Curvature (m) Stress Gradient 1 (MPa) Cantilever (100 nm) 0.30 500 .0104 41 Cantilever (100 nm) 0.30 300 .0033 81 Planar Rotator (20 nm) 0.35 2000 7.20x10 6 +130 Planar Rotator (20 nm) 0.35 2000 7.40.x10 6 +126 Cantilever (20 nm) 0.35 1000 9.50x10 6 +10 1 (a) (b) Figure 4. 1 2 Optical profilometer data of poly SiC cantilevers micromachined from poly SiC grown from (a) a 20 nm poly Si seed layer and, (b) a 100 nm thick poly Si seed layer. Notice that bowing is present in the X profile and Y profile data due to biaxial bending. Also note the scale difference between both profiles exaggerates the bowing in the Y profile. Images courtesy of Richard Everly, USF NREC, Tampa FL.

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96 CHAPTER 5 : SUMMARY AND FUTURE WORK S 5 .1 Summary A low temperature h eteroepitaxial process has been developed and characterized for the growth of 3C SiC on 50 mm (111)Si substrates. A “baseline” high temperature process was first developed from a previously established 3C SiC on (100)Si high temperature growth process. F rom this baseline process, a low temperature baseline process at 1200C was developed optimized and then applied to 3C SiC growth on a poly Si/ SiO 2 / (111)Si compliant substrate stack. The initial base line for 3C SiC deposition was achieved using a two step growth process, carbonization of the Si substrates proceeded with a growth plateau. The substrate was first heated from room temperature to 1135C in a mixture of a H 2 /C 3 H 8 ( 10 slm /16 sccm) at 400 Torr. Once at 1135C, the substrate was maintained a t this temperature for two minutes to carbonize the surface. The temperature was then increased from 1135C to 1380C. During this temperature ramp, the H 2 flow was increased to 40 slm and the pressure was reduced from 400 Torr to 100 Torr. The SiH 4 was introduced into the gas mixture at 10sccm and increased at intervals to the final flow rate of 220sccm. Meanwhile, the propane was simultaneously decreased at intervals to 6 sccm. The resulting film was specular and demonstrated low crystal defects as m easured via XRD and TEM analysis.

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97 The high temperature baseline process was then adapted for low temperature growth. The carbonization occurred at 1135C while 10 slm of H 2 and 16 sccm of C 3 H 8 flowed through the reactor. The carbonization process lasted for a two minute duration. The temperature was ramped from 1135C to 1200C. It was discovered after several low temperature optimization experiments that a lower flow rate of the H 2 carrier was required than the high temperature growth process. During the temperature ramp from the carbonization plateau to the growth plateau, a H 2 flow rate of 25 slm was implemented. In order to increase the deposition rate at the lower temperature, the growth pressure was decreased to 75 Torr, the minimum chamber pres sure possible for the MF2 CVD reactor. Under the se optimized conditions, the deposition rate improved from 1.4 morphology. Finally, the optimized low temperature process was used to deposit 3C SiC on an oxide compliant substrate. Compliant substrates should soften at the deposition temperature and allow the strain inherent to heteroepitaxy to reside in the substrate thus ensuring a high quality film is formed. Deposition experiment s on the poly Si/ SiO 2 / (111)Si stacks and various orientations of crystalline Si substrates were performed in tandem. Initial measurements using XRD revealed crystal quality that rivaled or exceeded the films deposited on the crystalline Si substrates. Further investigation using TEM and AFM analysis revealed that the films deposited on the compliant substrate stack were highly textured polycrystalline silicon carbide which seems to be ideal for MEMS applications

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98 Based on this result MEMS structures wer e designed and structures fabricated in order to fully determine the stress strain relationship in these poly SiC on polysil i con films. Successful MEMS structures, consisting of cantilevers, bridges, comb drives and rotating probes, were realized in two se ts of experiments. In the first set an acetate mask results helped to define the optimum polysilicon deposition thickness and temperature, and it was shown that poly SiC stru ctures fabricated on 20 nm and 100 nm thick polysilicon films contained tensile and compressive residual stress (i.e., cantilevers were bowed up and down, respectively). Based on these important findings, a more accurate mask set was designed and fabricate d using chrome on quartz. 5 .2 Future Work A cost effective growth process capable of producing low stress SiC will need to be developed in order for silicon carbide to be considered a commercially viable material for electronic and MEMS applications. U nfortunately, (111) oriented 3C SiC films grown directly on crystalline Si substrates are plagued by stress related issues, such as film deformation, commonly referred to as wafer bow, and fracturing, that overwhelm any benefits achieved to date Several techniques have been investigated to overcome the mismatch issues associated with SiC heteroepitaxial growth, but compliant substrates offer the most promising approach for the realization of devices formed on misma tched heteroepitaxial materials (Ayers 20 08) A wide variety of compliance methods have been developed over the years where a majority of the methods involve a thin film serving as a crystal seed template layer for epitaxial growth that decouples the thicker substrate from

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99 the epitax ial film (Ay ers 2008) The benefit of using an oxide based compliant substrate is that the oxide can be easily etched away thus it serves double duty as a MEMS release layer. This would be invaluable for the advancement of the SiC based MEMS and bio MEMS which is th e research vision of the USF SiC Group at the University of South Florida. 5 .2.1 3C SiC Growth on SOI Substrates As previously discussed, oxide based compliant substrates offer a stress relaxation mechanism and the benefit of an etch stop release layer. The work done on the poly Si/ SiO 2 / Si compliance stack offers many avenues to explore. While the benefit of using a CVD deposited poly seed layer is that it can be deposited using readily accessible tools, producing the very thin films necessary for com pliancy but potentially leaving “pinholes” within the seed layer. A viable solution to overcome this issue is to grow thicker CVD deposited Si films and follow with dry oxidation and HF etching of the Si layer. The low oxidation rate of dry oxidation wo uld offer better control of the seed layer thickness. The poly Si/ SiO 2 / Si stack produces highly oriented polycrystalline 3C SiC, but a monocrystalline template is needed to produce highly crystalline 3C SiC. Initial work in the USF SiC Group involved t he growth of 3C SiC on SOI via cold wall CVD This work was conducted by Dr. R. L. Myers Ward during her MS thesis research using silicon bonded wafers produced by Dr. Karl Hobart of NRL Work on this Si/ poly SiC SOI substrate was continued by S. Harvey v ia hot wall CVD using the MF1 reactor (Harvey 2006)

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100 The compliancy of the oxide layer could be supplemented with the incorporation of various dopants into the silicon over layer (SOL) of the SOI substrate to create a buffer layer to deposit 3C SiC. Si x Ge (1 x) alloys have already been incorporated into the SOL of SOI substrates and have demonstrated improved epitaxial film quality when compa red to non compliant substrates (Ayers 2008) What was lacking during the previous work on SOI substrates in our gr oup was a high quality, low temperature 3C SiC on Si growth process and now that this process has been developed as part of this work perhaps it is time to revisit SOI as a means to form high quality films for electronic device applications. 5 .2.2 Residua l Stress Characterization The fundamental issue regarding heteroepitaxial growth, or any film growth for that matter, is the degree of in plane film stress and how the film responds to that stress. Characterization the 3C SiC film stress is going to be n ecessary in order to quantify and evaluate the effectiveness of 3C SiC growth on future compliant substrates. O nly recently have tools become readily available at USF to make the necessary measurements. A recently established collaboration with Dr. A. Vo linsky in the mechanical engineering department has provided us with new characterization opportunities. Nanoindentation can provide important data regarding film hardness and fracture toughness. Several tools are available for wafer/film deformation ana lysis from which film stress can be extracted via the modified Stoney’s equation. While deformation analysis provides valuable stress related data, it tends to be sensitive and assumptions made in the derivation of the modified Stoney’s equation can produ ce large

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101 errors. Other techniques will need to be incorporated in order to supplement this data. Micro Raman Spectroscopy and XRD analysis can prove useful for quantifying in plane film strain/ stress of highly textured 3C SiC films by measuring the peak shifts in stressed films, however XRD can be ver y sensitive to measurement error if the peaks are characterization protocol of the SiC Group at USF will provide enhanced feedback for continued improvement of the 3C SiC heteroepitaxy process. 5 .2.3 MEMS F abrication Perhaps the most obvious future work task emanating from this thesis research is to take the materials developed and form high quality MEMS structures, either for mechanical MEMS or bio MEMS applications. Given the thrust of the USF SiC group into the bioengineering arena, this work would support a whole host of research on going in the group and thus allow for critical mass to be achieved, which is difficult to do in a university research group that is no t located within a research center. Three tasks are recommended in this area. 1) micro machine 3C SiC on (100)Si films and compare stress values to realized structure bow so as to correlate and correct stress measurement analysis and modified S toney ’s equ ation methods discussed in the previous section. 2) grow additional poly 3C SiC on oxide films, micro machine them and compare the structure bow with pre release mechanical stress measurements to see how well they correlate. And finally

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102 3) re start 3C S iC on SOI substrate research, both for MEMS applications as well as realizing high quality 3C SiC films for electronic applications. If these 3 tasks are pursued there is a high probability that breakthroughs in 3C SiC on Si technology can be made so that this polytype of SiC, the so called ‘dark horse’ of SiC, can take its place as the preferred polytype due to its lower cost of epi growth and possibility for realization on large area, inexpensive Si substrates. To achieve this goal clearly more work need s to be done but the ground work has been laid in this thesis research as well as others around the world and there is hope that this dream may become a reality in the near future.

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103 REFERENCES [1] Anzalone, R., et al. "Heteroepitaxial growth of (111) 3C S iC on (110) Si substrate by second order twins." Appl. Phys. Lett. 92, no. 22 (2008). [2] Ayers, J. E. "Compliant Substrates for Heteroepitaxial Semiconductor Dvices: Theory, Experiment, and Current Directions." Journal of Electronic Materials 37, no. 10 (2008): 1511 1523. [3] Beheim, G. M., and L. J. Evans. "Deep Reactive Ion Etching for the Micromaching of Silicon Carbide." In MEMS Design and Fabrication 85 87. Boca Raton, FL: Taylor and Francis Group, 2006. [4] Camardo, M., A. La Magna, and F. L aVia. "Monte Carlo study of step flow to island nucleation transition for close packed structures." Surface Science 603 (2009): 2226 2229. [5] Carter, G., J. B. Casady, M. Okhuysen, J. D. Scofield, and S. E. Saddow. "Preliminary investigation of 3C SiC on silicon for biomedical applications." Mater. Sci. Forum 338 342 (2000): 1149 1152. [6] Casady, J. B., and R. W. Johnson. "Status of Silicon Carbide (SiC) as a wide bandgap semiconductor for high temperature applications: A review." Solid State El ectronics 39, no. 10 (1996): 1409 1422. [7] Cho, N. H., and C. B. Carter. "Formation, faceting, and interaction behaviors of antiphase boudaries in GaAs thin films." Journal of Materials Science 36 (2001): 4209 4222. [8] Coletti, C., C. L. Frewin, M. H etzel S. E. Saddow, C. Virojanadara, and U. Starke. "Surface studies of hydrogen etched 3C SiC(001) on Si(001)." Appl. Phys. Lett. 91 (2007). [9] Coletti, C., C.L. Frewin, A.M. Hoff, S.E. Saddow. "Electronic Passivation of 3C SiC(001) via hydrogen trea tment." Electrochemical and Solid State Letters 11, no. 10 (2008): H285 287. [10] Cree Inc. 2009. www.cree.com [11] D'Arrigo, G., A. Severino, G. Milazzo, C. Bongiorno, N. Piluso, G. Abbondanza, M. Mauceri, G. Condo relli, F. La Via. "3C SiC heteroepitaxial growth on Inverted Silicon Pyramids (ISP)." Mater. Sci. Forum 645 648 (2010): 135 138.

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111 APPENDICES

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112 Appendix A M echanics of the B iaxial D eflection of a Plate Many of the results used to analyze the mechanical properties of thin films are based on the solutions to fundamental mechanic al problems, e.g. a simply bent beam, a plate deformed by a bending moment, etc. When a film has a thickness, t f that is substantially smaller than the lateral length, L, and thickness of the substrate on which the film is deposited, t s then simple beam mechanics can be applied to understand the deflection response of the film to an applied force. The stress state of the film substrate system is analyzed using the biaxial deflection of a plate as a model, shown in Figure 2.14(a). (a) (b) Figure A.1 (a) Schematic of a bending moment applied to a plate and a cross section diagram (b) showing the resulting stress gradient Referring to Figure 2.14(b), a beam has a bending moment, M, applied so the beam is placed in a pure bending state. The or igin of the coordinate system is located at

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113 Appendix A (Continued) the neutral axis of the purely bent beam. The isotropic, biaxial stress distribution directed along the length of the simple bent beam is given by: y zz xx (2.6) The first subscript denotes the direction of the applied force (stress) and the second subscript denotes the direction of the normal of the plane on which the force (stress) is xx means the force (stress) is directed along t he x axis and is applied to the plane whose normal is parallel to the x axis, in the case of Figure 2.14(b), the y z plane. The distance from the neutral axis along the y direction, y, is the moment arm. By relating the bending stresses in the beam with the b found: M = h/2 h/2 xx ydy = h/2 h/2 2 dy y = 12 h 3 (2.7) 3 h M 12

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114 Appendix A (Continued) Inserting into equation 2.6 yields, 3 zz xx h y M 12 (2.8) Referenci ng Figure 2.15, an expression is derived relating the bending strain of a beam to the curvature. Using equation 2.3 and the relationship of the arc length to the subtended angle and radius (i.e. definition of a radian), the following expression is defined : y R y R R y R L L y xx (2.9) between curvature and the strain in the beam. y y R 1 xx (2.10)

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115 Appendix A (Continued) Figure A.2 Geometric parameters defining a simply bent beam. xx (y), from the strain curvature relationship of equation 2.10, we employ Hooke’s Law: zz yy xx xx E 1 (2.11) xx zz ), no st ress fields exist in the y yy = 0), and the magnitudes of the bending stress strain are dependent on the y distance from the neutral axis, equation 2.11 reduces to: y E 1 y xx xx (2.12)

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116 Appendix A (Continued) xx (y) with the result from the moment analysis in which the stress was related to the bending moment (equation 2.8), and then incorporating the relationship between curvature and strain (equation 2.10), the relation between curvature and the applied moment is: 3 h M 12 E 1 (2.13) Figure A.3 Cantilever deformed by a bending moment.


xml version 1.0 encoding UTF-8 standalone no
record xmlns http:www.loc.govMARC21slim xmlns:xsi http:www.w3.org2001XMLSchema-instance xsi:schemaLocation http:www.loc.govstandardsmarcxmlschemaMARC21slim.xsd
leader nam 22 Ka 4500
controlfield tag 007 cr-bnu---uuuuu
008 s2011 flu ob 000 0 eng d
datafield ind1 8 ind2 024
subfield code a E14-SFE0004958
035
(OCoLC)
040
FHM
c FHM
049
FHMM
090
XX9999 (Online)
1 100
Locke, Christopher William.
0 245
Stress-strain management of heteroepitaxial polycrystalline silicon carbide films
h [electronic resource] /
by Christopher William Locke.
260
[Tampa, Fla] :
b University of South Florida,
2011.
500
Title from PDF of title page.
Document formatted into pages; contains 125 pages.
Includes vita.
502
Disseration
(Ph.D.)--University of South Florida, 2011.
504
Includes bibliographical references.
516
Text (Electronic dissertation) in PDF format.
520
ABSTRACT: Silicon carbide (SiC) is one of the hardest known materials and is also, by good fortune, a wide bandgap semiconductor. While the application of SiC for high-temperature and high-power electronics is fairly well known, its utility as a highly robust, chemically-inert material for microelectrical mechanical systems (MEMS) is only beginning to be well recognized. SiC can be grown on both native SiC substrates or on Si using heteroepitaxial growth methods which affords the possibility to use Si micromachining methods to fabricate advanced SiC MEMS devices. The control of film stress in heteroepitaxial silicon carbide films grown on polysilicon-on-oxide substrates has been investigated. It is known that the size and structure of grains within polycrystalline films play an important role in determining the magnitude and type of stress present in a film, i.e. tensile or compressive. Silicon carbide grown on LPCVD polysilicon seed-films exhibited a highly-textured grain structure and displayed either a positive or negative stress gradient depending on the initial thickness of the polysilicon seed-layer. In addition a high-quality (111) oriented 3C-SiC on (111)Si heteroepitaxial process has been developed and is reported. SiC MEMS structures, both polycrystalline (i.e., poly-3C-SiC) and monocrystalline (i.e., 3C-SiC) were realized using micromachining methods. These structures were used to extract the stress properties of the films, with a particular focus on separating the gradient and uniform stress components.
538
Mode of access: World Wide Web.
System requirements: World Wide Web browser and PDF reader.
590
Advisor:
Saddow, Stephen E.
653
Chemical Vapor Deposition
Heteroepitaxy
Polysilicon
Residual Stress
Silicon Carbide
690
Dissertations, Academic
z USF
x Electrical Engineering Materials Science
Doctoral.
773
t USF Electronic Theses and Dissertations.
4 856
u http://digital.lib.usf.edu/?e14.4958